JP3913241B2 - Driving method of plasma display panel - Google Patents

Description

  The present invention relates to a method for driving a matrix display type plasma display panel (hereinafter referred to as PDP).

  An AC (alternating discharge) type PDP is known as one of such matrix display type PDPs. The AC-type PDP includes a plurality of column electrodes (address electrodes) and a plurality of row electrode pairs that are arranged orthogonally to the column electrodes and form one scan line as a pair. Each of these row electrode pairs and column electrodes is covered with a dielectric layer with respect to the discharge space, and a discharge cell corresponding to one pixel is formed at the intersection of the row electrode pair and the column electrode. .

  At this time, since the PDP uses a discharge phenomenon, the discharge cell has only two states of “light emission” and “non-light emission”. Therefore, the subfield method is used to realize halftone luminance display using such PDP. In the subfield method, a display period of one field is divided into N subfields, and a light emission period having a period length corresponding to the weighting of each bit digit of pixel data (N bits) is assigned to each subfield. The light emission is driven.

  For example, as shown in FIG. 1, when one field period is divided into six subfields SF1 to SF6, light emission driving is performed at a light emission period ratio of SF1: 1 SF2: 2SF3: 4SF4: 8SF5: 16SF6: 32. carry out. For example, as shown in FIG. 1, when the discharge cell emits light with a luminance of “32”, light emission is performed only with SF6 among the subfields SF1 to SF6. Further, when light is emitted with luminance "31", light emission is performed in the subfields SF1 to SF5 other than the subfield SF6. This makes it possible to express halftone luminance in 64 levels.

  As apparent from the sequence of FIG. 1, the number of subfields may be increased in order to increase the number of gradations. However, since a pixel data writing process for selecting a light emitting cell is required for one subfield, increasing the number of subfields increases the pixel data writing process in one field. The light emission period (the length of the sustain light emission process) is relatively shortened and the luminance is lowered.

  In order to display a television image on such a PDP, some kind of image processing for increasing the number of gradations is required. For example, error diffusion processing is known as a multi-gradation technique. The error diffusion process is a method of artificially increasing the gradation by adding an error between pixel data and a threshold value for a certain pixel (discharge cell) to pixel data of peripheral pixels.

  However, when the number of original gradations is small, the error diffusion pattern becomes conspicuous and there is a problem that the S / N deteriorates.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a plasma display panel driving method capable of improving the gradation expression power while improving the display quality.

The method of driving a plasma display panel according to claim 1, wherein a discharge corresponding to a pixel is provided at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged to intersect the row electrodes. The gradation display is performed by dividing the display period of each field in the video signal into N (integer greater than or equal to 2) subfields each assigned a different number of times of light emission. A method for driving a plasma display panel, wherein in each of the N subfields, each of the discharge cells is set to one of a non-light emitting cell or a light emitting cell according to pixel data for each pixel based on the video signal. In the pixel data writing process, only the discharge cells set in the light emitting cells are assigned to the light emitting circuits assigned to the subfields. And a sustain light emission process for an amount corresponding to the repeating emitted in the execution, of the N of the sub-field in the discharge cells belonging to one row of the odd-numbered rows and even rows of the plasma display panel The number of times of light emission assigned to the subfield for which the assignment of the number of times of light emission is small at the kth (k: an integer less than or equal to N) is the other of the odd-numbered rows and the even-numbered rows. Is greater than the number of times of light emission assigned to the sub-field with the smallest assignment of the number of times of light emission in the discharge cells belonging to, and is the number of times of light emission of (k + 1) th in the discharge cells belonging to the other row. Is less than the number of times of light emission assigned to the subfield having a smaller assignment, and (in the discharge cells belonging to the one row ( The number of times of light emission assigned to the subfield with the smallest number of times of light emission assigned to the (+1) th is assigned to the subfield with the smallest number of times of light emission assigned to the (k + 1) th discharge cell belonging to the other row. Oh Ru at large than that of the light-emitting number of times you are.

The plasma display panel driving method according to claim 8 is a plasma display panel driving method for gray-scale driving a plasma display panel in which discharge cells carrying pixels are arranged in a matrix according to a video signal, Each of the discharge cells belonging to one of the odd-numbered row and the even-numbered row of the plasma display panel is assigned a first A luminance level to a (N) A luminance level (N is 2 or more) according to the video signal. Of the odd-numbered row and the even-numbered row, and the discharge cells belonging to the other row among the odd-numbered row and the even-numbered row, respectively. And a second light emission driving step for emitting light at any one of the first B luminance level to the (N) B luminance level according to the first to (N) B luminance levels. ) The (k) A luminance level having the kth (k: 1 to N) luminance level that is the kth lowest among the A luminance levels is the kth luminance among the first to (N) B luminance levels. The level is higher than the lower (k) B luminance level and smaller than the (k + 1) B luminance level having the (k + 1) th lowest luminance level among the first to (N) B luminance levels. And the (k + 1) A luminance level having the (k + 1) th lowest luminance level among the first to (N) A luminance levels is greater than the (k + 1) B luminance level. .

In the discharge cells belonging to one of the odd-numbered row and the even-numbered row, the number of times of light emission is reduced to the kth (k: an integer of 1 to less than N) in each of the N subfields. The number of times of light emission to be assigned to the subfield is greater than the number of times of light emission assigned to the kth subfield with the smallest number of times of light emission in the discharge cells belonging to the other row and (k + 1) in the discharge cells belonging to the other row. The number of times of light emission is smaller than the number of times of light emission assigned to the subfield having the smallest assignment. Further, the number of times of light emission to be assigned to the (k + 1) th sub-field with the smallest number of times of light emission in the discharge cells belonging to one row is smaller, and the number of times of light emission to be assigned to the (k + 1) th time in the discharge cells belonging to the other row is smaller. This is larger than the number of times of light emission assigned to the subfield .

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is a diagram showing a configuration of a plasma display device for driving a plasma display panel (hereinafter referred to as a PDP) based on a driving method according to the present invention.

  In FIG. 2, an A / D converter 1 samples an analog input video signal in accordance with a clock signal supplied from the drive control circuit 2 and converts it to, for example, 8-bit pixel data (input pixel data) for each pixel. ) Converted to D and supplied to the data conversion circuit 30.

  The drive control circuit 2 generates a clock signal for the A / D converter 1 and a write / read signal for the memory 4 in synchronization with the horizontal and vertical synchronization signals in the input video signal. Further, the drive control circuit 2 generates various timing signals for driving and controlling the address driver 6, the first sustain driver 7 and the second sustain driver 8 in synchronization with the horizontal and vertical synchronization signals.

  The data conversion circuit 30 converts the 8-bit pixel data D into 8-bit converted pixel data (display pixel data) HD and supplies the converted data to the memory 4. The conversion operation of the data conversion circuit 30 will be described later.

The memory 4 sequentially writes the converted pixel data HD in accordance with the write signal supplied from the drive control circuit 2. When the writing for one screen (n rows and m columns) is completed by such a writing operation, the memory 4 reads the converted pixel data HD _11-nm for one screen by dividing it into each bit digit. Are sequentially supplied to the address driver 6 line by line.

In response to the timing signal supplied from the drive control circuit 2, the address driver 6 outputs m pieces of pixel data having voltages corresponding to the logical levels of the converted pixel data bits for one row read from the memory 4. Pulses are generated and applied to the column electrodes D _{1 to} D _m of the PDP 10, respectively.

PDP10 is provided with the column electrodes D ₁ to D _m as address electrodes, the row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n are arranged orthogonal to these column electrodes. In the PDP 10, a row electrode corresponding to one row is formed by a pair of the row electrode X and the row electrode Y. That is, the first row electrode pair in the PDP 10 is the row electrodes X ₁ and Y ₁ , and the nth row electrode pair is the row electrodes X _n and Y _n . The row electrode pair and the column electrode are covered with a dielectric layer with respect to the discharge space, and a discharge cell corresponding to one pixel is formed at the intersection of each row electrode pair and the column electrode.

Each of the first sustain driver 7 and the second sustain driver 8 generates various drive pulses as described below in accordance with the timing signal supplied from the drive control circuit 2, and outputs these drive pulses to the row electrodes X ₁ to X _{1 of the} PDP 10. applied to X _n and Y ₁ to Y _n.

3, the address driver 6, various driving the first sustain driver 7 and second sustain driver 8 each applied PDP10 column electrodes D ₁ to D _m, row electrodes X ₁ to X _n and Y ₁ to Y _n It is a figure which shows the application timing of a pulse.

  In the example shown in FIG. 3, the display period of one field is divided into eight subfields SF1 to SF8 to drive the PDP 10. Within each subfield, pixel data writing process Wc is performed in which pixel data is written to each discharge cell of PDP 10 to set a light emitting cell and a non-light emitting cell, and only the light emitting cell is used as a weight for each subfield. The sustain light emission process Ic is performed to maintain the light emission for the corresponding period (number of times). Further, the simultaneous reset process Rc for initializing all the discharge cells of the PDP 10 is executed only in the first subfield SF1, and the erase process E is executed only in the last subfield SF8.

First, the in the simultaneous reset process Rc, the first sustain driver 7 and second sustain driver 8, although such a reset pulse shown in FIG. 3 with respect PDP10 the row electrodes X ₁ to X _n and Y ₁ to Y _n, respectively RP _x and RP _Y are applied simultaneously. Depending on the application of these reset pulses RP _x and RP _Y, all the discharge cells in the PDP10 is then reset discharge uniformly predetermined wall charge in each discharge cell is formed. Thereby, all the discharge cells are set to the light emitting cells.

Then, in the pixel data writing step Wc of Fig. 3, the address driver 6, the pixel data pulse group DP1 ₁ ~ _n of each _{row, DP2 1 ~ n, DP3 1} ~ n, ····, DP8 1 ~ n Are sequentially applied to the column electrodes D _{1 to} D _m as shown in FIG. That is, in the subfield SF1, the address driver 6 generates pixel data pulse groups DP1 ₁ to DP1 ₁ corresponding to the first to n-th rows generated based on the first bit of each of the converted pixel data HD _{11-nm. As} shown in FIG. 3, _n is sequentially applied to the column electrodes D _{1 to} D _m for each row. Further, in the subfield SF2, pixel data pulse groups DP2 ₁ to _n generated on the basis of the second bit of each of the converted pixel data HD _11-nm are sequentially supplied for each row as shown in FIG. The voltage is applied to the column electrodes D _{1 to} D _m . At this time, the address driver 6 generates a high-voltage pixel data pulse and applies it to the column electrode D only when the bit logic of the converted pixel data is, for example, the logic level “1”. At the same timing as the application timing of each pixel data pulse group DP, the second sustain driver 8 generates scan pulses SP as shown in FIG. 3 and sequentially applies them to the row electrodes Y ₁ to Y _n . Go. Here, a discharge (selective erasure discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. The wall charges remaining inside are selectively erased. Due to the selective erasing discharge, the discharge cell initialized to the light emitting cell state in the simultaneous reset process Rc changes to a non-light emitting cell. It should be noted that no discharge is generated in the discharge cells formed in the “column” to which the high voltage pixel data pulse is not applied, and the state is initialized in the simultaneous reset process Rc, that is, the state of the light emitting cell. To maintain.

  That is, according to the execution of the pixel data writing process Wc, a light emitting cell whose light emission state is maintained in a sustain light emission process, which will be described later, and a non-light emitting cell that remains in an extinguished state are alternatively set according to the pixel data. Then, so-called pixel data is written.

Further, in the sustain light emission process Ic shown in FIG. 3, the first sustain driver 7 and the second sustain driver 8 alternate with respect to the row electrodes X _{1 to} X _n and Y _{1 to} Y _n as shown in FIG. Sustain pulses IP _X and IP _Y are applied to. At this time, the discharge cells in which the wall charges remain due to the pixel data writing process Wc, that is, the light emitting cells, emit discharge light during the period in which the sustain pulses IP _X and IP _Y are alternately applied. The light emission state is maintained repeatedly. The light emission maintenance period (number of times) is set corresponding to the weighting of each subfield.

  FIG. 4 is a diagram showing a light emission drive format in which the light emission sustain period (number of times) for each subfield is described.

The drive mode (A) in FIG. 4 is used, for example, during light emission driving in an even field (or even frame), and the drive mode (B) in an odd field (or odd frame). That is, during the display period of the even field, the light emission period in the sustain light emission process Ic for each of the subfields SF1 to SF8 is as shown in the drive mode (A).
SF1: 3
SF2: 11
SF3: 20
SF4: 30
SF5: 40
SF6: 51
SF7: 63
SF8: 37
Is set to
During the display period of the odd field, the light emission period in the sustain light emission process Ic for each of the subfields SF1 to SF8 is as shown in the drive mode (B).
SF1: 1
SF2: 6
SF3: 16
SF4: 24
SF5: 35
SF6: 46
SF7: 57
SF8: 70
Is set to

At this time, the emission period ratio in each of the subfields SF1 to SF8 is non-linear (that is, the inverse gamma ratio, Y = X ² , 2), thereby correcting the non-linear characteristic (gamma characteristic) of the input pixel data D. I am doing so.

  That is, in each sustain light emission process Ic, only the discharge cells set as the light emission cells in the pixel data writing process Wc executed immediately before that are in the drive mode (A) during the even field display period. During the display period, light is emitted over the light emission period shown in the drive mode (B).

In the erase process E shown in FIG. 3, the address driver 6 generates an erase pulse AP and applies it to each of the column electrodes D _{1 -m} . Further, the second sustain driver 8 generates an erase pulse EP simultaneously with the application timing of the erase pulse AP and applies it to the row electrodes Y _{1 to} Y _n . By simultaneously applying these erasing pulses AP and EP, an erasing discharge is generated in all the discharge cells in the PDP 10, and the wall charges remaining in all the discharge cells are extinguished.

  That is, by executing the erase process E, all the discharge cells in the PDP 10 become non-light emitting cells.

  FIG. 5 is a diagram showing all the patterns of light emission driving performed based on the light emission driving format as shown in FIG.

  As shown in FIG. 5, selective erasing discharge is performed on each discharge cell only in the pixel data writing process Wc in one of the subfields SF1 to SF8 (indicated by black circles). . That is, wall charges formed in all the discharge cells of the PDP 10 by performing the simultaneous reset process Rc remain until the selective erasing discharge is performed, and the sustain light emission process in each subfield SF existing in the meantime. In Ic, discharge light emission is promoted (indicated by a white circle). Therefore, each discharge cell becomes a light emitting cell until the selective erasing discharge is performed in the subfield indicated by the black circle in FIG. 5, and in the sustain light emission process Ic in each subfield existing in the meantime, FIG. The light is emitted at the light emission period ratio as shown in FIG.

  At this time, as shown in FIG. 5, the number of times each discharge cell transitions from the light emitting cell to the non-light emitting cell is always less than or equal to one within one field period. That is, a light emission driving pattern that once returns a discharge cell set as a non-light emitting cell to a light emitting cell again within one field period is prohibited.

  Therefore, it is sufficient to perform the simultaneous reset operation with strong light emission regardless of the image display only once in one field period as shown in FIGS. The decrease can be suppressed.

  Further, the selective erasing discharge carried out within one field period is once at most as shown by the black circles in FIG. 5, so that the power consumption can be suppressed. Further, as shown in FIG. 5, there is no light emission pattern in which the period in which the discharge cells are in the light emitting state (indicated by white circles) and the period in which the discharge cells are in the non-light emitting state are reversed in one field period. False contours can be prevented.

At this time, according to the light emission drive pattern shown in FIG.
In the display period of the even field, as shown in the light emission luminance (A) in the figure,
{0: 3: 14: 34: 64: 104: 155: 218: 255}
The light emission drive capable of expressing the luminance of 9 gradations composed of the following light emission luminance ratio is made,
In the display period of the odd field, as shown in the light emission luminance (B) in the figure,
{0: 1: 7: 23: 47: 82: 128: 185: 255}
The light emission driving capable of expressing the luminance of 9 gradations having the light emission luminance ratio is performed.

  In other words, two types of nine gradations of light emission drive having different light emission periods to be performed in each subfield are alternately performed for each field (frame). According to such driving, the number of visually displayed gradations increases from 9 gradations when integrated in the time direction. Accordingly, the dither and error diffusion patterns due to the multi-gradation processing described later are less noticeable and the S / N feeling is improved.

  FIG. 6 is a diagram showing an internal configuration of the data conversion circuit 30 shown in FIG.

  As shown in FIG. 6, the data conversion circuit 30 includes an ABL circuit 31, a first data conversion circuit 32, a multi-gradation processing circuit 33, and a second data conversion circuit 34.

The ABL (automatic brightness control) circuit 31 is a pixel for each pixel sequentially supplied from the A / D converter 1 so that the average brightness of the image displayed on the screen of the PDP 10 is within a predetermined brightness range. It adjusts the luminance level for the data D, and supplies the time resulting luminance adjusted pixel data D _BL to the first data conversion circuit 32.

  The luminance level is adjusted before the inverse gamma correction is performed by setting the ratio of the number of times of light emission in the subfield to be nonlinear as described above. That is, the ABL circuit 31 automatically adjusts the luminance level of the pixel data D in accordance with the average luminance of the inverse gamma converted pixel data obtained by performing inverse gamma correction on the pixel data D (input pixel data). As a result, display quality deterioration due to brightness adjustment is prevented.

  FIG. 7 is a diagram showing an internal configuration of the ABL circuit 31. As shown in FIG.

7, the level adjustment circuit 310 outputs the luminance adjusted pixel data D _BL obtained by adjusting the level of the pixel data D in accordance with the average brightness determined by the average brightness detection circuit 311 to be described later. The data conversion circuit 312 detects the average luminance level as the inverse gamma conversion pixel data Dr obtained by converting the brightness adjustment pixel data _DBL into inverse gamma characteristics (Y = X ^2.2 ) having non-linear characteristics as shown in FIG. This is supplied to the circuit 311. That is, by performing inverse gamma correction processing on the brightness adjustment pixel data _DBL , the pixel data (inverse gamma conversion pixel data Dr) corresponding to the original video signal whose gamma correction has been canceled is restored. The average luminance detection circuit 311 obtains the average luminance of the inverse gamma conversion pixel data Dr and supplies it to the level adjustment circuit 310.

  Further, the average luminance detection circuit 311 selects a luminance mode capable of driving the PDP 10 to emit light at an average luminance corresponding to the average luminance from luminance modes 1 to 4 as shown in FIG. 9, for example. The luminance mode signal LC indicating the luminance mode is supplied to the drive control circuit 2. The average luminance detection circuit 311 uses the drive mode (A) in FIG. 9 when performing drive display for the even field, and uses the drive mode (B) in FIG. 9 when performing drive display for the odd field. The luminance mode as described above is selected. Here, according to the luminance mode signal LC as shown in FIG. 9, the drive control circuit 2 is to maintain the light emission in the sustain light emission process Ic of each of the subfields SF1 to SF8 shown in FIG. 4 (that is, the sustain pulse). Set the number of IP applications).

At this time, the light emission period in each subfield shown in FIG. 4 indicates the light emission period when the luminance mode 1 is set. If the luminance mode 2 is set,
For even fields,
SF1: 6
SF2: 22
SF3: 40
SF4: 60
SF5: 80
SF6: 102
SF7: 126
SF8: 74
For odd fields,
SF1: 2
SF2: 12
SF3: 32
SF4: 48
SF5: 70
SF6: 92
SF7: 114
SF8: 140
The light emission drive in each subfield is performed in the light emission period.

Even in such light emission driving, the ratio of the number of times of light emission in each of the subfields SF1 to SF8 is set to non-linear (that is, the inverse gamma ratio, Y = X2, ² ). The characteristic (gamma characteristic) is corrected.

First data converter circuit 32 in FIG. 6, the luminance adjusted pixel data D _BL of 256 gradations in eight bits supplied from the ABL circuit 31 (0 to 255), the converted pixel data of 8 bits (0 to 128) converted into HD _p and supplies the multi-gradation processing circuit 33.

  FIG. 10 is a diagram showing an internal configuration of the first data conversion circuit 32.

10, the data conversion circuit 321, it converts the luminance adjusted pixel data D _BL into the converted pixel data A of 8 bits (0 to 128) based on it such conversion characteristics as shown in FIG. 11 the selector 322 To supply. Data conversion circuit 323, and supplies this to the selector 322 is converted into the converted pixel data B of 8 bits (0 to 128) based on it such conversion characteristics as shown in FIG. 12 the luminance adjusted pixel data D _BL. Note that specifically, each data conversion circuit 321 and 323, according to which it such a conversion table shown in FIGS. 13 and 14 based on the conversion characteristics shown in FIG. 11 and FIG. 12, the luminance adjusted pixel data D _BL Converted into converted pixel data A and B. The selector 322 from among these converted pixel data A and B, alternatively select the person according to the logic level of the conversion characteristics selection signal, and outputs it as the converted pixel data HD _p. Such a conversion characteristic selection signal is supplied from the drive control circuit 2 shown in FIG. 2 and has a logic level “1” to “0” or “0” from “0” according to the vertical synchronization timing of the input pixel data D. The signal transitions to 1 ". Here, the conversion characteristics in FIG. 11 and the drive mode (B) in FIG. 4 are paired with the conversion characteristics in FIG. 12 and the drive mode (A) in FIG. That is, the selector 322 selects the conversion pixel data B in the field (even field) in which the drive mode (A) in FIG. 4 is set, and the field (odd field) in which the drive mode (B) in FIG. 4 is set. In selects converted pixel data a, it is to output as the converted pixel data HD _P. The conversion characteristics are set according to the number of bits of input pixel data, the number of compression bits by multi-gradation described later, and the number of display gradations. As described above, the first data conversion circuit 32 is provided in the preceding stage of the multi-gradation processing circuit 33 to be described later, and the conversion is performed according to the display gradation number and the compression bit number by the multi-gradation, thereby adjusting the luminance. pixel data D _BL of upper bit group (corresponding to multi-gradation pixel data) and low-order bit group (truncated data: error data) cut to a bit boundary, to perform multi-gradation processing based on the signal It has become. This prevents generation of luminance saturation due to multi-gradation processing and generation of a flat portion of display characteristics that occurs when the display gradation is not at the bit boundary (that is, generation of gradation distortion).

The configuration shown in such FIG. 10, the first data conversion circuit 32, the luminance adjusted pixel data D _BL of 8 bits supplied (0-255) from the ABL circuit 31, the conversion for each field (frame) characteristics (FIGS. 11, 12) to the converted pixel data HD is converted into _p multi-gradation processing circuit 33 of 8 bits while switching the (0-128).

  FIG. 15 is a diagram showing an internal configuration of the multi-gradation processing circuit 33. As shown in FIG.

  As shown in FIG. 15, the multi-gradation processing circuit 33 includes an error diffusion processing circuit 330 and a dither processing circuit 350.

First, the data separation circuit 331 in the error diffusion processing circuit 330 has the lower 2 bits in the 8-bit converted pixel data HD _P supplied from the first data conversion circuit 32 as error data and the upper 6 bits as display data. As separate. The adder 332 delays the addition value obtained by adding the lower 2 bits in the converted pixel data HD _P as the error data, the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335. Supply to circuit 336. The delay circuit 336 delays the addition value supplied from the adder 332 by a delay time D having the same time as the clock cycle of the pixel data, and uses the delayed value as a delay addition signal AD ₁ for the coefficient multiplier 335 and the delay circuit 337. Respectively. The coefficient multiplier 335 supplies a multiplication result obtained by multiplying the delayed addition signal AD ₁ by a predetermined coefficient value K ₁ (for example, “7/16”) to the adder 332. The delay circuit 337 supplies the signal obtained by further delaying the delay addition signal AD ₁ by a time of (one horizontal scanning period−the delay time D × 4) to the delay circuit 338 as a delay addition signal AD ₂ . The delay circuit 338 supplies the signal obtained by further delaying the delay addition signal AD ₂ by the delay time D to the coefficient multiplier 339 as the delay addition signal AD ₃ . Also, the delay circuit 338 supplies the delayed multiplier signal AD ₂ further delayed by the delay time D × 2 to the coefficient multiplier 340 as a delayed add signal AD ₄ . Further, the delay circuit 338 supplies the delayed multiplier signal AD ₂ delayed by the delay time D × 3 to the coefficient multiplier 341 as a delayed add signal AD ₅ . The coefficient multiplier 339 supplies the multiplication result obtained by multiplying the delay addition signal AD ₃ by a predetermined coefficient value K ₂ (for example, “3/16”) to the adder 342. The coefficient multiplier 340 supplies a multiplication result obtained by multiplying the delay addition signal AD ₄ by a predetermined coefficient value K ₃ (for example, “5/16”) to the adder 342. The coefficient multiplier 341 supplies a multiplication result obtained by multiplying the delay addition signal AD ₅ by a predetermined coefficient value K ₄ (for example, “1/16”) to the adder 342. The adder 342 supplies an addition signal obtained by adding the multiplication results supplied from the coefficient multipliers 339, 340, and 341 to the delay circuit 334. The delay circuit 334 delays the added signal by the time corresponding to the delay time D and supplies the delayed signal to the adder 332. The adder 332 adds the error data (the lower two bits in the converted pixel data HD _P ), the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335. When there is no carry, a carry-out signal C _O having a logic level “0” and when there is a carry is generated and supplied to an adder 333. The adder 333 outputs the display data (upper 6 bits in the converted pixel data HD _P ) plus the carry-out signal C _O as 6-bit error diffusion processing pixel data ED.

  The operation of the error diffusion processing circuit 330 having such a configuration will be described below.

For example, when obtaining the error diffusion processing pixel data ED corresponding to the pixel G (j, k) of the PDP 10 as shown in FIG. 16, first, the pixel G (j, k) on the left side of the pixel G (j, k) is first obtained. k-1), upper left pixel G (j-1, k-1), upper right pixel G (j-1, k), and upper right pixel G (j-1, k + 1) Each error data corresponding to each, that is,
Error data corresponding to pixel G (j, k-1): delayed addition signal AD ₁
Error data corresponding to pixel G (j-1, k + 1): delayed addition signal AD ₃
Error data corresponding to pixel G (j−1, k): delayed addition signal AD ₄
Error data corresponding to pixel G (j-1, k-1): delayed addition signal AD ₅
Each is weighted and added with predetermined coefficient values K _{1 to} K ₄ as described above. Next, the lower 2 bits of the converted pixel data HD _P , that is, error data corresponding to the pixel G (j, k) is added to this addition result, and the 1-bit carryout signal C _O obtained at this time is added. the upper 6 bits in the converted pixel data HD _P, that is, the pixel G (j, k) error diffusion processing pixel data ED those obtained by adding the display data corresponding to the.

With this configuration, the error diffusion processing circuit 330 recognizes the upper 6 bits in the converted pixel data HD _P as display data and the remaining lower 2 bits as error data, and generates peripheral pixels {G (j, k−1), G (j-1, k + 1), G (j-1, k), G (j-1, k-1)} are weighted and added to reflect the display data. I have to. By this operation, the luminance of the lower 2 bits in the original pixel {G (j, k)} is expressed in a pseudo manner by the peripheral pixels, and therefore the number of bits is smaller than 8 bits, that is, the display data is 6 bits. Thus, luminance gradation equivalent to the 8-bit pixel data can be expressed.

If this error diffusion coefficient value is added to each pixel at a constant rate, noise due to the error diffusion pattern may be visually confirmed, and the image quality is impaired. Accordingly, the error diffusion coefficients K _{1 to} K ₄ to be assigned to each of the four pixels may be changed for each field as in the case of the dither coefficient described later.

The dither processing circuit 350 performs a dither process on the error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330, thereby maintaining a luminance gradation level equivalent to the 6-bit error diffusion processing pixel data ED. Also, multi-gradation processing pixel data D _{S in} which the number of bits is further reduced to 4 bits is generated. In this dither process, one intermediate display level is expressed by a plurality of adjacent pixels. For example, when performing gradation display corresponding to 8 bits using upper 6 bits of pixel data of 8 bits of pixel data, a set of four pixels adjacent to each other on the left, right, and top is taken as one set. Four dither coefficients a to d having different coefficient values are assigned to each pixel data corresponding to the pixel and added. According to such dither processing, four different combinations of intermediate display levels are generated with four pixels. Therefore, even if the number of bits of pixel data is 6 bits, the luminance gradation level that can be expressed is 4 times, that is, halftone display equivalent to 8 bits is possible.

  However, if a dither pattern consisting of dither coefficients a to d is added to each pixel, noise due to the dither pattern may be visually confirmed and image quality is impaired.

  Therefore, the dither processing circuit 350 changes the dither coefficients a to d to be assigned to the four pixels for each field.

  FIG. 17 is a diagram showing an internal configuration of the dither processing circuit 350.

  In FIG. 17, a dither coefficient generation circuit 352 generates four dither coefficients a, b, c, and d for every four adjacent pixels, and sequentially supplies these to the adder 351.

  For example, as shown in FIG. 18, the pixel G (j, k) and pixel G (j, k + 1) corresponding to the jth row and the pixel G (j + 1, k) corresponding to the (j + 1) th row ) And four dither coefficients a, b, c and d corresponding to the four pixels G (j + 1, k + 1), respectively. At this time, the dither coefficient generation circuit 352 changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.

That is, in the first first field,
Pixel G (j, k): Dither coefficient a
Pixel G (j, k + 1): Dither coefficient b
Pixel G (j + 1, k): Dither coefficient c
Pixel G (j + 1, k + 1): Dither coefficient d
In the next second field,
Pixel G (j, k): Dither coefficient b
Pixel G (j, k + 1): Dither coefficient a
Pixel G (j + 1, k): Dither coefficient d
Pixel G (j + 1, k + 1): Dither coefficient c
In the next third field,
Pixel G (j, k): Dither coefficient d
Pixel G (j, k + 1): Dither coefficient c
Pixel G (j + 1, k): Dither coefficient b
Pixel G (j + 1, k + 1): Dither coefficient a
And in the fourth field,
Pixel G (j, k): Dither coefficient c
Pixel G (j, k + 1): Dither coefficient d
Pixel G (j + 1, k): Dither coefficient a
Pixel G (j + 1, k + 1): Dither coefficient b
The dither coefficients a to d are repeatedly generated by the assignment as described above and supplied to the adder 351. The dither coefficient generation circuit 352 repeatedly performs the operations of the first field to the fourth field as described above. That is, when the dither coefficient generation operation in the fourth field is completed, the operation returns to the operation in the first field again, and the above-described operation is repeated. The adder 351 supplies the pixel G (j, k), pixel G (j, k + 1), pixel G (j + 1, k), and pixel G (j) supplied from the error diffusion processing circuit 330. + 1, k + 1) is added to each of the error diffusion processing pixel data ED corresponding to each of the dither coefficients a to d assigned to each field as described above, and the dither addition pixel data obtained at this time is added. This is supplied to the upper bit extraction circuit 353.

For example, in the first field shown in FIG.
Error diffusion processing pixel data ED corresponding to the pixel G (j, k) + dither coefficient a,
Error diffusion pixel data ED corresponding to pixel G (j, k + 1) + dither coefficient b,
Error diffusion pixel data ED corresponding to the pixel G (j + 1, k) + dither coefficient c,
Each of the error diffusion processing pixel data ED + dither coefficient d corresponding to the pixel G (j + 1, k + 1) is sequentially supplied to the upper bit extraction circuit 353 as dither addition pixel data. Upper bit extracting circuit 353 extracts until the upper 4 bits of such dither-added pixel data, and outputs it as a multi-gradation pixel data D _S.

As described above, the dither processing circuit 350 shown in FIG. 17 changes the dither coefficients a to d to be assigned corresponding to each of the four pixels for each field, thereby reducing visual noise due to the dither pattern. seeking a multi-gradation pixel data D _S of reduced so while also visually multi-gradation to 4-bit (0 to 7), is to supply it to the second data conversion circuit 34.

The second data conversion circuit 34 converts the multi-gradation pixel data D _S into conversion pixels composed of first to eighth bits corresponding to the subfields SF1 to SF8 in FIG. 4 according to the conversion table as shown in FIG. Data (display pixel data) HD is converted. In FIG. 19, the bit having the logic level “1” among the first to eighth bits in the converted pixel data HD is subjected to selective erasing discharge in the pixel data writing process Wc in the subfield SF corresponding to the bit. It indicates that it will be carried out (indicated by a black circle).

  The converted pixel data HD is supplied to the address driver 6 via the memory 4 as shown in FIG. At this time, the converted pixel data HD has any one of nine patterns as shown in FIG. The address driver 6 assigns each of the first to eighth bits in the converted pixel data HD to each of the subfields SF1 to SF8, and only when the bit logic is the logic level “1”, In the pixel data writing process Wc, a high-voltage pixel data pulse is generated and applied to the column electrode D of the PDP 10. As a result, the selective erasing discharge is generated. Accordingly, each discharge cell becomes a light emitting cell until the selective erasing discharge is performed in the subfield indicated by the black circle in FIG. 19, and in the sustain light emission process Ic in each of the continuous subfields existing therebetween, As shown in FIG. 4, light emission is performed at a light emission period ratio.

Thereby, during the even field (frame) display period, as shown in the light emission luminance (A) of FIG.
{0: 3: 14: 34: 64: 104: 155: 218: 255}
9-level light emission drive is made,
During the odd field (frame) display period, as shown in the light emission luminance (B) of FIG.
{0: 1: 7: 23: 47: 82: 128: 185: 255}
Thus, the light emission drive of 9 gradations is performed.

  FIG. 20 shows the relationship between the above-mentioned two types of 9-level light emission luminance (display luminance level) and the input pixel data D. FIG.

  In FIG. 20,-■-indicates the relationship between the input pixel data D and the display luminance level in the drive mode (A) and-♦-indicates the drive mode (B), respectively. From this figure, the gradation level expressed in one drive mode by changing the drive pattern for each field (frame), that is, the number of times of light emission (number of sustain pulses) in the sustain light emission process Ic of each subfield. It can be seen that the gradation level expressed in the other drive mode is set to be between. Therefore, due to the integration effect in the time direction, the number of visually displayed gradations is increased from 9 gradations, and the gradation expression is improved.

  Further, a value between adjacent gradation levels, for example, a value between the light emission luminance “3” and the light emission luminance “14” in the driving mode (A) (a level corresponding to the lower 4 bits of the input pixel data D). Is expressed by multi-gradation processing such as the above-described error diffusion processing and dither processing.

  When multi-gradation processing such as error diffusion processing and dither processing is performed, if the number of original display gradations is small, the multi-gradation processing pattern is noticeable and the S / N feeling deteriorates. Thus, by changing the light emission drive pattern for each field (frame), the number of display gradations in the visual field increases, so that the pattern of multi-gradation processing becomes less conspicuous and the S / N feeling is improved.

  Further, it can be seen from FIG. 20 that the input pixel data D is subjected to inverse gamma correction by setting the light emission frequency ratio in the sustain light emission process Ic of each subfield to the reverse gamma ratio.

  As described above, although the number of gradations in the drive mode (A) and the drive mode (B) is 9 gradations as described above, the light emission drive pattern is changed for each field (frame) as described above. By combining with the multi-gradation processing, the visual gradation expression is equivalent to 256 gradations.

  At this time, as shown in FIG. 19, the number of times that the discharge cell transitions from the light emitting cell to the non-light emitting cell within one field period is always set to 1 or less. Therefore, the above-described simultaneous reset operation with strong light emission, which is not involved in image display, needs to be performed only once within one field period as shown in FIG. Power consumption can be reduced.

  Furthermore, as shown in FIG. 19, since there is no light emission pattern in which the period in the light emitting state (indicated by white circles) and the period in the non-light emitting state are reversed within one field period, Can be prevented.

  In the above embodiment, as a pixel data writing method, wall charges are formed in advance in each discharge cell at the beginning of one field, all discharge cells are set as light emitting cells, and selection is made according to pixel data. In particular, the case where the so-called selective erasure address method in which pixel data is written by erasing the wall charges has been described.

  However, the pixel data writing method can be similarly applied to a case where a so-called selective writing address method in which wall charges are selectively formed according to pixel data is employed.

  FIG. 21 is a diagram showing a light emission drive format when this selective write address method is employed.

Further, FIG. 22, the application of various drive pulses to be applied according PDP10 column electrodes D ₁ to D _m based on the light emission driving format shown in FIG. 21, the row electrodes X ₁ to X _n and Y ₁ to Y _n It is a figure which shows a timing.

  Further, FIG. 23 is a diagram showing a conversion table used in the second data conversion circuit 34 when this selective write address method is adopted, and all the patterns of light emission driving performed within one field period.

As shown in FIG. 22, when the selective write address method is adopted, first, in the simultaneous reset process Rc in the first subfield SF8, the first sustain driver 7 and the second sustain driver 8 are connected to the PDP 10 as shown in FIG. simultaneously applying a respective reset pulses RP _x and RP _Y to the row electrodes X and Y. As a result, all discharge cells in the PDP 10 are reset and discharged, and wall charges are forcibly formed in each discharge cell (R ₁ ). Immediately thereafter, the first sustain driver 7 erases the wall charges formed in all the discharge cells by simultaneously applying the erase pulse EP to the row electrodes X _{1 to} X _n of the PDP 10 (R ₂ ). . That is, according to the execution of the simultaneous reset process Rc shown in FIG. 22, all the discharge cells in the PDP 10 are initialized to the non-light emitting cell state.

  In the pixel data writing process Wc, a discharge (selective writing discharge) is generated only in the discharge cells at the intersection between the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. As a result, wall charges are selectively formed in the discharge cells. Due to the selective write discharge, the discharge cell initialized to the non-light emitting cell state in the simultaneous reset process Rc is changed to the light emitting cell. It should be noted that no discharge is generated in the discharge cells formed in the “column” to which the high-voltage pixel data pulse is not applied, and the state is initialized in the simultaneous reset process Rc, that is, the non-light emitting cell. Maintain state.

  That is, by executing the pixel data writing process Wc, a light emitting cell whose light emission state is maintained in a sustain light emission process, which will be described later, and a non-light emitting cell that remains in an extinguished state are alternatively set according to the pixel data. In other words, pixel data is written to each discharge cell.

  Here, when the light emission driving by the selective writing address method is performed, as shown in FIG. 23, selective writing is performed only in the subfield SF corresponding to the bit of the logical level “1” in the converted pixel data HD. Discharging is performed (indicated by black circles). At this time, the non-light-emitting state is maintained in the subfield existing from the first subfield SF8 until this selective write discharge is performed, and the subfield SF (black circle) in which this selective write discharge is performed is maintained. And the light emission state is maintained in the subfield SF (indicated by white circles) existing thereafter.

  As described above, in the driving method shown in FIGS. 3 to 23, all the discharge cells are initialized to either the light emitting cell or the non-light emitting cell only in the first subfield within one field period. Only in this subfield, pixel data writing is performed in which each discharge cell is set as a non-light emitting cell or a light emitting cell in accordance with the pixel data. With this driving method, in the case of the selective erasing address method, the light emission state is sequentially started from the first subfield of one field as the luminance to be displayed increases. On the other hand, in the case of the selective writing address method, the luminance to be displayed. As the value increases, the light emission state starts in order from the last subfield of one field. Here, the light emission periods (number of times) in each subfield are different from each other, for example, two systems of light emission drive such as drive mode (A) and drive mode (B) shown in FIG. As a result, the number of luminance gradations on the eye is increased.

  FIG. 24 is a diagram showing a specific operation of the driving method shown in FIGS. 3 to 23 described above.

  For example, when the input pixel data is “178”, the display luminance is about “116” by inverse gamma correction.

That is, in the first field (odd field), the drive mode (B) in FIG. 4B and the conversion characteristics in FIG. 11 are selected, and, for example, by multi-gradation processing,
Display luminance “82” in which the pixel G (j, k) has five subfields SF1 to SF5 in a light emitting state,
Display luminance “128” in which the pixel G (j, k + 1) has six subfields SF1 to SF6 in a light emitting state,
Display luminance “128” in which the pixel G (j + 1, k) has six subfields SF1 to SF6 in a light emitting state,
The pixel G (j + 1, k + 1) has a display luminance “128” in which the six subfields SF1 to SF6 are in a light emitting state,
The display luminance “116” is expressed by the average luminance of four pixels adjacent vertically and horizontally.

Next, in the second field (even field), the driving mode (A) in FIG. 4A and the conversion characteristics in FIG. 12 are selected, and by multi-gradation processing, for example,
Display luminance “155” in which pixel G (j, k) has six subfields SF1 to SF6 in a light emitting state,
Display luminance “104” in which the pixel G (j, k + 1) has five subfields SF1 to SF5 in a light emitting state,
Display luminance “104” in which the pixel G (j + 1, k) has five subfields SF1 to SF5 in a light emitting state,
The pixel G (j + 1, k + 1) has the display luminance “104” in which the five subfields SF1 to SF5 are in the light emitting state,
The display luminance “116” is expressed by the average luminance of four pixels adjacent vertically and horizontally.

  In the first, third, fifth, and seventh fields, which are odd fields, the drive mode (B) in FIG. 4B and the conversion characteristics in FIG. 11 are selected, and four pixels are assigned to each. By changing the assigned error diffusion or dither coefficient value in each field, the display luminance of each pixel changes as shown in FIG.

  Similarly, in the second, fourth, sixth, and eighth fields that are even fields, the drive mode (A) in FIG. 4A and the conversion characteristics in FIG. 12 are selected and assigned to each of the four pixels. By changing the error diffusion or dither coefficient value to be changed in each field, the display luminance of each pixel is changed as shown in FIG.

  By combining the method for changing the light emission drive pattern for each field (frame) as described above and the multi-gradation processing, it is possible to improve visual gradation expression capability and display quality.

  However, if the two types of light emission drive having different light emission periods as described above are alternately performed for each field (frame), flickers may occur because the barycentric positions of the light emission within one field period are shifted from each other. .

  This is because, as shown in FIG. 4, the light emission period (number of times of light emission) in the sustain light emission process of each subfield of the drive mode (A) and the drive mode (B) is set to a different value. In the driving mode (A) and the driving mode (B) shown in FIG. 4, for the same input pixel data D, the barycentric position of light emission in the driving mode (B) is always in the driving mode (A). Be on the back side.

  Here, the barycentric position of light emission is determined based on the length of the pixel data writing process, the length of the sustain light emission process, and the weight of the light emission period in the subfield that is in the light emission state within one field period.

  FIG. 25 is a diagram schematically showing a shift in the barycentric position of light emission in the even field and the odd field in FIG.

For example, in the even field (driving mode (A)) in FIG. 24, as shown in FIG. 25 (A), the luminances of a plurality of pixels are averaged to visually compare the subfields SF1 to SF5 in the driving mode (A). period of approximately 1/4 of the sustain light emission process of the whole period and sub-fields SF6 sustain light emission process is a light emitting state, the center of gravity of light emission becomes T _1.

Also, in the odd field (drive mode (B)) of FIG. 24, as shown in (B) of FIG. 25, the luminance of a plurality of pixels is averaged and the subfields SF1 to SF5 in the drive mode (B) are visually observed. period of approximately 3/4 of the sustain light emission process of the whole period and sub-fields SF6 sustain light emission process is a light emitting state, the center of gravity of light emission is T _2.

  As described above, the average display luminance is substantially the same in both the even field in the drive mode (A) and the odd field in the drive mode (B), but flicker occurs due to the deviation of the center of gravity of light emission.

  Each of FIGS. 26 and 27 is a diagram showing an example of a light emission drive format designed to prevent such flicker.

First, in the light emission drive format shown in FIG. 26, the light emission drive start timing shown in the drive mode (A) is set for a predetermined period ΔT from the light emission drive start timing shown in the drive mode (B). It was designed to be delayed. Thereby, the deviation between the light emission gravity center positions T ₁ and T ₂ is reduced, and flicker is reduced.

Here, flicker becomes more conspicuous as the display luminance level is higher. Therefore, during the predetermined period ΔT, light emission gravity center position T ₁ in the driving mode (A) and light emission in the driving mode (B) at the maximum display luminance level “255”. The center of gravity position T ₂ is set to a constant value so as to coincide with each other.

Note that the amount of deviation between the center of gravity T ₁ of light emission in the drive mode (A) and the center of gravity T ₂ of light emission in the drive mode (B) varies depending on the display luminance level, and the amount of deviation is at the maximum display luminance level. The maximum amount is obtained, and the amount of deviation decreases as the display brightness level decreases. The change in the amount of shift due to the display luminance level is small, and flicker is not noticeable when the display luminance level is low. Therefore, even if the predetermined period ΔT is set to a constant value as described above, the effect of suppressing flicker is not achieved. There is enough. However, in order to further suppress flicker, the above-described predetermined period ΔT may be changed in accordance with the display luminance level so that the barycentric positions of light emission always coincide.

On the other hand, in the light emission driving format shown in FIG. 27, the execution period Ta of the pixel data writing process Wc in each of the subfields SF1 to SF4 in the driving mode (A) is set to the pixel data writing process Wc in the driving mode (B). By making it longer than the execution period Tb, the deviation between the light emission gravity center positions T ₁ and T ₂ is reduced, and flicker is reduced. For example, the execution period Ta is made longer than the execution period Tb by widening the pulse width of the scan pulse SP applied to the row electrode of the PDP 10 in the pixel data writing process Wc of each of the subfields SF1 to SF4 in the drive mode (A). To do.

  In the above embodiment, as shown in the drive mode (A) and the drive mode (B), two types of light emission drives having different light emission periods in each subfield are alternately performed for each field (frame). However, switching may be performed for each line of the PDP 10.

  FIG. 28 is a diagram showing an example of a light emission drive format made in view of such points.

In Figure 28, the pixel data writing process W _AC, selective erasure discharge is implemented for all the rows of the PDP 10. On the other hand, in the pixel data writing process W _1C , selective erasing discharge is performed only for even-numbered rows of the PDP 10, and in the pixel data writing process W _2C , selective erasing discharge is performed only for odd-numbered rows.

That is, in the discharge cells in even rows among the discharge cells formed in the first to nth rows of the PDP 10, based on the drive mode (A) of FIG.
SF1: 1
SF2: 6
SF3: 16
SF4: 24
SF5: 35
SF6: 46
SF7: 57
SF8: 70
The light emission drive in each subfield is carried out at a light emission period ratio of
In the odd-numbered discharge cells, based on the drive mode (B) of FIG.
SF1: 3
SF2: 11
SF3: 20
SF4: 30
SF5: 40
SF6: 51
SF7: 63
SF8: 37
The light emission drive in each subfield is performed at the light emission period ratio.

  Further, as shown in the drive modes (A) and (B) of FIG. 28, two types of light emission drive having different light emission periods in each subfield are performed for each field (frame) and one line of the PDP 10. It may be carried out by alternately switching every time.

At this time, in the pixel data writing process W _1C shown in FIG. 28, the selective erasure discharge is performed only on the discharge cells in the even-numbered rows of the PDP 10 during the display period of the odd-numbered frames, and the odd-numbered discharges in the display period of the even-numbered frames. Selective erasing discharge is performed only on the discharge cells in the row. On the other hand, in the pixel data writing process W _2C , selective erasure discharge is performed only for the odd-numbered discharge cells of the PDP 10 during the odd-frame display period, and for the even-numbered discharge cells during the even-frame display period. Only perform selective erasing discharge.

  FIG. 29 is a diagram showing a form of light emission driving performed by such driving.

  As shown in FIG. 29, during the odd-frame display period, the drive mode (A) of FIG. 28 is applied to the even-numbered discharge cells of the PDP 10 and the drive mode of FIG. 28 is applied to the odd-numbered discharge cells. The light emission driving based on (B) is performed. Further, during the display period of the even frame, the light emission based on the drive mode (B) of FIG. 28 is applied to the discharge cells of the even row of the PDP 10 and the drive mode (A) of FIG. 28 is applied to the discharge cells of the odd row. Drive is performed. According to such driving, flickers caused by alternately performing two types of light emission driving such as driving modes (A) and (B) having different light emission periods for each field (frame) can be prevented.

  Note that the drive mode to be changed for each field (frame) or for each row is not limited to the two types as described above. In short, it is only necessary to prepare three or more types of drive modes having different light emission periods in each subfield, and to perform light emission driving by sequentially switching these for every field (frame) or every row.

  In the above-described embodiment, selective erasure (writing) is performed by simultaneously applying the scanning pulse SP and the high-voltage pixel data pulse in any one of the sub-fields SF1 to SF8 in the pixel data writing process Wc. The discharge is caused to occur.

However, if the amount of charged particles remaining in the discharge cell is small, the selective erasing (writing) discharge does not occur normally even if the scanning pulse SP and the high-voltage pixel data pulse are applied simultaneously, and the discharge cell In some cases, the wall charges inside cannot be erased (formed) normally. At this time, even if the pixel data D after A / D conversion is data indicating low luminance, light emission corresponding to the maximum luminance is performed, which causes a problem that the image quality is remarkably deteriorated. For example, when the selective erasure address method is adopted as the pixel data writing method, the converted pixel data HD is
[01000000]
In this case, as shown by the black circle in FIG. 19, the selective erasing discharge is performed only in the subfield SF2, and at this time, the discharge cell is changed to a non-light emitting cell. Thereby, sustain light emission should be performed only in SF1 of subfields SF1 to SF8. However, if the selective erasure in the subfield SF2 fails and the wall charges remain in the discharge cells, the sustain light emission is performed not only in the subfield SF1 but also in the subsequent subfields SF2 to SF8. As a result, the highest luminance display is achieved.

  Therefore, by adopting a light emission drive pattern as shown in FIGS. 30 and 31, such an erroneous light emission operation is prevented. 30 shows a light emission drive format when the selective erase address method is adopted, and FIG. 31 shows a light emission drive format when the selective write address method is adopted.

  “*” Shown in FIGS. 30 and 31 indicates that either the logical level “1” or “0” may be used, and the triangle mark indicates that the “*” is the logical level “1”. This indicates that selective erasing (writing) discharge is performed as long as possible.

  In short, since there is a possibility that writing of pixel data may fail in the first selective erasing (writing) discharge, selective erasing (writing) discharge is performed again in at least one of the subfields existing thereafter. By doing so, the writing of the pixel data is ensured and an erroneous light emission operation is prevented.

It is a figure which shows the conventional light emission drive format for implementing halftone display of 64 gradations. 1 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to a driving method according to the present invention. It is a figure which shows an example of the application timing of the various drive pulses applied to PDP10. It is a figure which shows the light emission drive format based on the drive method of this invention. It is a figure which shows an example of the pattern of the light emission drive implemented based on the light emission drive format shown by FIG. 2 is a diagram showing an internal configuration of a data conversion circuit 30. FIG. 2 is a diagram showing an internal configuration of an ABL circuit 31. FIG. 6 is a diagram illustrating conversion characteristics in a data conversion circuit 312. FIG. It is a figure which shows the correspondence of luminance mode and the light emission period implemented in each subfield. 2 is a diagram showing an internal configuration of a first data conversion circuit 32. FIG. FIG. 6 is a diagram illustrating a first conversion characteristic in the first data conversion circuit 32. FIG. 6 is a diagram illustrating a second conversion characteristic in the first data conversion circuit 32. It is a figure which shows the conversion table based on the conversion characteristic shown by FIG.11 and FIG.12. It is a figure which shows the conversion table based on the conversion characteristic shown by FIG.11 and FIG.12. 3 is a diagram illustrating an internal configuration of a multi-gradation processing circuit 33. FIG. 5 is a diagram for explaining the operation of an error diffusion processing circuit 330. FIG. 3 is a diagram showing an internal configuration of a dither processing circuit 350. FIG. 6 is a diagram for explaining the operation of a dither processing circuit 350. FIG. FIG. 5 is a diagram illustrating an example of all patterns of light emission driving performed based on the light emission driving format shown in FIG. 4 and a conversion table used in the second data conversion circuit 34 when the light emission driving is performed. FIG. 6 is a diagram illustrating a relationship between two types of 9-level light emission luminance (display luminance level) and input pixel data D; It is a figure which shows the light emission drive format at the time of employ | adopting the selective writing address method. It is a figure which shows the application timing of the various drive pulses applied to PDP10 when the selective write address method is employ | adopted. It is a figure which shows an example of the conversion table used by the 2nd data conversion circuit 34 when implementing all the patterns of the light emission drive at the time of employ | adopting the selective writing address method, and this light emission drive. It is a figure which shows the specific operation | movement of the drive method shown by FIGS. It is a figure for demonstrating the shift | offset | difference of the light emission gravity center position which arises by the light emission drive by each of drive mode (A) and (B). It is a figure which shows an example of the light emission drive format which prevents the flicker resulting from the shift | offset | difference of the light emission gravity center position which arises by the light emission drive by each of drive mode (A) and (B). It is a figure which shows another example of the light emission drive format which prevents the flicker resulting from the shift | offset | difference of the light emission gravity center position which arises by the light emission drive by each of drive mode (A) and (B). It is a figure which shows the light emission drive format used when switching drive mode (A) and (B) for every line, or for every line and every field (frame), and performing light emission drive. It is a figure for demonstrating the operation | movement at the time of switching the drive mode (A) and (B) for every row and every field (frame), and performing light emission drive. It is a figure which shows another example of the light emission drive pattern at the time of employ | adopting the selective erase address method. It is a figure which shows another example of the light emission drive pattern at the time of employ | adopting the selective writing address method.

Explanation of main part codes

2 drive control circuit 6 address driver 7 first sustain driver 8 second sustain driver 10 PDP
30 Data conversion circuit 31 ABL circuit 31
32 first data conversion circuit 33 multi-gradation processing circuit 34 second data conversion circuit
330 Error diffusion processing circuit
350 Dither processing circuit

Claims (9)

A plasma display panel in which a discharge cell corresponding to a pixel is formed at each intersection of a plurality of row electrodes arranged for each scan line and a plurality of column electrodes arranged to cross the row electrodes is used as a video signal. A display method for driving a plasma display panel in which gradation display is performed by dividing a display period of each field into N (integer greater than or equal to 2) subfields each assigned a different number of times of light emission.
In each of the N subfields, a pixel data writing step for setting each of the discharge cells as one of a non-light emitting cell or a light emitting cell according to pixel data for each pixel based on the video signal, and the light emitting cell And performing a sustain light emission process in which only the discharge cells set to be repeatedly emitted for the number of times of light emission assigned to the subfield, and
Of the N subfields in the discharge cells belonging to one of the odd-numbered rows and the even-numbered rows of the plasma display panel, the k-th (k is an integer of 1 to less than N) in the N subfields. The number of times of light emission assigned to the subfield with the smaller number of times of light emission is assigned to the kth number of times of light emission in the discharge cells belonging to the other of the odd-numbered row and the even-numbered row. More than the number of times of light emission assigned to the subfield that is larger than the number of times of light emission assigned to the smaller subfield and is assigned to the (k + 1) th smallest number of times of light emission in the discharge cells belonging to the other row. Is also small,
The number of times of light emission assigned to the (k + 1) th subfield with the smallest number of times of light emission in the discharge cells belonging to the one row is the number of times of light emission assigned to the (k + 1) th time in the discharge cells belonging to the other row. the driving method of a plasma display panel, characterized in Oh Rukoto large than the number of light emissions which assignments are assigned to the subfield becomes small. The number of times of light emission assigned to each of the N subfields in the discharge cells belonging to the one row, and each of the N subfields in the discharge cells belonging to the other row. 2. The plasma display panel driving method according to claim 1 , wherein the number of times of light emission is changed for each field in the video signal . Performing a reset process for initializing all the discharge cells only in the light-emitting cells or the non-light-emitting cells only in the first subfield in the display period of each field;
Only in the pixel data writing process of any one of the N subfields, the discharge cell is changed from the state of the light emitting cell to the state of the non-light emitting cell or the state of the non-light emitting cell according to the pixel data. 3. The method of driving a plasma display panel according to claim 1 , wherein a pixel data pulse having a voltage to be changed from a state to a state of the light emitting cell is applied to the column electrode . The second pixel data pulse having the same voltage as the pixel data pulse is applied to the column electrode in the pixel data writing process in a subfield immediately after the first pixel data writing process. Item 4. A driving method of a plasma display panel according to Item 3 . The method as claimed in claim 1, wherein the provision of the erase step for the state of only all of the discharge cells non-light emitting cell in the subfield of the last in the display period of each field. In the reset process, all the discharge cells are initialized to the state of the light emitting cells, and in the pixel data writing process, the discharge cells are selectively erased and discharged in accordance with the pixel data, thereby making the discharge cells non-discharged. 4. The method of driving a plasma display panel according to claim 3, wherein the method is set to a light emitting cell . N + 1 gradation driving is performed by causing the light emitting cell to emit light only in the sustain light emission process in each of the n subfields (n is 0 to N) continuous from the head of the display period of each field. The method for driving a plasma display panel according to claim 1 or 3 . A plasma display panel driving method for driving a plasma display panel in which discharge cells carrying pixels are arranged in a matrix in a gray scale according to a video signal,
Each of the discharge cells belonging to one of the odd-numbered row and the even-numbered row of the plasma display panel is assigned a first A luminance level to a (N) A luminance level (N is 2 or more) according to the video signal. A first light emission driving step of emitting light at a luminance level of any one of
Each of the discharge cells belonging to the other of the odd-numbered row and the even-numbered row has a luminance of any one of a first B luminance level to a (N) B luminance level according to the video signal. A second light emission driving process for emitting light at a level,
Among the first to (N) A luminance levels, the (k) A luminance level having the kth (k: 1 to N) luminance level is the first to (N) B luminance levels. (K + 1) th brightness level which is greater than the (k) B brightness level and the (k + 1) th brightness level is lower than each of the first to (N) B brightness levels. The (k + 1) A luminance level is smaller than the B luminance level and has the (k + 1) th lowest luminance level among the first to (N) A luminance levels. features and to pulp plasma display panel driving method that is larger than the luminance level. Of the number of times of light emission assigned to each of the N (integers greater than or equal to 2) subfields, the number of times of light emission assigned to the subfield arranged at the beginning of the display period of each field is the smallest . The method of driving a plasma display panel according to claim 1 .

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