JP3910986B2 - Optical disk device - Google Patents

Description

The present invention relates to an optical disc apparatus provided with a data recording clock signal generator for generating a recording clock signal for recording data provided in a data recording apparatus of a recording medium such as an optical disc capable of recording data and a hard disk.

  Recording media such as CD-R, CD-RW, DVD-R, and DVD-RAM are known as optical disks having data recording tracks wobbled with a wobble signal having a predetermined frequency component. There is a data recording clock signal generator (see, for example, Patent Document 1 and Patent Document 2) that generates a recording clock signal that is phase-synchronized with the wobble signal of these optical disks.

  In addition, as a property of the data rewritable optical disk, if recording is repeated many times in the same place, the recording mark and its periphery deteriorate due to thermal stress etc., and the next time a different signal is recorded, the mark cannot be recorded accurately. However, in order to alleviate such problems, the recording start point can be changed randomly, and the repeated use of the same location can be prevented to average and reduce the fatigue of the disc material. In particular, there have been optical disk recording methods and optical disk devices (see, for example, Patent Document 3 and Patent Document 4) that improve the number of repeated uses.

  Furthermore, there is an optical disk (for example, see Patent Document 5) in which address information is superimposed on a wobble signal by phase modulation, and there is also a data recording clock signal generator that generates a recording clock signal that is phase-synchronized with the wobble signal of the optical disk. .

FIG. 14 is a block diagram showing a configuration example of a conventional optical disk drive device.
First, the optical disk 1 has a data recording track wobbled with a wobble signal having a predetermined frequency component.

FIG. 15 is an explanatory diagram showing an example of the structure of a wobbling data recording track on the optical disc 1.
A groove portion indicating the position of the track is wobbled corresponding to the address information, and the address information and the synchronization signal are modulated and superimposed on the wobble signal.

In the conventional optical disk drive shown in FIG. 14, a laser beam is emitted from an optical pickup (PU) 2 toward a data recording track on the optical disk 1.
Then, the laser beam reflected by the track on the optical disc 1 is returned to the optical pickup 2 and converted into an electric signal by the detector in the optical pickup 2.

The amplifier 3 amplifies the electric signal detected by the optical pickup 2 and outputs a reproduction signal (RF) corresponding to the data recorded on the optical disc 1 and a wobble signal (WBL) corresponding to the wobbling of the track.
The reproduction signal (RF) is detected when data is reproduced, and the wobble signal (WBL) is detected by both data recording and reproduction operations.

  The recording clock generation circuit 4 generates a recording clock signal (WCLK) that is phase-synchronized with the wobble signal (WBL).

FIG. 16 is a block diagram showing a configuration example of the conventional recording clock generation circuit shown in FIG.
The recording clock generation circuit 4 is configured by a so-called PLL (Phase Locked Loop) circuit.
The phase comparator 41 compares the phase difference between the wobble signal (WBL) and a signal (frequency-divided clock) obtained by dividing the recording clock signal (WCLK) into a predetermined ratio by the frequency divider 45.

The output from the phase comparator 41 is converted into a voltage signal by the charge pump 42, smoothed by the filter 43, and input to a VCO (Voltage Controlled Oscillator).
The frequency of the output clock of the VCO, that is, the recording clock signal (WCLK) is controlled by the input voltage. As a result, the phase of the recording clock signal (WCLK) is synchronized with the wobble signal (WBL).

Returning to FIG. 14, the synchronization detection circuit 5 and the address decoder 6 of the conventional optical disk drive apparatus detect the synchronization signal and address information superimposed on the wobble signal, respectively.
When data is recorded, the data encoder 8 performs a predetermined modulation process on the recording data in synchronization with the recording clock signal (WCLK).

The LD driver 9 modulates the intensity of the laser beam emitted from the optical pickup 2 according to the modulated recording data.
As a result, data recording is performed in synchronization with the wobble signal of the data recording track.
JP-A-10-293926 JP-A-11-66563 Japanese Patent Publication No. 8-10489 Japanese Patent Laid-Open No. 10-3667 Japanese Patent Laid-Open No. 10-69646

  However, the technique described in Patent Document 3 described above averages and reduces the fatigue of the disk material by making the recording start point randomly variable and preventing repeated use of the same location. In order to increase the number of times of repeated use, a plurality of analog delay circuits must be used to obtain the random recording start point, and there has been a problem that the apparatus cost becomes high.

  Next, in the conventional recording clock generation circuit as described above, if the wobble signal is normally detected, the phase of the recording clock signal (WCLK) is always synchronized with the wobble signal (WBL).

  However, there may be small defects on the optical disk, and dust may adhere to the surface of the optical disk, and the wobble signal is lost at the part where such defects or dust are attached, and normal. Detection may not be performed.

  Therefore, since the recording clock generation circuit constituted by the conventional PLL circuit as described above has a so-called PLL flywheel effect, the phase of the wobble signal and the recording clock signal is detected for a small missing wobble signal. Synchronization is kept.

  However, if the wobble signal loss is large, the phase of the wobble signal and the recording clock signal is shifted during the loss, and after the loss, the recording clock signal has a phase shift that is an integral multiple of the wobble signal period. There may be a so-called bit slip that is phase-synchronized with the state.

  When a bit slip occurs, the phase shift between the wobble signal and the recording clock cannot be recovered, and the recording data is recorded in a state shifted from a predetermined position.

In addition, when data recording to a certain sector is completed after bit slip has occurred, when data is newly recorded from the succeeding sector, data overlap or unnecessary blanks occur at the connection portion of the recording data. .
In such a case, there is a problem that the worst situation that data in the vicinity of the recording data connection portion cannot be reproduced correctly is likely to be caused.

  Next, in the case of an optical disc in which address information is superimposed on a wobble signal by phase modulation (for example, see Patent Document 5), there is a portion where a sudden change occurs in the wobble signal phase due to phase modulation, and a conventional recording clock is generated. The circuit has a problem that a phase shift occurs between the wobble signal and the recording clock signal.

This invention has been made to solve the above problems, even in the case of an optical disk obtained by superposing by phase modulating the address information into the wobble signal, Ru is generated recording clock phase-synchronized stably wobble signal an object of the present invention and this.

In order to achieve the above object, the present invention provides data to an optical disc having a data recording track having a predetermined frequency component and wobbling a wobble signal in which address information and a synchronization signal are superimposed by phase modulation at a predetermined timing. an optical disk apparatus having a data recording clock signal generator for generating a recording clock signal is phase locked to the wobble signal when recording, the data recording clock signal generator, extract the wobble signal A wobble signal extracting means for performing recording, a recording clock signal dividing means for generating a divided clock signal obtained by dividing the recording clock signal, and a phase difference by comparing phases of the wobble signal and the divided clock signal. a phase difference signal generating means for generating a signal, the position generated by the phase difference signal generating means Recording clock generated with a frequency control signal generating means for generating a frequency control signal based on the difference signal, the recording clock signal having a frequency controlled based on the frequency control signal generated by the frequency control signal generating means Signal generating means for detecting a synchronization signal superimposed on the wobble signal, and in a predetermined detection section in which the address information on the optical disk and the synchronization signal are phase-modulated, the phase difference signal generating means A synchronization detection circuit that prevents generation of a phase difference signal, a data encoder that modulates recording data in synchronization with the recording clock signal and outputs an encoder synchronization signal at a predetermined timing, and the synchronization detection circuit A synchronization determination circuit for monitoring the timing of the detected synchronization signal and the encoder synchronization signal; Means for adjusting the phase of the recording clock signal from the data recording clock signal generator so as to eliminate the difference when there is a difference in timing between the synchronization signal detected by the synchronization detection circuit and the encoder synchronization signal to provide an optical disc apparatus provided with and.

The optical disk apparatus according to the present invention masks the operation of the phase comparator at a portion where a sudden change in the wobble signal phase is caused by the phase modulation, so that no phase shift occurs between the wobble signal and the recording clock signal. It is possible to generate a recording clock that is phase-synchronized stably.

Hereinafter, the best mode for carrying out the present invention will be specifically described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration example of a reference example of the present invention and an optical disk drive device according to an embodiment of the present invention. Components common to the optical disk drive device shown in FIG. The description is omitted.

  The recording clock generating circuit 4 of this optical disk drive device is a recording clock that is phase-synchronized with the wobble signal when recording data on the optical disk 1 having a data recording track wobbled with a wobble signal having a predetermined frequency component. This is a data recording clock signal generating device for generating a signal, and the recording clock generating circuit 4 or the like functions as the following means according to the present invention and the reference example of the present invention.

  A wobble signal extracting means for extracting the wobble signal; a recording clock signal dividing means for generating a divided clock signal obtained by dividing the recording clock signal; and a phase of the wobble signal and the divided clock signal. Phase difference signal generating means for generating a phase difference signal by comparison, frequency control signal generating means for generating a frequency control signal based on the phase difference signal generated by the means, and the frequency control generated by the means Recording clock signal generating means for generating the recording clock signal having a frequency controlled based on the signal, and the reference frequency division when the recording clock signal dividing means divides the recording clock signal Frequency division ratio setting means for setting the ratio and a frequency division ratio different from the reference frequency division ratio according to a predetermined order.

  And means for changing the order of combinations of reference frequency division ratios set for the recording clock frequency dividing means and frequency division ratios different from the reference frequency division ratio each time data is recorded on the optical disk.

  Further, a synchronization detection means for detecting a synchronization signal superimposed on the wobble signal, a synchronization relationship determination means for determining a synchronization relationship between the synchronization signal detected by the means and the recording data of the optical disc, and the means When it is determined that the timing of the recording data is delayed with respect to the synchronization signal, the average value of the frequency division ratio set in the recording clock frequency dividing means is longer than the reference frequency division ratio. If it is determined that the timing of the recording data is advanced with respect to the synchronization signal, the average value of the frequency division ratio set in the recording clock frequency dividing means is higher than the reference frequency division ratio. Control means to make the value short.

The phase of the wobble signal when recording data on an optical disc having a data recording track having a predetermined frequency component and wobbling with a wobble signal in which address information and a synchronization signal are superimposed by phase modulation at a predetermined timing. An optical disc apparatus comprising a data recording clock signal generator for generating a synchronized recording clock signal, wherein the data recording clock signal generator comprises a wobble signal extraction means for extracting the wobble signal, and the recording Recording clock signal frequency dividing means for generating a frequency-divided clock signal obtained by frequency-dividing the clock signal, and phase difference signal generating means for generating a phase difference signal by comparing the phases of the wobble signal and the frequency-divided clock signal When the frequency control signal based on the phase difference signal generated by the phase difference signal generating means Comprising a frequency control signal generating means for generating, and recording clock signal generating means for generating the recording clock signal having a frequency controlled based on the frequency control signal generated by the frequency control signal generating means, the While detecting the synchronization signal superimposed on the wobble signal, the phase difference signal generating means does not generate the phase difference signal in the predetermined detection section where the address information on the optical disc and the synchronization signal are phase-modulated. A synchronization detection circuit that performs synchronization with the recording clock signal, modulates the recording data, and outputs an encoder synchronization signal at a predetermined timing, and the synchronization signal detected by the synchronization detection circuit and the encoder synchronization A synchronization determination circuit that monitors the timing of the signal and the synchronization detection circuit When there is a difference in timing between the signal and the encoder synchronization signal, means for adjusting the phase of the recording clock signal from said data recording clock signal generator so as to eliminate the difference.

  And a data recording clock signal generator for generating a recording clock signal phase-synchronized with the wobble signal when data is recorded on an optical disk having a data recording track wobbled with a wobble signal having a predetermined frequency component. A wobble signal extracting means for extracting the wobble signal, a recording clock signal dividing means for generating a divided clock obtained by dividing the recording clock signal, and the wobble signal and the divided clock signal. A phase difference signal generating means for comparing the phases to generate a phase difference signal; a first frequency control signal generating means for generating a first frequency control signal based on the phase difference signal generated by the means; and the wobble Wobble signal dividing means for dividing the signal by a predetermined dividing ratio, and the wobble signal divided by the means. The wobble signal period counting means for counting the period of the recording clock signal with the period of the recording clock signal, second frequency control signal generating means for generating a second frequency control signal based on the period counted by the means, and the wobble signal When the period counted by the period counting means is within a predetermined range, the recording clock signal having a frequency controlled by the first frequency control signal generated by the first frequency control signal generating means is generated. When the period is outside a predetermined range, a recording clock signal is generated for generating the recording clock signal having a frequency controlled by the second frequency control signal generated by the second frequency control signal generating means. means.

Furthermore, a data recording clock signal generator for generating a recording clock signal phase-synchronized with the wobble signal when data is recorded on an optical disc having a data recording track wobbled with a wobble signal having a predetermined frequency component A wobble signal extracting means for extracting the wobble signal, a recording clock signal dividing means for generating a divided clock obtained by dividing the recording clock signal, the wobble signal and the divided clock signal, A phase difference signal generating means for generating a phase difference signal by comparing phases of the first frequency control signal, a first frequency control signal generating means for generating a first frequency control signal based on the phase difference signal generated by the means, and A wobble signal dividing means for dividing the wobble signal by a predetermined dividing ratio, and a wob divided by the means. Wobble signal period counting means for counting the period of the signal by the period of the recording clock signal; second frequency control signal generating means for generating a second frequency control signal based on the period counted by the means; and the wobble When the period counted by the signal period counting means is within a predetermined range, the recording clock signal having a frequency controlled by the first frequency control signal generated by the first frequency control signal generating means is generated. And the recording having the frequency controlled by the second frequency control signal generated by the second frequency control signal generating means when it is continuously detected a predetermined number of times that the period is outside the predetermined range. Recording clock signal generating means for generating a recording clock signal.
Each of the above functions will be described in the following order.

First, a recording clock generation circuit according to a reference example of the present invention will be described.
FIG. 2 is a block diagram showing an example of the internal configuration of the recording clock generation circuit 4 of the reference example of the present invention shown in FIG. 1, and the same reference numerals are given to portions common to FIG.
The recording clock generation circuit 4 is constituted by a so-called PLL (Phase Locked Loop) circuit, and generates a recording clock signal (WCLK) that is phase-synchronized with the wobble signal (WBL).

The frequency divider 45 outputs a frequency-divided clock signal obtained by frequency-dividing the recording clock signal (WCLK) according to the frequency-division ratio control signal output from the frequency-division ratio setting table 47.
The divided clock signal is fed back to the phase comparator 41 and also input to the divided clock counter 46.

The frequency-divided clock counter 46 changes the count value for each edge of the frequency-divided clock signal.
The frequency division ratio setting table 47 outputs a frequency division ratio control signal to the frequency divider 45 according to the count value of the frequency division clock counter 46 and the frequency division condition setting value.

FIG. 3 is a diagram showing a more detailed configuration example of the frequency divider 45, the frequency divided clock counter 46, and the frequency division ratio setting table 47.
This frequency-divided clock counter (2 bit Cnt) 46 is constituted by a 2-bit counter.

  Further, the frequency divider 45 includes an A counter (A Cnt: 4 bit Cnt) 451 which is a 4-bit counter, a B counter (B Cnt: 3 bit Cnt) 453 which is a 3-bit counter, a synchronous SRFF 455, an inverter (Inv) 453, and the like. And a multiplexer (Mux) 454 having a 3to1 configuration.

  The A counter 451, the B counter 452, and the synchronous SRFF 455 are supplied with a recording clock signal (WCLK) (not shown). In the following description, one period of the recording clock signal is expressed as 1T. To do.

  The Qb output and Q output of the synchronous SRFF 455 are connected to the count enable input (EN) of the A counter 451 and the B counter 452, respectively.

  The S input of the synchronous SRFF 455 is connected to a signal indicating that the A counter 451 has a full count output (= 15), that is, the count value of the A counter 451 is the maximum value “15”.

  The R input of the synchronous SRFF 455 is connected to a full count output (= 7) of the B counter 452, that is, a signal indicating that the count value of the B counter 452 is the maximum value “7”.

The full count output (= 15) of the A counter 451 is also connected to the load input (LD) of the B counter 452.
The full count output (= 7) of the B counter 452 is also connected to the load input (LD) of the A counter 451.

  The data input (Di) of the A counter 451 receives one value selected by the multiplexer 454 from among the values “7”, “8”, and “9”, and the load (LD) input is activated. In this case, the count value of the A counter 451 is set to one of “7”, “8”, and “9”.

  When the value “0” is input to the data input (Di) of the B counter 452 and the load (LD) input becomes active, the count value of the B counter 452 is set to “0”.

Next, the operation of the frequency divider 45 will be described.
The A counter 451 and the B counter 452 perform count operations alternately.
The A counter 451 performs a counting operation from an initial value of “7”, “8”, or “9” to a final value “15” depending on the value selected by the multiplexer 454.
That is, the A counter 451 counts for 7T, 8T, or 9T by one count operation.

The B counter 452 performs a count operation from the initial value “0” to the final value “7”.
That is, the B counter 452 counts for 8T in one count operation.

The divided clock is a signal obtained by inverting the Q output of the synchronous SRFF 455 by the inverter 453.
Therefore, the operation for one cycle of the divided clock is a combination of one count operation of the A counter 451 and one count operation of the B counter 452, and the period is 15T, 16T, or It will be 17T minutes.

  That is, the reference frequency division ratio of the frequency divider 45 is “16”, and the frequency division ratio can be changed by ± 1 with respect to the reference frequency division ratio.

A full count output (= 7) of the B counter is connected to the count enable input (EN) of the divided clock counter 46.
Therefore, the frequency-divided clock counter 46 counts the count value every time the operation of one cycle of the frequency-divided clock that combines one count operation of the A counter 451 and one count operation of the B counter 452 is completed. Let me up.
Since the frequency-divided clock counter 46 is a 2-bit counter here, the count value is a value from 0 to 3.

The division ratio setting table 47 receives 2-bit count data from the frequency division clock counter 46 and 2-bit data as a division condition setting value.
The frequency division ratio setting table 47 outputs a frequency division ratio control signal according to the truth table shown in Table 1 according to the count value of the frequency division clock counter 46 and the frequency division condition setting value.

The frequency division ratio control signal of the frequency division ratio setting table 47 is connected to the multiplexer 454, and the initial value of the A counter 451 is selected according to the frequency division ratio control signal.
The multiplexer 454 selects the value “7” when the frequency division ratio control signal (Sel7) is active, and selects the value “8” when the frequency division ratio control signal (Sel8) is active. When the ratio control signal (Sel9) is active, the value “9” is selected.

FIG. 4 is a timing chart for explaining the operation of the frequency divider 45, and the operation of the frequency divider 45 shown in FIG.
FIG. 4 shows a timing chart of four stages at the same time. When the first stage is the division condition setting value = 0, the second stage is the division condition setting value = 1, and the third stage is the division condition. When the set value = 2, the fourth stage is the respective operation timing when the dividing condition set value = 3.

  Further, the timing diagram of the divided clock counter value from “0” to “3” is shown in the horizontal direction in FIG. 7. After the divided clock counter value becomes “3”, “0” is again displayed. Return to "".

First, the operation when the frequency division condition setting value = 0 is described.
Based on the truth table of Table 1, when the division condition setting value = 0, the division ratio setting table 47 indicates that the division ratio control signal (Sel8) regardless of the count value from the division clock counter 46. Activate only.

  Therefore, the initial value of the A counter 451 is set to “7” at the beginning of all the divided clock cycles, and the count operation of the A counter 451 is 8T in all divided clock cycles. The cycle period is 16T.

Next, the operation when the frequency division condition setting value = 1 is described.
The initial value of the A counter 451 in the divided clock cycle when the divided clock counter value becomes “0” is the multiplexer immediately before that, that is, the last multiplexer cycle at which the count value of the divided clock counter 46 becomes “4”. Depends on the output from 454.

  Based on the truth table in Table 1, when the frequency division condition setting value = 1 and the frequency division clock counter value = 4, the frequency division ratio control signal (Sel7) is active. The initial value of the A counter 451 in the divided clock cycle when the value becomes “0” is “7”.

  Therefore, the count operation of the A counter 451 in the divided clock cycle in which the count value of the divided clock counter 46 is “0” is 9T, and the period of one cycle of the divided clock is 17T.

In the same manner as described above, the divided clock cycle period at which the count value of the divided clock counter 46 is “1” is 15T.
Further, the divided clock cycle period at which the count value of the divided clock counter 46 is “2” is 16T.
Further, the divided clock cycle period at which the count value of the divided clock counter 46 is “3” is 16T.

  That is, when the division condition setting value = 1, the cycle of one cycle of the divided clock is not constant, and the pattern of “17T → 15T → 16T → 16T →, 17T → 15T → 16T → 16T →...” Is repeated. .

In the same manner as described above, when the division condition setting value = 2, the period of one cycle of the divided clock is “17T → 15T → 17T → 15T →, 17T → 15T → 17T → 15T →,. Repeat pattern.
When the division condition setting value = 3, the cycle of one cycle of the divided clock repeats the pattern of “17T → 16T → 16T → 15T →, 17T → 16T → 16T → 15T →.

In this way, it is considered how the phase of the divided clock changes when the period of one cycle of the divided clock is changed in a predetermined pattern.
When the division condition setting value = 0, the cycle of one cycle of the divided clock is always 16T, and 16T is the reference division ratio as described above.

In the following description, the phase change of the divided clock signal will be described with reference to the phase of the divided clock signal when the division condition setting value = 0.
The phase that the phase comparator 41 pays attention to is the rising edge phase of the divided clock signal.

Since the divided clock is obtained by inverting the Q output of the synchronous SRFF 455, attention is paid to the falling edge phase of the Q output of the synchronous SRFF 455 in FIG.
When the division condition setting value = 1, the divided clock cycle period at which the count value of the divided clock counter 46 is “0” is 17T. Therefore, the falling edge phase of the Q output of the synchronous SRFF 455 is divided. There is a delay of 1T with respect to the clock reference phase.

  Further, since the divided clock cycle period at which the count value of the divided clock counter 46 becomes “1” is 15T, the falling edge phase delay of the immediately preceding cycle is subtracted and the Q output of the synchronous SRFF 455 falls. The edge phase matches the divided clock reference phase.

  Furthermore, since the divided clock cycle period at which the count value of the divided clock counter 46 becomes “2” and “3” is 16T, the falling edge phase of the Q output of the synchronous SRFF 455 matches the divided clock reference phase. To do.

  That is, when the division condition setting value = 1, the divided clock phase repeats the pattern “1T delay → match → match → match →...” With respect to the divided clock reference phase.

  In the same manner as described above, when the division condition setting value = 2, the divided clock phase repeats the pattern “1T delay → match → 1T delay → match →...” With respect to the divided clock reference phase.

  When the division condition setting value = 3, the divided clock phase repeats the pattern of “1T delay → 1T delay → 1T delay → match →...” With respect to the divided clock reference phase.

Next, the relationship between the wobble signal (WBL) phase and the recording clock signal (WCLK) phase when the divided clock phase changes as described above will be described.
The operation time constant of the PLL is generally set to a period longer than the phase comparison period.
Therefore, even if the divided clock phase changes as described above, the recording clock signal frequency is maintained at a substantially constant value so that the average phase of the divided clock signal matches the wobble signal phase in a steady state. Lock state can be obtained.

  FIG. 5 is a diagram illustrating the timing of the wobble signal (WBL), the recording clock signal (WCLK), and the divided clock signal that are locked in a steady state when the dividing condition setting value = 1.

  (A) to (d) in the upper part of the figure show the relationship among the wobble signal (WBL), the divided clock signal, and the count value of the divided clock counter 46, and the lower (e) to (g). In FIG. 2, the rising edge portion where the phase comparison is performed is enlarged to show the relationship between the wobble signal (WBL), the recording clock signal (WCLK), and the divided clock signal, respectively.

As described above, in the locked state in the steady state, the average phase of the divided clock signal matches the wobble signal phase.
As a result, the phase of the divided clock with respect to the wobble signal has a relation of “0.75T delay → 0.25T advance → 0.25T advance → 0.25T advance →...” As shown in FIG. .

When the division condition setting value = 1, considering that only the divided clock phase when the count value of the divided clock counter 46 is “0” is delayed by 1T with respect to the divided clock reference phase, the wobble signal The divided clock reference phase with respect to the phase always advances by “0.25T”.
This is equivalent to the recording clock signal phase with respect to the wobble signal phase being advanced by “0.25T”.

  Although not shown in the figure, in the same manner as described above, when the dividing condition setting values = 2 and 3, the recording clock signal phase with respect to the wobble signal phase is “0.5T” and “0.75T”, respectively. Go ahead.

  In this manner, the recording clock generation circuit 4 sets the phase relationship between the wobble signal and the recording clock signal to 0.25T in accordance with the frequency division condition setting value in the range of “0” to “3”. The unit can be changed from “0T” to “0.75T”.

  Next, control when the recording clock generation circuit changes the phase relationship between the wobble signal and the recording clock signal more greatly will be described based on the timing chart of FIG.

The upper part of FIG. 6 shows the operation timing of the frequency divider 45 when the frequency division condition setting value is changed from “3” to “0”.
Here, the timing at which the frequency division condition setting value is changed from “3” to “0” is made to coincide with the timing at which the count value of the frequency division clock counter 46 is changed from “3” to “0”.

  The frequency division condition setting value is “3” and the frequency division clock cycle period at which the count value of the frequency division clock counter 46 is “3” is 15T as described above.

  In the frequency division clock cycle period in which the frequency division condition setting value is “0” and the count value of the frequency division clock counter 46 is “0”, the initial value of the A counter 451 is “3”. ", And the count value of the frequency-divided clock counter 46 is set at the stage of" 3 ", so it becomes 17T.

  Similarly, the frequency division clock cycle period at which the frequency division condition setting value is “0” and the count value of the frequency division clock counter 46 is “1”, “2”, “3” is as described above. 16T.

  That is, the divided clock cycle period immediately after the dividing condition setting value is changed from “3” to “0” is different from the divided clock cycle period in which the dividing condition setting value remains “0”. After that, the phase shift due to the 1T period addition remains accumulated.

  Therefore, when the dividing condition setting value is set to “3” and the phase of the recording clock signal is advanced by 0.75T with respect to the wobble signal, the dividing condition setting value is changed to “0”. The phase of the recording clock signal relative to the signal is advanced by 1T.

  When the dividing condition set value is further changed from “1 → 2 → 3” from this state, the phase of the recording clock signal with respect to the wobble signal in the steady state is “1.25T → 1.5T → 1.75T”. It will be in the “advanced” state.

The lower part of FIG. 6 shows the operation timing of the frequency divider 45 when the frequency division condition setting value is changed from “0” to “3”.
Here, the timing at which the frequency division condition setting value is changed from “0” to “3” is made to coincide with the timing at which the count value of the frequency division clock counter 46 is changed from “3” to “0”.

  The frequency division clock cycle period at which the frequency division condition setting value is “0” and the count value of the frequency division clock counter 46 is “3” is 16T as described above.

  In the frequency division clock cycle period in which the frequency division condition setting value is “3” and the count value of the frequency division clock counter 46 is “0”, the initial value of the A counter 451 is “0”. ", And the count value of the frequency-divided clock counter 46 is set at the stage of" 3 ", so it becomes 16T.

  Similarly, the divided clock cycle period when the dividing condition setting value is “3” and the count value of the divided clock counter 46 is “1”, “2”, “3” is as described above. Respectively, "16T", "16T", and "15T".

  That is, the divided clock cycle period immediately after the dividing condition setting value is changed from “0” to “3” is different from the divided clock cycle period in which the dividing condition setting value remains “3”. The period of the minute is subtracted, and thereafter, the phase shift due to the period addition of 1T remains accumulated.

  Therefore, when the division condition setting value is set to “0” and the division condition setting value is changed to “3” from the state in which the phase of the recording clock signal coincides with the wobble signal, the recording condition for the wobble signal is recorded. The phase of the clock signal is delayed by 0.25T.

  When the dividing condition set value is further changed from “2 → 1 → 0” from this state, the phase of the recording clock signal with respect to the wobble signal in the steady state is “0.25T → 0.5T → 0.75T delayed. It becomes a state.

  In this manner, the recording clock generation circuit of this reference example has a phase dividing condition setting value in the range of “0” to “3”, and the phase relationship between the wobble signal and the recording clock signal is 0 according to the value. Not only can be changed from “0T” to “0.75T” in increments of 25T, but the frequency division condition setting value is increased to a binary counter expression such as “3 → 0 → 1 → 2 → 3 ...” Or the phase relationship between the wobble signal and the recording clock signal is changed infinitely in units of 0.25T by decreasing it as “0 → 3 → 2 → 1 → 0...” be able to.

  In the recording clock generation circuit of the reference example of the present invention described above, the count length of the frequency dividing clock counter 46 is set to “4”, and the repetition cycle of the frequency division ratio change of the frequency divider 45 is set to “4”. The setting unit of the phase relationship between the wobble signal and the recording clock signal is “0.25T”, but the count length is made longer and the repetition cycle of the change in the division ratio is also made longer, so that the finer The phase relationship can be set in units.

Next, a recording clock generation circuit according to another reference example of the present invention will be described.
This recording clock generation circuit has the same configuration as shown in FIGS. 2 and 3 and is used as the recording clock generation circuit 4 of the optical disk drive device shown in FIG. 1 as described above. It is slightly different from the above.

  In this case, the recording clock generation circuit 4 randomly selects a dividing condition setting value set in the recording clock generation circuit 4 every time data is recorded on the optical disc 1 by a controller (not shown).

  In this way, according to the recording clock generation circuit 4, the phase relationship between the wobble signal and the recording clock signal changes randomly every time data is recorded on the optical disc, and the same location in the recording area of the optical disc is repeated. Can be prevented, and fatigue of the disk material can be averaged and reduced, and as a result, the number of repeated uses can be improved.

  In addition, since the recording start point can be randomly varied without using an analog delay circuit, the apparatus cost can be reduced and the apparatus can be provided at a low price.

Next, a recording clock generation circuit according to still another reference example of the present invention will be described.
This recording clock generation circuit has the same configuration as shown in FIGS. 2 and 3 and is used as the recording clock generation circuit 4 of the optical disk drive device shown in FIG. 1 as described above. It is slightly different from the above two.

  This recording clock generation circuit is configured as shown in FIGS. 2 and 6 as in the other reference examples, and is used as the recording clock generation circuit 4 of the optical disk drive shown in FIG.

  In this case, the address information and the synchronization signal are modulated and superimposed on the wobble signal on the optical disc 1 which records data with the recording clock generated by the recording clock generation circuit 4.

The synchronization detection circuit 5 of the recording clock generation circuit 4 detects the synchronization signal superimposed on the wobble signal and outputs the wobble synchronization signal.
The address decoder 6 detects address information superimposed on the wobble signal.

In addition to modulating the recording data in synchronization with the recording clock signal (WCK), the data encoder 8 inserts a synchronization signal into the modulation data.
Also, an encoder synchronization signal is output at the timing of the synchronization signal insertion.
The synchronization determination circuit 11 monitors the timing of the wobble synchronization signal and the encoder synchronization signal.

Normally, in a state where the phases of the wobble signal and the recording clock signal are synchronized, the timings of the wobble synchronization signal and the encoder synchronization signal match.
However, when a bit slip occurs in the recording clock generation circuit 4, a phase shift occurs between the wobble signal and the recording clock, and therefore a timing difference is generated between the wobble synchronization signal and the encoder synchronization signal by the amount of the generated bit slip. .

  Therefore, when a timing difference occurs between the wobble synchronization signal and the encoder synchronization signal, the synchronization detection circuit 5 changes the frequency division condition setting value set in the recording clock generation circuit 4 according to this difference.

FIG. 7 is a timing chart of various signals used to explain the operation of the synchronization detection circuit 5 when a bit slip occurs in the optical disk drive shown in FIG.
In the example shown in the figure, a bit slip occurs between the second and third synchronization signals from the left, and a timing difference is generated between the third wobble synchronization signal and the encoder synchronization signal.

  In addition, because of the occurrence of bit slip, the phase of the recording clock is delayed with respect to the wobble signal, so that the wobble synchronization signal is generated at a timing earlier than the position where the encoder synchronization signal is generated.

  In such a case, the synchronization detection circuit 5 changes the dividing condition setting value in the direction of advancing the phase of the recording clock signal in order to correct the phase delay of the recording clock caused by the bit slip.

  When the control is performed as described above, in the recording clock generation circuit 4 shown in FIGS. 2 and 3, the division condition setting value is expressed as a binary counter type such as “0 → 1 → 2 → 3 → 0 → 1. By increasing the frequency to 1, the phase of the recording clock with respect to the wobble signal can be advanced by 0.25T.

Further, the synchronization detection circuit 5 changes the frequency division condition setting value until there is no timing difference between the wobble synchronization signal and the encoder synchronization signal.
As a result, the phase delay of the recording clock caused by the bit slip can be corrected.

  In this way, according to the recording clock generation circuit, even when the recording clock signal has a bit slip with respect to the wobble signal due to a lack of the wobble signal, the phase shift between the wobble signal and the recording clock is recovered. It is possible to restore the recorded data to a predetermined position.

Next, a recording clock generation circuit according to an embodiment of the present invention will be described.
FIG. 8 is a block diagram showing the configuration of the recording clock generation circuit according to the embodiment of the present invention, which is substantially the same as the configuration of the recording clock generation circuit shown in FIG. The place where the signal is input is different.

This recording clock generation circuit is also used as the recording clock generation circuit of the optical disc driving apparatus shown in FIG.
Further, in this case, the address information and the synchronizing signal are phase-modulated and superimposed on the wobble signal on the optical disc 1 which records data with the recording clock generated by the recording clock generation circuit.

FIG. 9 is an explanatory diagram illustrating a waveform example of a phase-modulated wobble signal.
In the optical disk drive of FIG. 1 using this recording clock generation circuit, the synchronization detection circuit 5 detects the synchronization signal superimposed on the wobble signal, and in the vicinity of the predetermined timing when the address information and the synchronization signal are phase-modulated, A phase comparison mask signal for masking phase difference detection is output to the phase comparator 41 shown in FIG.

FIG. 10 is an explanatory diagram showing an example of timing when the synchronization detection circuit 5 outputs a phase comparison mask signal.
As shown in the figure, a synchronization signal (wobble synchronization signal) superimposed on the wobble signal is detected, and a phase comparison mask signal is output in the detection period of the synchronization signal on the optical disc 1 and the address signal (address information detection signal). To do.

  In this way, according to the recording clock generation circuit, the operation of the phase comparator 41 is masked in a portion where a sudden change in the phase of the wobble signal is caused by the phase modulation, so that the phase between the wobble signal and the recording clock signal is A shift is eliminated, and a recording clock signal that is stably phase-synchronized with the wobble signal can be generated.

Next, a recording clock generation circuit of still another reference example of the present invention will be described.
FIG. 11 is a block diagram showing a configuration of a recording clock generation circuit according to still another reference example of the present invention. Components common to the recording clock generation circuit shown in FIGS. 2, 8, and 16 are denoted by the same reference numerals. Is attached.

  This recording clock generation circuit is also used as the recording clock generation circuit of the optical disc driving apparatus shown in FIG.

  In this recording clock generation circuit, the frequency comparator 401 divides the wobble signal by a predetermined ratio, counts the period of the divided wobble signal by the period of the recording clock signal, and determines the frequency difference according to the count value. A signal is output to the charge pump 402 and a switching signal is output to the multiplexer 403.

The charge pump 402 converts the frequency difference signal into a voltage signal.
The multiplexer 403 selects and outputs one of the outputs of the charge pump 42 and the charge pump 402 according to the switching signal from the frequency comparator 401.

12 is a block diagram showing an internal configuration of the frequency comparator 401 shown in FIG.
The counter 4011 of the frequency comparator 401 divides the wobble signal (WBL) by a predetermined ratio and outputs the divided wobble pulse to the counter 4012 and the register 4013, respectively.

The counter 4012 counts the number of divided clocks and is reset for each divided wobble pulse.
The register 4013 is loaded with the count value of the counter 4012 immediately before being reset for each divided wobble pulse.

  As a result, the register 4013 is loaded with a value obtained by counting the period of the divided wobble signal by the period of the recording clock signal, and the value is smaller in the divided clock frequency than the wobble signal frequency. Sometimes it is a small value, and when it is large, it is a large value, which is a value indicating the divided clock frequency with respect to the wobble signal frequency.

The data comparator 4014 outputs a Down signal when the value of the register 4013 is larger than a predetermined value, and outputs an Up signal when it is smaller.
The data comparator 4014 activates the switching signal (Mux) so as to select the output of the charge pump 42 when the value of the register 4013 is within a predetermined range, and when the value is outside the predetermined range, The switching signal (Mux) is made inactive so as to select the output of the charge pump 402.
The value in the predetermined range is selected so as to correspond to the capture range of the PLL circuit.

  As a result, when the relationship between the wobble signal frequency and the recording clock frequency is outside the capture range, the VCO 44 in FIG. 11 approaches the capture range according to the Up signal or the Down signal output from the frequency comparator 401. When it enters the capture range, it is driven according to the output of the phase comparator 41.

  In this way, according to the recording clock generation circuit, the PLL can be locked quickly even if the relationship between the wobble signal frequency and the recording clock frequency is outside the capture range.

Next, a recording clock generation circuit of still another reference example of the present invention will be described.
The recording clock generation circuit has the same configuration as that of the recording clock generation circuit shown in FIG. 11, but the internal configuration of the frequency comparator 401 is different from that described above. Then, it is used as a recording clock generation circuit of the optical disc driving apparatus shown in FIG.

FIG. 13 is a block diagram showing the internal configuration of the frequency comparator 401 of the recording clock generation circuit of still another reference example of the present invention.
The configuration of the frequency comparator 401 includes a counter 4011, a counter 4012, a register 4013, and a data comparator 4014 in the same manner as that shown in FIG. Further, a new counter 4015 and a flip-flop 4016 are provided.

The data comparator 4014 of the frequency comparator 401 activates the switching signal (Mux) when the register 4013 value is within a predetermined range.
The flip-flop 4016 is set when the switching signal (Mux) becomes active, and activates the switching signal (Mux ′) as its output.

  The data comparator 4014 inactivates the switching signal (Mux) when the value of the register 4013 is outside the predetermined range, but the switching signal (Mux ′) does not become inactive immediately.

When the switching signal (Mux) is inactive, the counter 4015 increases the count value for each divided wobble pulse.
Further, the counter 4015 resets the count value by the divided wobble pulse when the switching signal (Mux) is active.
When the count value reaches a predetermined value, a reset signal is output to the flip-flop 4016, and the switching signal (Mux ′) is made inactive.

  Thus, when it is continuously detected a predetermined number of times that the count value loaded into the register 4013 is outside the predetermined range, the switching signal (Mux ′) is made inactive.

  Therefore, it is possible to prevent the frequency comparator 401 from erroneously determining that the wobble signal frequency and the recording clock frequency are outside the capture range due to a lack of the wobble signal or the like, even though the relationship between the wobble signal frequency and the recording clock frequency is within the capture range. .

  Thus, according to the recording clock generation circuit, the PLL can be locked quickly even if the relationship between the wobble signal frequency and the recording clock frequency is outside the capture range, and the wobble signal can be output while the PLL is locked. It is possible to prevent an unnecessary pull-in operation from occurring due to a lack of the.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a configuration example of a reference example of the present invention and an optical disk drive device according to an embodiment of the present invention. FIG. 2 is a block diagram showing an internal configuration example of a recording clock generation circuit of a reference example of the present invention shown in FIG. 1. FIG. 3 is a diagram illustrating a more detailed configuration example of a frequency divider, a frequency division clock counter, and a frequency division ratio setting table illustrated in FIG. 2. FIG. 3 is a timing diagram of various signals for explaining the operation of the frequency divider shown in FIG. 2.

FIG. 3 is a diagram illustrating timings of a wobble signal, a recording clock signal, and a divided clock signal in a locked state in a steady state when the division condition setting value = 1 in the recording clock generation circuit illustrated in FIG. 2. FIG. 3 is a timing diagram of various signals for explaining control when the phase relationship between a wobble signal and a recording clock signal in the recording clock generation circuit shown in FIG. FIG. 3 is a timing chart of various signals used for explaining the operation of the synchronization detection circuit when a bit slip occurs in the optical disk drive shown in FIG. 1.

1 is a block diagram showing a configuration of a recording clock generation circuit according to an embodiment of the present invention. FIG. FIG. 2 is an explanatory diagram showing a waveform example of a phase-modulated wobble signal of the optical disc shown in FIG. 1. FIG. 3 is an explanatory diagram illustrating an example of timing when the synchronization detection circuit illustrated in FIG. 1 outputs a phase comparison mask signal. It is a block diagram which shows the structure of the recording clock generation circuit of the further another reference example of this invention. It is a block diagram which shows the internal structure of the frequency comparator shown in FIG.

It is a block diagram which shows the internal structure of the frequency comparator of the further another reference example of this invention. It is a block diagram which shows the structural example of the conventional optical disk drive device. 3 is an explanatory diagram showing an example of the structure of a wobbling data recording track on the optical disc 1. FIG. FIG. 15 is a block diagram illustrating a configuration example of a conventional recording clock generation circuit illustrated in FIG. 14.

Explanation of symbols

1: Optical disc 2: Optical pickup (PU) 3: Amplifier 4: Recording clock generation circuit 5: Synchronization detection circuit 6: Address decoder 7: Data decoder 8: Data encoder 9: LD driver 10: Spindle motor 11: Synchronization determination circuit 41 : Phase comparator 42, 402: Charge pump 43: Filter 44: VCO 45: Divider 46: Dividing clock counter 47: Dividing ratio setting table 451: A counter 452: B counter 453: Inverter 403, 454: Multiplexer 455: Synchronous SRFF 401: Frequency comparator 4011, 4012, 4015: Counter 4013: Register 4014: Data comparator 4016: Flip-flop

Claims (1)

Phase-synchronized with the wobble signal when recording data on an optical disc having a data recording track having a predetermined frequency component and wobbling with a wobble signal in which address information and a synchronization signal are superimposed by phase modulation at a predetermined timing An optical disc apparatus provided with a data recording clock signal generator for generating a recording clock signal,
The data recording clock signal generator includes a wobble signal extraction means for extracting the wobble signal,
A recording clock signal dividing means for generating a divided clock signal obtained by dividing the recording clock signal;
A phase difference signal generating means for comparing the phases of the wobble signal and the divided clock signal to generate a phase difference signal;
And frequency control signal generating means for generating a frequency control signal based on the phase difference signal generated by the phase difference signal generating means,
Recording clock signal generating means for generating the recording clock signal having a frequency controlled based on the frequency control signal generated by the frequency control signal generating means,
While detecting the synchronization signal superimposed on the wobble signal, the phase difference signal generating means generates a phase difference signal in a predetermined detection section where the address information on the optical disk and the synchronization signal are phase-modulated. A synchronization detection circuit to prevent
A data encoder that modulates recording data in synchronization with the recording clock signal and outputs an encoder synchronization signal at a predetermined timing;
A synchronization determination circuit that monitors the timing of the synchronization signal detected by the synchronization detection circuit and the encoder synchronization signal;
Means for adjusting the phase of the recording clock signal from the data recording clock signal generator so as to eliminate the difference when there is a difference in timing between the synchronization signal detected by the synchronization detection circuit and the encoder synchronization signal And an optical disc apparatus.

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