JP3903716B2 - Microcomputer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer, and particularly suitable for configuring an electronic control device that performs a predetermined operation when a binary signal to be monitored reaches a specific level that is one of a high level and a low level. Related to a microcomputer.
[0002]
[Prior art]
Conventionally, for example, in an electronic control device mounted on a vehicle, when the door of the vehicle is opened and the binary switch signal from the door switch reaches the level indicating “door open”, the lamp is turned on, When a binary operation request signal from another device reaches the level indicating “operation request”, communication with the device is started, and so on, the binary signal from the outside is high level and low level. Often, it is configured to perform a predetermined action when a certain level is reached. The binary signal is a binary amplitude signal that is either high level or low level.
[0003]
In order to realize the above function (that is, a function of performing a predetermined operation when a binary signal from the outside reaches a specific level, hereinafter referred to as a signal interlocking function). In addition, a microcomputer that controls the operation of the electronic control device (hereinafter referred to as a microcomputer) inputs the level of an external binary signal (hereinafter also referred to as a monitoring target signal) corresponding to the signal interlocking function to an input terminal (input). When the signal level is periodically read from the port) and it is detected that the signal level has reached a predetermined level, processing corresponding to a predetermined operation is performed.
[0004]
In addition, for example, in an electronic control device mounted on a vehicle, the signal interlocking function may have to be realized when the engine is stopped when the battery is not charged. For this reason, it is necessary to realize the signal interlocking function with less power consumption.
Therefore, the conventional electronic control apparatus employs the following [Conventional Example 1] or [Conventional Example 2] configuration and method in order to realize the above-described signal interlocking function with low power consumption (current consumption). .
[0005]
[Conventional example 1]
First, FIG. 6 is a block diagram showing the electronic control device of the first conventional example.
In the following description, the low active signal is a signal generated in a signal line pulled up to a power supply voltage corresponding to a high level by a resistor in the electronic control unit, and the signal line is connected via a switch or the like. It is a low active signal that becomes low level when connected to the ground potential. Conversely, a high active signal is a signal generated on a signal line that is pulled down to the ground potential by a resistor in the electronic control unit. When the signal line is connected to the power supply voltage via a switch or the like, the high active signal is high. It is a highly active signal that becomes level. And here, the monitoring target signal corresponding to the signal interlocking function is a low active signal, and when the signal becomes a low level, a predetermined operation is performed. Further, as shown in FIG. It is assumed that the signal is input to the input terminal (input port) B1 of the microcomputer 101 that controls the operation of the electronic control device via the signal line L1.
[0006]
As shown in FIG. 6, the electronic control device of Conventional Example 1 includes a CPU (that is, a central processing unit including an instruction decoding unit and a calculation unit) 103 that operates according to a program as a microcomputer that controls the operation of the device. In addition to the I / O port 105, a microcomputer 101 including a wake-up control unit 107 that performs control to wake up the CPU 103 from a stopped state to an operating state is used.
[0007]
In the microcomputer 101, a signal line L1 for the monitoring target signal is connected to an input terminal B1 assigned to input a monitoring target signal (a binary signal to be monitored). The signal line L1 is connected to a ground potential (= 0 V) corresponding to a low level when a switch in the vehicle is turned on.
[0008]
Furthermore, this electronic control device has one end connected to the signal line L1 and a pull-up resistor Ru for pulling up the signal line L1 to a power supply voltage Vd (5 V in this example) corresponding to a high level. And an energization circuit 109 that energizes the pull-up resistor Ru in accordance with an energization signal output from the output terminal (output port) A of the microcomputer 101.
[0009]
The energization circuit 109 includes an NPN transistor Tr1 that is turned on when the energization signal from the microcomputer 101 is at a high level, a current limiting resistor R1 that supplies the energization signal to the base of the NPN transistor Tr1, and a collector of the NPN transistor Tr1. Are connected in series between the resistor R2 and R3, the base is connected to the connection point between the resistors R2 and R3, the emitter is connected to the power supply voltage Vd, and the collector is the pull-up resistor Ru. The PNP transistor Tr2 is connected to the end opposite to the signal line L1.
[0010]
Therefore, in this energization circuit 109, when the energization signal from the microcomputer 101 becomes high level and the first stage NPN transistor Tr1 is turned on, the second stage PNP transistor Tr2 is turned on, and the pull-up resistor Ru is supplied with power. The voltage Vd is applied, and the pull-up resistor Ru is energized.
[0011]
In such an electronic control device of Conventional Example 1, as shown in FIG. 7, the microcomputer 101 operates intermittently, and at each operation, the microcomputer 101 operates at a high level from the output terminal A to the energizing circuit 109 as described later. A signal reading process with an energizing signal output control function is performed while the energization signal is output, and the level of the monitoring target signal is read from the input terminal B1, and the level read by the process is twice the previous value and the current value. Only when the values are continuously the same, the noise value filtering process is performed such that the current value is updated and stored as the determination level of the monitoring target signal (that is, the level determined to be true). . Then, as shown at time t1 in FIG. 7, the microcomputer 101 detects that the monitoring target signal has reached a specific level (in this example, low level) based on the result of the filtering process (specifically, the filtering process). When it is determined that the determination level of the monitoring target signal has reached a specific level), the operation is continued and processing corresponding to the predetermined operation is performed. In FIG. 7, “with signal” means that the monitored signal is at a specific level indicating that a predetermined operation should be performed, and “without signal” means This means that the monitoring target signal is not at the specific level. This also applies to other drawings described later.
[0012]
Specifically, the signal reading process with the energization signal output control function first outputs a high level energization signal from the output terminal A as shown in () in FIG. The NPN transistor Tr1 is turned on, and when a preset signal read timing time Tm has elapsed since that time, the level of the input terminal B1 is read, and then the output of the energization signal is stopped (the output terminal A of This is a process of a procedure of turning off the NPN transistor Tr1 by returning the output level to a low level. The signal read timing time Tm is electrically stable after a high level energization signal is output in consideration of the capacity of the signal line L1 and the operation delay of the energization circuit 109. It is set to a value longer than the delay time until.
[0013]
That is, if the power supply voltage Vd is always applied to the pull-up resistor Ru, the current flowing through the pull-up resistor Ru becomes one of the causes for increasing the power consumption of the electronic control device. Therefore, only when the signal level is read from the input terminal B1, the energization to the pull-up resistor Ru (specifically, the application of the power supply voltage Vd to the pull-up resistor Ru) is performed, thereby reducing unnecessary power consumption. To do.
[0014]
In the microcomputer 101, the CPU 103 executes a predetermined operation stop instruction to stop its own operation (that is, the program execution operation that is the original operation of the microcomputer) and issues an operation request to the wake-up control unit 107. Then, the wake-up control unit 107 starts counting the timer time set in advance by the CPU 101, and when the timer time has elapsed, the CPU 103 wakes up from the stop state to the operating state.
[0015]
Therefore, in the electronic control device of Conventional Example 1, when the CPU 103 determines that it is not necessary to operate, the CPU 103 stops its own operation and issues an operation request to the wake-up control unit 107. Thereafter, the wake-up control unit The signal reading process with the energization signal output control function and the filter process are executed each time the signal is raised from the stop state to the operation state by 107, and the monitoring target signal is not at a specific level based on the result of the filter process. If it is determined that it is not necessary to operate, it stops its own operation again and issues an operation request to the wake-up control unit 107. Conversely, if the monitoring target signal is at a specific level If the determination is made, the program of the microcomputer 101 (that is, the program executed by the CPU 103) is performed so that the operation state is continued and necessary processing is performed. Beam) is set.
[0016]
That is, if the setting is made in this way, and the state where the monitoring target signal is not at a specific level continues, the CPU 103 stops the operation and then measures the time as shown in FIG. When the timer time Ti ("intermittent operation interval Ti" in FIG. 7) elapses, the operation temporarily stops and the operation is stopped again for the timer time Ti. The intermittent operation is repeated. When the monitoring target signal becomes a specific level and the CPU 103 detects this, the operation is continued as it is and processing necessary for a predetermined operation is performed.
[0017]
According to the electronic control device of the conventional example 1, since the CPU 103 having a particularly large power consumption among the constituent elements of the microcomputer is operated not intermittently but intermittently. Electric power can be suppressed to a low level, and thus power consumption in the entire electronic control apparatus can be suppressed.
[0018]
On the other hand, when the monitoring target signal is not a low active signal but a high active signal, as shown in FIG. 6, the signal line L2 that propagates the high active signal is grounded by a pull-down resistor Rd in the electronic control unit. It will be pulled down to the potential.
[0019]
The pulled-down signal line L2 is connected to one of the input terminals (in this example, the input terminal B2) of the microcomputer 101 through, for example, an input protection resistor R4. In this case, The energization circuit 109 is deleted, and the CPU 103 of the microcomputer 101 does not perform the energization signal output control described above as a process for reading the level of the monitoring target signal from the input terminal B2 (that is, the energization signal should not be output). However, it simply reads the signal level at the input terminal B2. Others are the same as when the monitoring target signal is a low active signal.
[0020]
That is, in the case of a high active signal, the power source for setting the signal to a high level exists outside the electronic control device, and the current flowing through the pull-down resistor Rd does not directly increase the power consumption of the electronic control device. Because.
Further, when there are a plurality of monitoring target signals and a low active signal and a high active signal are mixed as the monitoring target signals, signal reading processing corresponding to each signal is performed in parallel. It will be.
[0021]
[Conventional example 2]
Next, FIG. 8 is a block diagram showing an electronic control device of Conventional Example 2. In FIG. 8, the same components as those in FIG. 6 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0022]
In the electronic control device of FIG. 8, a microcomputer 201 having a variable operation speed is used as a microcomputer for controlling the operation of the electronic control device. That is, in addition to the CPU 103 and the I / O port 105, the microcomputer 201 includes a frequency control circuit 203 that generates a clock having a frequency specified by the CPU 103 and outputs the clock as an operation clock of the CPU 103.
[0023]
In the microcomputer 201, during normal operation of executing the program, the CPU 103 sets the frequency of the operation clock output from the frequency control circuit 203 to a normal high frequency (for example, several tens of MHz), and at high speed. If it is determined that normal operation is no longer necessary, the frequency of the operation clock output from the frequency control circuit 203 is set to a frequency lower than normal (for example, several MHz), and the power consumption is low. It becomes a state.
[0024]
Then, as shown in FIG. 9, the CPU 103 reads the level of the monitoring target signal from the input terminal every fixed time Tk (“signal reading interval Tk” in FIG. 9) while operating at a low speed. When the above filtering process is executed and it is determined that the monitoring target signal has reached a specific level based on the result of the filtering process as shown at time t2 in FIG. 9, the operation speed is returned from the low speed to the high speed, The process corresponding to the operation is performed.
[0025]
In such an electronic control device of Conventional Example 2, the power consumption can be reduced by the amount of time during which the CPU 103 of the microcomputer 201 operates at a lower speed than normal.
In the conventional example 2, as in the conventional example 1, when the monitoring target signal is a low active signal, the above-described energization circuit 109 is provided as shown in FIG. As shown in () of FIG. 9, the signal reading process with the energization signal output control function described above is executed as a process for reading the level of the monitoring target signal.
[0026]
[Problems to be solved by the invention]
However, in the conventional examples 1 and 2, since the CPU 103 of the microcomputer operates, it is difficult to realize a significant reduction in power consumption.
In particular, in the first conventional example, the CPU 103 must be woken up and read the signal level every short time (for example, every several tens of ms) so that the detection delay of the monitoring target signal does not become a problem. There is a limit to the reduction, and in Conventional Example 2, although the CPU 103 operates at a low speed, the effect of reducing power consumption is still small.
[0027]
Further, in the above-described conventional examples 1 and 2, a software process is required for reading a signal at regular intervals, and if the above-described filter process for noise suppression and the signal reading process with the energization signal output control function are performed. Further, the processing load increases.
The present invention has been made in view of such problems, and has a signal interlocking function of performing a predetermined operation when a monitoring target signal becomes a specific level which is one of a high level and a low level. An object of the present invention is to provide a microcomputer suitable for realizing low power consumption.
[0028]
[Means for Solving the Problems and Effects of the Invention]
In the microcomputer according to claim 1, which is made to achieve the above object, the operation can be stopped by the CPU executing a predetermined instruction, as in the microcomputer 101 of the first conventional example. In particular, this microcomputer is provided with automatic signal reading means. The automatic signal reading means inputs the level of a binary signal to be monitored (hereinafter referred to as a monitoring target signal) supplied to a predetermined input terminal of the microcomputer when the CPU stops operating. The determination is made by reading from the terminal at regular intervals, and when the determination level reaches a specific level, the CPU is woken up from the stopped state to the operating state. In addition, about this point, Claim 2 mentioned later is mentioned. , 3 The same applies to each microcomputer.
[0029]
Therefore, according to the present microcomputer, it is possible to detect that the monitoring target signal has reached a specific level while stopping the operation of the CPU having particularly high power consumption. The signal interlocking function of performing the above operation can be realized with much less power consumption than in the past.
[0030]
In other words, if the CPU determines that it is not necessary to operate, it stops its own operation, and then, if it is caused to enter the operating state by the automatic signal reading means, the processing corresponding to the predetermined operation is executed. This is because, by setting the program such as, the signal operation function can be realized by reducing the operation period of the CPU to the minimum.
[0031]
Further, since the automatic signal reading means is configured to read the level of the monitoring target signal at regular intervals, the processing load on the CPU can be reduced and the noise resistance is also excellent. In other words, even if noise is superimposed on the monitoring target signal to the input terminal, false detection will not occur unless noise is generated in synchronization with the timing of reading the signal level from the input terminal (so-called sampling timing). is there.
As described in claim 5, The automatic signal reading means is configured such that the predetermined time is set by the CPU (in other words, by a program). If The interval for reading the level of the monitoring target signal from the input terminal can be arbitrarily set, and versatility can be improved.
[0032]
By the way, the automatic signal reading means is configured such that the level read from the input terminal is directly used as the judgment level of the monitoring target signal (that is, the level of the monitoring target signal judged by the automatic signal reading means). You may ,in front Only when the level read from the input terminal is continuously the same for a plurality of predetermined times, the filter processing such as updating the judgment level of the monitoring target signal to the level read this time is performed. For example, the noise resistance can be further improved without increasing the CPU processing load.
[0033]
However, when such a filtering process is performed, the delay time from when the monitoring target signal actually changes to a specific level until it is detected becomes large.
Therefore, the claim 1 In the microcomputer, the automatic signal reading means reads the operation mode M1 for performing the filtering process according to a command from the CPU (in other words, by a program), and reads from the input terminal without performing the filtering process. It is configured to be switchable to the operation mode M2 in which the level is directly used as the judgment level of the monitoring target signal.
[0034]
Such claims 1 According to the microcomputer, when the noise resistance is prioritized, the operation mode M1 is set. When the detection speed (detection sensitivity) is prioritized, the operation mode M2 is set. It is done.
[0036]
Next, the claim 2 In the microcomputer, the automatic signal reading means applies a voltage to a pull-up resistor that pulls up a signal line that supplies the monitoring target signal to the input terminal before reading the level of the monitoring target signal from the input terminal. An energization signal output control is performed in which an energization signal is output from a predetermined output terminal of the microcomputer and the output of the energization signal is stopped when the level of the monitoring target signal is read from the input terminal.
[0037]
This claim 2 According to the microcomputer, when the monitoring target signal is a low active signal and the signal line of the monitoring target signal is pulled up outside the microcomputer, the signal reading process with the energization signal output control function described above is performed. It can be carried out. Only when the signal level is read from the input terminal, voltage is applied to the pull-up resistor (and energized to the pull-up resistor), and wasteful power consumption can be reduced as much as possible. become.
[0038]
And further claims 2 In this microcomputer, the automatic signal reading means waits until the level of the monitoring target signal is read after the energization signal is output (that is, the signal reading timing time Tm in FIGS. 7 and 9 described above). Is configured to be set by a CPU (in other words, by a program).
[0039]
This claim 2 According to the microcomputer, when the signal reading process with the energization signal output control function is performed, the waiting time is appropriately set according to the electrical characteristics of the signal line of the monitoring target signal and the peripheral circuit of the microcomputer. High versatility can be obtained.
[0040]
by the way , Supervisor When the target signal is a high active signal, or when the target signal is a low active signal, but there is no problem even if a voltage is always applied to the pull-up resistor of the signal line, the energization signal output If signal reading processing with a control function is not required, the output terminal for outputting the energization signal may not be actually used. However, in that case, one output terminal is wasted.
[0041]
Therefore, the claim 3 In the microcomputer, the automatic signal reading means is responsive to a command from the CPU (in other words, by a program) in an operation mode in which the energization signal output control is performed and an operation mode in which the energization signal output control is not performed. It is configured to be configurable.
Such claims 3 According to the microcomputer, when the signal reading process with the energization signal output control function is not required, the automatic signal reading means is set so as not to perform the energization signal output control, so that the output terminal is set to other It becomes possible to use it for a use.
[0042]
Next, in the microcomputer of claim 4, In the microcomputer of Claims 1-3, The input terminal from which the automatic signal reading means reads the signal level is set by the CPU (in other words, by the program) to one of a plurality of terminals of the microcomputer. According to this microcomputer, the input terminal for the monitoring target signal can be arbitrarily selected from a plurality of terminals, which is convenient. Furthermore, the microcomputer according to claims 2 and 3 is more convenient if the output terminal for outputting the energization signal described above can be arbitrarily selected from a plurality of terminals.
On the other hand, in the microcomputer according to any one of claims 1 to 5, as described in claim 6, the automatic signal reading means has the specific level (that is, the level of the monitoring target signal for waking up the CPU) determined by the CPU (in other words, If it is configured to be set (by a program), a predetermined operation is performed when the monitoring target signal becomes low level, and a predetermined operation is performed when the monitoring target signal becomes high level It becomes possible to cope with both the case of high active and the versatility can be improved.
[0043]
Next, the claim 7 The microcomputer of claim 1 to claim 1. 6 The microcomputer is provided with timer wake-up control means. Then, the timer wake-up control means, upon receiving an operation request from the CPU, similarly to the wake-up control unit 107 incorporated in the microcomputer 101 of the conventional example 1 described above, the time set by the CPU (timer time). ) Is started, and when the time has elapsed, the CPU is woken up from the stopped state to the operating state.
[0044]
For this reason, the claim 7 In the microcomputer, as in the conventional microcomputer 101, the CPU sets the timer time counted by the timer wake-up control means in advance and operates the timer wake-up control means when stopping its own operation. When a request is issued and the timer wake-up control means is put into an operation state, the necessary processing is executed, and when the processing is completed, the operation is stopped again and an operation request is issued to the timer wake-up control means. If the program is set to perform, the CPU wakes up when the timer time elapses after stopping the operation, and then stops the operation again for the timer time. It becomes possible to perform intermittent operation that repeats (operation stop).
[0045]
This claim 7 According to the microcomputer, the timer time is set to a time longer than the interval at which the automatic signal reading means reads the level of the monitoring target signal (the fixed time), and the timer wakes up every time the CPU stops the operation. If an operation request is issued to the control means, even if the signal to be monitored does not change to a specific level due to disconnection of the signal line, even if the CPU is not caused by the action of the automatic signal reading means, By the action of the timer wake-up control means, the CPU can be woken up periodically (every timer time), and the reliability and stability of the operation can be improved. For example, every time the CPU wakes up from a stopped state, if the processing of checking and repairing the internal data of the microcomputer is performed, it is possible to reliably prevent the operation of the microcomputer from becoming unstable. be able to.
[0046]
In this case, even when the monitoring target signal does not really change to a specific level, the CPU operates periodically by the action of the timer wake-up control means, but the wake-up interval is monitored from the input terminal. Since the level of the target signal can be set much longer than the time interval at which the level of the target signal must be read, the signal interlocking function can be realized with much less power consumption than in the past.
[0047]
Next, the claim 8 In the microcomputer of claim 1 to claim 1 7 In the microcomputer, the automatic signal reading means is provided with a read result storage unit which can read the stored contents by the CPU. The reading result storage unit stores the judgment level of the monitoring target signal by the automatic signal reading means.
[0048]
Such claims 8 According to the microcomputer, when the CPU wakes up from the stop state to the operation state, the CPU reads the storage contents of the read result storage unit, and the reason for the wakeup this time is due to the change of the monitoring target signal to a specific level. It becomes possible to confirm whether or not. Therefore, the certainty and reliability of processing can be improved. In particular, the claims 7 When a means for waking up the CPU is provided in addition to the automatic signal reading means as in the microcomputer, it is possible to identify the cause of the CPU waking up, which is very advantageous.
[0049]
Next, the claim 9 In the microcomputer of the above, 8 In the microcomputer, the automatic signal reading means is configured to be operable even when the CPU is operating in accordance with a command from the CPU (in other words, by a program).
Such claims 9 According to this microcomputer, it is possible to reduce the processing load that the CPU must execute in order to grasp the level of the monitoring target signal during normal operation. That is, the CPU can read the judgment level of the monitoring target signal by the automatic signal reading means at any timing from the reading result storage unit by operating the automatic signal reading means even during the normal operation in which the CPU is operating. Because it is good.
[0050]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an electronic control device according to an embodiment to which the present invention is applied will be described with reference to the drawings.
First, FIG. 1 is a configuration diagram illustrating the configuration of an electronic control device 1 according to an embodiment and a single chip microcomputer 2 mounted thereon. In FIG. 1, the same components as those in FIG. 6 described above are denoted by the same reference numerals, and detailed description thereof is omitted. In addition, the electronic control device 1 according to the present embodiment, when a low active signal as a monitoring target signal supplied via the signal line L1 becomes a low level as a specific level, a predetermined operation (for example, Lamps, etc.).
[0051]
As shown in FIG. 1, the electronic control device 1 of the present embodiment is equipped with a single chip microcomputer 2 that controls the operation of the device 1, and the signal line L1 is connected to the input terminal B1 of the microcomputer 2. Has been.
Further, in the electronic control device 1 of the present embodiment, one end is connected to the signal line L1 and the signal line L1 corresponds to the high level, similarly to the electronic control device of Conventional Example 1 (FIG. 6). While the pull-up resistor Ru for pulling up to the power supply voltage Vd (= 5V) and the high-level energization signal is output from the output terminal A of the microcomputer 2, the energization to the pull-up resistor Ru (specifically, the power supply) An energization circuit 109 that performs application of the voltage Vd) is provided.
[0052]
Next, the microcomputer 2 includes, as basic components, a CPU 3 that operates according to a program, a ROM 5 that stores programs and fixed data in advance, a RAM 6 that temporarily stores the calculation results by the CPU 3, and the microcomputer 2 An I / O port 7 for inputting / outputting signals from / to the outside via a terminal is provided.
[0053]
Further, the microcomputer 2 cooperates with the oscillation element 8 provided outside the microcomputer 2 to generate a main clock (several MHz to several tens of MHz in the present embodiment) that is an operation clock of the CPU 3, and Main clock generator 13 comprising an oscillation controller 11 for controlling the main oscillation circuit 9 and intermittent operation for controlling the CPU 3 to operate intermittently (intermittent operation) in cooperation with the oscillation controller 11. An operation control unit 15, an automatic reading circuit 17 that operates in response to a command from the CPU 3 and reads a signal level from a terminal of the microcomputer 2 via the I / O port 7 at regular intervals; In cooperation with the oscillation element 18 provided outside the microcomputer 2, a sub clock (several tens KHz in this embodiment) having a frequency lower than that of the main clock is generated. And a blanking oscillation circuit 19.
[0054]
In the microcomputer 2 of the present embodiment, each of the oscillation control unit 11, the intermittent operation control unit 15, and the automatic reading circuit 17 operates by receiving a subclock that is constantly generated by the sub oscillation circuit 19.
In the present embodiment, the automatic reading circuit 17 corresponds to an automatic signal reading unit, and the oscillation control unit 11 and the intermittent operation control unit 15 correspond to a timer wakeup control unit.
[0055]
Here, the CPU 3 can stop its own operation by executing a specific operation stop command in the same manner as the CPU 103 of the conventional example 1 described above. The CPU 3 issues an operation request to the intermittent operation control unit 15 when the operation is stopped by itself (that is, when the operation stop command is executed).
[0056]
On the other hand, the intermittent operation control unit 15 includes a register 15a in which a time to be measured (timer time) is set (written) by the CPU 3.
The intermittent operation control unit 15 normally gives an operation instruction to the oscillation control unit 11 of the main clock generation unit 13 to cause the oscillation control unit 11 to operate the main oscillation circuit 9. When an operation request is received (that is, when the CPU 3 stops operation), a stop instruction is output to the oscillation control unit 11 to stop the operation of the main oscillation circuit 9 from the oscillation control unit 11, and the CPU 3 performs the above operation in advance. The timer time set in the register 15a is started to be counted. When the timer time has elapsed, an operation instruction is output to the oscillation control unit 11 again, and the oscillation control unit 11 resumes the operation of the main oscillation circuit 9. .
[0057]
Further, when the intermittent operation control unit 15 receives the operation request from the CPU 3 and outputs a stop instruction to the oscillation control unit 11, the intermittent operation control unit 15 sends a stop notification signal indicating that the operation of the CPU 3 has stopped to the automatic reading circuit 17. Output. In the present embodiment, the stop notification signal is a one-shot pulse signal having an extremely short pulse width.
[0058]
The oscillation control unit 11 of the main clock generation unit 13 switches between operation and non-operation of the main oscillation circuit 9 according to the operation instruction and stop instruction from the intermittent operation control unit 15. When the operation of the main oscillation circuit 9 is started in response to an operation instruction from the control unit 15, when a predetermined oscillation stabilization wait time that is considered that the frequency of the main clock is stabilized from that time point, A RUN signal for raising the CPU 3 from the stopped state to the operating state is output.
[0059]
The oscillation stabilization wait time is provided to wake up the CPU 3 after the main clock frequency is reliably stabilized, and is counted based on the number of sub-clocks. The oscillation control unit 11 includes a register 11a in which the oscillation stabilization waiting time is set (written) by the CPU 3. In the present embodiment, the oscillation control unit 11 uses the RUN signal until the next stop instruction is received from the intermittent operation control unit 15 (that is, the operation of the CPU 3 stops and the operation of the main oscillation circuit 9 is performed next). It will continue to output until it is stopped. The RUN signal is also supplied to the automatic reading circuit 17, and the automatic reading circuit 17 detects whether the CPU 3 is in an operating state based on the RUN signal.
[0060]
In the microcomputer 2 including the oscillation control unit 11 and the intermittent operation control unit 15, the CPU 3 sets a timer time in advance in the register 15 a of the intermittent operation control unit 15 and there is no processing to be executed. If it is determined that the operation can be stopped, the above-described operation stop command is executed, the operation is stopped, and an operation request is output to the intermittent operation control unit 15. The intermittent operation of the CPU 3 as shown in the lower part (operation that periodically repeats the operation and the non-operation) is realized.
[0061]
That is, when the CPU 3 determines that the operation may be stopped and stops its own operation and outputs an operation request to the intermittent operation control unit 15, the intermittent operation control unit 15 instructs the oscillation control unit 11 to stop. Is output to stop the operation of the main oscillation circuit 9 and the timer time set in the register 15a is started. When the timer time elapses, an operation instruction is output again to the oscillation control unit 11 to The operation of the oscillation circuit 9 is resumed. Then, when the above-described oscillation stabilization wait time elapses from that point, the RUN signal is output from the oscillation control unit 11 to the CPU 3 and the CPU 3 wakes up from the stop state to the operation state. By being repeated, the intermittent operation of the CPU 3 is performed.
[0062]
On the other hand, in the microcomputer 2 of the present embodiment, when the intermittent operation control unit 15 receives an operation request from the CPU 3 and outputs a stop instruction to the oscillation control unit 11, the value of the timer time set in the register 15a. Is 0, the operation of the main oscillation circuit 9 is stopped until the wake-up request described later is output from the automatic reading circuit 17, and when the wake-up request is output from the automatic reading circuit 17, An operation instruction is output to the oscillation control unit 11 to cause the oscillation control unit 11 to resume operations of the main oscillation circuit 9 and the CPU 3. Therefore, in the microcomputer 2 of the present embodiment, if the program is set so that 0 is set in the register 15a, the CPU 3 remains in a stopped state until a wake-up request is output from the automatic reading circuit 17. You can also.
[0063]
Further, the intermittent operation control unit 15 automatically reads while the timer time set in the register 15a is being measured (that is, until the timer time elapses after the CPU 3 stops operating). Even when a wake-up request is output from the circuit 17, an operation instruction is output to the oscillation control unit 11 to cause the oscillation control unit 11 to resume operations of the main oscillation circuit 9 and the CPU 3.
[0064]
Next, the automatic reading circuit 17 will be described.
As shown in FIG. 2, the automatic reading circuit 17 indicates a reading result storage unit 17 a whose stored contents can be read by the CPU 3, and a terminal from which the circuit 17 should read a signal level among a plurality of input terminals of the microcomputer 2. A storage unit 17b in which the read terminal command information is written by the CPU 3 and a storage unit 17c in which the signal read interval (that is, the time interval for reading the signal level at the above-mentioned fixed time) Tk is written. Basically, the signal level of a terminal (hereinafter referred to as a read target terminal) corresponding to the read terminal command information written in the storage unit 17b is read at every predetermined time Tk written in the storage unit 17c. The determined level (hereinafter referred to as a determination level) is updated and stored in the read result storage unit 17a.
[0065]
Further, the automatic reading circuit 17 is also provided with other storage units 17d to 17h in which various information for determining more detailed operation contents of the circuit 17 is written by the CPU 3.
That is, as shown in FIG. 2, the automatic reading circuit 17 operates when the operation mode of the circuit 17 is stopped by the CPU 3, and the determination level of the signal at the reading target terminal is set to a specific level. Then, the CPU 3 writes 1-bit mode command information to be set to either the wake-up operation mode for waking up the CPU 3 or the free-run operation mode that operates in parallel with the CPU 3 when the CPU 3 is operating. A storage unit 17d and a storage unit 17e in which the specific level (that is, an input level for waking up the CPU 3 in the wake-up operation mode) is written by the CPU 3 are provided.
[0066]
When the mode command information in the storage unit 17d is a value indicating the wake-up operation mode (that is, when the operation mode is set to the wake-up operation mode by the CPU 3), the automatic reading circuit 17 When the stop signal is output from the intermittent operation control unit 15, the operation is started, and the signal level of the read target terminal is read and determined every certain time Tk written in the storage unit 17 c. At the same time, the determination level is updated and stored in the read result storage unit 17a. When the determination level matches the input level (specific level) of the storage unit 17e, the above-described wake-up request is output to the intermittent operation control unit 15. Then, the operation of the main oscillation circuit 9 is resumed and the CPU 3 is woken up from the stopped state to the operating state. Further, in this wake-up operation mode, when the above-described RUN signal is output from the oscillation control unit 11, the automatic reading circuit 17 determines that the CPU 3 has resumed operation and stops its own operation.
[0067]
The automatic reading circuit 17 includes the storage unit 17. d When the mode command information is a value indicating the free-run operation mode (that is, when the operation mode is set to the free-run operation mode by the CPU 3), the operation is performed according to the operation command from the CPU 3, Perform basic operations. That is, the signal level of the read target terminal is read and determined every fixed time Tk written in the storage unit 17c, and the determination level is updated and stored in the read result storage unit 17a.
[0068]
Further, the automatic reading circuit 17 includes a storage unit 17f in which 1-bit filter processing command information for setting the presence / absence of the filter processing function is written by the CPU 3, and a 1-bit for setting the presence / absence of the energization signal output control function. The storage unit 17g in which the energization signal output control command information is written by the CPU 3, and the signal read timing time Tm when energization signal output control is performed (claim) 2 And a storage unit 17h written by the CPU 3.
[0069]
Then, the automatic reading circuit 17 determines whether the filter command information in the storage unit 17f is a value indicating the presence of the filter processing function (that is, the filter is executed by the CPU 3 in both the wake-up operation mode and the free-run operation mode). When the operation mode is set to execute the process), the read result is obtained only when the level read from the read target terminal is the same continuously for a plurality of predetermined times (in this embodiment, twice). Filter processing for noise countermeasures is performed in which the determination level of the read target signal stored in the storage unit 17a is updated to the level read this time. Conversely, when the filter command information in the storage unit 17f is a value indicating that there is no filter processing function (that is, when the CPU 3 is set to an operation mode in which no filter processing is performed), the information is read from the read target terminal. The level is stored as it is in the reading result storage unit 17a as the determination level of the signal to be read.
[0070]
Furthermore, the automatic reading circuit 17 is set to an operation mode in which the energization signal output control command information in the storage unit 17g is a value indicating that the energization signal output control function is present (that is, the CPU 3 performs the energization signal output control). When the signal level is read from the read target terminal, the high level is output from the output terminal A of the microcomputer 2 at a timing before the signal read timing time Tm written in the storage unit 17h. The energization signal output control is performed such that the output of the energization signal is stopped when the signal level is read from the read target terminal. Therefore, in this case, the automatic reading circuit 17 outputs a high level energization signal from the output terminal A to turn on the NPN transistor Tr1 of the energization circuit 109 as shown in () in FIG. A signal with an energization signal output control function that reads the signal level from the read target terminal when the signal read timing time Tm of the storage unit 17h elapses, and then stops the output of the energization signal and turns off the NPN transistor Tr1. The reading process is performed every fixed time Tk.
[0071]
On the contrary, the automatic reading circuit 17 sets the operation mode in which the energization signal output control function is not performed by the CPU 3 when the energization signal output control command information in the storage unit 17g is a value indicating that there is no energization signal output control function. In such a case, the energization signal output control as described above is not performed, and the output terminal A is opened under the management of the circuit 17 so that it can be used for other purposes.
[0072]
Here, in the present embodiment, read terminal command information indicating the input terminal B1 of the microcomputer 2 is written in the storage unit 17b of the automatic read circuit 17. As described above, in the electronic control device 1 of the present embodiment, the signal line L1 of the monitoring target signal corresponding to the signal interlocking function is connected to the input terminal B1 of the microcomputer 2, and the input terminal B1 is connected to the input terminal B1. This is to make it a signal reading target terminal.
[0073]
A value indicating the wake-up operation mode is written as mode command information in the storage unit 17d, and a low level is written as a specific level for waking up the CPU 3 in the storage unit 17e. . This is because, as described above, in the electronic control device 1 of the present embodiment, when the monitoring target signal supplied via the signal line L1 becomes low level, it is necessary to perform a predetermined operation that is determined in advance. It is.
[0074]
Further, for example, 50 ms is written as a signal reading interval in the storage unit 17c, and a value indicating the presence of a filter processing function is written as filter processing command information in the storage unit 17f.
Further, a value indicating that the energization signal output control function is present is written in the storage unit 17g as the energization signal output control command information. As described above, in the electronic control device 1 of the present embodiment, the monitoring target signal supplied through the signal line L1 is a low active signal, and the pull-up resistor Ru that pulls up the signal line L1 is used. This is to reduce the power consumption of the as much as possible. Further, a value slightly longer than the delay time from when the high-level energization signal is output from the microcomputer 2 until the state of the signal line L1 is electrically stabilized is written in the storage unit 17h as the signal read timing time Tm. It is.
[0075]
In such a microcomputer 2 of this embodiment, the CPU 3 determines that it is not necessary to operate at least when the monitoring target signal supplied via the signal line L1 is not at a low level, Stop operation.
When the CPU 3 stops operating, as shown in FIG. 3, the automatic reading circuit 17 uses the input terminal B1 as a signal reading target terminal and performs signal reading processing with the above-mentioned energization signal output control function at regular time intervals Tk. And the above filter processing.
[0076]
After that, when the signal line L1 is connected to the ground potential via a switch or the like and becomes a “signal present” state as shown in FIG. 3, a signal reading process and a filtering process with an energization signal output control function are performed from that point. Is performed twice at time ta, the judgment level of the signal to be monitored by the filter processing in the automatic reading circuit 17 (that is, the level in the reading result storage unit 17a) becomes a low level, and the automatic reading circuit 17 operates intermittently. A wake-up request is output to the control unit 15 to restart the operation of the main oscillation circuit 9 and to wake up the CPU 3 to an operating state.
[0077]
When the operation is resumed, the CPU 3 reads the judgment level of the monitoring target signal from the reading result storage unit 17a of the automatic reading circuit 17, and if the read level is a low level, the reason for getting up this time is the low level of the monitoring target signal. It is determined that the change is due to a change in level, and a control process for executing a predetermined operation (for example, lighting of a lamp) determined in advance in relation to the monitoring target signal is executed.
[0078]
According to the microcomputer 2 of the present embodiment as described above, it is detected that the monitoring target signal has become a low level as a specific level while the CPU 3 and the main oscillation circuit 9 with particularly large power consumption are stopped. The signal interlocking function of performing a predetermined operation when the monitoring target signal reaches a specific level can be realized with much less power consumption than in the past.
[0079]
Further, since the automatic reading circuit 17 performs the filtering process, it can improve the noise resistance without increasing the processing load on the CPU 3 at all.
In addition, when giving priority to the sensitivity of detecting that the monitoring target signal has reached a specific level rather than noise resistance, a value indicating no filtering function is written in the storage unit 17f of the automatic reading circuit 17, The automatic reading circuit 17 may be set so as not to perform the filter processing.
[0080]
Further, the microcomputer 2 of this embodiment includes an intermittent operation control unit 15 and an oscillation control unit 11 as timer wake-up control means. As described above, the CPU 3 is connected to the register 15a of the intermittent operation control unit 15. It can be operated intermittently at the set timer time interval.
[0081]
Therefore, if a timer time longer than the interval at which the automatic reading circuit 17 reads the level of the monitoring target signal (that is, the signal reading interval to be written to the storage unit 17c) is set in the register 15a, as illustrated in FIG. In addition, even if the monitoring target signal does not reach a specific level and the situation continues for a long time and the CPU 3 is not caused by the action of the automatic reading circuit 17, the action of the intermittent operation control unit 15 and the oscillation control unit 11 causes the CPU 3 Can be generated at each timer time, and as a result, the reliability and stability of the operation can be improved. In other words, every time the CPU 3 wakes up from a stopped state, if the internal data of the microcomputer 2 is checked and repaired or initialized, the operation of the microcomputer 2 becomes unstable. It is because it can prevent reliably.
[0082]
Further, in the microcomputer 2 of the present embodiment, the automatic reading circuit 17 can be set to a free-run operation mode that operates in parallel with the CPU 3 by mode command information written in the storage unit 17d.
For this reason, it is possible to reduce the processing load that the CPU 3 has to execute in order to grasp the level of the monitoring target signal during the normal operation.
[0083]
That is, as shown in FIG. 5, the CPU 3 sets the operation mode of the automatic reading circuit 17 to the free-run operation mode and gives an operation command to the automatic reading circuit 17 during the normal operation in which the CPU 3 is operating. This is because the above-mentioned basic operation is performed by the automatic reading circuit 17 and the judgment level of the monitoring target signal by the automatic reading circuit 17 may be read from the reading result storage unit 17a at an arbitrary timing.
[0084]
On the other hand, the automatic reading circuit 17 can arbitrarily select a terminal for reading a signal level (reading target terminal) by a reading terminal command information to be written in the storage unit 17b, and a monitoring target signal for causing the CPU 3 to wake up. The input level can be set to either the high level or the low level depending on the level written in the storage unit 17e. Further, the automatic reading circuit 17 can arbitrarily set whether or not to perform the energization signal output control by the energization signal output control command information written in the storage unit 17g.
[0085]
Thus, for example, in FIG. 1, a high active signal generated on the signal line L2 connected to the input terminal B2 of the microcomputer 2 is a monitoring target signal, and when the signal changes from low level to high level, a predetermined predetermined operation is performed. Is to be written, the read terminal command information indicating the input terminal B2 is written in the storage unit 17b, and the high level is written in the storage unit 17e as a specific level for waking up the CPU 3. In the storage unit 17g, a value indicating no energization signal output control function may be written as the energization signal output control command information.
[0086]
Further, in the automatic reading circuit 17, the signal reading interval Tk can be arbitrarily set by the value written in the storage unit 17c, and the signal reading timing time Tm in the energization signal output control is set by the value written in the storage unit 17h. Can be set arbitrarily.
[0087]
For this reason, the microcomputer 2 of this embodiment has very high versatility.
As mentioned above, although one Embodiment of this invention was described, it cannot be overemphasized that this invention can take a various form.
For example, in the microcomputer 2 of the above embodiment, if the output terminal for outputting the energization signal to the energization circuit 109 can be arbitrarily selected from a plurality of terminals, versatility can be further improved. .
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating configurations of an electronic control device and a microcomputer according to an embodiment.
FIG. 2 is a block diagram illustrating an automatic reading circuit in a microcomputer.
FIG. 3 is an explanatory diagram illustrating an operation when an automatic reading circuit wakes up a CPU from a stopped state to an operating state in a microcomputer.
FIG. 4 is an explanatory diagram for explaining an example of use of a microcomputer.
FIG. 5 is an explanatory diagram for explaining another use example of a microcomputer;
FIG. 6 is a configuration diagram illustrating an electronic control device of Conventional Example 1.
FIG. 7 is an explanatory diagram for explaining the operation of the electronic control device of Conventional Example 1;
FIG. 8 is a configuration diagram illustrating an electronic control device of Conventional Example 2.
FIG. 9 is an explanatory diagram for explaining the operation of the electronic control device according to the second conventional example.
[Explanation of symbols]
1 ... Electronic control unit 2 ... Microcomputer
A ... Output terminal B1, B2 ... Input terminal 3 ... CPU 5 ... ROM
6 ... RAM 7 ... I / O port 8,18 ... oscillating element
9 ... Main oscillation circuit 11 ... Oscillation controller 13 ... Main clock generator
15 ... Intermittent operation control section 11a, 15a ... Register 17 ... Automatic reading circuit
19 ... Sub oscillation circuit 109 ... Energization circuit L1, L2 ... Signal line
Ru: Pull-up resistor Rd: Pull-down resistor
Tr1 ... NPN transistor Tr2 ... PNP transistor

Claims (9)

A microcomputer including a CPU that operates according to a program, and the CPU can stop the operation by executing a predetermined instruction,
When the CPU stops operating, the level of a binary signal to be monitored (hereinafter referred to as a monitoring target signal) supplied to a predetermined input terminal of the microcomputer is read from the input terminal at regular intervals. And when the determination level reaches a specific level, the CPU includes an automatic signal reading means for waking up the CPU from the stopped state to the operating state,
Further, the automatic signal reading means includes
Only when the level read from the input terminal is continuously the same for a plurality of predetermined times, the judgment mode of the monitoring target signal is updated to the level read this time, an operation mode for performing a filtering process, Without being subjected to the filtering process, it is configured to be switchable to an operation mode in which the level read from the input terminal is set as the determination level of the monitoring target signal as it is according to a command from the CPU;
A microcomputer characterized by. A microcomputer including a CPU that operates according to a program, and the CPU can stop the operation by executing a predetermined instruction,
When the CPU stops operating, the level of a binary signal to be monitored (hereinafter referred to as a monitoring target signal) supplied to a predetermined input terminal of the microcomputer is read from the input terminal at regular intervals. And when the determination level reaches a specific level, the CPU includes an automatic signal reading means for waking up the CPU from the stopped state to the operating state,
Further, the automatic signal reading means includes
Before reading the level of the monitoring target signal from the input terminal, an energization signal for applying a voltage to a pull-up resistor that pulls up a signal line that supplies the monitoring target signal to the input terminal Output from the output terminal, and when the level of the monitoring target signal is read from the input terminal, the output of the energization signal is stopped, the energization signal output control is performed, and the monitoring target signal is output after the energization signal is output. The waiting time until the level is read is configured to be set by the CPU,
A microcomputer characterized by. A microcomputer including a CPU that operates according to a program, and the CPU can stop the operation by executing a predetermined instruction,
When the CPU stops operating, the level of a binary signal to be monitored (hereinafter referred to as a monitoring target signal) supplied to a predetermined input terminal of the microcomputer is read from the input terminal at regular intervals. And when the determination level reaches a specific level, the CPU includes an automatic signal reading means for waking up the CPU from the stopped state to the operating state,
Further, the automatic signal reading means includes
Before reading the level of the monitoring target signal from the input terminal, an energization signal for applying a voltage to a pull-up resistor that pulls up a signal line that supplies the monitoring target signal to the input terminal An operation mode in which the output of the energization signal is stopped when the level of the monitoring target signal is read from the input terminal and the energization signal output control is performed, and an operation mode in which the energization signal output control is not performed. And being configured to be settable in accordance with a command from the CPU,
A microcomputer characterized by. The microcomputer according to any one of claims 1 to 3,
Input terminals before Symbol automatic signal reading means to read the signal level, by the CPU, it is set to any of a plurality of terminals of the microcomputer,
A microcomputer characterized by. The microcomputer according to any one of claims 1 to 4,
The automatic signal reading means is configured so that the predetermined time is set by the CPU;
A microcomputer characterized by. The microcomputer according to any one of claims 1 to 5,
The automatic signal reading means is
The specific level is configured to be set by the CPU;
A microcomputer characterized by. The microcomputer according to any one of claims 1 to 6,
Upon receiving an operation request from the CPU, timer wake-up control means for starting the time measurement set in advance by the CPU and wake-up the CPU from the stop state to the operation state when the time has elapsed. Having
A microcomputer characterized by. The microcomputer according to any one of claims 1 to 7,
The automatic signal reading means includes
The determination level of the monitoring target signal by the automatic signal reading means is stored, and a reading result storage unit that can read the stored content by the CPU is provided,
A microcomputer characterized by. The microcomputer according to claim 8,
The automatic signal reading means is
It is configured to be operable even when the CPU is operating according to a command from the CPU.
A microcomputer characterized by.

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