JP3999212B2 - Display device and driving method thereof - Google Patents

Description

  The invention disclosed in this specification relates to a peripheral driving device for driving a pixel portion of a liquid crystal electro-optical device. In particular, the present invention relates to a peripheral drive circuit of a liquid crystal electro-optical device that should operate with low power consumption.

  FIG. 29 is a schematic configuration diagram of a generally known liquid crystal electro-optical device. The liquid crystal electro-optical device drives a pixel matrix portion (2901) for displaying an image and a pixel matrix portion (2901). A signal line driver circuit (2902) and a scanning line driver circuit (2903) are included. The pixel matrix (2901) is connected to the scanning line driver circuit (2903) and the signal line driver circuit (2902) by a scanning line (2904) and a signal line (2905), respectively.

  In the pixel matrix portion (2901), the scanning lines (2904) and the signal lines (2905) are arranged in a matrix. In particular, in an active matrix liquid crystal display device, a pixel thin film transistor (hereinafter, a thin film transistor is abbreviated as a TFT) (2906) is disposed at the intersection. The gate electrode of the pixel TFT (2906) is connected to the scanning line (2904), the source electrode is connected to the signal line (2905), and the drain electrode is connected to the pixel electrode of the liquid crystal capacitor (2907). A storage capacitor (2908) is connected in parallel to the liquid crystal capacitor (2907). Since the liquid crystal capacitor (2907) cannot have a large capacitance value, the storage capacitor (2908) holds charges.

  The signal line driver circuit (2902) includes a shift register circuit (2909), a buffer circuit (2910), and a sampling circuit (2911). On the other hand, the scanning line driving circuit (2903) includes a shift register (2916) and a NAND circuit inverter type buffer (2917).

  30A and 30B are circuit diagrams of the shift register circuits (2909) and (2916), and FIG. 30A is a circuit diagram of a shift register circuit configured by a clocked inverter (3001). FIG. 30B is a circuit diagram of a shift register circuit constituted by transmission gates (3002).

  When an image is displayed on the pixel matrix portion (2901), a signal synchronized with the video signal is input from the input terminal (2912) to the shift register (2909) in the signal line driver circuit (2902). The input signal is sequentially shifted in accordance with the clock pulse by the register of the shift register (2909), and is input to the inverter type buffer circuit (2910) and stored therein. The buffer circuit (2910) controls on / off of the analog switch (2913) of the sampling circuit (2911).

  When the analog switch (2913) is turned on, the video signal line (2915) and the storage capacitor (2914) are short-circuited, and the storage capacitor (2914) is charged with electric charge. The electric charge is held as a video signal sampled at the same time. When the analog switch (2913) is turned on again, the charge in the storage capacitor (2914) is discharged, and the sampled video signal is transmitted to the pixel TFT (2906) through the signal line (2905).

  In the scanning line driver circuit (2903), the scanning line (2904) is generated by the shift register (2916) and the NAND circuit inverter type buffer (2917) in accordance with the input signal synchronized with the vertical synchronizing signal and the clock synchronized with the horizontal synchronizing signal. ) Are sequentially driven to control on / off of the pixel TFT (2906).

  When a voltage exceeding the threshold voltage is applied to the gate electrode of the pixel TFT (2906) by the scanning line (2904), the pixel TFT (2906) is turned on, and the drain electrode and the source electrode of the pixel TFT (2906) are short-circuited. It becomes a state. In this state, the sampled video signal is transmitted from the storage capacitor (2914) to the pixel TFT (2906) via the signal line (2905), and the liquid crystal capacitor (2907) and the storage capacitor (2908) are charged. . When the pixel TFT (2906) is turned off, the drain electrode of the pixel TFT (2906) is opened, and the charge accumulated in the liquid crystal capacitor (2907) and the storage capacitor (2908) is then turned on by the pixel TFT (2906). Hold until state.

  Note that in the signal line driver circuit (2903) and the scanning line driver circuit (2902), a decoder circuit can be used instead of the shift register circuits (2909) and (2916).

  FIG. 31 is a circuit diagram of a signal line driver circuit configured using a decoder circuit. In this case, the pixels and the addresses are made to correspond one-to-one. In the case of writing a video signal to a pixel, an address signal is input to the signal line driver circuit via an address signal input line (3101). According to the address signal, the NAND gate (3102) selects a signal line and outputs the signal to the analog switch (3103). In the analog switch (3103), on / off of the storage capacitor (3104) is controlled, and a video signal is sampled and held in the storage capacitor (3104) as an electric charge.

  Alternatively, a decoder circuit and a counter circuit can be used instead of the shift register circuits (2909) and (2916) in the signal line driver circuit (2903) and the scan line driver circuit (2902).

  FIG. 32 is a circuit diagram of a signal line driving circuit constituted by a decoder circuit and a counter circuit. The counter circuit (3202) counts the clock pulse input (3201), and inputs the count result as an address signal to the NAND gate (3203). According to the address signal, the NAND gate (3203) selects a signal line and inputs a signal to the corresponding analog switch (3204). When a signal from the NAND gate (3203) is input to the analog switch (3204), the video signal is sampled and held in the storage capacitor (3205) as an electric charge.

  Conventionally, a peripheral driving circuit of a liquid crystal electro-optical device is manufactured by a CMOS circuit on a transparent substrate on which a pixel matrix is formed. FIG. 33 is a circuit configuration diagram of a shift register constituted by a CMOS circuit, and corresponds to the shift register shown in FIG.

  In the case where the peripheral circuit is configured by a CMOS circuit, there is a problem that the number of processes increases because the P-channel TFT and the N-channel TFT are manufactured on the same substrate. Furthermore, there is a characteristic defect that it is difficult to obtain uniform characteristics between the P-channel TFT and the N-channel TFT.

  Conventionally, in order to solve the above-described problem, the peripheral drive circuit is composed of a one-conductive type TFT and an element such as a resistor to simplify the process and make the characteristics of the element uniform.

  FIG. 34 is a block diagram of a shift register circuit composed of a P-channel TFT and a resistor. FIG. 35 is a configuration diagram of a basic gate circuit using a P-channel TFT and a resistor, and shows a configuration diagram of a NAND circuit, a NOR circuit, and an inverter circuit. These basic circuits can constitute a JK flip-flop, a counter circuit, or the like. FIG. 36 is a block diagram of a JK-flip-flop, and FIG. 37 is a block diagram of a 4-bit counter circuit.

The 4-bit counter circuit shown in FIG. 37 generates a ripple carry output signal, counter bit outputs Q _{1 to} Q ₄ , and an inverted output signal thereof in accordance with power, clear, clock, and enable input signals.

  However, a peripheral drive circuit using a P-channel TFT and a resistor has a problem that power consumption is large. For example, in the shift register circuit shown in FIG. 34, when the P-channel TFT (3401) is turned on, the power supply (3402) and the ground (3403) are short-circuited by the resistor (3404), and a through current flows. Electric power increases.

  If the resistance value of the resistor (3404) is increased so that no current flows, it becomes difficult to discharge, the change from the power supply potential to the ground potential is delayed, and the frequency characteristics are deteriorated. Conventionally, since the frequency characteristic is prioritized, it is difficult to increase the resistance (3404).

  High power consumption is a major obstacle when used for electronic devices such as portable information devices.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a peripheral drive circuit for a liquid crystal electro-optical device that can reduce power consumption required when driving the entire liquid crystal electro-optical device, even if a peripheral drive circuit with high power consumption is used. Is to provide.

  In order to solve the above-described problems, the configuration of the peripheral drive circuit of the liquid crystal electro-optical device according to the present invention includes a shift register circuit configured by connecting a plurality of registers and a power supply for supplying power to the register. In a peripheral drive circuit of a liquid crystal electro-optical device having a circuit, when a signal is input to one of the registers, the power supply circuit stops power supply to at least one register other than the register It is characterized by.

  The shift register of the peripheral drive circuit of the liquid crystal electro-optical device sequentially transmits one signal by delaying the signal in synchronization with the clock signal. Therefore, a part of the whole functions as a shift register. Therefore, according to the present invention, power is supplied only to a functioning register to reduce power consumption of the entire peripheral drive circuit.

  The operation of the peripheral drive circuit having the above configuration will be described with reference to FIG. FIG. 1 is a configuration diagram of a liquid crystal display device, in which a liquid crystal display unit (101), a signal line driver circuit, and a peripheral driver circuit are provided on the same substrate. In the signal line driving circuit, a shift register (102) composed of a plurality of stages of registers, a buffer (104), and a sampler (105) are sequentially connected, and the output of the sampler (105) is connected to a liquid crystal display unit (via a signal line). 101). On the other hand, in the scanning line driving circuit, the shift register (108) and the buffer (109) are sequentially connected, and the output of the buffer (109) is connected to the liquid crystal display unit (101) through the scanning line.

  In the signal line driver circuit, when a signal is input to the N-th register (103) of the shift register (102), the final stage of the buffer (104) and the sampler (105) are not affected. The power supply to the register (106) before the (N-1) -th stage after the signal transmission is completed can be stopped while maintaining the power.

  Furthermore, it is also possible to stop the power supply to the registers (107) in the (N + 1) th and subsequent stages waiting for signal input.

  Similarly, for the shift register (108) of the scanning line driver circuit, when there is an input signal in the Nth stage register (110) while maintaining power so as not to affect the buffer (109), the (N− 1) It is possible to stop power supply to the register (111) before the stage and the register (112) after the (N + 1) th stage.

  Note that in the shift register of the peripheral driver circuit, when the outputs of the adjacent two-stage registers are simultaneously active, the (N− 1) Since the output of the register at the stage is also active, it is possible to stop the power supply to the register before the (N-2) -th stage.

  Furthermore, when the pulse width is surely equal to one cycle of the clock, power is supplied to the (N + 1) -th stage register that does not output an active signal when a signal is input to the N-th stage register. Then, based on the next clock change, the signal is reliably transmitted to the (N + 1) -th stage register. Accordingly, when a signal is input to the Nth stage register, it is possible to stop power supply to the (N + 2) th stage and subsequent registers. When the pulse width of the input signal is allowed to change due to the element delay, it is possible to stop the power supply to the registers in the (N + 1) th and subsequent stages.

  When priority is given to reducing the number of elements over reducing power consumption, the register that stops power supply when the input signal reaches the Nth stage register is not necessarily the (N-2) th stage. The register is not limited to the register before the current and the (N + 2) th and subsequent stages.

  For example, it is possible to continue supplying power to the (N-2) -th stage register and not supply power to the (N-3) -th, (N-4) -th stage, etc. It is. Therefore, it is also possible to stop power supply to the shift register of the (N−x) th stage [x ≧ 2].

  Further, when an input signal reaches the Nth stage register, power is supplied to the (N + 2) th stage register, and power is supplied to the (N + 3) th stage, (N + 4) th stage, and the like. It is also possible not to supply. Therefore, it is also possible to stop the power supply to the (N + y) -th stage [y ≧ 2] register.

  For example, when a shift register circuit or a power supply circuit is composed of a P-channel type thin film transistor and a resistor, each circuit consumes a large amount of power, but only the portion that should function is operating, so the overall power consumption is reduced. Can be suppressed. In particular, the power consumption of the power supply circuit that is always operating is preferably smaller than the power consumption of the shift register circuit.

  Further, another configuration of the peripheral driving circuit of the liquid crystal electro-optical device according to the present invention includes a block configured by connecting a plurality of registers, a shift register circuit configured by connecting the blocks in a plurality of stages, And a power supply circuit that is connected to each block and supplies power to the register, and the power supply circuit when a signal is input to a register that constitutes one of the blocks The supply circuit is characterized in that power supply to other than the block is stopped.

  In the peripheral drive circuit having the above-described configuration, an arbitrary number of registers are grouped into blocks in the shift register, and power supply is controlled for each block. By adopting this configuration, the control circuit can be simplified rather than controlling the registers one by one.

  The operation of the peripheral drive circuit having the above configuration will be described with reference to FIG. The register blocks (202) to (204) are formed by collecting some registers of the shift register (201). The control circuit (205) supplies control signals (206) to (208) for each register block.

  A control signal (208) for supplying power is input to the shift register block (204) in which there is a register to which the input signal (209) to be shifted is input, and power is supplied. Further, signals (206) and (207) for stopping power supply are input to the register block (202) after transmitting the input signal to be shifted and the register block (203) waiting for signal input. Then, the power supply is stopped.

  In the configuration described above, power must be supplied to these blocks during a period in which the input signal is transferred between the two blocks. The power supply to the block having no error may be stopped.

  Further, another configuration of the peripheral drive circuit of the liquid crystal electro-optical device according to the present invention is a power supply drive circuit that supplies power to the peripheral drive circuit in the peripheral drive circuit of the liquid crystal electro-optical device that specifies the pixel of the pixel unit. The power supply circuit is characterized in that the power supply to at least a part other than the peripheral drive circuit specifying the pixel is stopped or the power supply is reduced.

  In the peripheral drive circuit of the liquid crystal electro-optical device having the above-described configuration, the power supply is stopped or the power supply is reduced in a portion where the peripheral drive circuit does not function, that is, a portion where pixels are not specified. .

  In this specification, to specify a pixel means to sample a video signal and charge a storage capacitor in a signal line driver circuit. Alternatively, the pixel TFT connected to the scanning line is turned on in the scanning line driving circuit.

  First, a circuit for specifying a pixel is set as a first circuit, and symbols are sequentially added. When the input signal reaches the Nth circuit, the output of the Nth circuit becomes active, and the (N−1) th circuit also becomes active. Therefore, in circuits other than these, since the active output is not obtained, the supplied power can be lowered. That is, it is possible to stop the power supply to the circuit portion before the (N-2) th or to reduce the power supply. Furthermore, the power supply to the (N + 1) th and subsequent circuit portions can be stopped or the power supply can be lowered.

  The power supply to the (N + 2) th and (N + 3) th circuit parts can be stopped or the power supply can be lowered while the power supply to the (N + 1) th circuit remains unchanged. Accordingly, it is possible to stop the power supply to the (N + x) -th stage [x ≧ 1] circuit or to lower the supply power.

  Further, power is supplied to the (N-2) th stage circuit, and no power is supplied to the (N-2) th stage, (N-3) th stage, or the like, or the supplied power is reduced. Is also possible. Therefore, it is possible to stop the power supply to the (N−y) -th stage [y ≧ 2] circuit or to lower the supply power.

  In order to drive the liquid crystal, a potential difference of about 5 V is required from the transmittance-voltage characteristics of the liquid crystal. However, since it deteriorates when a direct current voltage is applied to the liquid crystal, it is necessary to drive the liquid crystal. The potential difference is required to be several tens of volts, and the power supply voltage of the peripheral drive circuit is required to be around 20V.

  Therefore, in the peripheral drive circuit where the pixel is not specified, the power consumption can be reduced by reducing the supply power to 20 V or less. Alternatively, the minimum required power consumption can be achieved by stopping the power supply to the part where the pixel is not specified. Note that power consumption can be reduced by setting the power supply voltage to 20 V only when the peripheral drive circuit is operated at 20 V or less to specify a pixel.

  For example, when the counter circuit of the peripheral drive circuit, the decoder circuit, etc. are composed of thin film transistors and resistors, each circuit consumes a large amount of power, but by operating only the part that should function, the overall power consumption is suppressed. be able to.

  Further, in order to solve the above-described problems, one of the configurations of the liquid crystal electro-optical device according to the present invention is that a plurality of pixels are arranged on a matrix, and the plurality of blocks are arranged so as to include at least one of the pixels. The peripheral drive circuit of the liquid crystal electro-optical device for driving the divided pixel portion has a power supply circuit for supplying power to the peripheral drive circuit, and a voltage is applied or sampled in the block. When there is no pixel to which a video signal is written, or when there is no pixel to which a sampled video signal is written, the power supply circuit includes at least a pixel corresponding to the pixel in the block among the peripheral drive circuits. The power supply is stopped for a part. Alternatively, the power supply is reduced.

  In the peripheral drive circuit having the above configuration, an arbitrary number of pixels are grouped into a block, and power supply is controlled for each circuit corresponding to the pixel in the block. Therefore, the pixels are blocked and the peripheral drive circuit is also blocked, and the power supply is controlled for each block. That is, the power supply is stopped or the power supply is reduced for a block in which no pixel is specified.

  First, a circuit for specifying a pixel is set as a first block, and symbols are sequentially added. When the input signal reaches the Nth block, the power supply to the (N-1) th block or earlier can be stopped or the supply power can be lowered. Furthermore, the power supply to the (N + 1) th and subsequent blocks can be stopped, or the power supply can be lowered.

  The power supply to the (N + 1) -th block can be stopped, or the power supply to the (N + 2) -th, (N + 3) -th, etc. block can be stopped or the power supply can be lowered. Therefore, it is possible to stop the power supply to the (N + x) -th stage [x ≧ 1] block or to reduce the power supply.

  In addition, power is supplied to the (N-1) th block, and power is not supplied to the (N-2) th, (N-3) th, or other blocks, or the supply power is reduced. Is also possible. Therefore, the power supply to the (N−y) th stage [y ≧ 1] block can be stopped, or the power supply can be lowered. It is also possible to lower the power supply voltage of the circuit portion.

  According to the present invention, in the peripheral drive circuit, power is supplied to a circuit to be operated and power supply to other circuits is stopped or power supply is reduced, so that power consumption of the entire circuit can be reduced. it can. In addition, malfunction of a circuit that should not be operated can be prevented.

  In particular, even when a peripheral drive circuit having a large power consumption constituted by a thin film transistor and a resistor is used, the entire peripheral drive circuit can be made extremely low in power consumption. For example, even if the number of stages of the shift register is increased, the operating power is supplied only to the register to which a signal is input, so that the power consumption does not increase.

  FIG. 3 is a partial circuit diagram of the shift register, and shows only three stages of registers. FIG. 4 is a chart of input / output signals of a three-stage register.

In the following first to fourth embodiments, a shift register having the configuration as shown in FIG. 3 and the input / output of the register as shown in FIG. 4 will be taken up.

  In the first embodiment, the shift register is divided into blocks and power is supplied to each block. Note that the control circuit for controlling power supply is configured by a CMOS circuit outside the transparent substrate on which the pixel matrix is formed.

FIG. 5 shows a case where eight stages of shift registers are made one block. Although it is possible to detect the input signal and generate the control signal, here, the fact that the control circuit (501) and the shift register (502) are synchronized is used.

  A signal from the clock oscillator (503) is input to the shift register (502) and the counter (504) of the control circuit (501). The output of the counter (504) becomes a control signal (506) by the decoder (505). The control signal (506) is input to the shift register (502).

  FIG. 6 shows a timing chart of the control signal (506) for the Nth block of the shift register (502). Based on the clock signal (601) of the clock oscillator (503), the decoder (502) creates a control signal (506). Three systems of signals are generated: a power supply signal (602), a clear signal (603) that is initialized when the Nth shift register block is activated, and a clock supply signal (604).

  In the case where 8 stages of registers are one block, in addition to the period (605) necessary for generating the output, power supply to the block starts at the time of (606) and the clock signal is input at the time of (607). start. By providing a time difference (608) without simultaneously supplying power and inputting a clock signal, the output at startup is ensured.

  Note that after the signal is input from the Nth block to the (N + 1) th block, the power supply to the Nth block may be stopped at any time, but here the power supply and the clock at the time of (609). Stop supplying.

  FIG. 7 shows a circuit for generating a control signal (506) to be supplied to the fourth block when the eight registers are one block.

  The output of the same clock oscillator (701) as the clock oscillator (503) in FIG. 5 is input to the binary counter (702). The output of the binary counter (702) is detected by AND circuits (703), (704), and (705), and is synthesized by OR circuits (706) and (707) to be a control signal.

  The AND circuit (703) is a period necessary for the shift register block to transmit an input signal inside the block, the AND circuit (704) is a clear period, and the AND circuit (705) is a period between the clear period and a period for transmitting the input signal. Select each.

  Accordingly, when the outputs of the AND circuits (703), (704), and (705) are ORed by the OR circuit (706), a power supply signal (602) is obtained. The output of the AND circuit (704) inverted by the inverter (708) is the clear signal (603), and the outputs of the AND circuits (703) and (705) are supplied by the OR circuit (708) to the clock supply signal (604). It becomes.

  FIG. 8 shows a circuit for supplying power to the shift register block using a P-channel TFT.

  The positive power line (801) is connected to the shift register block (803) through the P-channel TFT (802).

  A power supply signal (602) is applied to the gate electrode of the P-channel TFT (802).

  FIG. 9 shows a clear circuit. A P-channel TFT (902) that determines the value of the storage loop of one stage (901) of the shift register at the time of startup is connected.

  A clear signal (603) is applied to the gate electrode of the P-channel TFT (902).

  Here, in order to determine the loop value so that the output of the buffer (903) does not change before and after the start of the shift register, when the output of the buffer (903) is a normal power supply potential, In the case of the ground potential, the drain electrode of the P-channel TFT (902) is connected to the contact (905).

  FIG. 10 shows a clock supply circuit. The clock lines (1001) and (1002) are connected to the shift register block (1005) through the P-channel TFTs (1003) and (1004).

  A clock supply signal (604) is applied to the gate electrodes of the P-channel TFTs (1003) and (1004).

  Regarding the shift register of this embodiment, the power consumption when used as a peripheral drive circuit of a liquid crystal electro-optical device is compared. The power consumption of one resistor is obtained by dividing the square of the power supply voltage per resistor by the resistance value. In the case of the conventional example shown in FIG. 32, there are three resistors in one stage of the shift register, and power is always supplied to all stages. Therefore, in the case of the conventional type, power consumption increases in proportion to the number of stages of the shift register.

  However, in the case of the first embodiment, the resistance in one stage of the shift register is three, but the power is always supplied to the circuit corresponding to the four stages of the shift register due to the eight stages of the shift register for signal transmission and the overlap of the control signal with the adjacent block. Is supplied, and no power is supplied to the other shift registers. Therefore, the power consumption of the peripheral drive circuit can be extremely reduced, and the power consumption does not change even if the number of shift register stages is increased.

  Specifically, assuming that a 640-stage shift register is operated with a power supply voltage of 20 V and a resistance of 300 kΩ, and that power supply potential output or ground potential output occurs with a probability of 1/2, power consumption Was 1280 mW in the conventional type, whereas in the configuration of Example 1, it could be 24 mW.

  In the second embodiment, a control circuit is provided for each register of the shift register, and a special signal is used from the outside.

  As shown in FIG. 11, a control circuit (1102) is provided for each register of the shift register (1101), an input signal (1103) is detected, and a control signal (1104) is created.

  If power is supplied after the input signal arrives, the pulse width is not guaranteed, so power is supplied before the input signal arrives. Specifically, power is supplied half a cycle before the basic clock to activate the register, and the supply of power is stopped after one cycle of the basic clock, that is, immediately after the register activates the output.

  FIG. 12 is a schematic diagram for explaining the operation of the shift register. 12A shows a state in which the Nth register is active, and FIG. 12B shows a state after one clock cycle from the state in FIG. 12A. As shown in FIG. 12a, the output signal (1203) of the Nth stage register (1202) of the shift register (1201) is connected to the (N + 1) th circuit (1205) of the control circuit (1204) and the (N− 2) Input to the first circuit (1206).

  In the (N + 1) th control circuit (1205), when the output signal (1203) of the Nth stage register (1202) becomes active, control is performed to supply power to the (N + 1) th stage register (1207). A signal (1208) is created to activate the (N + 1) -th stage register.

  In the (N-2) th control circuit (1206), when the output (1203) of the Nth stage register (1202) becomes active, power is supplied to the (N-2) th stage shift register (1209). The control signal (1210) for stopping is generated, and the (N-2) -th stage register is stopped.

  When the next clock pulse is input to the shift register (1201), as shown in FIG. 12B, the (N + 2) -th control circuit (1211) causes the (N + 1) -th stage register (1207). When the output signal (1212) becomes active, a control signal (1214) for supplying power to the (N + 2) -th stage register (1213) is created, and the (N + 2) -th stage register is activated.

  In the (N−1) th control circuit (1215), when the output (1212) of the (N + 1) th stage register (1207) becomes active, the shift register (1216) of the (N−1) th stage is activated. A control signal (1217) for stopping power supply is generated, and the (N-1) th stage register is stopped.

  Each time a clock signal is newly input to the shift register, the above operation is repeated to start and stop the register sequentially.

  The output of the buffer (104) in FIG. 1 must not change so that the sampler (105) in FIG. 1 does not malfunction even if power is supplied to the shift register or stopped. From this, it is considered that the output of the buffer (104) in FIG. 1 is reliable, and the signal in the shift register (1101) is uncertain during the period when power is not supplied to the shift register (1101) in FIG. In the second embodiment, the output of the buffer is used as the input of the next register.

  Based on this, FIG. 13 shows a timing chart for one stage of the register. The Nth stage adjustment input A (1303) power supply potential (1304) is generated from the basic clock (1301) and the buffer output (1302) of the (N−1) th stage register. Here, one stage of the register operates for 1.5 cycles of the basic clock. However, since the control signal is delayed from the rising and falling edges of the clock, the basic clock is used as an input signal to the Nth stage register. 2 periods are created, and the pulse width is surely set to one basic clock period.

  That is, the power supply potential (1308) of the Nth stage adjustment input B (1307) is generated from the inverted signal (1305) of the basic clock and the buffer output (1306) of the (N + 1) th stage register. Then, the input adjustment signals A (1303) and B (1307) are set to active high to perform a logical OR, and an adjustment signal such as (1309) is created.

  If this is the case, the buffer output signal (1302) of the (N−1) -th register changes with a delay from the basic clock (1301), so that a malfunction signal is generated at (1310) of the adjustment signal (1309).

  In this case, the operation is ensured by masking with a clock (1311) having a cycle 1.5 times the basic clock. By these signals, the buffer output (1312) of the Nth stage register can be formed.

  Here, the power supply signal in the N-th stage is as shown in (1313). In order to avoid the change of the input signal width due to the element delay, the power supply is performed half a cycle of the basic clock before the input signal arrives. Begin.

  As the control circuit, it is desirable to use a logic circuit because it can store (hold state) and requires low power consumption. In the second embodiment, consider a circuit centered on a capacitor that is easy to configure, although the frequency characteristic is poor.

  FIG. 14 shows a control circuit. When the capacitor (1401) is in a charged state, power supply to the shift register is stopped, and in a discharged state, a control signal output (1402) for supplying power to the shift register is generated.

  The P-channel TFT (1403) sets the initial state of the control circuit after the entire circuit is powered on. That is, before inputting an input signal to the shift register, a ground potential signal is applied to the gate electrode of the P-channel TFT (1403) to charge the capacitor (1401).

  In the Nth control circuit, in order not to miss the input signal, when the input signal reaches the (N−1) th stage register, the Nth stage register is activated and the next clock The input signal is captured by change.

  Therefore, the P-channel TFT (1404) uses the buffer output of the (N−1) -th stage register as the input of the gate electrode. As a result, when the buffer output of the (N−1) -th stage register becomes the ground potential, the capacitor (1401) is discharged to generate a signal for supplying power to the N-th stage register.

  Similarly, in the Nth control circuit, when the input signal reaches the (N + 2) -th stage register, the N-th stage register is not outputting an active signal, and the power supply is stopped. Good.

  Therefore, the P-channel TFT (1405) uses the buffer output of the (N + 2) -th stage shift register as the input of the gate electrode. As a result, when the buffer output of the (N + 2) -th shift register becomes the ground potential, the capacitor (1401) is charged and the power supply to the N-th shift register is stopped. Here, (1406) is a resistor for power supply protection.

  FIG. 15 shows the N-th stage register and buffer. For the signal adjustment unit (1501), a basic clock is applied to the gate electrode of the P-channel TFT (1502), a clock of 1.5 times the mask is applied to the gate electrode of the P-channel TFT (1503), and the P-channel TFT (1504). The buffer output of the (N−1) -th stage register is applied to the gate electrode of), and the falling edge of the buffer output of the N-th stage register, that is, the signal (1303) in FIG.

  The basic clock is inverted to the gate electrode of the P-channel TFT (1505), the clock of 1.5 times the mask is applied to the gate electrode of the P-channel TFT (1506), and the gate electrode of the P-channel TFT (1507) is The buffer output of the (N + 1) stage shift register is applied, and the rising edge of the buffer output of the Nth stage register, that is, the signal (1307) in FIG. 13 is generated.

  Therefore, the output of the signal adjustment unit is the signal (1309) in FIG. Basically, since the P-channel TFTs (1504) and (1507) are in the OFF state, no current flows through the normal resistor (1508), and therefore no control signal is input to the signal adjustment unit.

  Conventionally, all stages are operated as shift registers, but a control signal is applied to the gate electrodes of P-channel TFTs (1590), (1510), and (1511), and power supply is stopped for an unnecessary period. Therefore, low power consumption is achieved in the entire shift register.

  A buffer in a period in which a memory loop is not formed by applying a 1.5-fold cycle clock to the gate electrode of the P-channel TFT (1512) and the output of the signal adjustment unit (1501) to the gate electrode of the P-channel TFT (1513). Make input.

  An inverted signal of a 1.5-fold clock is applied to the gate electrode of the P-channel TFT (1514), and the output of the inverter (1516) constituting the memory loop is applied to the gate electrode of the P-channel TFT (1515).

  Basically, the P-channel TFT (1515) and the resistor (1517) constitute an inverter. A memory loop is formed by this inverter and an inverter composed of a P-channel TFT (1518) and a resistor (1519).

  The P-channel TFT (1520) and the resistor (1521) constitute a buffer. Here, the P-channel TFT (1522) is used to prevent each of the outputs of the shift register from being determined when clearing, and to prevent the charged state of the capacitor of the control circuit from being secured.

  If the current capacity of the P-channel TFT is large, P-channel TFTs (1509), (1510), and (1511) for supplying power can be combined into one.

  When it is not necessary to guarantee the pulse width of the input signal, it is possible to synchronize the control signal with the basic clock and supply power to one stage of the shift register for one cycle with the circuit configuration of the second embodiment.

  Regarding the shift register of this embodiment, the power consumption when used as a peripheral drive circuit of a liquid crystal electro-optical device is compared. The power consumption of one resistor is obtained by dividing the square of the power supply voltage per resistor by the resistance value. In the case of the conventional example shown in FIG. 32, there are three resistors in one stage of the register, and power is always supplied to all the stages. Therefore, in the case of the conventional type, power consumption increases in proportion to the number of stages of the shift register.

  However, in the case of the peripheral drive circuit shown in the second embodiment, there are three resistors in one register stage, but power is always supplied to the three register stages, and power is not supplied to the other registers. Therefore, the power consumption of the peripheral drive circuit can be extremely reduced, and the power consumption does not change even if the number of shift register stages is increased.

  Specifically, assuming that a 640-stage shift register is operated with a power supply voltage of 20 V and a resistance of 300 kΩ, and that power supply potential output or ground potential output occurs with a probability of 1/2, power consumption Was 1280 mW in the conventional type, whereas in the configuration of Example 2, it could be 6 mW.

  Embodiment 3 shows a case where a control circuit is provided for each register in a shift register. In the second embodiment, a portion in which a malfunction is prevented by a clock having a 1.5 times period is dealt with by providing a circuit for masking the clock. Therefore, the main signal routing and control circuit is the same as that of the second embodiment.

  FIG. 16 shows a timing chart of the first stage of the shift register. In the signal adjustment unit, the power supply potential (1604) of the Nth stage input (1603) is generated from the inversion (1601) of the basic clock and the buffer output (1602) of the (N-1) th stage register.

  Further, the clock (1605) is desirable in terms of timing as a signal for forming the memory loop, but since the control signal of the Nth stage is as (1606), a memory loop is formed immediately after startup (1607), and the Nth The column input (1603) is not accepted.

  Therefore, the clock (1605) is masked with the control signals (1606) and (1608) to create a loop formation signal like (1609). Thus, the Nth stage buffer output (1610) is created.

  FIG. 17 shows the configuration of the N-th stage register. For the signal adjustment unit (1701), the basic clock is applied to the gate electrode of the P-channel TFT (1702), and the buffer output of the (N-1) th stage register is applied to the gate electrode of the P-channel TFT (1703). The signal is set when the Nth stage register is activated.

  A circuit (1704) for selecting a clock has an Nth control signal applied to the gate electrode of the P channel TFT (1705), an (N + 1) th control signal applied to the gate electrode (1706) of the P channel TFT, and a P channel type. An inversion of the basic clock is applied to the gate electrode (1707) of the TFT to obtain an output (1708). The signal forming the memory loop is created by inverting the signal (1708).

  A circuit (1709) and a buffer circuit (1710) constituting the memory loop are the same as those in the second embodiment. Here, the P-channel TFTs (1711), (1712), (1713), (1714), and (1715) are for power supply, and the P-channel TFT (1716) is for clear execution.

  Regarding the shift register of this embodiment, the power consumption when used as a peripheral drive circuit of a liquid crystal electro-optical device is compared. The power consumption of one resistor is obtained by dividing the square of the power supply voltage per resistor by the resistance value. In the case of the conventional example shown in FIG. 34, there are three resistors in one register stage, and power is always supplied to all stages. Therefore, in the case of the conventional type, power consumption increases in proportion to the number of register stages.

  However, in the peripheral drive circuit shown in the third embodiment, there are five resistors in one register stage, but power is always supplied to only three stages of the register, and no power is supplied to the other shift registers. Therefore, the power consumption of the peripheral drive circuit can be made extremely small, and the power consumption does not change even if the number of register stages is increased.

  Specifically, assuming that a 640-stage shift register is operated with a power supply voltage of 20 V and a resistance of 300 kΩ, and that power supply potential output or ground potential output occurs with a probability of 1/2, power consumption Was 1280 mW in the conventional type, whereas in the configuration of Example 3, it could be 10 mW.

  The fourth embodiment shows a case where the power supply is for two cycles of the basic clock. In the second and third embodiments, the power is supplied for a period of 1.5 cycles of the basic clock, but in the fourth embodiment, the circuit is simplified by using two cycles.

  The signal flow is shown in FIG. 18a. The configuration of the shift register (1801), buffer (1802), and control circuit (1803) is not changed. When the output of the Nth stage register becomes active in synchronization with the clock by the active output (1804) from the (N-1) th stage register, the buffer (1805) corresponding to the Nth stage register becomes active. The output (1806) is changed.

  The buffer output (1806) is input to the (N + 2) th control circuit (1807) and the (N-2) th control circuit (1808), and when the Nth stage buffer output becomes active, the (N + 2) th The first control circuit (1807) generates a power supply signal (1809), and the (N-2) th control circuit (1808) generates a power supply stop signal (1810).

  The signal flow after a half cycle of the basic clock from FIG. 18a is shown in FIG. 18b. In the fourth embodiment, the output of the Nth stage register is used as the input of the (N + 1) th stage register instead of the Nth buffer output.

  A time chart is shown in FIG. The clock (1901) captures an input signal, and clock inversion (1902) forms a storage loop.

  The control signal is as shown in (1903), and power is supplied for two cycles of the basic clock.

  The output of the Nth stage register is as shown by the solid line (1904). In the (N + 1) -th stage register, since the signal is captured in the periods (1905) and (1906), it does not have to be the dotted line in (1904). Further, when (1907) is used as a signal input to the buffer for the Nth stage register, no malfunction occurs in the buffer output (1908).

  FIG. 20 shows a circuit diagram. The output of the Nth stage register (2001) becomes the input of the Nth stage buffer (2002) and the (N + 1) th stage register.

  The output of the buffer (2002) becomes the input of the (N + 2) th and (N-2) th control circuits (2003), and generates a control signal.

  In the shift register, P-channel TFTs (2004), (2005), and (2006) that supply power are connected in series to each inverter of the shift register of FIG.

  It is also possible to combine the source electrodes of P-channel TFTs (2007), (2008), and (2009) forming an inverter into one point and connect them to a power source through one P-channel TFT that controls power supply. .

  The buffer circuit (2002) and the control circuit (2003) have the same configuration as that of the second embodiment. That is, the input to the gate electrode of the P-channel TFT (2011) that discharges the Nth control circuit capacitor (2010) is the (N-2) th buffer output, and the P-channel TFT ( The input to the gate electrode 2012) is the (N + 2) th buffer output.

  Here, the P-channel TFTs (2013) and (2014) are clock synchronous analog switches, and the P-channel TFTs (2015) and (2016) are for clear execution.

  Regarding the shift register of this embodiment, the power consumption when used as a peripheral drive circuit of a liquid crystal electro-optical device is compared. The power consumption of one resistor is obtained by dividing the square of the power supply voltage per resistor by the resistance value. In the case of the conventional example shown in FIG. 34, there are three resistors in one stage of the shift register, and power is always supplied to all stages. Therefore, in the case of the conventional type, power consumption increases in proportion to the number of stages of the shift register.

  However, in the case of the peripheral drive circuit shown in the fourth embodiment, there are three resistors in one stage of the shift register, but power is always supplied to only four stages of the shift register, and power is supplied to the other shift registers. Not. Therefore, the power consumption of the peripheral drive circuit can be made extremely small, and the power consumption does not change even if the number of shift register stages is increased.

  Specifically, assuming that a 640-stage shift register is operated with a power supply voltage of 20 V and a resistance of 300 kΩ, and that power supply potential output or ground potential output occurs with a probability of 1/2, power consumption Was 1280 mW in the conventional type, but in the configuration of Example 4, it could be 8 mW.

  In the following Examples 5 to 7, a circuit configuration for setting a power supply voltage to a required value when specifying a pixel is shown. This is also a circuit configuration for lowering the power supply voltage in a non-functioning part.

  Assume that a peripheral driver circuit is configured using a shift register circuit, and a circuit is realized by a one-conductivity type TFT, here a P-channel type TFT and a resistor. FIG. 21 shows a shift register circuit. As shown in FIG. 21, in this embodiment, one stage (2101) is a circuit composed of three inverters (2102), (2103), (2104) and two analog switches (2105), (2106). Point to. Here, (2107) is a buffer for turning on / off the analog switch.

  In FIG. 22, the solid line indicates the power supply voltage that can drive the liquid crystal, and the dotted line indicates the power supply voltage that achieves low power consumption. Considering the voltage change range of the video signal that drives the liquid crystal, the buffer for operating the analog switch requires a power supply voltage of about 20V. Thus, the buffer output for turning on / off the analog switch composed of the P-channel TFT is normally a power supply potential of about 20 V, as shown in (2201), and a ground potential at the time of sampling. Therefore, a waveform (2202) that is normally a ground potential and has a potential of about 20 V during sampling is required as a buffer input.

  Now consider a shift register circuit that produces buffer inputs. The shift register circuit is considered to shift the sampling timing as an input signal. Therefore, when making a sampling timing in the shift register, that is, when an input signal is present in the N-th stage register, if the power supply voltage to the N-th stage register is about 20 V, the buffer analog switch -It is possible to drive the liquid crystal through the video signal. On the other hand, when there is no input signal, the power supply voltage of the shift register circuit can be lowered as long as the shift register circuit does not malfunction. In this circuit configuration, the power supply potential for driving the liquid crystal is not constantly used, and the power supply voltage can be lowered within a range where the logic is not inverted, so that power consumption is reduced.

  FIG. 23 shows a circuit configuration in which a power supply voltage capable of driving a liquid crystal and a power supply voltage realizing low power consumption are supplied to one stage of the shift register circuit (2301). By turning on the P-channel TFT (2302), the power supply voltage (high voltage power supply) that can drive the liquid crystal is used. By turning on the P-channel TFT (2303), the power supply voltage is low. (Low voltage power supply) is supplied.

  FIG. 24 shows a circuit for controlling the power supply circuit. FIG. 24 shows a control circuit corresponding to the Nth stage (2401) of the shift register circuit and a method for extracting a signal for operating the control circuit.

  The capacitor (2402) of the control circuit corresponding to the Nth stage of the shift register circuit operates as follows. When the liquid crystal is charged to a voltage capable of driving, a power supply voltage for reducing power consumption is supplied to the Nth stage of the shift register circuit. On the contrary, when the capacitor is discharged near the ground potential, a power supply voltage capable of driving the liquid crystal is supplied to the Nth stage of the shift register circuit.

  The operation of the control circuit is as follows. First, the P-channel TFT (2403) is turned on in advance, and the capacitor (2402) is charged to a potential capable of driving the liquid crystal. After charging, the P-channel TFT (2403) is turned off. That is, in the initial state, a power supply potential with low power consumption is supplied. The output of the (N-1) th stage register (2404) is connected to the gate electrode of the P-channel TFT (2405) through a buffer.

  As a result, when the input signal reaches the (N−1) -th stage register circuit, the capacitor is discharged near the ground potential. The potential of the capacitor becomes a power supply voltage control signal that can drive the liquid crystal in synchronization with the clock by the P-channel TFT (2406). Furthermore, it becomes a power supply voltage control signal for reducing power consumption via the inverter (2407).

  Therefore, when the capacitor of the control circuit corresponding to the Nth stage register is discharged, the power supply voltage capable of driving the liquid crystal is supplied to the Nth stage register circuit, and the supply of power to reduce power consumption is stopped. Here, when the power supply potential of the shift register becomes low, a control circuit with a high power supply potential malfunctions at the output of the shift register. In order to avoid this, a buffer output that is constantly used at a power supply potential capable of driving the liquid crystal is used.

  Further, since the power supply control signal may simultaneously turn on the P-channel TFTs (2302) and (2303) due to the time delay of the inverter and the power supply may be short-circuited, the power supply that can drive the liquid crystal by the resistor (2408) The voltage control signal is distorted to delay the turning on of the P-channel TFT (2302), thereby avoiding a power supply short circuit.

  Further, the output of the (N + 1) -th stage register (2409) is connected to the gate electrode of the P-channel TFT (2410) through a buffer. When the input signal reaches the (N + 1) -th stage register, the capacitor is charged to a power supply potential capable of driving the liquid crystal. As a result, a power supply voltage with low power consumption is supplied to the Nth stage register circuit, and the supply of power that can drive the liquid crystal is stopped.

  With this circuit configuration, the power supply voltage can be set to a required value only when the analog switch is turned on for sampling. In other cases, power consumption can be reduced in the entire circuit by setting the power supply voltage to low power consumption.

  The power consumption of the peripheral drive circuit of this embodiment is compared. The power consumption of one resistor is obtained by dividing the square of the power supply voltage by the resistance value for each resistor. It is assumed that a voltage of 20V that can drive the liquid crystal is constantly applied to the circuit shown in FIG. It is assumed that there are three resistors per register, the resistance value is 300 kΩ, and a ground potential output or a power supply potential output occurs with a probability of 1/2. If the shift register circuit has a 640-stage configuration and the buffer is removed, the power consumption is 1280 mW. On the other hand, in the present embodiment, it is as follows. The voltage for driving the liquid crystal is 20 V, the voltage for low power consumption is 5 V, four resistors per shift register, and the resistance value is 300 kΩ. Of the 640 stages of the shift register circuit, the power supply voltage capable of driving the liquid crystal is supplied to the second stage, and the power supply voltage for low power consumption is supplied to the 638 stage. From these assumptions, the power consumption can be calculated as 111 mW.

  Thus, power consumption can be reduced with the circuit configuration according to this embodiment.

  In the following embodiments, a circuit configuration is shown in which power is supplied only to a portion where a pixel is specified, and power supply is stopped in a portion where a pixel is not specified. In this embodiment, a peripheral driving circuit that specifies a pixel using a decoder circuit and a counter circuit is assumed.

  The output of the counter circuit (including the inverted output) is passed through a decoder circuit composed of the basic gate circuit shown in FIG. If the decoder circuit is also used as a buffer, the power of the counter circuit is reduced in order to reduce power consumption. Since it is impossible to separate the counter circuit into a part for specifying pixels and a part for which pixels are not specified in the circuit configuration shown in FIG. 37, the counter circuit is divided.

  An address corresponding to a signal line or a scanning line is not generated by one counter, but a counter circuit with a small number of bits is used as shown in FIG. The necessary number of counter circuits are prepared, and they are sequentially operated to generate a local address, thereby specifying a pixel. As a result, power supply to the counter circuit that does not need to be operated can be stopped. Here, (2501) is a pixel matrix, (2502) is a divided counter circuit, (2503) is a decoder circuit, and (2504) is a control circuit.

  FIG. 26 shows the divided counter circuit, decoder circuit, and control circuit. When a ripple carry occurs in the (N−1) th counter circuit (2601), the Nth counter circuit (2602) starts to supply power, and the (N + 1) th counter circuit (2603) counts. When started, the supply of power to the Nth counter circuit is stopped.

  The control circuit is the same as that of the fifth embodiment. One conductivity type TFT for initial setting, here a P-channel TFT (2604), a P-channel TFT (2605) for discharging a capacitor to start power supply, and power supply It is composed of a P-channel TFT (2606) for charging the capacitor to stop and a capacitor (2607) for memory retention. The output value of the Nth counter circuit is indefinite when power is supplied. Accordingly, when the ripple carry of the (N-1) th counter circuit occurs and the supply of power is started, the clear is executed. A circuit for generating a clear signal is composed of a P-channel TFT (2608).

  A circuit for supplying power can be realized by connecting a P-channel TFT in series between the source electrode of the P-channel TFT in FIG. 22 and the power supply, and controlling the power supply with the P-channel TFT. In FIG. 26, P-channel TFTs additionally connected in series are collectively shown as a P-channel TFT (2609). An enable signal for the Nth counter circuit (2602) is supplied by a P-channel TFT (2609).

  The power supply stop of the Nth counter circuit uses the output of the decoder circuit (2610) that detects the minimum value output of the (N + 1) th counter circuit.

  FIG. 27 shows a timing chart of the Nth counter circuit. Immediately after the power supply (2701) is turned on, a clear signal (2703) of the Nth counter circuit is formed by the ripple carry (2702) of the (N-1) th counter circuit. The output (2704) of the Nth counter circuit is input to the decoder circuit to generate a decode signal (2705). The power supply to the Nth counter circuit is stopped at the next clock pulse that outputs the ripple carry.

  The power consumption of the peripheral drive circuit of this embodiment is compared. The power consumption of one resistor is obtained by dividing the square of the power supply voltage by the resistance value for each resistor. If an address signal is generated for 640 pixels, a 10-bit counter is required. One counter bit corresponds to one JK flip-flop, and 10 gates are required for one JK flip-flop. Therefore, there are only 100 JK flip-flops for connecting the power source and the ground. In addition, 16 gates are required, and there is one resistor for connecting the power source and the ground for one gate. Therefore, a total of 116 resistors connect the power source and the ground. The resistance value is 300 kΩ and the power supply voltage is 20V. The ground potential output or the power supply potential output occurs with a probability of 1/2. Excluding the decoder circuit also serving as a buffer, the power consumption is 77 mW.

  On the other hand, in the present embodiment, it is as follows. Since the 4-bit counter is sequentially used regardless of the number of pixels, it can be considered that the 4-bit counter is normally operating. That is, there are four JK-flip flops and ten resistors per JK-flip flop. In addition, since eight gates are required between the JK-flip flops, the total number of resistors that connect the power source and the ground is 48. The resistance value is 300 kΩ and the power supply voltage is 20V. The ground potential output or the power supply potential output occurs with a probability of 1/2. From this assumption, the power consumption is 32 mW except for the decoder circuit also serving as a buffer.

  Further, as the number of scanning lines or signal lines increases, the power consumption increases logarithmically in the case of the peripheral drive circuit configuration including only the decoder circuit and the counter circuit. Does not occur. Thus, it can be seen that the power consumption can be reduced with the circuit configuration according to the present embodiment.

  In the following embodiment, a circuit configuration for setting a power supply voltage to a required value when specifying a pixel is shown. This is also a circuit configuration for lowering the power supply voltage in a non-functioning part.

  As in the sixth embodiment, the present embodiment assumes a peripheral drive circuit that specifies a pixel using a decoder circuit and a counter circuit. However, the counter circuit has a 6-bit output.

  FIG. 28 shows a circuit configuration. The control circuit (2801) has the same configuration as that of the fifth embodiment. The signal for starting power supply to the Nth counter circuit (2802) uses the ripple carry of the (N-1) th counter circuit (2803). The signal for stopping power supply to the Nth counter circuit uses the output of the decoder circuit (2805) that detects the minimum value output of the (N + 1) th counter circuit (2804). As an enable signal for the Nth counter circuit, a signal for controlling a power supply voltage with low power consumption is used. From now on, the Nth counter circuit is in a clear state and waits for the next enable signal to become active. Therefore, it is not necessary to execute clear even when the power supply voltage changes.

  The power consumption of the peripheral drive circuit of this embodiment is compared. The power consumption of one resistor is obtained by dividing the square of the power supply voltage by the resistance value for each resistor. If an address signal is generated for 640 pixels, a 10-bit counter is required. One counter bit corresponds to one JK-flip-flop, and 10 gates are required for one JK-flip-flop. Therefore, there are only 100 resistors that are connected to the power supply and the ground. In addition, 16 gates are required, and there is one resistor for connecting the power source and the ground for one gate. Therefore, a total of 116 resistors are connected to the power source and the ground. The resistance value is 300 kΩ and the power supply voltage is 20V. The ground potential output or the power supply potential output occurs with a probability of 1/2. Excluding the decoder circuit also serving as a buffer, the power consumption is 77 mW.

  On the other hand, in the present embodiment, it is as follows. Eleven 6-bit counters are required for 640 pixels. Among these, a voltage of 20V that can drive a liquid crystal is supplied to one, and a voltage of 5V that reduces power consumption is supplied to the remaining ten. In the 6-bit counter circuit, there are six JK flip-flops and ten resistors per JK flip-flop. Further, since 12 gates are required between the JK-flip flops, a total of 72 resistors connect the power source and the ground. It is assumed that the resistance value is set to 300 kΩ and the ground potential output or the power supply potential output occurs with a probability of 1/2. From this assumption, the power consumption is 62 mW except for the decoder circuit also serving as a buffer. With the circuit configuration according to this embodiment, power consumption can be reduced.

It is a schematic block diagram of the liquid crystal electro-optical apparatus for demonstrating the effect | action of this invention. It is a block circuit diagram of a shift register for explaining the operation of the present invention. It is a block diagram of the shift register of Examples 1-4. It is a timing chart figure of the input-output signal of the shift register of Examples 1-4. 3 is a block circuit diagram of the shift register of Embodiment 1. FIG. 3 shows a timing chart of a shift register. It is a block diagram of a decoder circuit. It is a block diagram of a power supply circuit. It is a block diagram of a clear circuit. It is a block diagram of a clock supply circuit. 6 is a block circuit diagram of a shift register of Embodiment 2. FIG. It is a schematic diagram which shows operation | movement of a shift register. It is a timing chart figure of 1 stage of registers. It is a block diagram of a control circuit. It is a block diagram of 1 stage of shift registers and 1 stage of buffers. FIG. 12 is a timing chart of one stage of the register according to the third embodiment. It is a block diagram of a register, a clock selection circuit, and a buffer. FIG. 10 is a block diagram illustrating the operation of a shift register according to a fourth embodiment. It is a timing chart figure of 1 stage of registers. It is a block diagram of 1 stage of shift registers, a control circuit, and 1 stage of buffers. FIG. 10 is a configuration diagram of a shift register using a one-conductivity type TFT according to a fifth embodiment. It is a timing chart figure of a shift register. It is a block diagram of the power supply voltage switching circuit by one conductivity type TFT. It is a block diagram of another power supply voltage switching control circuit. FIG. 16 is a configuration diagram of a divided counter and decoder according to the sixth embodiment. FIG. 10 is a configuration diagram of a power supply stop type counter and a control circuit according to a sixth embodiment. FIG. 10 is a configuration diagram of a timing chart of a counter circuit according to a sixth embodiment. FIG. 10 is a configuration diagram of a power supply voltage drop counter and a control circuit according to a seventh embodiment. FIG. 6 is a configuration diagram of a peripheral drive circuit of a liquid crystal electro-optical device of Conventional Example 1. It is a block diagram of the shift register comprised by the clocked inverter, and the shift register comprised by the transmission gate. It is a block diagram of a signal line drive circuit using an address decoder. It is a block diagram of a signal line drive circuit using a counter and an address decoder. It is a block diagram of the shift register of the clocked inverter structure of a CMOS circuit. It is a block diagram of the shift register comprised by P channel type TFT and resistance. It is a block diagram of the basic gate circuit by one conductivity type TFT. It is a block diagram of a JK-flip flop. It is a block diagram of a 4-bit counter.

Explanation of symbols

101: Display matrix unit 102, 108: Shift registers 103, 106, 107, 110-112 ... Shift register block 104, 109 ... Buffer 105 ... Sampling circuit 401 ... Shift register 402 ˜404... Shift register block 405... Control circuit 406, 407... Power supply stop signal 408... Power supply signal 409.

Claims (4)

A display device having a pixel portion and a peripheral drive circuit for driving the pixel portion,
The peripheral drive circuit includes a shift register configured by connecting a plurality of registers, a power supply circuit that supplies power to the register, and a control circuit that controls the power supply circuit,
The control circuit includes:
A resistor connected to a power source; a first P-channel thin film transistor; a second P-channel thin film transistor; a third P-channel thin film transistor; and a capacitor;
The source electrode of the first P-channel type thin film transistor and the source electrode of the second P-channel type thin film transistor are connected to the power source through the resistor,
The drain electrode of the first P-channel thin film transistor and the drain electrode of the second P-channel thin film transistor are connected to the source electrode of the third P-channel thin film transistor and one electrode of the capacitor,
The drain electrode of the third P-channel type thin film transistor and the other electrode of the capacitor are connected to the ground,
When an input signal is applied to the Nth register that identifies the Nth [N is a natural number] pixel in the pixel portion of the peripheral drive circuit, the (N + x) th [x ≧ 2] th pixel is applied. The power supply to the (N + x) th and subsequent registers that specify pixels and the (Ny) th and previous registers that specify the (N−y) th [y ≧ 2] pixels are stopped. ,
In the Nth control circuit,
A control signal from the (N + x + 1) th register is input to the gate electrode of the second P-channel thin film transistor,
A control signal from the (N−y) th register is input to the gate electrode of the third P-channel thin film transistor,
Display device comprising Rukoto outputs control signals to the power supply circuit for supplying power to the registers from one of the electrodes the N-th of the capacitor. A display device having a pixel portion and a peripheral drive circuit for driving the pixel portion,
The peripheral drive circuit includes a shift register configured by connecting a plurality of registers, a power supply circuit that supplies power to the register, and a control circuit that controls the power supply circuit,
The control circuit includes:
A resistor connected to a power source; a first P-channel thin film transistor; a second P-channel thin film transistor; a third P-channel thin film transistor; and a capacitor;
The source electrode of the first P-channel type thin film transistor and the source electrode of the second P-channel type thin film transistor are connected to the power source through the resistor,
The drain electrode of the first P-channel thin film transistor and the drain electrode of the second P-channel thin film transistor are connected to the source electrode of the third P-channel thin film transistor and one electrode of the capacitor,
The drain electrode of the third P-channel type thin film transistor and the other electrode of the capacitor are connected to the ground,
When an input signal is applied to the Nth register that identifies the Nth [N is a natural number] pixel in the pixel portion of the peripheral drive circuit, the (N + x) th [x ≧ 2] th pixel is applied. Supply power is reduced for the (N + x) th and subsequent registers that specify pixels and the (Ny) th and previous registers that specify the (N−y) th [y ≧ 2] pixels. ,
In the Nth control circuit,
A control signal from the (N + x + 1) th register is input to the gate electrode of the second P-channel thin film transistor,
A control signal from the (N−y) th register is input to the gate electrode of the third P-channel thin film transistor,
Display device comprising Rukoto outputs control signals to the power supply circuit for supplying power to the registers from one of the electrodes the N-th of the capacitor. A driving method of a display device having a pixel portion and a peripheral driving circuit for driving the pixel portion,
The peripheral drive circuit includes a shift register configured by connecting a plurality of registers, a power supply circuit that supplies power to the register, and a control circuit that controls the power supply circuit,
The control circuit includes:
A resistor connected to a power source; a first P-channel thin film transistor; a second P-channel thin film transistor; a third P-channel thin film transistor; and a capacitor;
The source electrode of the first P-channel type thin film transistor and the source electrode of the second P-channel type thin film transistor are connected to the power source through the resistor,
The drain electrode of the first P-channel thin film transistor and the drain electrode of the second P-channel thin film transistor are connected to the source electrode of the third P-channel thin film transistor and one electrode of the capacitor,
The drain electrode of the third P-channel type thin film transistor and the other electrode of the capacitor are connected to the ground,
When an input signal is applied to the Nth register for specifying the Nth [N is a natural number] pixel in the pixel portion in the peripheral drive circuit, the (N + 1) th pixel is specified. A control signal for supplying power to the (N + 1) th register is output from the (N + 1) th control circuit;
A control signal for stopping power supply to the (N-2) th register for specifying the (N-2) th pixel is output from the (N-2) th control circuit ;
In the Nth control circuit,
A control signal from the (N + 3) th register is input to the gate electrode of the second P-channel thin film transistor,
A control signal from the (N−2) th register is input to the gate electrode of the third P-channel thin film transistor,
A method for driving a display device, comprising: outputting a control signal to a power supply circuit that supplies power from one electrode of the capacitor to the Nth register . A driving method of a display device having a pixel portion and a peripheral driving circuit for driving the pixel portion,
The peripheral drive circuit includes a shift register configured by connecting a plurality of registers, a power supply circuit that supplies power to the register, and a control circuit that controls the power supply circuit,
The control circuit includes:
A resistor connected to a power source; a first P-channel thin film transistor; a second P-channel thin film transistor; a third P-channel thin film transistor; and a capacitor;
The source electrode of the first P-channel type thin film transistor and the source electrode of the second P-channel type thin film transistor are connected to the power source through the resistor,
The drain electrode of the first P-channel thin film transistor and the drain electrode of the second P-channel thin film transistor are connected to the source electrode of the third P-channel thin film transistor and one electrode of the capacitor,
The drain electrode of the third P-channel type thin film transistor and the other electrode of the capacitor are connected to the ground,
When an input signal is applied to the Nth register for specifying the Nth [N is a natural number] pixel in the pixel portion in the peripheral drive circuit, the (N + 1) th pixel is specified. A control signal for supplying power to the (N + 1) th register is output from the (N + 1) th control circuit;
From the (N-2) th control circuit, a control signal for reducing the supply power is output to the (N-2) th register that identifies the (N-2) th pixel ,
In the Nth control circuit,
A control signal from the (N + 3) th register is input to the gate electrode of the second P-channel thin film transistor,
A control signal from the (N−2) th register is input to the gate electrode of the third P-channel thin film transistor,
A method for driving a display device, comprising: outputting a control signal to a power supply circuit that supplies power from one electrode of the capacitor to the Nth register .

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