JP3989639B2 - IC test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC test apparatus for testing a mixed IC including an AD converter or DA converter among semiconductor integrated circuit elements.
[0002]
[Prior art]
FIG. 3 shows a schematic configuration of a general IC test apparatus. The IC test apparatus shown in FIG. 3 mainly shows the configuration of an IC test apparatus for testing a hybrid IC including a digital IC such as a memory or a logic circuit. In the figure, TES indicates the entire IC test apparatus. The IC test apparatus TES includes a main controller 111, a pattern generator 112, a timing generator 113, a waveform formatter 114, a logic comparator 115, a driver 116, an analog comparator 117, a failure analysis memory 118, a logic amplitude reference voltage source 121, The reference voltage source 122, the device power source 123, and the like are included.
[0003]
The main controller 111 is generally constituted by a computer system. The main controller 111 mainly controls the pattern generator 112 and the timing generator 113 according to a test program created by a user, and generates test pattern data from the pattern generator 112. Data is converted into a test pattern signal having an actual waveform by the waveform formatter 114, and the test pattern signal is applied to the IC 119 under test through a driver 116 that amplifies the voltage to a waveform having an amplitude value set by the logic amplitude reference voltage source 121. Remember.
[0004]
The response signal read from the IC under test 119 is compared with the reference voltage supplied from the comparison reference voltage source 122 by the analog comparator 117, and whether or not it has a predetermined logic level (H logic voltage, L logic voltage). The signal determined to have a predetermined logic level is compared with the expected value output from the pattern generator 112 by the logic comparator 115, and if a mismatch with the expected value occurs, the read address It is determined that there is a defect in the memory cell, a defect address is stored in the defect analysis memory 118 every time a defect occurs, and it is determined whether or not the defective cell can be repaired at the end of the test, for example.
[0005]
Here, the timing generator 113 determines the timing for defining the rising timing and the falling timing of the waveform of the test pattern signal applied to the IC 119 to be tested, and the timing of the strobe pulse that defines the timing of the logical comparison by the logic comparator 115. appear.
Each of these timings is described in a test program created by the user, and the IC under test 119 is operated at a timing intended by the user, and whether or not the operation is normal can be tested.
[0006]
The waveform formatter 114, the driver 116, the analog comparator 117, the logic comparator 115, and the failure analysis memory 118 shown in FIG. 3 are provided for the number of pins that can be tested by the IC test apparatus, and which pins are input-only pins. Or even if it is assigned to an output-only pin, an input / output pin, and a power supply pin, it is configured so that it can cope with it.
Generally, an IC test apparatus generally has a testable number of pins of about 256 pins to 512 pins.
[0007]
[Problems to be solved by the invention]
By the way, when testing an IC having an AD converter, for example, among the ICs, each bit signal of the AD conversion output output from the AD converter is sequentially fetched into the memory in the output order, for example, for one cycle of an analog waveform. A method is adopted in which digital data is taken into a memory and the AD converter is evaluated by analyzing the data in the state taken in the memory.
[0008]
For this purpose, the logic comparator 115 is set to a through state (the input signal is output as it is), only the analog comparator 117 is compared, and the AD analysis output is taken into the failure analysis memory 118.
However, generally, in a test such as a logic IC, since the storage capacity of the failure analysis memory 118 is small, data for one cycle of an analog waveform cannot be taken into the failure analysis memory 118.
[0009]
For this reason, conventionally, as shown in FIG. 4, a large-capacity memory 130 is provided in place of the failure analysis memory 118, and data of each bit of the AD converter is written into the large-capacity memory 130 or several bits worth of data. The AD converter output for several bits is stored in the large-capacity memory 130, and the AD converter is evaluated by analyzing the AD conversion output fetched in the large-capacity memory 130.
[0010]
FIG. 5 shows an IC test apparatus for testing an IC equipped with a DA converter. In this case, an AD converter 140 is provided. The AD converter 140 converts an analog signal output from the IC under test 119 into a digital signal, and each bit signal output from the AD converter 140 is stored in the large-capacity memory 130. The configuration is memorized.
For this reason, when testing an IC equipped with either an AD converter or a DA converter, the large-capacity memory 130 must be mounted in addition to the failure analysis memory 118. An IC test apparatus configured to be able to test a mounted mixed IC has a drawback that the manufacturing cost increases.
[0011]
An object of the present invention is to provide an inexpensive IC test apparatus capable of testing a mixed IC equipped with an AD converter or a DA converter.
[0012]
[Means for Solving the Problems]
In the present invention, a failure analysis memory which is not in use in a failure analysis memory provided for each pin is connected in cascade to form a large-capacity memory, and this large-capacity memory has an AD conversion output or a DA conversion. The present invention proposes an IC test apparatus capable of storing AD conversion data obtained by performing AD conversion on an output again and evaluating an AD converter or a DA converter mounted on an IC under test.
[0013]
Therefore, according to the IC test apparatus of the present invention, since a large capacity memory is not required in addition to the failure analysis memory, there is an advantage that it can be manufactured at low cost.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows the configuration of the main part of an IC test apparatus according to the present invention. In the present invention, the AD converter output signal taken out from one output terminal AD _OUT1 of the AD converter of the IC 119 to be tested is input to the selector 150 through the analog comparator 117 and the logical comparator 115 set to the through state. 150 is distributed to a plurality of defect analysis memories 118A to 118N in a non-use state, and AD conversion output signals are taken into the plurality of defect analysis memories 118A to 118N in a cascade manner.
[0015]
FIG. 1 shows a configuration for storing an output signal for one bit of the AD converter. The defect analysis memories 118A to 118N are provided in the channels of all testable pins of the IC test apparatus, as described in the part describing the entire IC test apparatus shown in FIG. Therefore, most of the failure analysis memories 118A to 118N mounted on the IC test apparatus are not in use. Incidentally, an IC test apparatus having 500 pins that can be tested is equipped with 500 defect analysis memories 118, but the number of defect analysis memories actually used is very small. .
[0016]
The present invention pays attention to this point and adopts a method of storing the bit data output to each output pin of the AD converter using the failure analysis memories 118A to 118N in the unused state in cascade. The use of large-capacity memory is unnecessary. Select first failure analysis memory 118A by the selector 150 in the example shown in FIG. 1, the failure analysis memory 118A to store for example the least significant bit data is output to the output terminal AD _OUT1 of mounting the AD converter under test IC119 Let
[0017]
When the failure analysis memory 118A outputs the overflow signal FULL, the overflow signal FULL is input to the select controller 151 through the OR gate OR, and the selector controller 151 controls the selector 150 to switch to the state of selecting the failure analysis memory 118B. When the failure analysis memory 118B overflows, the selector 150 switches to the failure analysis memory 118C and stores data in the failure analysis memory 118C. Output terminals AD _OUT2 of the AD converter, AD _OUT3 ... are also intended to be stored using the failure analysis memory 118 in the same manner to the unused state.
[0018]
Reference numeral 152 denotes a register that stores the address of the failure analysis memory in the unused state. Each time the overflow signal FULL is input from the OR gate OR to the select controller 151, the address of the next failure analysis memory in the unused state is designated, and the selector 150 selects the failure analysis memory according to the address. Show.
[0019]
FIG. 2 shows an embodiment of an IC test apparatus for evaluating whether or not an analog signal output from the DA converter is normal when the DA converter is mounted in the IC 119 to be tested.
In this case, an analog signal output from the DA conversion output terminal DA _{OUT of the} IC under test 119 is input to the AD converter 140 and converted into a digital signal by the AD converter 140. Each bit signal output from the AD converter 140 (showing the configuration of one bit in FIG. 2) is stored in the failure analysis memories 118A, 118B, 118C,. .
[0020]
By configuring in this way, there is an advantage that an evaluation test can be executed only with a failure analysis memory even with an IC equipped with a DA converter.
[0021]
【The invention's effect】
As described above, according to the present invention, a mixed IC equipped with an AD converter or a DA converter stores, for example, digital data for one cycle of an output digital signal or analog signal in a memory, and the digital data In the IC test apparatus for analyzing the operation of the AD converter or the DA converter and evaluating the operation of the AD converter or DA converter, the IC test apparatus uses a failure analysis memory in an unused state as a memory for storing data for one cycle of the analog waveform. The increase in the manufacturing cost of the IC is negligible compared to that of an IC test apparatus that only tests a general memory, and there is an advantage that it can be manufactured at a lower cost than an IC test apparatus equipped with a conventional large-capacity memory. can get.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an IC test apparatus according to the present invention.
FIG. 2 is a block diagram showing a modified embodiment of the IC test apparatus according to the present invention.
FIG. 3 is a block diagram for explaining the entire IC test apparatus.
FIG. 4 is a block diagram for explaining a conventional technique.
FIG. 5 is a block diagram for explaining another example of the prior art.
[Explanation of symbols]
115 Logical Comparator 117 Analog Comparator 118A to 118N Failure Analysis Memory 119 IC under Test
140 AD converter 150 Selector 151 Select controller 152 Register

Claims (2)

The output of each bit of the above-mentioned AD converter of the IC under test having the AD converter is taken into a large-capacity memory as a signal under test, and the AD converter is evaluated by analyzing the signal under test fetched into the large-capacity memory. In IC test equipment,
An analog comparator that compares the signal output from the output terminal of the AD converter with a reference value and outputs data determined to have a predetermined logic level;
A register for storing the address of the failure analysis memory in the unused state and notifying this address to the select controller;
Based on the address specified by the select controller, a selector that distributes the output of the analog comparator to the plurality of unused failure analysis memories in a cascade manner;
A plurality of failure analysis memories for storing output data from the selector and outputting a FULL signal to the select controller when overflowing;
Each time the FULL signal is input, the select controller that specifies the address of the next non-use defect analysis memory to the selector;
An IC test apparatus comprising: The analog signal output from the DA converter of the IC under test with the DA converter is AD-converted by the AD converter, and the AD conversion output is taken into the large-capacity memory as the signal under test and taken into the large-capacity memory. In an IC test apparatus for analyzing a signal under test and evaluating a DA converter,
An analog comparator that compares the signal output from the output terminal of the AD converter with a reference value and outputs data determined to have a predetermined logic level;
A register for storing the address of the failure analysis memory in the unused state and notifying this address to the select controller;
Based on the address specified by the select controller, a selector that distributes the output of the analog comparator to the plurality of unused failure analysis memories in a cascade manner;
A plurality of failure analysis memories for storing output data from the selector and outputting a FULL signal to the select controller when overflowing;
Each time the FULL signal is input, the select controller that specifies the address of the next non-use defect analysis memory to the selector;
An IC test apparatus comprising:

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