JP3977676B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a high voltage semiconductor element such as a punch-through IGBT (PT-IGBT) and a method for manufacturing the same.
[0002]
[Prior art]
An IGBT (Insulated Gate Bipolar Transistor) is known as one of high voltage semiconductor devices. FIG. 10 shows a cross-sectional view of a conventional punch-through IGBT. In the figure, reference numeral 81 denotes a high-resistance n ⁻ -type base layer, and a p-type base layer 82 is formed in the n ⁻ -type base layer 81. An n-type emitter layer 83 is formed in the p-type base layer 82.
[0003]
On the p-type base layer 82 sandwiched between the n-type emitter layer 83 and the n ⁻ -type base layer 81, a gate electrode 85 is provided via a gate insulating film 84. The gate electrode 85 is made of, for example, polysilicon.
[0004]
The emitter electrode 86 is connected to the n-type emitter layer 83 and the p-type base layer 82 through a contact hole opened in the interlayer insulating film 87. The emitter electrode 86 is made of a metal such as Al. Further, the surface of the n ⁻ -type base layer 81 including the gate electrode 85 and the emitter electrode 86 is covered with a passivation film (not shown).
[0005]
On the other hand, a p ⁺ type collector layer 89 is provided on the back surface of the n ⁻ type base layer 81 via an n ⁺ type buffer layer 88. A collector electrode 90 is provided on the p ⁺ -type collector layer 89. The collector electrode 90 is made of a metal such as Al.
[0006]
However, this type of PT-IGBT has the following problems. The PT-IGBT shown in FIG. 10 is manufactured using a thick epitaxial wafer in which an n ⁺ -type buffer layer 88 and an n ⁻ -type base layer 81 are previously formed on a p ⁺ -type collector layer 89.
[0007]
Specifically, first, an n ⁺ -type buffer layer 88 having a thickness of 15 μm and an n ⁻ -type base layer 81 having a thickness of 60 μm are sequentially epitaxially grown on a p ⁺ -type collector layer 89 having a thickness of 625 μm. An epitaxial wafer is formed. Next, the back surface of the p ⁺ -type collector layer 89 is polished so that the thickness of the p ⁺ -type collector layer 89 is reduced to 175 μm and used as a substrate.
[0008]
However, it is expensive to produce such an epitaxial wafer having a thickness of 700 μm, and the PT-IGBT shown in FIG. 10 is expensive.
[0009]
In order to solve such a problem, the present inventors considered using a normal wafer in which the n ⁺ type buffer layer 88 and the p ⁺ type collector layer 89 are not formed in advance.
[0010]
That is, after forming a p-type base layer 82, an n-type emitter layer 83, a gate insulating film 84, a gate electrode 85, an interlayer insulating film 87, an emitter electrode 86, and a passivation film (not shown) on the surface of the wafer, an n ⁻ type is formed. N-type impurity ions and p-type impurity ions are sequentially implanted into the back surface of the base layer 81, and subsequently, a laser is irradiated from the back surface of the n ⁻ -type base layer 81 in order to activate these n-type and p-type impurities. An attempt was made to form the n ⁺ -type buffer layer 88 and the p ⁺ -type collector layer 89.
[0011]
However, since the melting depth by this type of laser irradiation (laser annealing) is within several μm and the irradiation time is short, the heat from the laser is not sufficiently transferred into the n ⁺ -type buffer layer 88, and n ⁺ A damage layer due to ion implantation or the like remains in the mold buffer layer 88. As a result, the collector-emitter saturation voltage (V _CE (sat)) increases in the element-on state, while a leak current occurs in the element-off state. Degradation of device characteristics occurs.
[0012]
The reason why V _CE (sat) increases is that, in the on state, the damaged layer functions as a hole injection trap. The reason why the leak current is generated is that, as shown in FIG. 11, when the damage layer 91 is depleted in the off state, it acts as a carrier generation center.
[0013]
One method for solving the problem caused by the remaining damage layer is to reduce the acceleration energy of the n-type impurity implanted into the n ⁺ -type buffer layer 88. This is because, as shown in FIG. 12, the activation rate of the n-type impurity increases as the acceleration energy Vacc decreases.
[0014]
Here, when the acceleration energy of the n-type impurity is reduced, the depth of the n ⁺ -type buffer layer 88 becomes shallow accordingly. For this reason, the influence of the diffusion of the p ⁺ type impurity on the concentration profile of the impurity in the n ⁺ type buffer layer 88 is increased, and the controllability of the concentration profile is lowered.
[0015]
A decrease in the controllability of the density profile leads to the following problems. When the controllability of the concentration profile is lowered, it becomes difficult or impossible to form the n ⁺ -type buffer layer 88 and the p ⁺ -type collector layer 89 having a desired concentration profile. As a result, desired device characteristics cannot be obtained, or the concentration profile varies depending on the device, and the device characteristics vary.
[0016]
In any case, since this type of PT-IGBT has its n ⁺ -type buffer layer and p ⁺ -type collector layer formed by ion implantation and laser annealing, V _CE (sat) increases or n ⁺ -type The controllability of the impurity concentration profile in the buffer layer is degraded.
[0017]
[Problems to be solved by the invention]
As described above, in this type of PT-IGBT, since the n ⁺ type buffer layer and the p ⁺ type collector layer are formed by ion implantation and laser annealing, V _CE (sat) increases or the n ⁺ type buffer layer increases. There is a problem that the controllability of the impurity concentration profile in the layer is lowered.
[0018]
Therefore, an object of the present invention is to provide a semiconductor device including a high breakdown voltage semiconductor element such as PT-IGBT and the method for manufacturing the same, which can suppress such deterioration of element characteristics and controllability of the concentration profile. .
[0019]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention is provided with a first base layer having a first conductivity type and a first base layer having a high resistance and provided in the first surface. A second base layer having a second conductivity type, an emitter layer provided in the second conductivity type base layer and having the first conductivity type, the emitter layer, and the first base layer; A gate electrode provided on the second base layer sandwiched by a gate insulating film, and a buffer layer provided on the second surface, having a high impurity concentration and having the first conductivity type And a collector layer provided in the buffer layer and having the second conductivity type,
(Density of activated first conductivity type impurities in the buffer layer by SR analysis [cm ⁻² ]) / (Density of first conductivity type impurities in the buffer layer by SIMS analysis [cm ⁻² ]) The first activation rate is 25% or more,
And (density of activated second conductivity type impurities in the collector layer by SR analysis [cm ⁻² ]) / (density of second conductivity type impurities in the collector layer by SIMS analysis [cm ⁻² ]) The defined second activation rate is higher than 0% and 10% or less.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0021]
1 to 6 are cross-sectional views showing a method for manufacturing a PT-IGBT according to an embodiment of the present invention.
[0022]
First, as shown in FIG. 1, an insulating film to be the gate insulating film 2 and a conductive film to be the gate electrode 3 are sequentially deposited on the surface of the n ⁻ type base layer 1, and then the conductive film and the insulating film are patterned. To do. The gate insulating film 2 is formed of, for example, a silicon oxide film and the gate electrode 3 is formed of, for example, polysilicon.
[0023]
As shown in FIG. 2, a p-type base layer 4 is formed in the n ⁻ -type base layer 1 in a self-aligned manner, and then an n-type emitter layer 5 is formed in the p-type base layer 4.
[0024]
As shown in FIG. 3, an interlayer insulating film 6 is deposited on the entire surface, contact holes are formed in the interlayer insulating film 6, and then an emitter electrode 7 that contacts the p-type base layer 4 and the n-type emitter layer 5 is formed. The emitter electrode 7 is made of Al, for example. It is preferable to form the emitter electrode 7 via the barrier metal film, instead of directly forming the emitter electrode 7 on the p-type base layer 4 and the n-type emitter layer 5.
[0025]
Thereafter, the surface of the n ⁻ -type base layer 1 including the gate electrode 3 and the emitter electrode 7 is covered with a passivation film (not shown) such as a polyimide film, and the n ⁻ -type base layer 1 is thinned according to the specified breakdown voltage. This is performed by polishing the back surface of the n ⁻ -type base layer 1. This polishing is performed by, for example, a CMP (Chemical Mechanical Polishing) method. Another method for thinning the n ⁻ -type base layer 1 is a method using mechanical polishing and wet etching. Mechanical polishing is performed first.
[0026]
As shown in FIG. 4, after implanting n-type impurity ions such as phosphorus on the back surface of the n ⁻ -type base layer 1 under the conditions of a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 160 KeV, for example, an energy density of 2. Excimer laser is irradiated on the back surface of the n ⁻ -type base layer 1 under the condition of 5 J / cm ² . n ^- by performing -type base layer 1 of the laser annealing melting the following areas 2μm from the back surface (first annealing), n ^- the back surface of the mold base layer 1 to form an n ⁺ -type buffer layer 8. The laser annealing temperature at this time is equal to or higher than the melting temperature of silicon, for example, 1300 ° C. or higher.
[0027]
The n ⁺ -type buffer layer 8 thus formed satisfies the activation rate a (first activation rate) ≧ 25% and has a thickness of 2 μm or less from the back surface of the n ⁻ -type base layer 1. is doing. The back surface of the n ⁻ type base layer 1 becomes the surface of the p ⁺ type collector layer 9 in the step of FIG.
[0028]
Here, the activation rate a is (density of the n-type impurity in the activated n ⁺ -type buffer layer 8 obtained by SR (spreading resistance) analysis [cm ⁻² ]) / (SIMS (Secondary Ion Mass Spectrometry). ) The density of n-type impurities in the n ⁺ -type buffer layer 8 obtained by analysis [cm ⁻² ]).
[0029]
The SR analysis is a well-known technique, but will be briefly described as follows. That is, if the distance between the two needles is sufficiently small (several tens to several hundreds of micrometers) and the radius of the surface where the tip contacts the sample is a, the relationship between the spreading resistance (Rs) and the specific resistance (ρ) Is given by Rs = ρ / 2a.
[0030]
FIG. 7 shows a state in which SR analysis is performed with an apparatus having a needle interval of 20 μm after obliquely polishing a pn junction subjected to impurity diffusion. In the figure, DOPING TYPE II corresponds to the n ⁺ type buffer layer 8, and DOPING TYPE I corresponds to the p ⁺ type collector layer 9 formed in a later process.
[0031]
Regard n ⁺ -type buffer layer 8 formed as described above, obtained in SR analysis, the activated n-type impurity density [cm ^-2] and the density of the n-type impurity obtained by the SIMS analysis [cm ^{- 2} ] is 2.7 × 10 ¹⁴ cm ⁻² and 1 × 10 ¹⁵ cm ⁻² , respectively, and the ratio thereof, that is, the activation rate a is a ≧ 25%.
[0032]
The reason why the activation rate a is set to 25% or more is that, as shown in FIG. 9, it has become clear that V _CE (sat) becomes sufficiently small in a region where a ≧ 25% or more. As for the leakage characteristics, it was confirmed that the leakage current was sufficiently small in the region where a ≧ 25%.
[0033]
Next, as shown in FIG. 5, boron ions (B ⁺ ) are implanted into the surface of the n ⁺ -type buffer layer 8 under the conditions of a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 50 KeV.
[0034]
Here, it is preferable that the amount of boron implanted is such a value that part of the p ⁺ -type collector layer 9 can be made amorphous by boron ion implantation. The reason is that, at the same annealing temperature, the activation rate of implanted boron ions is higher in the amorphous state, which is a continuous disorder, than in a layer including a partial disorder. It is.
[0035]
Specifically, when the dose amount [cm ⁻² ] of the p-type impurity in the region within 2 μm from the surface of the p ⁺ -type collector layer 9 is 1 × 10 ¹⁵ cm ⁻² , activation after sintering at 450 ° C. The rate b (second activation rate) is about 3%, and when the dose [cm ⁻² ], which is a smaller value, is 1 × 10 ¹⁴ , the activation rate b is less than 1%.
[0036]
That is, with respect to the p ⁺ -type collector layer 9, when the dose amount [cm ⁻² ] of the p-type impurity is 1 × 10 ¹⁵ cm ⁻² , the density [cm ^-2 ] and the density [cm ^-2 ] of the p-type impurity obtained by SIMS analysis are 3 × 10 ¹³ cm ^-2 and 1 × 10 ¹⁵ cm ^-2 , respectively, and the ratio thereof, that is, the activation rate b Is about 3%.
[0037]
Further, when the dose amount [cm ⁻² ] of the p-type impurity is 1 × 10 ¹⁴ cm ⁻² , the density of the activated p-type impurity obtained by SR analysis and the density of the p-type impurity obtained by SIMS analysis [Cm ⁻² ] is 6 × 10 ¹¹ cm ⁻² and 1 × 10 ¹⁴ cm ⁻² , respectively, and the activation rate b is less than 1%.
[0038]
Furthermore, the dose of boron that can be made amorphous is about 10 ¹⁵ cm ⁻² or more.
[0039]
Next, as shown in FIG. 6, Al—Si is formed on the p ⁺ -type collector layer 9 into which boron ions are implanted by sputtering using a target made of a material obtained by adding Si to Al (Al—Si target). After the collector electrode 10 is formed, a 450 ° C. sintering (second annealing) is performed on the collector electrode 10. Here, the temperature of the sinter is 450 ° C., but is not limited thereto. The upper limit of the temperature is determined by the material of the emitter electrode 7 and the material of the passivation film.
[0040]
That is, it is necessary to set the upper limit of the sintering temperature below the melting point of the material of the emitter electrode 7 or below the temperature at which the quality of the passivation film is maintained. For example, when polyimide is used as the passivation film, the upper limit of the sintering temperature is 560 ° C.
[0041]
The sintering also serves as the annealing for activating the boron ions implanted into the surface of the n ⁺ -type buffer layer 8, thereby without increasing the number of processes, p ⁺ -type collector n ⁺ -type buffer layer 8 Layer 9 can be formed. The sinter is a heat treatment (furnace annealing) using an electric furnace.
[0042]
The activation rate of boron ions in the 450 ° C. sinter is less than 1.0%. Here, as described above, if a part of the p ⁺ -type collector layer 9 is made amorphous in the boron ion implantation step of FIG. 5, it is possible to expect a higher activation rate.
[0043]
The p ⁺ -type collector layer 9 is formed so that the activation rate b (second activation rate) is higher than 0% and 10% or less. The definition of the activation rate b is the same as the definition of the activation rate a, and (the density of p-type impurities in the activated p ⁺ -type collector layer 9 obtained by SR analysis [cm ⁻² ]) / (The density [cm ⁻² ] of the p-type impurity in the p ⁺ -type collector layer 9 obtained by SIMS analysis). The reason why the value (%) of the activation rate b falls within the above range ( 0 <b ≦ 10 ) is that boron ions are activated by the sinter.
[0044]
Thereafter, a step of forming a V / Ni / Au electrode (not shown) by sputtering according to a well-known method and a step of dicing continue.
[0045]
FIG. 8 shows the n ⁺ type of PT-IGBT examined by SIMS analysis in the case where activation of phosphorus ions and boron ions is performed by a sinter and in the case where activation of phosphorus ions and boron ions is performed by laser annealing. The impurity concentration distribution in the buffer layer and the p ⁺ -type collector layer is shown.
[0046]
From FIG. 8, in the case of laser annealing, diffusion of boron ions occurs in the region of the surface layer of the p ⁺ type collector layer of 0.1 μm, but in the case of the sinter, in the region of the surface layer of the p ⁺ type collector layer of 0.1 μm. It can be seen that almost no diffusion of boron ions occurs. That is, by activating boron ions with a sinter, an impurity concentration distribution similar to the Gaussian distribution can be realized.
[0047]
Therefore, as in this embodiment, even if phosphorus ions are activated by laser annealing and a relatively shallow n ⁺ type buffer layer is formed, if boron ions are activated by a sinter, a p ⁺ type collector diffusion to boron of the n ⁺ -type buffer layer in the layer can be sufficiently prevented, it becomes possible to prevent deterioration in controllability of the concentration profile of phosphorus in the n ⁺ -type buffer layer.
[0048]
That is, annealing for activating the first conductivity type impurity ions implanted into the first conductivity type base layer and annealing for activating the second conductivity type impurity ions implanted into the first conductivity type buffer layer. Are performed in separate steps, and the second conductive type impurities are hardly diffused into the first conductive type base layer, which is a cause of deterioration in device characteristics and concentration profile controllability. 2 is performed, it becomes possible to manufacture a semiconductor device including a high-breakdown-voltage semiconductor element such as PT-IGBT that can suppress deterioration of element characteristics and controllability of the concentration profile. The condition is, for example, that the temperature of the second annealing is lower than the temperature of the first annealing.
[0049]
In addition, since it is possible to suppress a decrease in controllability of the concentration profile, there is also a problem of the related art that a desired element characteristic that is derived due to a decrease in controllability cannot be obtained or the element characteristic varies depending on the element. can be solved.
[0050]
Thus, by obtaining an n ⁺ -type buffer layer and a p ⁺ -type collector layer having a desired concentration profile, desired device characteristics can be obtained.
[0051]
In the above, in order to prevent the p-type impurity in the p ⁺ -type collector layer from diffusing into the n ⁺ -type buffer layer, the temperature control is performed such that the temperature of the second annealing is lower than the temperature of the first annealing. However, instead, the annealing time control, or both temperature control and time control may be used.
[0052]
The present invention is not limited to the above embodiment. For example, the first conductivity type has been described as n-type and the second conductivity type as p-type, but conversely, the first conductivity type may be p-type and the second conductivity type may be n-type.
[0053]
In the above-described embodiment, the sintering process of the collector electrode 10 also serves as the boron ion activation process in the p ⁺ -type collector layer 9, but the sintering process of the collector electrode 10 and the boron ion activation process May be performed by different heat treatments. In this case, optimization of each heat treatment becomes easy.
[0054]
Furthermore, although the PT-IGBT discrete device has been described above, the PT-IGBT and other circuits such as a control circuit and a protection circuit thereof may be formed in the same chip.
[0055]
Furthermore, although the case of PT-IGBT has been described in the above embodiment, the present invention can also be applied to other high voltage semiconductor elements such as IEGT (Injection Enhancement Gate Transistor). That is, the present invention can be applied to a semiconductor element (semiconductor device) having a semiconductor structure of a first conductive type base layer with high resistance / first conductive type buffer layer with high impurity concentration / second conductive type collector layer. is there.
[0056]
【The invention's effect】
As described above, according to the present invention, regarding the first conductivity type buffer layer constituting the PT-IGBT, the density of the activated first conductivity type impurity in the buffer layer according to SR analysis [cm ⁻² ]. ) / (The density of the first conductivity type impurity in the buffer layer by SIMS analysis [cm ⁻² ]), the first activation rate a is 25% or more, and the second conductivity type collector layer , (Density of activated second conductivity type impurities in the collector layer by SR analysis [cm ⁻² ]) / (density of second conductivity type impurities in the collector layer by SIMS analysis [cm ⁻² ]) Since the defined second activation rate b is 0 <b ≦ 10 %, V _CE (sat) can be made sufficiently small, and the leakage current can be sufficiently reduced in terms of leakage characteristics. .
[0057]
Also, annealing for activating the first conductivity type impurity ions implanted into the first conductivity type base layer and activating the second conductivity type impurity ions implanted into the first conductivity type buffer layer. The annealing is performed in separate steps, and the diffusion of the second conductivity type impurity into the first conductivity type base layer, which causes the deterioration of the device characteristics and the controllability of the concentration profile, hardly occurs. Thus, since the second annealing is performed, it is possible to suppress a decrease in controllability of the impurity concentration profile in the buffer layer of the first conductivity type.
[Brief description of the drawings]
FIG. 1 is a part of a cross-sectional view showing a method of manufacturing a PT-IGBT according to an embodiment of the present invention.
FIG. 2 is a part of a sectional view showing a method for manufacturing a PT-IGBT according to an embodiment of the present invention.
FIG. 3 is a part of a cross-sectional view showing a method for manufacturing a PT-IGBT according to an embodiment of the present invention.
FIG. 4 is a part of a cross-sectional view showing a method for manufacturing a PT-IGBT according to an embodiment of the present invention.
FIG. 5 is a part of a cross-sectional view showing a method for manufacturing a PT-IGBT according to an embodiment of the present invention.
FIG. 6 is a part of a cross-sectional view showing a method for manufacturing a PT-IGBT according to an embodiment of the present invention.
FIG. 7 is a diagram for explaining SR analysis;
FIG. 8 is a diagram showing the results of examining impurity concentration distributions in an n ⁺ -type buffer layer and a p ⁺ -type collector layer by SIMS analysis.
FIG. 9 is a diagram showing the relationship between the activation rate a of the n ⁺ -type buffer layer and V _CE (sat).
FIG. 10 is a cross-sectional view showing a conventional PT-IGBT.
FIG. 11 is a diagram for explaining a mechanism of leakage current of a conventional PT-IGBT.
FIG. 12 is a diagram showing the dependence of the activation rate of the first conductivity type impurity ion-implanted on the acceleration energy.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... n ^- type base layer, 2 ... Gate insulating film, 3 ... Gate electrode, 4 ... P-type base layer, 5 ... N-type emitter layer, 6 ... Interlayer insulating film, 7 ... Emitter electrode, 8 ... N ⁺ type buffer Layer, 9... P ⁺ type collector layer, 10... Collector electrode

Claims (5)

A first base layer having high resistance and first and second surfaces and having a first conductivity type; a second base layer provided in the first surface and having a second conductivity type;
Provided on the base layer of the second conductivity type, an emitter layer having the first conductivity type,
A gate electrode provided on the second base layer sandwiched between the emitter layer and the first base layer via a gate insulating film;
A buffer layer provided on the second surface, having a high impurity concentration and having the first conductivity type;
A collector layer provided on the buffer layer and having the second conductivity type;
(Density of activated first conductivity type impurities in the buffer layer by SR analysis [cm ⁻² ]) / (Density of first conductivity type impurities in the buffer layer by SIMS analysis [cm ⁻² ]) The first activation rate is 25% or more,
And (density of activated second conductivity type impurities in the collector layer by SR analysis [cm ⁻² ]) / (density of second conductivity type impurities in the collector layer by SIMS analysis [cm ⁻² ]) A semiconductor device characterized in that the second activation rate defined is higher than 0% and not higher than 10%. The semiconductor device according to claim 1, wherein the buffer layer is formed in the base layer within 2 μm from the surface of the collector layer. Dose amount of the second conductivity type impurity in the collector layer in the region within 2 μm from the surface of the collector layer [cm ^-2 ] Is 1 × 10 ¹⁵ cm ^-2 The semiconductor device according to claim 1 or 2, which is as described above. Preparing a first base layer having a first conductivity type and having a high resistance and first and second surfaces;
An insulating film to be a gate insulating film and a conductive film to be a gate electrode are sequentially deposited on the first surface,
Sequentially patterning the conductive film and the insulating film to expose a portion of the first surface;
Forming a second base layer having a second conductivity type in a self-aligned manner in the exposed first surface;
Selectively forming an emitter layer having the first conductivity type in the second base layer;
Forming an emitter electrode on the emitter layer;
Implanting first impurity ions having the first conductivity type into the second surface;
Activating the first impurity ions by first annealing to form a buffer layer having a high impurity concentration and the first conductivity type on the second surface;
Implanting second impurity ions having the second conductivity type into the surface of the buffer layer;
Activating the second impurity ions by second annealing to form a collector layer having the second conductivity type in the buffer layer;
The method of manufacturing a semiconductor device, wherein the second annealing is performed at a temperature lower than that of the first annealing, the first annealing is laser annealing, and the second annealing is furnace annealing. (Density of activated first conductivity type impurities in the buffer layer by SR analysis [cm ^-2 ]) / (Density of first conductivity type impurities in the buffer layer by SIMS analysis [cm ^-2 ] The first activation rate defined by]) is 25% or more,
And (density of activated second conductivity type impurities in the collector layer by SR analysis [cm ^-2 ]) / (Density of second conductivity type impurities in the collector layer by SIMS analysis [cm ^-2 The method of manufacturing a semiconductor device according to claim 4, wherein the second activation rate defined by]) is higher than 0% and not higher than 10%.

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