JP3975371B2 - Wiring board manufacturing method - Google Patents
Wiring board manufacturing method Download PDFInfo
- Publication number
- JP3975371B2 JP3975371B2 JP20439097A JP20439097A JP3975371B2 JP 3975371 B2 JP3975371 B2 JP 3975371B2 JP 20439097 A JP20439097 A JP 20439097A JP 20439097 A JP20439097 A JP 20439097A JP 3975371 B2 JP3975371 B2 JP 3975371B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- adhesive
- copper foil
- base material
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000463 material Substances 0.000 claims description 17
- 239000000853 adhesive Substances 0.000 claims description 15
- 230000001070 adhesive effect Effects 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 239000011889 copper foil Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 description 10
- 229920001721 polyimide Polymers 0.000 description 9
- 239000000758 substrate Substances 0.000 description 7
- 238000002507 cathodic stripping potentiometry Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000004809 Teflon Substances 0.000 description 3
- 229920006362 Teflon® Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- BQCIDUSAKPWEOX-UHFFFAOYSA-N 1,1-Difluoroethene Chemical compound FC(F)=C BQCIDUSAKPWEOX-UHFFFAOYSA-N 0.000 description 1
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 229920001646 UPILEX Polymers 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007766 curtain coating Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007755 gap coating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- UCHOFYCGAZVYGZ-UHFFFAOYSA-N gold lead Chemical compound [Au].[Pb] UCHOFYCGAZVYGZ-UHFFFAOYSA-N 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Landscapes
- Laminated Bodies (AREA)
- Casting Or Compression Moulding Of Plastics Or The Like (AREA)
Description
【0001】
【発明の属する技術分野】
本発明は、配線板の製造法、特に半導体パッケージ用の配線板の製造法に関する。
【0002】
【従来の技術】
電子機器の小型化に伴って、半導体パッケージにおいて更なる小型化の要求が強くなってきた。この小型化に対応するものとして、半導体チップとほぼ同サイズのいわゆるチップサイズパッケージ(以下、CSPという。)が提案されている。これは、半導体チップの周辺部でなく、実装領域内に外部配線基板との接続部を有するパッケージである。
【0003】
具体例としては、バンプ付きポリイミドフィルムを半導体チップの表面に接着し、チップと金リード線により電気的接続を図った後、エポキシ樹脂等をポッティングして封止することが、雑誌“NIKKEI MATERIALS & TECHNOLOGY 94.4、No.140”のP18〜19により知られ、仮基板上に半導体チップ及び外部配線基板との接続部に相当する位置に金属バンプを形成し、半導体チップをフェースダウンボンディングすることが、論文“Smallest Flip-Chip-Like Package CSP(The Second VLSI Packaging Workshop of Japan、P46〜50、1994)”により知られている。
【0004】
【発明が解決しようとする課題】
各種提案されているCSPの中で、ポリイミドフィルムをベースとするCSPは、信頼性とコストを両立できるものとして期待されている。しかしながら、穴あけした接着剤付きのポリイミドフィルム基板と、銅箔を大型サイズで加圧・加熱して積層一体化した場合、銅箔と接着剤間でズレが発生し、穴内にベース基材の接着剤が露出した状態となり、この穴に形成するはんだボールの接続面積が、小さくなるという課題がある。
【0005】
本発明は、銅箔と接着剤間のズレの抑制に優れ、信頼性と経済性とに優れた半導体パッケージ用の配線板の製造法を提供することを目的とする。
【0006】
【課題を解決するための手段】
本発明の配線板の製造法は、少なくとも片面に、Bステージの接着剤を塗布したフレキシブル基材に穴をあけたものと、銅箔とを、接着剤が銅箔に接するように重ね、フレキシブル基材の裏面にクッション材を重ね、加圧・加熱して積層一体化する工程を有する配線板の製造法において、フレキシブル基材にダミー用の穴をあけることを特徴とする。
【0007】
フレキシブル基材2としては、ポリイミド樹脂、エポキシ樹脂等によるプラスチックフィルムが好適であり、この他に、ポリイミド樹脂、またはエポキシ樹脂をガラス不織布等基材に含浸させ、加熱硬化したものが使用できる。
【0008】
接着剤1としては、ポリイミド樹脂やエポキシ樹脂が使用でき、ギャップコートやカーテンコートや印刷法等によって基材上に塗布し、加熱硬化して半硬化状態(Bステージ)にしたものを用いる。
【0009】
次に、ダミーの穴あけには、ドリル、パンチあるいはレーザ加工によって行うことができ、この穴は直径1.0mm以上であることが好ましい。穴径が1.0mm未満であると、銅箔と接着剤のズレの抑制に効果が少ない。
また、穴あけを行う箇所は、できるだけ、半導体パッケージとなる製品の外側にするのが好ましい。
【0010】
クッション材8としては、テフロン、ポリイミド、フッ化ビニリデン等のフィルムを用いることができる。
【0011】
(作用)
本発明において、ダミー穴により、クッション材が変形してダミー内に入り、基材のズレを抑制する。
【0012】
【実施例】
実施例1
1)フレキシブル基材2として、厚さ50μmのポリイミドフィルムであるユーピレックスS(宇部興産株式会社製、商品名)に、接着剤1として、ポリイミド系接着剤であるN4接着剤(日立化成工業株式会社製、商品名)を約10μm塗布し、180℃で、130分間乾燥してBステージ状態にし、500mm角に切断し、配線エリア内にはんだボール接合のための直径0.4mmの穴をドリルであけた。
2)図3に示すように、配線エリア外に、直径1.5mmの穴11を、ドリルであけた。
3)クッション材として、厚さ80μmのテフロンフィルムであるUL900(日東電気工業株式会社製、商品名)を、250mm角に切断した。
4)鏡板9として、厚さ1.5mmのステンレス製鉄板上に、前記工程で作製したクッション材8の250mm角のテフロンフィルムを4枚並べたのち、上記穴あけしたフレキシブル基材2を重ね、さらに、厚さ18μmの銅箔であるSLP−18(日本電解株式会社製、商品名)を重ね、さらに、鏡板9として、厚さ1.5mmのステンレス製鉄板を重ね、250℃で30kgf/cm2の条件で60分間、加圧・加熱して積層一体化した。
5)厚さ25μmのエッチング用ドライフィルムであるフォテックH−W425(日立化成工業株式会社製、商品名)を100℃で、4kgf/cm2、ラミネート速度1.5m/分の条件でラミネートした後、フォトマスクを介して、80mJ/cm2の条件で露光し、現像し、エッチングレジストを形成し、そのエッチングレジストに覆われていない箇所を、塩化第二鉄エッチング溶液で選択的にエッチング除去し、レジストを剥離して、配線パターンを形成した。
6)次に、厚さ5μmの無電解ニッケルめっきと、厚さ0.4μmの無電解金めっきを行った。
【0013】
実施例2
1)実施例1の(1)と同様の工程を実施する。
2)配線エリア外に、直径3.0mmの穴をパンチであける。
3)実施例1の(3)〜(6)と同様の工程を実施する。
【0014】
比較例
1)実施例1の(1)と(3)〜(6)と同様の工程を実施する。
【0015】
本発明の実施例1及び2の最大ズレ量は、20μmであった。一方、比較例の場合は、最大ズレ量は、90μmであり、本発明による銅箔と接着剤間のズレ抑制効果が認められた。
【0016】
【発明の効果】
以上に説明したように、本発明によって、銅箔と接着剤間のズレの抑制に優れ、信頼性と経済性とに優れた半導体パッケージ用の配線板の製造法を提供することができる。
【図面の簡単な説明】
【図1】本発明の一実施例を示す各工程における断面図である。
【図2】本発明の一実施例を示す断面図である。
【図3】本発明の一実施例を示す上面図である。
【符号の説明】
1.接着剤 2.フレキシブル基材
4.穴 6.銅箔
7.配線パターン 8.クッション材
9.鏡板 11.ダミー穴[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board for a semiconductor package.
[0002]
[Prior art]
Along with the downsizing of electronic devices, there is an increasing demand for further downsizing of semiconductor packages. In order to cope with this downsizing, a so-called chip size package (hereinafter referred to as CSP) that is approximately the same size as a semiconductor chip has been proposed. This is a package having a connection portion with an external wiring board in the mounting region, not in the peripheral portion of the semiconductor chip.
[0003]
As a specific example, a polyimide film with bumps is bonded to the surface of a semiconductor chip, electrical connection is made between the chip and a gold lead wire, and then epoxy resin or the like is potted to seal the magazine “NIKKEI MATERIALS & It is known from P18-19 of TECHNOLOGY 94.4, No. 140 ", and forming a metal bump on the temporary substrate at a position corresponding to the connection portion between the semiconductor chip and the external wiring board, and bonding the semiconductor chip face down, It is known by the paper “Smallest Flip-Chip-Like Package CSP” (The Second VLSI Packaging Workshop of Japan, P46-50, 1994).
[0004]
[Problems to be solved by the invention]
Among various proposed CSPs, a CSP based on a polyimide film is expected to achieve both reliability and cost. However, when a polyimide film substrate with a holed adhesive and copper foil is laminated and integrated by pressing and heating in a large size, a gap occurs between the copper foil and the adhesive, and the base substrate adheres within the hole. There is a problem that the agent is exposed and the connection area of the solder ball formed in the hole is reduced.
[0005]
An object of this invention is to provide the manufacturing method of the wiring board for semiconductor packages excellent in suppression of the shift | offset | difference between copper foil and an adhesive agent, and excellent in reliability and economical efficiency.
[0006]
[Means for Solving the Problems]
The method for producing a wiring board according to the present invention comprises a flexible base material coated with a B-stage adhesive on at least one side and a copper foil layered so that the adhesive is in contact with the copper foil. In a method for manufacturing a wiring board having a process of stacking and integrating a cushioning material on the back surface of a base material and pressurizing and heating, dummy holes are formed in the flexible base material.
[0007]
As the flexible substrate 2, a plastic film made of polyimide resin, epoxy resin, or the like is suitable. In addition, a material obtained by impregnating a substrate such as glass nonwoven fabric with polyimide resin or epoxy resin and heat-curing it can be used.
[0008]
As the adhesive 1, a polyimide resin or an epoxy resin can be used, and it is applied on a substrate by gap coating, curtain coating, printing method, or the like, and is heated and cured to be a semi-cured state (B stage).
[0009]
Next, a dummy hole can be formed by drilling, punching, or laser processing, and the hole preferably has a diameter of 1.0 mm or more. When the hole diameter is less than 1.0 mm, the effect of suppressing the displacement between the copper foil and the adhesive is small.
Further, it is preferable that the hole is formed as much as possible outside the product to be a semiconductor package.
[0010]
As the
[0011]
(Function)
In the present invention, the cushion material is deformed and enters the dummy by the dummy hole, and the displacement of the base material is suppressed.
[0012]
【Example】
Example 1
1) As flexible substrate 2, Upilex S (trade name) manufactured by Ube Industries, Ltd., which is a polyimide film with a thickness of 50 μm, and N4 adhesive (Hitachi Chemical Industry Co., Ltd.), which is a polyimide adhesive, as adhesive 1 (Product name, product name) is applied about 10 μm, dried at 180 ° C. for 130 minutes to form a B stage, cut into a 500 mm square, and a 0.4 mm diameter hole for solder ball bonding is drilled in the wiring area. Opened.
2) As shown in FIG. 3, a
3) As a cushion material, UL900 (trade name, manufactured by Nitto Denki Kogyo Co., Ltd.), which is a Teflon film having a thickness of 80 μm, was cut into 250 mm square.
4) After arranging four 250 mm square Teflon films of the
5) After laminating Photec H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.), a dry film for etching having a thickness of 25 μm, at 100 ° C. under conditions of 4 kgf / cm 2 and a laminating speed of 1.5 m / min. , Exposed to light through a photomask at 80 mJ / cm 2 , developed, formed an etching resist, and selectively etched away portions not covered with the etching resist with a ferric chloride etching solution The resist was removed to form a wiring pattern.
6) Next, electroless nickel plating with a thickness of 5 μm and electroless gold plating with a thickness of 0.4 μm were performed.
[0013]
Example 2
1) The same process as (1) of Example 1 is performed.
2) A hole with a diameter of 3.0 mm is punched outside the wiring area.
3) The same steps as (3) to (6) of Example 1 are performed.
[0014]
Comparative Example 1) The same steps as (1) and (3) to (6) of Example 1 are performed.
[0015]
The maximum deviation amount of Examples 1 and 2 of the present invention was 20 μm. On the other hand, in the case of the comparative example, the maximum shift amount was 90 μm, and the effect of suppressing the shift between the copper foil and the adhesive according to the present invention was recognized.
[0016]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a method for manufacturing a wiring board for a semiconductor package, which is excellent in suppressing a deviation between a copper foil and an adhesive, and excellent in reliability and economy.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view in each step showing an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing an embodiment of the present invention.
FIG. 3 is a top view showing an embodiment of the present invention.
[Explanation of symbols]
1. Adhesive 2. 3. Flexible base material Hole 6. Copper foil7.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20439097A JP3975371B2 (en) | 1997-07-08 | 1997-07-30 | Wiring board manufacturing method |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18193297 | 1997-07-08 | ||
JP9-181932 | 1997-07-08 | ||
JP20439097A JP3975371B2 (en) | 1997-07-08 | 1997-07-30 | Wiring board manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH1177721A JPH1177721A (en) | 1999-03-23 |
JP3975371B2 true JP3975371B2 (en) | 2007-09-12 |
Family
ID=26500919
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20439097A Expired - Lifetime JP3975371B2 (en) | 1997-07-08 | 1997-07-30 | Wiring board manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3975371B2 (en) |
-
1997
- 1997-07-30 JP JP20439097A patent/JP3975371B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH1177721A (en) | 1999-03-23 |
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