JP3973934B2 - High voltage semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high voltage semiconductor device having an insulated gate structure.
[0002]
[Prior art]
In recent years, an insulated gate bipolar transistor (IGBT) capable of voltage control is used in a wide range of fields such as motor control as a high voltage semiconductor switching device capable of self-extinguishing.
[0003]
The principal part of an example of the IGBT according to the prior art is shown in the sectional view of FIG. The IGBT 200 shown in FIG. 1 includes an n-type base layer 10, a p-type base layer 22 selectively formed on the surface portion of the n-type base layer 10, and an n-type diffused and formed on the surface portion of the p-type base layer 22. A mold emitter layer 42. A gate electrode 54 is formed on the n-type base layer 10, the p-type base layer 22 and the n-type emitter layer 42 via a gate oxide film 52. An emitter electrode 58 is formed so as to be in contact with both the n-type emitter layer 42 and the p-type base layer 22. The IGBT 200 is also a p-type emitter formed through an n-type buffer layer 72 on the surface of the n-type base layer 10 opposite to the surface on which the p-type base layer 22 and the n-type emitter layer 42 are formed. A layer 74 is further provided. A collector electrode 76 is formed on the p-type emitter layer 74.
[0004]
Next, the operation of the IGBT 200 shown in FIG. 11 will be described. When a positive voltage is applied to the gate electrode 54 with respect to the potential of the emitter electrode 58 in a state in which a positive voltage is applied to the collector electrode 76 with respect to the potential of the emitter electrode 58 of the IGBT 200, the surface of the p-type base layer 22. An n-type inversion layer is formed in the n-type inversion layer, whereby the n-type emitter layer 42 and the n-type base layer 10 are short-circuited. Electrons are injected from the n-type emitter layer 42 into the n-type base layer 10 through the inversion layer. Holes are injected from the p-type emitter layer 74 into the n-type base layer 10 in accordance with the current caused by the electrons injected into the n-type base layer 10. These carriers (electrons and holes) injected into the n-type base layer 10 are accumulated in the n-type base layer 10 to cause conductivity modulation, whereby the IGBT 200 is turned on.
[0005]
When a negative voltage with respect to the potential of the emitter electrode 58 is applied to the gate electrode 54 with the IGBT 200 turned on, the n-type inversion layer disappears, and electrons are injected from the n-type emitter layer 42 into the n-type base layer 10. Stop. Thereafter, the carriers accumulated in the n-type base layer 10 are also discharged, and the IGBT 200 is turned off.
[0006]
Here, in order to reduce the voltage drop (energization loss) between the collector and the emitter in the on state of the IGBT 200, the carrier concentration in the n-type base layer 10 in the on state may be increased. At this time, if the carrier concentration on the collector side is increased, the switching loss (turn-off loss) at the time of turn-off increases. Therefore, a method for increasing the carrier concentration on the emitter side is generally selected.
[0007]
[Problems to be solved by the invention]
However, with respect to IGBTs according to the prior art, a structure for increasing the carrier concentration on the emitter side has not been sufficiently studied.
[0008]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high voltage semiconductor device capable of reducing current loss without increasing turn-off loss.
[0009]
[Means for Solving the Problems]
The present invention aims to solve the above problems by the following means.
[0010]
According to an aspect of the present invention, the first conductivity type base layer is selectively formed on a surface portion of a region excluding a peripheral portion, and the first conductivity type base layer has a first surface on the surface portion of the first surface. A first conductivity type barrier layer selectively formed to have an impurity concentration substantially higher than that of the one conductivity type base layer;
A second conductivity type base layer selectively formed on a surface portion of the first conductivity type barrier layer;
A first conductivity type emitter layer selectively formed on a surface portion of the second conductivity type base layer;
A gate electrode formed through a gate insulating film so as to face the first conductivity type barrier layer, the second conductivity type base layer, and the first conductivity type emitter layer;
A first main electrode formed in contact with the second conductivity type base layer and the first conductivity type emitter layer;
A first conductivity type buffer layer formed on a second surface that is opposite to the first surface of the first conductivity type base layer;
A second conductivity type emitter layer formed in contact with the first conductivity type buffer layer;
A second main electrode formed in contact with the second conductivity type emitter layer;
The first conductive type barrier layer and the second conductive type are selectively formed separately from the first conductive type barrier layer at a surface portion of the periphery of the first surface of the first conductive type base layer. A second conductivity type ring layer disposed to surround the base layer and connected to the first main electrode;
A high voltage semiconductor device is provided.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, some embodiments of the present invention will be described with reference to the drawings. In the following description, n-type is used as the first conductivity type, and p-type is used as the second conductivity type. In addition, components having substantially the same function and configuration are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0013]
(1) First Embodiment FIG. 1 shows a cross-sectional view of a main part of a first embodiment of a high voltage semiconductor device according to the present invention. The IGBT 1 shown in the figure further includes an n-type barrier layer 12 inserted between the n-type base layer 10 and the p-type base layer 22, and this point is different from the conventional IGBT 200 shown in FIG. The other configuration of the IGBT 1 is substantially the same as that of the IGBT 200 of FIG. The impurity concentration of the n-type barrier layer 12 is set higher than that of the n-type base layer 10. When the conduction loss of the IGBT 1 having such an n-type barrier layer 12 is examined by device simulation, it is as shown in FIG. In this simulation, a 4.5 kV breakdown voltage element is assumed, the thickness of the n-type base layer 10 is 450 μm, the cell size is 70 μm, the diffusion depth of the p-type base layer 22 is 5 μm, and the collector side structure is all Same structure. Accordingly, carriers are accumulated on the emitter side of the n-type base layer 10 as the conduction loss decreases.
[0014]
As shown in FIG. 2, the conduction loss decreases as the diffusion depth of the n-type barrier layer 12 increases. However, when the diffusion depth exceeds 10 μm, the conduction loss is saturated and the conduction loss does not decrease. Accordingly, the diffusion depth of the n-type barrier layer 12 is desirably 10 μm or more.
[0015]
The manufacturing method of the semiconductor device of this embodiment will be described with reference to the schematic cross-sectional views of FIGS.
[0016]
First, as shown in FIG. 3, an n-type buffer layer 72 and a p-type emitter layer 74 are formed in advance on the back side of the n-type base layer 10, and in this state, ions are applied to the surface of the n-type base layer 10. An n-type impurity such as phosphorus is introduced by a method such as irradiation. The amount of the n-type impurity to be introduced is desirably 2E12 cm ⁻² or less from the viewpoint of preventing a decrease in breakdown voltage. Thereafter, high-temperature heat treatment is performed in an oxidizing atmosphere to diffuse impurities in the n-type base layer 10 to form the n-type barrier layer 12.
[0017]
Next, as shown in FIG. 4, a gate oxide film 52 and a gate electrode 54 are selectively formed on the n-type barrier layer 12 by patterning using a resist.
[0018]
Thereafter, as shown in FIG. 5, the p-type base layer 22 and the n-type emitter layer 42 are formed by diffusion using the gate electrode 54 as a mask, and an insulating film 57 is formed so as to cover the gate electrode 54.
[0019]
Thereafter, through holes TH (see FIG. 1) are formed in the insulating film 57 to form the emitter electrode 58, and finally, the collector electrode 76 is formed on the back surface, whereby the IGBT 1 in FIG. 1 is manufactured.
[0020]
(2) Second Embodiment FIG. 6 is a cross-sectional view showing the main part of a second embodiment of the high voltage semiconductor device according to the present invention. As is clear from comparison with the IGBT 1 shown in FIG. 1, the IGBT 2 of the present embodiment includes the gate electrode 55 formed not on the entire surface on the n-type barrier layer 12 but only on a part of the region. By configuring the gate electrode in this way, the feedback capacitance of the semiconductor device can be reduced. As a result, the stability of the element operation can be increased. In addition, since the input capacitance is reduced as the feedback capacitance is reduced, the burden on the gate drive circuit can be reduced.
[0021]
(3) Third Embodiment FIG. 7 is a cross-sectional view showing the main part of a third embodiment of the high voltage semiconductor device according to the present invention. The IGBT 3 of this embodiment is different from the first embodiment described above in that it has a buried gate structure. That is, the n-type barrier layer 14 is formed on the n-type base layer 10, and the p-type base layer 24 is formed on the n-type barrier layer 14. A trench groove having a depth reaching the middle of the n-type barrier layer 14 through the p-type base layer 24 is formed, and a gate electrode 64 is formed in the trench groove via a gate oxide film 62. An n-type emitter layer 44 is formed on the surface portion of the p-type base layer 24 so as to be in contact with the trench. An emitter electrode 86 is formed so as to be in contact with both the n-type emitter layer 44 and the p-type base layer 24. On the other hand, a p-type emitter layer 74 is formed via an n-type buffer layer 72 on the surface of the n-type base layer 10 opposite to the surface on which the n-type barrier layer 14 is provided. A collector electrode 76 is formed on the p-type emitter layer 74.
[0022]
The current loss can be reduced by forming the n-type barrier layer 14 also by the IGBT 3 of the present embodiment.
[0023]
A modification of the IGBT of the present embodiment is shown in FIG. The IGBT 4 shown in the figure is configured so as not to be connected to the emitter electrode by covering the region between the trenches where the n-type emitter layer 44 is not formed in the surface region of the p-type base layer 26 with an insulating film 84. . By adopting such a configuration, resistance when holes injected from the p-type emitter layer 74 into the n-type base layer 10 are discharged to the emitter electrode 86 through the p-type base layer 26 is increased. . Thereby, holes are accumulated more excessively in the n-type base layer 10. That is, the effect of inserting the n-type barrier layer 14 is further enhanced. As a result, energization loss can be further reduced.
[0024]
(4) Fourth Embodiment FIG. 9 is a sectional view of a fourth embodiment of the high voltage semiconductor device according to the present invention. In FIG. 9, the junction termination | terminus part of IGBT5 of this embodiment is also shown collectively. The left side of FIG. 9 is the element part, and the right side of the page is the joining terminal part. The closer to the right edge of the paper, the closer to the periphery of the element. Normally, a p-type ring layer 102 for stabilizing the potential is formed in contact with the p-type base layer 36 at the junction termination portion, and a p-type RESURF layer 104 having a low concentration is formed outside the p-type ring layer 102. Is formed. In addition, an n-type stop layer 106 for stabilizing the potential is formed on the outermost periphery (periphery) of the element.
[0025]
An electrode (not shown) for stabilizing the potential is formed on the n-type stop layer 106, and an insulating film (not shown) is formed on the junction termination portion to protect the element surface. In addition, if a high resistance film is used instead of the surface protection insulating film, the influence of external charges can be prevented from reaching the inside of the element, so that the breakdown voltage can be stabilized.
[0026]
In the present embodiment, the p-type RESURF layer 104 having a low concentration is completely depleted in the non-conducting state of the element, and this produces the same effect as a negative charge is introduced into the surface of the p-type RESURF layer 104. As a result, the electric field at the junction termination portion is relaxed, so that the breakdown voltage of the element can be increased.
[0027]
From the viewpoint of preventing a decrease in breakdown voltage, the n-type barrier layer 16 and the p-type ring layer 102 are preferably formed apart from each other. In that case, unlike the IGBT 1 shown in FIG. 1, the n-type barrier layer may not be formed in the outer cell.
[0028]
(5) Fifth Embodiment FIG. 10 is a cross-sectional view showing the main part of a fifth embodiment of the high voltage semiconductor device according to the present invention. In FIG. 10, the junction termination | terminus part of IGBT6 of this embodiment is also shown collectively. The left side of FIG. 10 is the element portion, and the right side of the paper is the joining end portion. The closer to the right side of the paper, the closer to the periphery of the element. In general, a p-type ring layer 102 for stabilizing the potential is formed in contact with the p-type base layer 36 at the junction termination portion, and a plurality of p-type guard ring layers 107 are further provided outside the p-type ring layer 102. Is formed. The p-type guard ring layer 107 is disposed so that the distance between the p-type guard ring layers 107 increases as the distance from the device edge increases. In FIG. 10, three p-type guard ring layers 107 are shown for simplicity of explanation, but the number is not limited to this and is determined according to the breakdown voltage of the element. In addition, an n-type stop layer 106 for stabilizing the potential is formed on the outermost periphery (periphery) of the element.
[0029]
An electrode (not shown) for stabilizing the potential is formed on the n-type stop layer 106, and an insulating film (not shown) for protecting the element surface is formed on the junction termination portion. If a high resistance film is used instead of the insulating film for surface protection, the influence of external charges can be prevented from reaching the inside of the element, so that the breakdown voltage can be stabilized.
[0030]
According to the IGBT 6 of the present embodiment, since the potentials of the plurality of p-type guard ring layers 107 gradually increase toward the periphery of the device when the device is in a non-conducting state, the electric field at the junction termination is alleviated. As a result, the breakdown voltage of the element can be increased.
[0031]
From the viewpoint of preventing a decrease in breakdown voltage, it is better to form the n-type barrier layer 16 and the p-type ring layer 102 separately from each other as shown in FIG. In that case, unlike the IGBT 1 shown in FIG. 1, the n-type barrier layer may not be formed in the outer cell.
[0032]
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be applied with various modifications within the technical scope. For example, in the above-described fourth embodiment, the case where the RESURF structure is provided as the junction termination structure has been described. However, the junction termination structure is not limited to the RESURF structure, but a guard ring structure, a field plate structure, an RFP (resistive field plate). ) A structure, a combination thereof, or a deformed structure can be applied.
[0033]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a high voltage semiconductor device that can reduce current loss without increasing turn-off loss.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a main part of a first embodiment of a high voltage semiconductor device according to the present invention.
FIG. 2 is a graph showing a simulation result of energization loss of the high voltage semiconductor device shown in FIG.
3 is a schematic cross-sectional view illustrating a method for manufacturing the high voltage semiconductor device shown in FIG. 1. FIG.
4 is a schematic cross-sectional view illustrating a method for manufacturing the high voltage semiconductor device shown in FIG.
5 is a schematic cross-sectional view illustrating a method for manufacturing the high voltage semiconductor device shown in FIG.
FIG. 6 is a cross-sectional view showing a main part of a second embodiment of a high voltage semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing a main part of a third embodiment of a high voltage semiconductor device according to the present invention.
8 is a cross-sectional view showing a modification of the high voltage semiconductor device shown in FIG.
FIG. 9 is a cross-sectional view showing a main part of a fourth embodiment of a high voltage semiconductor device according to the present invention.
FIG. 10 is a cross-sectional view showing a main part of a fifth embodiment of the high voltage semiconductor device according to the present invention.
FIG. 11 is a cross-sectional view showing a main part of an example of a conventional IGBT.
[Explanation of symbols]
1-5 IGBT
10 n-type base layers 12, 14, 16 n-type barrier layers 22, 26, 32, 34, 36 p-type base layers 42, 44, 46 n-type emitter layer 52 Gate oxide films 54, 55, 64, 94 Gate electrode 58 , 86, 92 Emitter electrode 72 n-type buffer layer 74 p-type emitter layer 76 collector electrode 102 p-type ring layer 104 p-type RESURF layer 107 p-type guard ring layer

Claims (5)

A first conductivity type base layer;
The first conductivity type base layer is selectively formed on a surface portion of a region excluding a peripheral portion, and is substantially more substantially on the surface portion of the first surface of the first conductivity type base layer than the first conductivity type base layer. A first conductivity type barrier layer selectively formed to have a high impurity concentration;
A second conductivity type base layer selectively formed on a surface portion of the first conductivity type barrier layer;
A first conductivity type emitter layer selectively formed on a surface portion of the second conductivity type base layer;
A gate electrode formed through a gate insulating film so as to face the first conductivity type barrier layer, the second conductivity type base layer, and the first conductivity type emitter layer;
A first main electrode formed in contact with the second conductivity type base layer and the first conductivity type emitter layer;
A first conductivity type buffer layer formed on a second surface that is opposite to the first surface of the first conductivity type base layer ;
A second conductivity type emitter layer formed in contact with the first conductivity type buffer layer ;
A second main electrode formed in contact with the second conductivity type emitter layer;
The first conductive type barrier layer and the second conductive type are selectively formed separately from the first conductive type barrier layer at a surface portion of the periphery of the first surface of the first conductive type base layer. A second conductivity type ring layer disposed to surround the base layer and connected to the first main electrode;
High-voltage semiconductor device according to claim Rukoto equipped with.   2. The high breakdown voltage according to claim 1, wherein the gate electrode is formed such that a portion facing the first conductivity type barrier layer is opposed to a partial region of the first conductivity type barrier layer. Semiconductor device. The first conductive barrier layer, claims, characterized in that it has the 10μm or more thick in the same direction as the direction from the first surface to the second surface of the first conductivity type base layer 3. A high breakdown voltage semiconductor device according to 1 or 2 . A surface portion of the first surface of the first conductivity type base layer, formed outside the second conductivity type ring layer, in contact with the second conductivity type ring layer, and the second conductivity type ring. high voltage semiconductor device according to claim 1 or 2, further comprising a second conductivity type RESURF layer disposed so as to extend toward the layer on the periphery of the element. The second conductivity type ring layer is selectively formed in a surface portion of the first surface of the first conductivity type base layer and in a region extending from the outside of the second conductivity type ring layer to the vicinity of the periphery of the element. and spaced, and high breakdown voltage semiconductor device according to claim 1 or 2, further comprising a plurality of second conductivity type guard ring layer disposed to be separated from each other.

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