JP3964629B2 - Data path abnormality detection method by patrol of disk array device and computer system provided with disk array device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data path abnormality detection method by patrol of a disk array device suitable for detecting an abnormality such as a data path between a host computer and a disk array device, and a computer system including the disk array device.
[0002]
[Prior art]
In a disk array device that has multiple disk storage devices and exchanges data with a host computer, a standardized interface such as SCSI (Small Computer System Interface) is used for the interface (host interface) with the host computer. It is common to be done. In a computer system in which such a host computer and a disk array device are connected, a parity check circuit is used as an example of a data protection mechanism when the host interface is a SCSI interface.
[0003]
[Problems to be solved by the invention]
As described above, conventionally, in a computer system including a disk array device that exchanges data with a host computer, a parity check circuit is used as a data protection mechanism in the case where the host interface is an SCSI interface. It was general.
[0004]
However, since the protection by the parity is confirmation of one data unit (for example, one byte unit), it is effective for detection of data shift, data omission, etc. when considered as a data block (for example, data block of sector size). There was no problem.
[0005]
Therefore, a method of adding a redundancy code (data check code) such as CRC (Cyclic Redundancy Check) in data block units is also conceivable. However, in this method, a special operation is required in the standardized interface, and the operation is restricted.
[0006]
The present invention has been made in view of the above circumstances, and its purpose is to provide a host computer and a disk in a disk array device even when the write data itself transferred from the host computer does not have a redundant code for data protection. A data path abnormality detection method by patrol of a disk array device and a computer system provided with the disk array device capable of improving the detection rate when a data error occurs due to an abnormality of a target data path with the storage device It is to provide.
[0007]
[Means for Solving the Problems]
The present invention relates to a computer system comprising a host computer on which a monitoring program operates, a disk array including a plurality of disk storage devices, and a disk array controller including a cache memory. When the write request issued to the disk array device matches the preset timing, the first write data transferred from the host computer to the disk array device and written to the cache memory in response to the write request is written. Redundant code is generated in units of data blocks of a preset size, and then the host computer issues an inquiry to the disk array device to monitor the data path between the host computer and the disk array device. When it is made in accordance with the above timing according to the monitoring program, the disk array device notifies the host computer of the data designation information for designating the first redundant code generated at that time and the corresponding data. Upon receiving the notification, the host computer reads the data designated by the notified data designation information from the cache memory to the host computer, and generates a second redundant code of the data in units of the data block according to the monitoring program. By comparing the generated second redundant code with the notified first redundant code, it is determined whether or not there is an abnormality in the data path between the host computer and the disk array device based on at least the comparison result It is characterized by that.
[0008]
In such a configuration, the disk array controller is transferred from the host computer to the disk array apparatus in response to the write request only when a write request issued from the host computer according to, for example, an application program matches a preset timing. A first redundant code of data temporarily stored in the internal cache memory is generated. Also, an inquiry for data path monitoring is sent from the host computer to the disk array device in correspondence with the above timing, and the first redundancy code and data designation information are notified to the host computer in response to this inquiry. The As a result, the host computer reads the data specified by the notified data specification information, that is, the data on the cache memory used for generating the first redundant code, and generates the second redundant code of the data. In comparison with the first redundancy code, the data path between the host computer and the disk array device (or more specifically, the data path between the host computer and the cache memory in the disk array controller). Abnormality, that is, abnormality of any circuit on the path).
[0009]
As described above, in the present invention, the first redundant code generation for the write data on the disk array device side is performed independently of the application program according to the setting from the monitoring program, and the inquiry to the disk array device on the host computer side. And reading the data specified by the data specification information acquired from the response to the inquiry, generating the second redundant code, and comparing the first and second redundant codes are communicated with the application program according to the monitoring program Without being performed independently from the application program.
[0010]
In general, in order to check the data path between the host computer and the disk array device by a monitoring program operating on the host computer, the host computer performs a write / read compare test on the disk array device. Is the most reliable and convenient. However, in order to securely protect the data, a process for exchanging data information with the application program is required. On the other hand, in the present invention, the data path can be confirmed regardless of the operation of the application program.
[0011]
Here, in order to check the data path regardless of the operation of the application program, it is preferable to apply a time interval or a write request count interval set in advance according to the monitoring program as the timing.
[0012]
Since the data path can be confirmed regardless of the operation of the application program, the data used for generating the first redundant code is updated before it is used for generating the second redundant code. There is a possibility. In this case, since the second redundant code is generated based on the updated data, the first and second redundant codes do not match regardless of whether the data path is abnormal. Therefore, if the first and second redundant codes do not match, the host computer inquires of the disk array device whether or not the original data in the cache memory has been updated, and a response indicating that it has not been updated is returned. Only in the case where it is done, the abnormality of the data path should be determined.
[0013]
The present invention also provides another specification on the cache memory that can be read only by a dedicated read request in accordance with a monitoring program from the host computer, for copying the data on the cache memory used for generating the first redundant code. A copy of the data stored in the area and not the original data on the cache memory used to generate the first redundant code, that is, the data in the specific area is read using the dedicated read request. The second redundant code is generated from the read data.
[0014]
In such a configuration, it is possible to prevent the data used for generating the second redundant code, that is, the data in the specific area from being updated by a write request according to an application program or the like.
[0015]
In addition, when writing write data transferred from a host computer and written in a cache memory to the disk storage device, the present invention writes a copy of the data in another specific area of the disk storage device and By making the data invalid data that cannot be seen by the application program and checking data, the data written in the specific area of the disk storage device is read out to the disk array controller and compared with the original data in the cache memory. It is also characterized by determining whether there is an abnormality in the data path between the array controller and the disk storage device. In this case as well, it is preferable to process the write data when writing of the write data from the cache memory to the disk storage device matches the preset interval (time interval or write interval) instead of all the write data.
[0016]
In such a configuration, the data in the cache memory written in the disk storage device is protected from updating as invalid data that cannot be seen by the application program and as check data, and a copy of the data written in the disk storage device is also obtained. Is stored in another specific area of the disk storage device so that the copy of the data is protected from being updated, that is, the factor that destroys the data is eliminated. By comparing with the original data (check data) on the cache memory, it is possible to correctly determine whether there is an abnormality in the data path between the disk array controller and the disk storage device.
[0017]
In addition to this, when writing the write data transferred from the host computer and written in the cache memory to the disk storage device, a third redundant code of the data is generated and held in the disk array controller, Data in the disk storage device used to generate the third redundant code is read out to the disk array controller to generate a fourth redundant code of the data, and the fourth redundant code is generated first. By comparing with the third redundant code, it is possible to determine whether there is an abnormality in the data path between the disk array controller and the disk storage device.
[0018]
The present invention related to the data path abnormality detection method by patrol of the disk array device described above is also established as an invention related to a computer system composed of a host computer and a disk array device, or an invention related to a disk array controller.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0020]
FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.
The computer system of FIG. 1 includes a disk array device 10 and a host computer 20 that uses the disk array device 10.
[0021]
The disk array device 10 includes a disk array 11 having a plurality of disk storage devices, for example, hard disk devices (hereinafter referred to as HDDs) 110, and a controller (disk array controller) 12 that controls the disk array 11.
[0022]
The disk array controller 12 includes a main control unit 120, a host interface 121, a disk interface 122 provided for each HDD 110, and a cache memory device 123. The main control unit 120, host interface 121, disk interface 122, and cache memory device 123 are interconnected by a data transfer bus 124. The data transfer bus 124 is, for example, a PCI bus (Peripheral) known as a standard bus.
Component Interconnect Bus).
[0023]
The main control unit 120 includes a microprocessor 125, a ROM (Read Only Memory) 126 storing a control program (firmware) executed by the microprocessor 125, and a RAM (Random Access Memory) 127 used when the program is executed. And a microprocessor unit. The microprocessor 125 controls data transfer between the interfaces 121 and 122 and the cache memory device 123.
[0024]
The host interface 121 is connected to the host computer 20 and serves as an interface with the host computer 20. The host interface 121 controls data transfer with the host computer 20 and transfers data from the host computer 20 to the cache memory device 123 or the RAM 127 (used by the microprocessor 125) via the data transfer bus 124. The control and the control of transferring the data in the cache memory device 123 or the RAM 127 to the host computer 20 are performed.
[0025]
The disk interface 122 is connected to the HDD 110, and controls a procedure for performing data transfer between the data transfer bus 124 and the HDD 110. Specifically, the disk interface 122 performs control to transfer data from the HDD 110 to the cache memory device 123 or the RAM 127 and control to transfer data in the cache memory device 123 or RAM 127 to the HDD 110.
[0026]
The cache memory device 123 includes a cache memory 128 for temporarily storing transfer data between the HDD 110 and the host computer 20, and a cache control LSI 129 that controls the cache memory 128. The cache memory 128 has a specific area 128a. This area 128a is managed separately from a cache area for storing transfer data between the HDD 110 and the host computer 20. The area 128a is used to temporarily hold a data address, a size, and a CRC code string to be described later.
[0027]
On the host computer 20, various application programs 21 used for performing processing intended by the user and the support program 22 operate in parallel. The support program 22 is monitoring software for causing the host computer 20 to function as monitoring means for monitoring the disk array device 10 and making various settings for the disk array device 10.
[0028]
Next, with regard to the operation of the configuration of FIG. 1, processing for detecting an abnormality in the data path between the host computer 20 and the disk array device 10 by the patrol for the disk array device 10 from the host computer 20 (first operation) 1) and a process for detecting a data path abnormality between the disk array controller 12 in the disk array device 10 and the HDD 110 (second data path abnormality detection process) will be described as an example.
[0029]
First, in order to facilitate understanding of the data path abnormality detection processing, refer to FIG. 2 for a conventionally known data flow when the host computer 20 requests data write / read from the disk array device 10. To explain.
[0030]
<Flow of write data>
A write request (write command) from the host computer 20, for example, a write request according to the application program 21 is transmitted via the path A 1 in FIG. 2, that is, the host interface 121 of the disk array controller 12 in the disk array device 10, and data transfer The data is transferred to the RAM 127 in the main controller 120 via the bus 124.
[0031]
Data (write data) from the host computer 20 is transferred to the cache memory device 123 via the path A2 in FIG. 2, that is, the host interface 121 of the disk array controller 12 and the data transfer bus 124. The data is temporarily stored in the cache memory 128 under the control of the cache control LSI 129 in the cache memory device 123.
[0032]
In the disk array device 10 shown in FIG. 1, in response to a write request from the host computer 20, a so-called write-back cache that returns completion of execution of the write request to the host computer 20 at the stage of writing the write data to the cache memory 128. The method is applied.
[0033]
Therefore, after the completion of execution of the write request is returned to the host computer 20, the microprocessor 125 in the disk array controller 12 interprets the write request and determines the write data division destination HDD 110. Then, the microprocessor 125 sends a write instruction to the corresponding disk interface 122 in the disk array controller 12 so that the corresponding write data on the cache memory 128 is transferred via the path A3 in the path of FIG. The data is transferred to the HDD 110 via the transfer bus 124 and the disk interface 122.
[0034]
<Flow of read data>
A read request (read command) from the host computer 20 is transferred to the RAM 127 in the disk array controller 12 via the path A1 in FIG.
[0035]
The microprocessor 125 in the disk array controller 12 interprets the read request from the host computer 20 and causes the cache control LSI 129 to determine whether or not the data specified by the request exists on the cache memory 128.
[0036]
If the data specified by the read request does not exist on the cache memory 128, the corresponding disk interface 122 is instructed to read out data stored in a plurality of HDDs 110, for example, from the HDD 110.
[0037]
Thereby, the disk interface 122 transfers the data instructed from the microprocessor 125, that is, the data requested from the host computer 20, from the HDD 110 to the cache memory 128 via the path A3 in FIG. At this time, in the case where it is predicted that the subsequent continuous data will be continuously read, the subsequent continuous data is generally transferred to the cache memory 128. However, since this prediction method is not directly related to the present invention, description thereof is omitted. The data transferred from the HDD 110 to the cache memory 128 is transferred to the host computer 20 via the path A2 in FIG.
[0038]
<First data path error detection process>
Next, a first data path abnormality detection process related to the present invention will be described with reference to FIG.
[0039]
First, in the disk array device 10, when a write request according to the application program 21 is given from the host computer 20, data write for writing the requested write data into the cache memory 128 is performed (step B1).
[0040]
The microprocessor 125 reads the write data written in the cache memory 128, and predetermines a data block (for example, a sector that is a recording unit of the HDD 110) by designation from the support program 22 operating on the host computer 20. A redundant code, for example, a CRC (Cyclic Redundancy Check) code is generated in units of data blocks matching the size, and the cache memory 128 together with the address of the corresponding data (here, the first disk address) and the size of the redundant code column The area is held in the upper area 128a (step B2).
[0041]
In the present embodiment, the CRC code generation is not performed every time a write request is sent from the host computer 20, but for example, as shown in FIG. Is performed only on the data written in response to However, if the write request is not executed at the timing of the fixed time interval T, a CRC code is generated for the data written in response to the first subsequent write request. The time interval T is set in advance by designation from the support program 22. As shown in FIG. 4B, every predetermined number (number) of write requests (here, every two write requests), that is, at a predetermined number (number) of write request intervals, CRC code generation may be performed on data written in response to the write request.
[0042]
In accordance with the support program 22, the host computer 20 makes an inquiry for data path monitoring to the disk array device 10 at the fixed time interval (or at a fixed number of write request intervals) (step B3).
In response to this, the microprocessor 125 in the disk array device 10 notifies the host computer 20 of the data address, size, and redundant code string held in the area 128a on the cache memory 128 (step B4). .
[0043]
When the host computer 20 is notified of the data address, size, and redundant code string from the disk array device 10 to the support program 22, the host computer 20 reads in accordance with the support program 22 to read data specified by the notified data address and size. The request is sent to the disk array device 10 (step B5).
[0044]
In response to this, the microprocessor 125 in the disk array apparatus 10 causes the cache control LSI 129 to read the corresponding data from the cache memory 128 and transfer it to the host computer 20 via the data transfer bus 124 and the host interface 121. (Step B6).
[0045]
When the corresponding data is returned from the disk array device 10 in response to the read request according to the support program 22, the host computer 20 generates a CRC code in units of data blocks for the data according to the support program 22, and first The CRC code notified from the disk array device 10 is compared (steps B7 and B8).
[0046]
If the two codes match as a result of the CRC code comparison (step B9), the host computer 20 determines the data path between the host computer 20 and the disk array device 10 (corresponding to the path A1 in FIG. 2). ) The above circuit is determined to be normal, and the next abnormality detection timing is awaited.
[0047]
On the other hand, if the two codes do not match as a result of the CRC code comparison (step B9), the mismatch is caused by overwriting (updating) the corresponding data, or the disk array device. 10, the host computer 20 determines whether or not the data has been updated with respect to the disk array device 10 according to the support program 22 in order to determine whether or not the circuit on the data path to the disk 10 is abnormal. An inquiry is made (step B10).
[0048]
In response to this inquiry, the microprocessor 125 in the disk array device 10 determines whether or not the corresponding data in the cache memory 128 has been updated (overwritten) by a new write request from the host computer 20 according to the application program 21. A response to be notified is returned to the support program 22 (step B11).
[0049]
In response to this response, the host computer 20 is notified that the corresponding data has not been updated (overwritten) in response to the read request according to the support program 22 (step B12). It is determined that there is an abnormality in the data path between the computer 20 and the disk array device 10, and more specifically, an abnormality in any circuit on the data path. In this case, the host computer 20 notifies the disk array device 10 and the application program 21 of the data path abnormality with the disk array device 10 according to the support program 22, and then operates to disconnect the disk array device 10 (step). B13, B14).
[0050]
On the other hand, when it is notified from the disk array device 10 that the corresponding data has been updated (overwritten) (step B12), the host computer 20 indicates that the cause of the CRC code mismatch between the disk array device 10 and the disk array device 10 is As it is impossible to determine whether or not there is an abnormality in the data path, the next abnormality detection (patrol) timing is awaited.
[0051]
In the above description, a response is returned from the disk array device 10 in response to an inquiry about the presence or absence of data update (data update confirmation) from the host computer 20, but the present invention is not limited to this. For example, when the data used to generate the CRC code in step B2 is updated before receiving a read request for the data according to the support program 22 from the host computer 20, the fact that It may be returned when it is updated, or it may be returned instead of the requested data when the read request is given.
[0052]
In addition, in order to prevent the data used to generate the CRC code from being overwritten by the application program 21, a copy of the data is checked (monitored) as data for check (monitoring), for example, the data address, It may be held together with the size and CRC code string and managed separately from the original data. However, in this case, the host computer 20 cannot read the corresponding data (check data) with a normal read request. Therefore, in step B5, it is preferable that the check data can be read by distinguishing it from a normal read request by a dedicated read request (read command).
[0053]
<Second data path error detection process>
Next, a second data path abnormality detection process related to the present invention will be described with reference to FIG.
[0054]
The feature of the second data path abnormality detection process in the present embodiment is that the disk array device at the time of writing that matches a preset interval (here, time interval) among the data writing from the cache memory 128 to the HDD 110. In the data path between the disk array 11 and the HDD 110, data is read / written to the management area of the microprocessor 125 reserved in the HDD 110 from the microprocessor 125 in the memory 10. The point is to confirm that no garbled error has occurred. The details of the second data path abnormality detection process are as follows.
[0055]
First, the microprocessor 125 writes (writes back) the data on the cache memory 128 to the HDD 110 (step C1). If this writing matches the above interval, the microprocessor 125 writes a copy of the data written in the HDD 110 in another specific area of the HDD 110 (step C2). This specific area is a management area of the microprocessor 125 that is not opened (not used) by the user. Therefore, the data on the management area is not overwritten with the user data. The microprocessor 125 sets the original data on the cache memory 128 as invalid data that cannot be seen by the application program 21 (user), and holds the data as HDD check data.
[0056]
Next, the microprocessor 125 reads the data stored in the specific area from the specific area of the HDD 110 into a work area (not shown) secured on the RAM 127, and the corresponding original data on the cache memory 128. The data path between the cache memory 128 and the HDD 110 (corresponding to the path A3 in FIG. 2), that is, between the disk array controller 12 and the HDD 110, is compared with the HDD check data. Whether the data path is normal or abnormal is determined (step C3).
[0057]
If an abnormality is determined in step C3, the microprocessor 125 sets a status for notifying that in the disk interface 122 so that it can be read from the host computer 20 according to the support program 22. Further, a configuration in which the disk array controller 12 does not respond to a request from the host computer 20 is possible.
[0058]
Note that the data read from the specific area of the HDD 110 is not read into the work area on the RAM 127 but is read into an area different from the original data on the cache memory 128, and the data on this different area and the original data on the cache memory 128 are read The microprocessor 125 may compare (HDD check data).
[0059]
Further, the cache control LSI 129 may compare the data on the separate area and the HDD check data on the cache memory 128. For this purpose, the microprocessor 125 specifies the start address and size on the cache memory 128 in which the data in the other area is stored, and the HDD check data are stored in the cache control LSI 129. The cache control LSI 129 may be activated by designating the start address and size on the cache memory 128 that is present. In this way, the cache control LSI 129 itself can compare the data in the area on the cache memory 128 specified by the head address and the size. Thus, instead of the comparison processing by the microprocessor 125 (program processing thereof), the comparison processing by the cache control LSI 129 (hardware) is performed, so that the processing speed can be increased.
[0060]
In addition, a CRC code of the data is generated when the data on the cache memory 128 is written to the HDD 110, and a CRC code is also generated when the data is read from the HDD 110, so that both CRC codes are compared. However, it is possible to detect an abnormality in the data path between the cache memory 128 and the HDD 110. Details of the procedure of the data path abnormality detection process (second data path abnormality detection process) by CRC code comparison will be described with reference to the flowchart of FIG.
[0061]
First, when the microprocessor 125 writes (writes back) the data on the cache memory 128 to the HDD 110, if this writing matches the above interval, the CRC code CRC1 of the data is set according to the support program 22. A data block of the same size (here, a data block that matches the sector size) is generated as a unit, and is stored in a work area on the RAM 127 (or a specific area 128a on the cache memory 128) (step D1).
[0062]
Next, the microprocessor 125 reads the data written in the HDD 110 in step D1, and generates a CRC code CRC2 of the data for each data block (step D2). The microprocessor 125 compares the generated CRC code CRC2 with the CRC code CRC1 generated at the time of writing to the previous HDD 110, so that the data path between the cache memory 128 and the HDD 110 is normal or abnormal. Is determined (step D3).
[0063]
In the above-described embodiment, the CRC code generation in the disk array controller 12 has been described as being performed by the microprocessor 125. However, the present invention is not limited to this. For example, the cache control LSI 129 may have the CRC code generation function (1) or (2) described below, and the cache control LSI 129 may generate a CRC code.
[0064]
<CRC code generation function (1)>
The CRC code generation function (1) is used when reading data from the cache memory 128, for example, at time intervals designated from the support program 22 of the host computer 20, that is, when transferring read data from the cache memory 128 to the host computer 20, or When the write data is transferred from the cache memory 128 to the HDD 110 and at a timing matching the above time interval, a CRC code corresponding to a preset data size is calculated from the support program 22 of the host computer 20 and designated in advance. This function stores the operation result in the register of the memory or cache control LSI 129.
[0065]
This CRC code generation function (1) can be used, for example, to generate a CRC code at step D1 in FIG. 6, that is, to generate a CRC code of the data when the data on the cache memory 128 is read and written to the HDD 110.
[0066]
<CRC code generation function (2)>
The CRC code generation function (2) is used when data is written to the cache memory 128, for example, at time intervals designated by the support program 22 of the host computer 20, that is, when write data is transferred from the host computer 20 to the cache memory 128, or When the read data is transferred from the HDD 110 to the HDD 110 and at a timing matching the above time interval, a CRC code corresponding to a data size set in advance from the support program 22 of the host computer 20 is calculated, and a memory designated in advance is calculated. Alternatively, it is a function for storing the operation result in the register of the cache control LSI 129.
[0067]
If the CRC code of the data is generated when the data transferred from the host computer 20 to the disk array device 10 is written into the cache memory 128 using the CRC code generation function (2), the CRC code is The host computer 20 (upper support program 22) can be notified in step B4 in the first data path error detection process.
[0068]
In addition, this invention is not limited to the said embodiment, In the implementation stage, it can change variously in the range which does not deviate from the summary. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention If (at least one of) is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.
[0069]
【The invention's effect】
As described above in detail, according to the present invention, the first redundant code generation for the write data on the disk array device side is performed independently of the application program according to the setting from the monitoring program, and the disk on the host computer side Reading the data specified by the data specifying information acquired from the inquiry to the array device and the response to the inquiry, generating the second redundant code, and comparing the first and second redundant codes are performed according to the monitoring program, It is performed independently from the application program without performing communication between them. Therefore, according to the present invention, even if the write data transferred from the host computer itself does not have a redundant code for data protection, a data error occurs due to an abnormal data path between the host computer and the disk array controller. In this case, the detection rate can be improved, and there is no need to exchange data between the application program and data.
[0070]
Further, according to the present invention, in the disk array controller, when the write data transferred from the host computer and written in the cache memory is written to the disk storage device, the write data is used, thereby the disk array controller and the disk storage. It is possible to monitor the data path abnormality with the apparatus and improve the detection rate when a data error occurs due to the data path abnormality.
[0071]
As described above, according to the present invention, it is possible to improve the detection rate when a data error occurs due to an abnormality in a target data path between the host computer and the disk storage device in the disk array device.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining a data flow when a data write / read is requested from the host computer 20 to the disk array device 10;
FIG. 3 is a flowchart for explaining a first data path abnormality detection process in the embodiment;
FIG. 4 is a view for explaining an example of CRC code generation conditions in the first data path abnormality detection process;
FIG. 5 is a flowchart for explaining second data path abnormality detection processing in the embodiment;
FIG. 6 is a flowchart for explaining a modification of the second data path abnormality detection process;
[Explanation of symbols]
10. Disk array device
12 ... Disk array controller
20: Host computer
21 ... Application program
22 ... Support program (monitoring program)
110: HDD (disk storage device)
120 ... Main control unit
121 ... Host interface
122 ... Disk interface
123 ... Cache memory device
124: Data transfer bus
125 ... Microprocessor
126 ... ROM
127 ... RAM
128: Cache memory
128a ... specific area
129: Cache control LSI

Claims (11)

A disk array controller including a host computer, a disk array including a plurality of disk storage devices, and a cache memory for controlling the disk array and temporarily storing transfer data between the host computer and the disk storage device And is applied to a computer system in which monitoring of the disk array device and various settings for the disk array device are performed by a monitoring program that operates in parallel with an application program on the host computer. A data path error detection method by patrol of a disk array device,
When a write request issued from the host computer to the disk array device matches a preset timing, it is transferred from the host computer to the disk array device and written to the cache memory in response to the write request. Generating a first redundant code of write data in units of data blocks of a preset size;
Performing an inquiry for data path monitoring between the host computer and the disk array device from the host computer to the disk array device at intervals corresponding to the timing according to the monitoring program;
In response to the inquiry, notifying the host computer of data designation information for designating the first redundant code generated at that time and the corresponding data;
Reading data designated by the data designation information notified from the disk array device from the cache memory to the host computer;
Generating a second redundant code of data read by the host computer in units of the data block according to the monitoring program;
The first redundant code notified from the disk array device is compared with the second redundant code, and whether there is an abnormality in the data path between the host computer and the disk array device based on at least the comparison result And a data path error detection method by patrol of the disk array device. 2. The data path abnormality detection method by patrol of a disk array device according to claim 1, wherein the timing is a time interval set in advance according to the monitoring program or an interval of the number of write requests. If the first redundant code and the second redundant code do not match, the host computer inquires to the disk array device whether or not the original data in the cache memory has been updated. In addition,
2. The disk array device according to claim 1, wherein when a response indicating that the original data has not been updated is returned, an abnormality in a data path between the host computer and the disk array device is determined. Data path error detection method by patrol of Another specific area on the cache memory in which a copy of the data on the cache memory used to generate the first redundant code can be read only by a dedicated read request according to the monitoring program from the host computer To keep
The step of reading data specified by the data specification information notified from the disk array device from the cache memory to the host computer reads the data in the specific area using the dedicated read request. Item 8. A data path error detection method by patrol of the disk array device according to Item 1. When writing the write data transferred from the host computer and written to the cache memory to the disk storage device, a copy of the data is written to another specific area of the disk storage device and the data on the cache memory The invalid data invisible to the application program,
Data between the disk array controller and the disk storage device is read by reading the data written in the specific area of the disk storage device to the disk array controller and comparing it with the original data on the cache memory. 2. The data path abnormality detection method by patrol of a disk array device according to claim 1, further comprising the step of determining whether there is a path abnormality. When writing the write data transferred from the host computer and written in the cache memory to the disk storage device, a third redundant code of the data is generated in units of the data block and stored in the disk array controller. Holding step;
Reading data in the disk storage device used to generate the third redundant code to the disk array controller and generating a fourth redundant code of the data in units of the data block;
By comparing the fourth redundant code with the third redundant code held in the disk controller, it is determined whether there is an abnormality in the data path between the disk array controller and the disk storage device. 2. The data path abnormality detection method by patrol of a disk array device according to claim 1, further comprising a step. Host computer on which various application programs operate, disk array including a plurality of disk storage devices, and cache memory for controlling the disk array and temporarily storing transfer data between the host computer and the disk storage devices In a computer system comprising a disk array device composed of a disk array controller incorporating
The disk array controller
When a write request issued from the host computer to the disk array device matches a preset timing, it is transferred from the host computer to the disk array device and written to the cache memory in response to the write request. First redundant code generation means for generating a first redundant code of write data in units of data blocks of a preset size;
In response to an inquiry from the host computer for monitoring the data path between the host computer and the disk array device, the first redundant code generated by the first redundant code generation means at that time And means for notifying the host computer of data designation information for designating the write data used to generate the first redundant code,
The host computer
Means for making the inquiry to the disk array device at intervals corresponding to the timing;
In response to the inquiry, the data is received from the disk array device, and the data is received in response to the first redundant code and data specifying information for specifying the write data used to generate the first redundant code. Means for reading the data from the disk array device by a read request for requesting data on the cache memory designated by the designation information;
Second redundant code generation means for generating a second redundant code of data read from the disk array device in response to the read request in units of the data block;
The second redundant code generated by the second redundant code generating means is compared with the first redundant code notified from the disk array device in response to the inquiry, and at least based on the comparison result A computer system comprising: means for determining whether or not a data path between the host computer and the disk array device is abnormal. The disk array controller
When writing the write data transferred from the host computer and written to the cache memory to the disk storage device, a copy of the data is written to another specific area of the disk storage device and the data on the cache memory Write data storage means that is invalid data that cannot be seen from the application program and is data for checking;
By reading the data written in the specific area of the disk storage device by the write data storage means to the disk array controller and comparing it with the original data on the cache memory, the disk array controller and the disk storage 8. The computer system according to claim 7, further comprising means for determining the presence / absence of an abnormality in the data path to the apparatus. The disk array controller
Third redundant code generation means for generating a third redundant code of the data in units of the data block when writing the write data transferred from the host computer and written in the cache memory to the disk storage device When,
Fourth redundant code generation means for reading data in the disk storage device used for generating the third redundant code and generating a fourth redundant code of the data in units of the data block;
By comparing the fourth redundant code generated by the fourth redundant code generating means with the third redundant code generated by the third redundant code generating means, the disk array controller and the disk 8. The computer system according to claim 7, further comprising means for determining whether there is an abnormality in a data path to the storage device. In a disk array controller including a cache memory for controlling a disk array including a plurality of disk storage devices and temporarily storing transfer data between a host computer on which various application programs operate and the disk storage device,
When writing the write data transferred from the host computer and written to the cache memory to the disk storage device, a copy of the data is written to another specific area of the disk storage device and the data on the cache memory Write data storage means that is invalid data that cannot be seen from the application program and is data for checking;
By reading the data written in the specific area of the disk storage device by the write data storage means to the disk array controller and comparing it with the original data on the cache memory, the disk array controller and the disk storage A disk array controller comprising: means for determining the presence / absence of an abnormality in a data path to the apparatus. In a disk array controller including a cache memory for controlling a disk array including a plurality of disk storage devices and temporarily storing transfer data between a host computer on which various application programs operate and the disk storage device,
When writing the write data transferred from the host computer and written in the cache memory to the disk storage device, a first redundancy code of the data is generated in units of data blocks of a predetermined size. Redundant code generation means,
Second redundant code generation means for reading data in the disk storage device used for generating the first redundant code and generating a second redundant code of the data in units of the data block;
The disk array controller and the disk are compared by comparing the second redundant code generated by the second redundant code generating means with the first redundant code generated by the first redundant code generating means. A disk array controller comprising: means for determining whether there is an abnormality in a data path to the storage device.

Images