JP3956980B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device and an electronic apparatus.

For example, in an active matrix TFT (Thin Film Transistor) type liquid crystal device, RGB data is analog-converted by a data line driving circuit and supplied as a data signal voltage to a data line in the liquid crystal panel. A data signal voltage supplied to each data line from the data line driving circuit, which is also a voltage supply source, charges each pixel corresponding to the selected scanning line. At this time, particularly in a large-screen liquid crystal device, when a scanning line is selected from the side closer to the data line driving circuit within one frame period, the data line driving circuit reaches the pixel to be charged toward the end of the frame period. The distance of becomes far.
JP-A-8-30240 JP-A-10-111673 JP-A-10-268842 JP 62-217225 A JP 7-318898 A JP-A-5-119748 JP-A-5-173504 JP-A-4-181213

  In the above-described liquid crystal device, when the data signal voltage is supplied to the data line, the wiring resistance / wiring capacitance increases and the influence of the wiring delay increases especially as the liquid crystal panel has a larger screen.

FIG. 21 shows a T-type or π-type model in which this wiring delay is simply modeled. FIG. 21A shows a voltage supply source 300 corresponding to a data line driving circuit of a liquid crystal device, a line L corresponding to a data line having parasitic resistances R1 to R3, and parasitic capacitances C _{1 to} C of the data lines and pixels. ₃ .

FIG. 21 (b), when a voltage is supplied to the line L from the voltage source 300, the time course of each of the capacitance C ₁ -C ₃ connected to each point of the point P ₁ to P ₃ are charged Show. The capacitor C _{1 at the} point P ₁ is rapidly charged because the distance from the voltage supply source 300 is the shortest. For this reason, the necessary voltage V ₁ can be reached at _a time point t _a between the predetermined periods t _{1 and} t ₂ . In comparison, the capacitor C _{3 at} the point P ₃ is farthest from the voltage supply source 300, and thus exhibits a charging characteristic with a gentle gradient. For this reason, the required voltage V ₁ cannot be reached during the predetermined period t _{1 to} t ₂ , and finally reaches the required voltage V ₁ at time t _c .

  The above-described model can be applied to a liquid crystal device, and there has been a problem that a selected pixel cannot be charged to a predetermined voltage within a predetermined period.

  The present invention has been made in view of such problems, and an object thereof is to provide an electro-optical device and an electronic apparatus that can charge a selected pixel to a predetermined voltage within a predetermined time.

  In order to solve the above-described problem, according to one embodiment of the present invention, a voltage is supplied to each pixel formed of an electro-optical material and corresponding to intersections of a plurality of scanning lines and a plurality of data lines, An electro-optical device that charges the pixel to a predetermined voltage within a charging period of the scanning line driving unit that sequentially supplies a scanning signal for selecting one of the plurality of scanning lines to the plurality of scanning lines. First data line driving means for supplying a data signal from one end of each of the plurality of data lines; and second data line driving means for supplying a data signal from the other end of each of the plurality of data lines; Means for supplying a data signal to each of the data lines from the second data line driving means in synchronization with a data signal being supplied to each of the data lines by the first data line driving means; And having the second data line driving means Data signal is supplied, characterized in that said gradation display accuracy than the data signal supplied from the first data line driving means is set low.

  According to one embodiment of the present invention, a data signal voltage can be supplied from both ends of each data line of an electro-optical panel, and a pixel cannot be sufficiently charged within a selection period due to parasitic resistance, parasitic capacitance, or the like. Can solve the problem.

  According to another aspect of the present invention, a voltage is supplied to each pixel formed of an electro-optical material and corresponding to the intersections of a plurality of scanning lines and a plurality of data lines, and is supplied within a predetermined charging period. An electro-optical device for charging the pixels to a predetermined voltage, the scanning line driving unit sequentially supplying a scanning signal for selecting one of the plurality of scanning lines to the plurality of scanning lines; A first data line driving means for supplying a data signal from one end of each of the data lines; a second data line driving means for supplying a data signal from the other end of each of the plurality of data lines; and the scanning line driving. Means for supplying a data signal from the second data line driving means to each of the data lines based on the distance between the scanning line selected by the means and the first data line driving means for supplying the data signal; The second data line drive Data signal supplied from the means is characterized in that said gradation display accuracy than the data signal supplied from the first data line driving means is set low.

  According to another aspect of the present invention, when the distance between the first data line driving unit that is a voltage supply source and each selected pixel is short, only the first data line driving unit is driven, and the distance is When the distance is long, the second data line driving means can be used in combination. In this way, the second data line driving means only needs to be driven when necessary, which can solve the problem that the pixel cannot be sufficiently charged within the selection period due to parasitic resistance, parasitic capacitance, etc. Electric power can be reduced.

  Further, in one aspect and another aspect of the present invention, the data signal supplied from the second data line driving unit is displayed in gray scale as compared with the data signal supplied from the first data line driving unit. The accuracy may be set low. In this case, the second data line driving means performs only coarse gradation display, and the detailed gradation display is performed by the first data line driving means. Even with this second data line driving means alone, if the selected pixel is close, it can be rapidly charged.

  In addition, the electro-optical device according to the invention can be applied to an electronic apparatus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram of a TFT liquid crystal device according to the first embodiment of the present invention.

  The liquid crystal device includes a liquid crystal panel 10, a signal control circuit unit 12, a gradation voltage circuit unit 14, a power supply circuit unit 16, a line driving circuit 20, a data line driving circuit 22, a transformer circuit 24, and the like.

Here, the pixels formed in the liquid crystal panel 10 are defined by M (1,1) to M (m, n). The generic term for the lines driven by the line driving circuit 20 is Y, and the generic term for the data lines driven by the data line driving circuit is X. Of these, Y ₁ , Y ₂ ,..., Yn are designated when a specific line is designated, and X ₁ , X ₂ ,..., Xm are designated when a specific data line is designated. Note that m and n are natural numbers.

The liquid crystal panel 10 is composed of (m × n) pixels (for example, in the present embodiment, described as m = 800, n = 600). In the liquid crystal panel 10, in a certain pixel M (1, 1) is the source of the thin-film transistor element (TFT element) 30 is the data line X ₁ is, lines Y ₁ to the gate are connected. The data lines X _{1 to} Xm are driven by the data line driving circuit 22 and the transformer circuit 24, and the lines Y _{1 to} Yn are driven by the line driving circuit 20, respectively. A pixel electrode 32 is provided at the drain of the TFT element 30. With the pixel electrode 32 as one end, the voltage stored in the capacitor 34 is applied to the liquid crystal layer. The capacitor 34 includes a pixel capacitor applied to the liquid crystal layer and a holding capacitor for holding a voltage. Although not shown, a counter electrode facing the pixel electrode 32 is usually provided through a liquid crystal layer.

  In the liquid crystal panel 10, (m × n) pixels having the same configuration as the pixel M (1, 1) as described above are formed.

  The liquid crystal device of FIG. 1 is supplied with a power supply, a data signal, and a synchronization signal from the outside.

  The signal control circuit unit 12 supplies the data signal Da, the clock signal CLK 1, and the horizontal synchronization signal Hsync to the data line driving circuit 22. For example, the data line driving circuit 22 latches the data signal Da, which is an RGB signal composed of 8 bits, at the timing of the clock signal CLK1. After the data signal Da for one line is latched, the horizontal synchronization signal Hsync is supplied to the data line driving circuit 22. Based on the horizontal synchronization signal Hsync, the latched data signal Da for one line is converted into an analog signal, then impedance-converted, and supplied to the data line X as the data signal voltage Vd.

Further, the signal control circuit unit 12 supplies the clock signal CLK 2 and the vertical synchronization signal Vsync to the line driving circuit 20. The line driving circuit 20 sequentially switches the line Y to be selected at the timing of the clock signal CLK2. During a period when a specific line Y is selected, a voltage V _g that turns on the gate of the TFT element 30 connected to the line Y is applied. In synchronization with the turning on of the gate, the data signal voltage Vd output from the data line driving circuit 22 is supplied to the data line X. After one frame period in which all the lines Y of the liquid crystal panel 10 (screen) are scanned, the vertical synchronization signal Vsync is supplied to the line driving circuit 20, whereby the line Y is scanned again from the head.

  The power supply circuit unit 16 supplies power to the gradation voltage circuit unit 14, the line drive circuit 20, the data line drive circuit 22, the transformer circuit 24, and the like.

  Next, the transformer circuit 24 will be described below with reference to FIGS.

  FIG. 2A shows a diagram in which the data signal voltage Vd supplied from the voltage follower 142 that is an internal circuit of the data line driving circuit 22 is supplied to the data line X through the transformer circuit 24.

  The transformer circuit 24 includes a voltage generation circuit 130, an addition circuit 140, and a switching element 144.

  The adder circuit 140 is a circuit that inverts and outputs the sum of input voltages, and superimposes the capacitor 134 having a linear charging characteristic and the original data signal voltage Vd supplied from the data line driving circuit 22. Note that the period during which the voltage of the capacitor 134 is superimposed is controlled by opening and closing the switching element 144.

As shown in FIG. 2A, the voltage generation circuit 130 includes a constant current circuit 132, a capacitor 134, a switching element 136, and the like. The constant current circuit 132 and the switching element 144 are connected in series via the voltage follower 138. Further, the capacitor 134 and the switching element 136 are connected in parallel with the node A ₁ as one end. The other end of the capacitor 134 and the switching element 136 are both grounded. The signal φ _W1 supplied to the switching element 136 is supplied in synchronization with the vertical synchronization signal Vsync supplied every frame period.

  A timing chart of the voltage generation circuit 130 is shown in FIG.

The switching element 136 is closed by the signal φ _W1 supplied based on the vertical synchronization signal Vsync which is a signal corresponding to the frame period f, and the charge accumulated in the capacitor 134 is discharged. Thereafter, the switching element 136 is opened, and the capacitor 134 is gradually charged in proportion to the time by the constant current circuit 52 as shown by the waveform C _W1 . Thus, the capacitor 134 exhibits a charging characteristic that is charged linearly from the voltage 0 to the voltage V _W1 during one frame period f.

  The switching element 144 is constituted by, for example, a P-channel MOS transistor, and its opening / closing is controlled by a measurement circuit 150 as shown in FIG.

As shown in FIG. 3A, the measurement circuit 150 includes a constant current circuit 152, a capacitor 154, a switching element 156, a buffer circuit 158, and the like. In the measurement circuit 150, the constant current circuit 152 and the buffer circuit 158 are connected in series. Further, the capacitor 154 and the switching element 156 are connected in parallel with the node A ₂ at the intermediate point as one end. The other ends of the capacitor 154 and the switching element 156 are grounded. The signal φ _S1 supplied to the switching element 156 is supplied in synchronization with the horizontal synchronization signal Hsync supplied to the measurement circuit 150 for each selection period.

  A timing chart of the measurement circuit 150 is shown in FIG.

The switching element 156 is closed by the signal φ _S1 supplied based on the horizontal synchronization signal Hsync that is a signal corresponding to each selection period Hn (1 ≦ n ≦ 600), and the electric charge accumulated in the capacitor 154 is discharged. At the same time, the buffer circuit 158 outputs an “L” level signal φ _S2 . Thereafter, the switching element 156 is opened, and the capacitor 154 is gradually charged in proportion to time by the constant current circuit 152 as shown by the waveform C _S1 . At the same time, at a certain time point t _S , the buffer circuit 158 outputs an “H” level signal φ _S2 .

Therefore, in the period t _S1 ~t _S in the selection period H ₁ shown in FIG. 3 (b), the switching element 144 is turned on, the voltage supplied from the voltage generating circuit 130 of the transformer circuit 24, the measuring circuit 150 The signal is supplied to the adding circuit 140 by control. Then, the boosted data signal voltage V _add is supplied to the data line X. On the other hand, in the period t _{S to} t _S2 , the switching element 144 is turned off, the voltage boosted by the voltage generation circuit 130 is not supplied to the addition circuit 140, and the original data signal voltage Vd is supplied to the data line X. Is done.

Further, in FIG. 4, in this way, shows a timing chart when the data signal voltage V _{the add} obtained by boosting the original data signal voltage Vd is generated by a transformer circuit 24. 4 to 6 described below, this liquid crystal device is driven by a dot inversion method in which the phase is inverted and driven for each dot.

In FIG. 4, the boosted data signal voltage V _add is obtained by using the voltage C _W1 of the capacitor 134 as the data at the timing when the output signal φ _S2 outputs the “H” level voltage in each of the selection periods H _{1 to} Hn. It is generated so as to be superimposed on the signal voltage Vd. By doing so, it becomes possible to superimpose a high voltage on the data signal voltage Vd as the distance between the data line driving circuit 22 as a voltage supply source and each selected pixel increases.

Further, as a modification, FIGS. 5 and 6 show that the voltage C _W1 level is configured as an appropriate circuit, converted by an arbitrary function, and the converted voltage C _W1 is converted into the original data signal voltage Vd. The timing chart when superimposing is shown.

In FIG. 5, the boosted data signal voltage V _add corresponds to C _W1 × C _W1 generated based on the voltage C _W1 level of the capacitor 134 shown in FIG. 2 at the same boost timing as in FIG. The voltage to be generated is further superimposed on the data signal voltage Vd. This also makes it possible to superimpose a higher voltage in the boosting period in which the original data signal voltage Vd is boosted.

In FIG. 6, the boosted data signal voltage V _add is superimposed on the voltage C _{W1 of the} capacitor 134 shown in FIG. 2 in correspondence with the original data signal voltage Vd level at the same boost timing as in FIG. It is generated in the form. Here, a voltage corresponding to C _W1 × Vd is superimposed on the data signal voltage Vd. By doing so, it is possible to superimpose the voltage level boosted corresponding to the original data signal voltage Vd, instead of superimposing the same voltage level uniformly on each original data signal voltage Vd. become.

  7 and 8 show circuit diagrams in the case where a transformer circuit is provided in the data line driving circuit 22 as a modification.

In the transformer circuit 200 of FIG. 7, switching elements 202 to 208 and a capacitor 210 are provided on the supply line that supplies the data signal voltage Vd to the data line X. The switching elements 202 and 208 are controlled to be opened and closed by the clock pulse θ, and the switching elements 204 and 206 are controlled by the clock pulse / θ. The clock pulse / θ is a signal indicating the inverse logic of the clock pulse θ. The clock pulse θ is supplied based on the output signal φ _S2 described above. Even with such a configuration, the capacitor 210 charged by the voltage generation circuit 130 can be superimposed on the original data signal voltage Vd.

Further, in the transformer circuit 220 of FIG. 8, a current mirror circuit configured by the switching elements 222 and 224 is provided. When the switching element 144 is turned on based on the output signal φ _S2 described above, the voltage generated by the voltage generation circuit 130 can be superimposed on the original data signal voltage.

  In the transformer circuit 24, the charging characteristics of the capacitor 134 and the capacitor 154 can be changed by changing the time constant τ of the voltage generation circuit 130, the measurement circuit 150, and the like.

In addition, the threshold voltage _Vth of the switching elements constituting the buffer circuit 158 of the measurement circuit 150 in FIG. 3 may be changed to change the output timing of the “H” and “L” levels. For example, as shown in FIG. 18A, the buffer circuit 158 has two inverter circuits 100 and 101 connected in series. The inverter circuit 100 includes an N channel type MOS transistor 110 and a P channel type MOS transistor 111. The inverter circuit 101 includes an N channel type MOS transistor 112 and a P channel type MOS transistor 113. FIG. 18B shows a cross-sectional view of the inverter 100, for example. In order to change the time until the buffer circuit 158 is turned on, for example, the concentration of the p-type well 104 or the concentration of the n-type well 105 of the inverter 100 is changed. As an example, the threshold voltage can be set lower by increasing the concentration of the n-type diffusion layer 104 of one or both of the N-type MOS transistors 110 and 112 of the inverters 100 and 101. Thereby, the buffer circuit 158 can be quickly turned on. Therefore, the period for boosting the original data signal voltage Vd in the transformer circuit 24 can be shortened.

  Further, the threshold voltage may be changed by changing the gate length or channel width of each of the N-channel MOS transistors 110 and 112 and the P-channel MOS transistors 111 and 113 constituting the inverter 100.

  In this way, the liquid crystal panel 10 can be adjusted to operate optimally by changing the time constant τ and the performance of the switching element itself.

  In this embodiment, the data signal voltage Vd supplied to each pixel corresponding to the scanned line is transformed by a transformer circuit within one frame period. At this time, a boosted high voltage is supplied to the data line X within a certain period within the selection period based on the distance between each selected pixel and the data line driving circuit. This can solve the problem that the pixel cannot be charged sufficiently within the selection period due to parasitic resistance, parasitic capacitance, and the like.

(Second Embodiment)
FIG. 9 is a block diagram of a TFT liquid crystal device according to the second embodiment.

  The liquid crystal device includes a liquid crystal panel 10, a signal control circuit unit 12, a gradation voltage circuit unit 14, a power supply circuit unit 16, a line driving circuit 20, a data line driving circuit 22, a transformer circuit 25, and a counter 26.

  The signal control circuit unit 12 supplies the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync to the counter 26, respectively. The counter 26 has a function of counting the horizontal synchronization signal Hsync, that is, the number of lines Y scanned within one frame period.

  The transformer circuit 25 includes, for example, a booster circuit that determines the boosted voltage level based on the count value of the counter 26, and an adder circuit that superimposes the voltage from the booster circuit on the original data signal voltage Vd. (Not shown).

  Now, the operation of the liquid crystal device in FIG. 9 will be described with reference to the timing chart shown in FIG. The liquid crystal panel 10 in FIG. 9 has a resolution of (800 × 600) pixels, for example. That is, the liquid crystal panel 10 includes pixels M (1, 1) to pixels M (800, 600).

In FIG. 10, for the sake of convenience, the liquid crystal panel 10 is divided into pixels M (1,1) to M (1,199), pixels M (1,200) to M (1,399), and pixel M (1,400). ) To pixel M (1,600). FIG. 10 shows an example of charging characteristics for each of the three pixels, the pixels M (1,1), M (1,200), and M (1,400), divided into these three regions. is there. In this case, a predetermined voltage V ₁ is applied from the data line driving circuit 22 to each of the three pixels M (1,1), M (1,200), and M (1,400).

FIG. 10A shows a state where the line Y ₁ is selected and the corresponding pixel M (1,1) is charged. Pixel M (1, 1) is a time t _a in the selection period t to the line Y ₁ is selected, and is charged to a predetermined voltage V _1.

FIG. 10B shows a state in which the pixel M (1, ₂₀₀ ) corresponding to the selected line Y ₂₀₀ is charged. Here, as described with reference to FIG. 21 described above, as the distance from the data line driving circuit 22 to each pixel to be charged increases, the charging characteristics of the pixel have a gentler gradient. A curve C _b shown in FIG. 10B shows a state in which the pixel M (1,200) is charged with the data signal voltage V ₁ supplied from the data line driving circuit 22. In this case, the predetermined voltage V ₁ is finally reached at time t ₂ approaching the end of the selection period t. However, the curve C _c shown in FIG. 10C has a gentler gradient in the charging characteristics of the pixel because the distance from the data line driving circuit 22 to the pixel to be charged is further increased. For this reason, the predetermined voltage V ₁ cannot be reached within the selection period t. In order to improve such charging characteristics, the pixel is rapidly charged by applying a voltage higher than a predetermined voltage for a certain period within the selection period t.

Here, when the pixel M (1,200) is selected in FIG. 10B, the counter value of the counter 26 indicates 200. At this time, the transformer circuit 25 boosts the data signal voltage V ₁ supplied from the data line driving circuit 22 based on the count value 200. The boosted data signal voltage V ₂ is supplied to the pixel M (1,200) during the period t _{1 to} t _b1 . The time t _b1 later, the voltage supplied to the pixel M (1,200) is Setsu換Ri the original data signal voltage V _1, at time t _b2, stabilized at the predetermined voltage V _1.

In FIG. 10C, similarly, the data signal voltage V ₃ boosted by the transformer circuit 25 is supplied to the pixel M (1,400) during the period t _{1 to} t _c1 . The time t _c1 later, the voltage supplied to the pixel M (1,400) is Setsu換Ri the original data signal voltage V _1, at time t _c2, is stabilized at a predetermined voltage V _1.

The boosted voltage V ₂ is higher than the predetermined voltage V ₁ , and when switched to the voltage V ₁ level at time t _b1 , the voltage can be stabilized at V ₁ within the selection period t. Is set. Similarly, the boosted voltage V ₃ is higher than the voltage V ₂ , and when switched to the voltage V ₁ level at time t _c1 , the voltage can be stabilized at V ₁ within the selection period t. Is set. On the contrary, it is desirable that both the time points t _b1 and t _c1 are set to a short time point from the time point t _{1 in} order to stabilize at the predetermined voltage V ₁ level within the selection time t.

Here, FIG. 11 shows another example of the present embodiment. FIG. 11 shows the charging characteristics when the period for boosting the data signal voltage V ₁ set in FIG. 10 is changed. The above-mentioned three regions are pixels M (1,1) to M (1,199), pixels M (1,200) to M (1,399), and pixels M (1,400) to M (1,600). ) Is supplied with the data signal voltage V ₁ from the data line driving circuit 22.

In FIG. 11B, the data signal voltage Vd is boosted during the period from t ₁ to t _b3 . The period from t _{1 to} t _b3 is set shorter than the corresponding period from t ₁ to t _b1 in FIG. As a result, the predetermined voltage V ₁ is reached at time t _b4 . Similarly in FIG. 11C, the period from t ₁ to t _c3 is shorter than the corresponding period from t ₁ to t _c1 in FIG. This reaches a predetermined voltage V ₁ at time t _c4 .

As described above, as shown in FIGS. 10 and 11, the voltage is selected within the predetermined period t by boosting the predetermined voltage V ₁ to a certain voltage level and changing the period during which the boosted voltage is applied. Each pixel can be controlled to be charged.

In this embodiment, as an example, the liquid crystal panel 10 is divided into three regions, and the data signal voltage V _add boosted by the transformer circuit 25 is supplied to each pixel in each region. However, the present invention is not particularly limited to these three regions, and the liquid crystal panel may be divided into more regions, and different boosted data signal voltages Vd may be supplied to the respective regions. More specifically, in FIG. 9, every time the horizontal synchronization signal Hsync is supplied to the counter 26, that is, every time one line is selected, the data signal voltage Vd supplied to each of the pixels is sequentially changed. The pressure may be increased with.

As described above, the charging characteristics can be changed by changing the time constant τ of each device provided in the transformer circuit 25 and the characteristics of the switching element itself. As a result, the period during which the boosted data signal voltage V _add is supplied to each of the data lines X can be changed as appropriate.

  Thus, in this embodiment, the data signal voltage supplied to each pixel corresponding to the scan-driven line is transformed by the transformer circuit within one frame period. At this time, the boosted high voltage is supplied to the data line X within a certain period within the selection period based on the distance between each selected pixel and the data line driving means. This can solve the problem that the pixel cannot be charged sufficiently within the selection period due to parasitic resistance, parasitic capacitance, and the like.

(Third embodiment)
12 includes a liquid crystal panel 10, a signal control circuit unit 12, a gradation voltage circuit unit 14, a power supply circuit unit 16, a line driving circuit 20, a data line driving circuit 22, a data line auxiliary driving circuit 40, and the like. ing. Here, for example, each 8-bit RGB signal Da is supplied to the data line driving circuit 22.

  The liquid crystal device in FIG. 12 is supplied with a power source, a data signal, and a synchronization signal from the outside.

  Note that the operations of the devices other than the data line auxiliary drive circuit 40 in FIG. 12 are the same as those in FIG.

  The signal control circuit unit 12 supplies each of the clock signal CLK1, the data signal Da, and the horizontal synchronization signal Hsync to the data line auxiliary drive circuit 40. The data line auxiliary drive circuit 40 is supplied with an 8-bit RGB data signal Da or an RGB data signal Da ′ having a lower number of gradations. In the present embodiment, each 8-bit RGB data signal Da is supplied to the data line auxiliary driving circuit 40 as the RGB data signal Da.

  The data line auxiliary drive circuit 40 latches the RGB data signal Da composed of 8 bits at the timing of the clock signal CLK1. In synchronization with the latch of the RGB data signal Da for one line, the horizontal synchronization signal Hsync is supplied to the data line auxiliary drive circuit 40. Based on the horizontal synchronization signal Hsync, the latched RGB data signal Da is converted into an analog signal, then subjected to impedance conversion and supplied to the data line X.

  The gradation voltage circuit unit 14 supplies a reference voltage set in the same voltage range to each of the data line driving circuit 22 and the data line auxiliary driving circuit 40 in order to perform gradation display.

In the liquid crystal device of FIG. 12, two drive circuits, the data line drive circuit 22 and the data line auxiliary drive circuit 40, are provided at positions facing the liquid crystal panel 10. Conventionally, the liquid crystal panel 10 is driven only by the data line driving circuit 22. However, in the liquid crystal device according to the present embodiment shown in FIG. 12, the data line auxiliary drive circuit 22 applies each of the data lines X from the direction of the line Y ₆₀₀ farthest from the data line drive circuit 22 that is a voltage supply source. A data signal voltage Vd is supplied. That is, the data line voltage is supplied to the data line X from the one end of the data line X in the data line driving circuit 22 and the other end of the data line X in the data line auxiliary driving circuit 40.

The operation will be described with reference to the timing chart of FIG. 13 based on the liquid crystal device of FIG. The data line auxiliary drive circuit 40 is driven in combination with the data line drive circuit 22. Hereinafter, for convenience, the liquid crystal panel 10 is divided into two areas, that is, a pixel M (1,1) to a pixel M (1,299) and a pixel (1,300) to a pixel (1,600). The case will be described. FIG. 13 shows the charging characteristics for each of the three pixels, pixel (1,1), pixel (1,300), and pixel (1,600). A curve C _k shows the charging characteristics in the conventional drive for comparison.

In FIG. 13A, since the distance between the data line driving circuit 22 which is a voltage supply source and the selected pixel (1, 1) is short, the pixel (1, 1) is rapidly charged, and the selection period t The predetermined voltage V ₁ is reached at time t _i .

In FIG. 13B, the distances between the data line driving circuit 22 and the data line auxiliary driving circuit 40 which are voltage supply sources and the selected pixel (1,300) are substantially the same. For this reason, the charging characteristic has a slightly gentle slope, and reaches the predetermined voltage V ₁ at the time point t _j within the selection period t.

In FIG. 13C, since the distance between the data line auxiliary drive circuit 40 which is a voltage supply source and the selected pixel (1,600) is short, the pixel (1,600) is rapidly charged, and the selection period The predetermined voltage V ₁ is reached at time t _k within t. Charging characteristic of each pixel in the present embodiment, based on the line Y _300, will exhibit substantially symmetrical charge characteristics.

In the present embodiment, the data line driving circuit 22 and the data line auxiliary driving circuit 40 perform the same gradation display, but the data line auxiliary driving circuit 40 is more than the data line driving circuit 22 as described above. Alternatively, a low gradation display may be performed. For example, as shown in FIG. 14A, only the upper 4-bit data signal Da ′ (1010) is supplied to the data line auxiliary drive circuit 40 with respect to the 8-bit data signal Da (10101010) of the data line drive circuit 22. You may supply. However, the range of the voltage amplitude supplied to the data line X from the data line driving circuit 22 and the data line auxiliary driving circuit 40 is set to be the same. As shown in FIG. 14 (b), to the data signal voltage V _{11, 12} supplied from the data line driving circuit 22 to the data line X, from the data line supplementary driving circuit 40, a data signal voltage V ₁₁ is data Supplied to line X. In this way, even if a rough data signal voltage is supplied to the data line X by the data line auxiliary driving circuit 40, the charging characteristic can be improved in substantially the same manner as the charging characteristic shown in FIG.

  As described above, by driving the two data line driving circuits provided so as to face the liquid crystal panel, the pixel cannot be sufficiently charged within the selection period due to parasitic resistance, parasitic capacitance, and the like. Can be solved.

(Fourth embodiment)
The liquid crystal device shown in FIG. 15 is provided with a counter 27 in the liquid crystal device shown in FIG. A data line auxiliary drive circuit 42 is provided instead of the data line auxiliary drive circuit 40 of FIG. The data line auxiliary drive circuit 42 further has a function of controlling the drive based on the count value supplied from the counter 27.

  The counter 27 receives the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync. Based on the horizontal synchronization signal Hsync, the number of lines Y scanned in one frame period is counted, and the count value is supplied to the data line driving circuit 22 and the data line auxiliary driving circuit 40. The counter 27 is reset by the vertical synchronization signal Vsync at the end of one frame period.

  For example, the 8-bit RGB data signal Da is supplied to the data line driving circuit 22. The data line auxiliary drive circuit 42 is supplied with RGB data signals Da ′ having gradations of 8 bits or lower. In the present embodiment, a coarse RGB data signal Da ′ of upper 4 bits of the RGB data signal Da is supplied to the data line auxiliary drive circuit 42.

  In the liquid crystal device of FIG. 15, two drive circuits of the data line drive circuit 22 and the data line auxiliary drive circuit 42 are opposed to the liquid crystal panel 10 as in the liquid crystal device of FIG. 12 described above. It is provided in the position to do. The data line drive circuit 22 supplies the data signal voltage to the data line X from one end of the data line X, and the data line auxiliary drive circuit 42 supplies the data signal voltage from the other end of the data line X.

  In the present embodiment, the driving of the data line auxiliary drive circuit 42 is controlled according to the distance between the data line drive circuit 22 that is a voltage supply source and the selected pixel.

This operation will be described with reference to the timing chart of FIG. 16 based on the liquid crystal device of FIG. The liquid crystal panel 10 is divided into two areas for convenience, pixel M (1,1) to pixel M (1,299) and pixel (1,300) to pixel (1,600). To do. A curve C _h is, for comparison, shows the charging characteristics of a conventional drive.

In FIG. 16A, the counter 27 receives the first horizontal synchronization signal Hsync and the count value becomes 1. Based on this count value, it is determined whether only the data line driving circuit 22 in FIG. 15 is driven or the data line auxiliary driving circuit 42 is also driven. In the present embodiment, only the data line driving circuit 22 is driven at a count value of 1 to 299, and the data line auxiliary driving circuit 42 is also driven in combination for a certain period within the frame period at a count value of 300 to 600. The Accordingly, in FIG. 16A, only the data line driving circuit 22 is driven and is stable at the predetermined voltage V ₁ at the time point t _g within the selection period t.

In FIG. 16B, the count value of the counter 27 is 400. Therefore, the data line driving circuit 22 and the data line auxiliary driving circuit 42 are driven simultaneously. The data line auxiliary driving circuit 42 supplies the upper 4 bits of each RGB signal Da ′ out of the information of each 8-bit RGB signal Da supplied to the data line driving circuit 22. This will be described again with reference to FIG. For example, as shown in FIG. 14A, the data line auxiliary drive circuit 42 converts the upper 4-bit signal data Da ′ (1010) of the 8-bit signal data Da (10101010) to the data lines X, respectively. To supply. Here, the voltage range of the reference voltage supplied from the gradation voltage circuit unit 14 is the same for both the data line driving circuit 22 and the data line auxiliary driving circuit 42. Therefore, as shown in FIG. 14B, the data line auxiliary drive circuit 42 supplies the data signal voltage V ₁₁ corresponding to the signal data Da ′ (1010) to the data line X ₁ . The 16-gradation data signal voltage V ₁₁ is coarse and slightly lower than the voltages V ₁₁ , ₁₂ that should be supplied to the pixel M (1,400). However, since the distance between the data line auxiliary drive circuit 42 as a voltage supply source and the pixel M (1,600) is short, the pixel M (1,400) is compared with the case where only the data line drive circuit 22 is driven. Is charged rapidly. In this embodiment shown in FIG. 13B, the driving of the data line auxiliary drive circuit 42 is used in combination during the period t _{1 to} t _h1 , so that the pixel M (1,400 at the time t _h2 within the selection period t. ) Can be charged up to a predetermined voltage V ₁ .

In this embodiment, as an example, the liquid crystal panel 10 is divided into two areas before and after the line Y ₃₀₀ is scanned, and only the data line driving circuit 22 is driven in one area, and the other area is driven. In addition to the data line driving circuit 22, the data line auxiliary driving circuit 42 is driven. However, the present invention is not particularly limited to determining whether or not to drive the data line auxiliary drive circuit 42 with the line Y ₃₀₀ as a boundary. It is desirable to determine the timing for driving the data line auxiliary drive circuit 40 in consideration of the charging characteristics of each pixel.

  In the present embodiment, whether or not to drive the data line auxiliary drive circuit 42 is determined with a certain time point in one frame period as a boundary. By doing so, power consumption can be suppressed as compared with the case where the data line auxiliary drive circuit 42 is always driven together with the data line drive circuit 22.

  Further, for example, in the present embodiment, the 4-bit data line auxiliary drive circuit 42 is used for the 8-bit data line drive circuit 22, but the 6-bit or 2-bit data line auxiliary drive circuit 42 is used. May be. Accordingly, among the 8-bit RGB data signals Da used in the present embodiment, the RGB data signals Da ′ such as the upper 6 bits or the upper 2 bits are replaced with the data line auxiliary drive circuit instead of the upper 4 bits. 42.

Furthermore, in the present embodiment, the data line driving circuit 22 and the data line auxiliary driving circuit 42 are driven in combination with a boundary when a certain line Y is scanned in one frame period. However, in the area corresponding to the above-described FIG. 16 (b), the predetermined period t ₁ ~t _h1 is only the data line supplementary driving circuit 42, the data line driving after the time t _h1 in the selection period t in the selection period t Only the circuit 22 may be driven. By doing so, the charging characteristics can be improved, and at the same time, the power consumption can be reduced.

  As described above, by driving the two data line driving circuits provided so as to face the liquid crystal panel, the pixel cannot be sufficiently charged within the selection period due to parasitic resistance, parasitic capacitance, and the like. Can be solved.

(Fifth embodiment)
FIG. 20 shows a modification of the liquid crystal device of FIG. 1 described above. For example, four line drive circuits 20-1, 20-2, 20-3, and 20-4, which are integrated circuits (ICs), are connected in series. The liquid crystal device formed is shown. In such a case, for example, when the scanning of the line in the line driving circuit 20-1 is completed, an enable signal that is a signal for transmitting the scanning is sent to the counter 28. This enable signal is counted by the counter 28. Based on this count value, different data signal voltages can be supplied to the data line X in each of the line drive circuits 20-1, 20-2, 20-3 and 20-4.

  Although not shown, in the other liquid crystal devices of FIGS. 12 and 15 and the like, when the line driving circuit 22 is composed of a plurality of line driving circuits, each line driving circuit is similarly set based on the count value of the enable signal. Different data signal voltages can be supplied to the data line X.

(Counter modification)
In the above-described embodiment, the timing for boosting the data signal voltage Vd by the counters 26, 27, and 28 or the timing for driving the data line auxiliary drive circuits 40 and 42 is determined. However, the timings described above may be determined by a measurement circuit as shown below. The configuration of a measurement circuit provided in place of the counter 26 and the operation of the liquid crystal device having the measurement circuit will be described below with reference to FIG.

  FIG. 17A shows a configuration of the measurement circuit 170, and FIG. 17B shows a timing chart thereof.

The measurement circuit 170 in FIG. 17A includes a constant current circuit 172, a capacitor 174, a switching element 176, and a buffer circuit 178. A constant current circuit 172 and a buffer circuit 178 are connected in series. Further, the capacitor 174 and the switching element 176 are connected in parallel with the node A ₃ at the intermediate point as one end. The other ends of the capacitor 174 and the switching element 176 are both grounded. The signal φ _r1 supplied to the switching element 176 is supplied in synchronization with the vertical synchronization signal Vsync supplied to the measurement circuit 170 every frame period.

FIG. 17B shows a timing chart of the measurement circuit 170. The switching element 176 is closed by the signal φ _r1 supplied based on the vertical synchronization signal Vsync that is supplied corresponding to each frame period f, and the charge accumulated in the capacitor 174 is discharged, and the buffer circuit From 178, an “L” level signal φ _r2 is output. Thereafter, the switching element 176 is opened, and the capacitor 174 is gradually charged in proportion to the time by the constant current circuit 172 as shown by the waveform C _r1 . At the same time, at a certain time point t _r , the buffer circuit 178 outputs an “H” level signal φ _r2 .

The counter 26 is controlled by a digital circuit that counts the input horizontal synchronization signal Hsync. In the measurement circuit 170 shown in FIG. 17, the capacitor 174 is charged by the constant current circuit 172 and controlled by an analog circuit that measures the timing when the buffer circuit 178 is turned on. In FIG. 9, the voltage supplied to the data line X according to the distance between the data line driving circuit 22 as a voltage supply source and each pixel to be charged can be obtained by using such a measurement circuit 170 instead of the counter 26. Can be changed. In this case, the liquid crystal device of Figure 9 for a period of t _r ~t _r2 is the transformer circuit 25 is driven, a certain period within the selection period t, boosted data signal voltage Vd is supplied to the data line X . The measurement circuit 170 can be similarly controlled by using it instead of the counters 26 and 27 of the liquid crystal device shown in FIGS.

  The counter 26 can determine whether or not to boost the data signal voltage Vd based on the counter value. In the measurement circuit 170, it is possible to determine whether or not to boost the data signal voltage Vd by changing the time until the buffer circuit 178 is turned on.

Further, by changing the time constant τ of the measurement circuit 170, the charging characteristics of the capacitor 174 can be changed. Alternatively, the threshold voltage V _th of the switching elements constituting the buffer circuit 178 of the measurement circuit 170 may be changed to change the output timing of the “H” and “L” levels.

  As described above, the timing of the time T until the capacitor is charged can be appropriately set within one frame period even by using the measurement circuit 170. Using this timing, the voltage of the data signal applied before and after the time T can be changed by the transformer circuit 25.

Furthermore, the measuring circuit 170 in FIG. 17, to have one buffer circuit 178, and a period of t _r1 ~t _r, but can be set to two periods of the duration of t _r ~t _r2, further, a plurality By providing this buffer circuit, a plurality of periods can be set.

Figure 19 Measurement circuit 180 (a), for example, are three buffer circuits 178-1,178-2 and 178-3 are connected in parallel to the node A ₃ as one end. The logic signals φ10 to φ12 of the three buffer circuits 178-1, 178-2, and 178-3 are set to have different logic output timings as shown in FIG. 19B. In the case of FIG. 19A, for example, for each of the logic outputs of the three buffer circuits 178-1, 178-2 and 178-3, a data signal voltage Vd can be obtained by appropriately combining a NAND circuit or a NOR circuit. It is possible to determine the timing for further superimposing the voltage on the.

By configuring the measurement circuit 180 in this way, four periods t _{1 to} t _m1 , t _{m1 to} t _m2 , t _{m2 to} t _m3, and t _{m3 to} t ₂ can be set. For example, in FIG. 9, it is possible to improve the charging characteristics of each selected pixel by transforming the data signal voltage Vd supplied from the data line driving circuit 22 by the transformer circuit 25 in each period. become.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention. For example, the present invention is not limited to those applied to the driving of the above-described TFT type liquid crystal device, but is an image display device based on a simple matrix, a TFD (Thin Film Diode) composed of two terminal elements, electroluminescence (EL), plasma. The present invention can also be applied to an image display device using a display device or the like.

  The present invention can be applied to various electronic devices including an electro-optical device, such as a mobile phone, a game device, an electronic notebook, a personal computer, a word processor, a television, and a car navigation device.

It is a figure which shows the liquid crystal device of 1st Embodiment. (A) is a figure which shows the transformer circuit provided in the liquid crystal device of FIG. (B) is a timing chart for explaining the operation of the transformer circuit. (A) is a figure which shows the measuring circuit provided in the transformer circuit of FIG. (B) is a timing chart for explaining the operation of the measurement circuit. It is a figure which shows the timing chart of the liquid crystal device using the transformer circuit shown in FIG. It is a figure which shows the timing chart of the liquid crystal device using the transformer circuit which has another form. It is a figure which shows the timing chart of the liquid crystal device using the transformer circuit which has another form. It is a modification of the internal circuit of the transformer circuit shown to Fig.2 (a). It is another modification of the internal circuit of the transformer circuit shown to Fig.2 (a). It is a figure which shows the liquid crystal device of 2nd Embodiment. It is a figure which shows the charging characteristic of each pixel M (1,1), M (1,200), and M (1,400) of the liquid crystal device shown in FIG. FIG. 10 is another diagram illustrating charging characteristics of the pixels M (1,1), M (1,200), and M (1,400) of the liquid crystal device illustrated in FIG. 9. It is a figure which shows the liquid crystal device of 3rd Embodiment. FIG. 13 is a diagram illustrating charging characteristics of each of pixels M (1,1), M (1,300), and M (1,600) of the liquid crystal device illustrated in FIG. (A) is a figure for demonstrating the data signal supplied to the data line auxiliary | assistant drive circuit in 3rd, 4th embodiment. (B) is a diagram showing the voltage supplied to the data line X from each of the data line driving circuit and the data line auxiliary driving circuit in the third and fourth embodiments. It is a figure which shows the liquid crystal device of 4th Embodiment. FIG. 16 is a diagram illustrating charging characteristics of pixels M (1,1) and M (1,400) of the liquid crystal device illustrated in FIG. 15. (A) is a figure which shows the measuring circuit which measures 1 frame period. (B) is a timing chart for explaining the operation of the measurement circuit. (A) is a figure which shows a buffer circuit. (B) is sectional drawing of an inverter. FIG. 18A is a circuit diagram showing another measurement circuit in which a plurality of buffer circuits are connected in parallel to the measurement circuit of FIG. (B) is a diagram showing a timing chart of the measurement circuit. It is a figure which shows the liquid crystal device of 5th Embodiment. (A) is a circuit diagram of a T-type or π-type model. (B) is a diagram showing the respective charging characteristics of the capacitor C _1, C ₂ and C _3.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Liquid crystal panel, 12 Signal control circuit, 14 Gradation voltage circuit part, 16 Power supply circuit part, 20, 20-1, 20-2, 20-3, 20-4 Line drive circuit, 22 1st data line drive circuit 24, 25 Transformer circuit, 26, 27, 28 Counter, 30 TFT element, 32 Pixel electrode, 34 Pixel capacity and retention capacity, 40, 42 Second data line drive circuit, 100, 101 inverter, 104 n-type diffusion layer 105 p-type diffusion layer, 110, 112 N-channel MOS transistor, 111, 113 P-channel MOS transistor, 130 voltage generation circuit, 132 constant current circuit, 134 capacitance, 136 switching element, 138 voltage follower, 140 addition circuit, 142 Voltage Follower, 144 Su Twitching element, 150 measurement circuit, 152 constant current circuit, 154 capacitance, 156 switching element, 158 buffer circuit, 170 measurement circuit, 172 constant current circuit, 174 capacitance, 176 switching element, 178, 178-1, 178-2, 178 -3, 178-4 Buffer circuit, 180 measuring circuit, 200 transformer circuit, 202, 204, 206, 208 switching element, 210 capacity, 212 voltage follower, 220 transformer circuit, 222, 224 switching element, 226 voltage follower, 300 voltage supply source

Claims (3)

Electricity is formed corresponding to the intersections of the plurality of scanning lines and the plurality of data lines, and supplies a voltage to each of the pixels made of the electro-optic material to charge the pixels to a predetermined voltage within a predetermined charging period. An optical device,
Scanning line driving means for sequentially supplying a scanning signal for selecting one of the plurality of scanning lines to the plurality of scanning lines;
First data line driving means for supplying a data signal from one end of each of the plurality of data lines;
Second data line driving means for supplying a data signal from the other end of each of the plurality of data lines;
Means for supplying a data signal to each of the data lines from the second data line driving means in synchronization with the data signal being supplied to each of the data lines by the first data line driving means;
Have
The data signal supplied from the second data line driving means has a gradation display accuracy set lower than that of the data signal supplied from the first data line driving means. Optical device. Electricity is formed corresponding to the intersections of the plurality of scanning lines and the plurality of data lines, and supplies a voltage to each of the pixels made of the electro-optic material to charge the pixels to a predetermined voltage within a predetermined charging period. An optical device,
Scanning line driving means for sequentially supplying a scanning signal for selecting one of the plurality of scanning lines to the plurality of scanning lines;
First data line driving means for supplying a data signal from one end of each of the plurality of data lines;
Second data line driving means for supplying a data signal from the other end of each of the plurality of data lines;
Based on the distance between the scanning line selected by the scanning line driving means and the first data line driving means for supplying a data signal, the second data line driving means is within the first vertical scanning period. Means for controlling the timing driven in combination with one data line driving means and supplying a data signal to each of the data lines from the second data line driving means,
The data signal supplied from the second data line driving means has a gradation display accuracy set lower than that of the data signal supplied from the first data line driving means. Optical device.   An electronic apparatus comprising the electro-optical device according to claim 1.