JP3948456B2 - Solid-state image sensor and control method of solid-state image sensor - Google Patents

Description

  The present invention relates to a solid-state imaging device suitable for use in an electronic still camera for digital recording, for example, and a control method for the solid-state imaging device.

  Recently, digital electronic still cameras are becoming popular. As a solid-state image sensor suitable for use in an electronic still camera, for example, a CCD image sensor, a sensor having a square lattice and all-pixel readout has been proposed. The square lattice equalizes the vertical interval and the horizontal interval between adjacent pixels, and is used to match the image pickup signal with a personal computer monitor. In order to generate an interlaced output signal, a CCD image sensor used in a conventional video camera or the like accumulates 1/60 seconds (one field) and reads out two pixels as shown in FIG. Interlaced scanning has been realized by mixing two pixels read out by a transfer CCD and shifting the positions of the pixels to be mixed in the odd and even fields.

  Such a CCD image sensor has a 1/60 second accumulation time, and therefore can capture a moving image better than a frame accumulation method with a 1/30 second accumulation time, but has a low vertical resolution. There are disadvantages. Therefore, it is not suitable as an image sensor for an electronic still camera. Therefore, as shown in FIG. 22, an all-pixel readout method has been proposed in which all the pixels are read out by accumulating for 1/30 second. According to this method, it is possible to prevent a decrease in vertical resolution. However, in order to output an image pickup signal from the image pickup device, when the number of pixels is the same, the time is twice as long as that of the image pickup device for a video camera described above. Need. More specifically, an imaging signal having a period of 1/30 second is generated.

  In the case of a digital electronic still camera, a monitor for displaying a captured image, for example, a liquid crystal monitor is often provided in order to focus at the time of shooting or to adjust the camera angle at the time of shooting. A liquid crystal monitor normally displays a television image in a 1/60 second non-interlaced scan. Therefore, as shown in FIG. 23, when an imaging signal having a 1/30 second period is supplied to a liquid crystal monitor as it is, there is a problem that distortion of a display image occurs. In order to avoid this, as shown in FIG. 24, it is necessary to convert the frame rate with respect to the liquid crystal monitor 62 by a VRAM (video RAM) 61 (or a frame memory). An imaging signal having a 1/30 second period is supplied to the VRAM 61, and a non-interlace signal having a 1/60 second period is generated at the output thereof.

  As described above, the image pickup device for reading all pixels is suitable as an image pickup device for an electronic still camera because it has a high vertical resolution. On the other hand, a VRAM or a frame memory is required to display a picked-up image on a normal television monitor. As a result, there was a problem that the cost increased. Furthermore, since the electronic still camera has automatic control devices such as an automatic focus control device, an automatic iris control device, and an automatic white balance control device, the long period of the output signal of the image sensor is a response to these automatic controls. The problem of slowing down occurred. Furthermore, there has been a problem that the motion of the image displayed on the monitor is not smooth.

  One method for solving the above problem is to increase the data rate of the output signal of the image sensor. However, it is necessary to provide a sampling rate converter for this purpose, and as the clock frequency increases, problems such as an increase in power consumption, an increase in cost of components used, and a deterioration in S / N occur. Therefore, a method for increasing the data rate of the imaging signal is not preferable.

  Accordingly, an object of the present invention is to provide a solid-state imaging device capable of outputting an imaging signal at a high speed and a control method for the solid-state imaging device.

In order to solve the above-described problem, the first invention is a plurality of photos arranged in a matrix shape in which light is incident through a plurality of color filters that are repeated in a vertical direction at a cycle of N (N is a natural number) pixels. A sensor, a vertical transfer unit that transfers charges read from a plurality of photosensors without mixing the charges from the photosensors arranged in the vertical direction, and a charge that is accumulated in the plurality of photosensors is transferred to the vertical transfer unit. The plurality of photosensors are composed of m (m is a natural number) first photosensor groups that are continuous in the vertical direction, and a number a times the pixel period N (a is a natural number). The second photosensor groups that are arranged in the vertical direction are alternately arranged in the vertical direction, and the signal supply unit transfers the charges accumulated in the first photosensor group to the vertical transfer unit. A first signal supplying unit of the order, that the second photosensors for transferring the charges accumulated in the vertical transfer portion group the second signal supply section is configured provided independently of each other This is a featured solid-state imaging device.

The second aspect of the invention is arranged in a matrix in which light is incident through a plurality of color filters repeated in a vertical direction with N (N is a natural number) pixel cycles, and m (m is a natural number) verticals. The first photo sensor group that is continuous in the direction and the second photo sensor group that is continuous in the vertical direction, which is a number (a is a natural number) times the pixel period N, are alternately arranged in the vertical direction. The charges read from the first photosensor group of the plurality of photosensors are transferred from the first signal supply unit to the vertical transfer unit that transfers the charges from the photosensors connected in the vertical direction without mixing. The charge read from the second photosensor group is transferred from the second signal supply unit provided independently of the first signal supply unit to the vertical transfer unit. To control a solid-state image sensor It is.

  As described above, the invention of claim 1 includes a plurality of photosensors arranged in a matrix in which light is incident through a plurality of color filters that are repeated in the vertical direction at a cycle of N (N is a natural number) pixels, A vertical transfer unit that transfers charges read from a plurality of photosensors without mixing the charges from the photosensors arranged in the vertical direction, and a transfer unit that transfers charges accumulated in the plurality of photosensors to the vertical transfer unit. The plurality of photosensors includes a signal supply unit, and a plurality of photosensors includes a first photosensor group that is continuous in the vertical direction of m (m is a natural number) and a vertical direction that is a times the pixel period N (a is a natural number). The second photosensor group that is connected to the first photosensor group is alternately arranged in the vertical direction, and the signal supply unit is configured to transfer the charge accumulated in the first photosensor group to the vertical transfer unit. Since the signal supply unit and the second signal supply unit for transferring the charge accumulated in the second photosensor group to the vertical transfer unit are included, the charge accumulated in the photosensor is transferred to the vertical transfer unit. Transfer is performed by using both the first and second signal supply units, and all pixels can be read out, and by using only the first signal supply unit, decimation readout can be performed. Since the number of pixels a times the pixel period N in the vertical direction of the color filter is thinned out in the vertical direction, the color order is kept the same as in the case of all pixel readout.

  According to a fourth aspect of the present invention, m (m is a natural number) elements are arranged in a matrix in which light is incident through a plurality of color filters that are repeated in a vertical direction with N (N is a natural number) pixel period. The first photosensor group that is continuous in the vertical direction and the second photosensor group that is continuous in the vertical direction, which is a number (a is a natural number) times the pixel period N, are alternately arranged in the vertical direction. The charges read from the first photosensor group of the plurality of photosensors transferred from the first signal supply unit to the vertical transfer unit that transfers the charges from the photosensors connected in the vertical direction without mixing. Since the charges read from the second photosensor group are transferred from the second signal supply unit to the vertical transfer unit, the transfer of the charges accumulated in the photosensor to the vertical transfer unit is performed. First and second All pixel readout can be performed by using the signal supply unit together, and thinning readout can be performed by using only the first signal supply unit, and at the time of thinning readout, the pixel period in the vertical direction of the color filter Since the number of pixels a times N is thinned out in the vertical direction, the color order is kept the same as in the case of all pixel readout.

  According to the present invention, a still image with good vertical resolution can be obtained by a full-frame imaging mode for reading out all pixels, and when used for display of a liquid crystal display or the like, by a line-thinning imaging mode, An imaging signal can be output at high speed. Therefore, the image pickup signal can be displayed on the monitor without providing the VRAM. Further, since the imaging signal can be output at a high speed, the response of an automatic control device such as autofocus can be accelerated. Furthermore, since the number of frames increases, there is an advantage that the monitor image moves smoothly.

  Further, in the present invention, since the image pickup signal is displayed during recording other than the period in which the image signal is written in the memory (DRAM), the period during which the display disappears can be minimized. Furthermore, since the image pickup signal is supplied to the display device during the reproduction of data from the recording medium, the display disappearance period can be minimized as in the recording.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the overall configuration of an embodiment of the present invention. Reference numeral 101 denotes a solid-state image sensor, for example, a CCD image sensor. The CCD image sensor 101 is a single-plate imager having three primary color filters, a complementary color filter, and the like. As will be described in detail later, the CCD image pickup device 101 has a full frame read operation mode (first image pickup mode) for reading all pixels and a line thinning operation mode for outputting a signal with a reduced number of lines. (Second imaging mode) can be switched. Subject light is incident on the image sensor 101 via the lens system 100.

  An output signal of the image sensor 101 is supplied to the sample hold / AGC circuit 102. In the full frame reading mode, the time for reading one image is 1/30 seconds, and in the line thinning mode, this is 1/60 seconds. The sample-and-hold is configured as a correlated double sampling circuit, and noise removal, waveform shaping, and defective pixel compensation are performed. The AGC controls the gain according to the brightness of the subject, and the gain is also controlled for automatic aperture adjustment. The output signal of the sample hold / AGC circuit 102 is supplied to the A / D converter 103. The A / D converter 103 generates a digital imaging signal in which one sample is 10 bits.

  The digitized imaging signal is supplied to the camera signal processing circuit 104 having an IC circuit configuration. The signal processing circuit 104 includes a digital clamp circuit, a luminance signal processing circuit, a color signal processing circuit, a contour correction circuit, a defect compensation circuit, an automatic iris control circuit, an automatic focus control circuit, an automatic white balance correction circuit, and a component signal (Y: A luminance signal, Cr, Cb: a digital video signal in which color difference signals are sampled at a sampling frequency of a ratio of 4: 1: 1), a synchronization signal generation circuit, a timing generator, an interface with a microcomputer, and the like. A more specific configuration of the signal processing circuit 104 will be described later. The component signal is converted into multiplexed data by the multiplexer.

  A microcomputer 105 controls signal processing. A control signal from the microcomputer 105 is supplied to the lens system 100, the electronic volume 106, the camera signal processing circuit 104, and the timing controller 107. The timing controller 107 includes a timing generator 108 and a CCD driving circuit 109. The electronic volume 106 generates a gain control signal for the sample hold and AGC circuit 102.

  A clock 3MCK having a frequency three times that of the clock MCK is supplied to the timing controller 107. Further, MCK and 3 / 2MCK are sent from the camera 107 to the camera signal processing circuit 104. As an example, the number of horizontal pixels of the image sensor 101 is 780, and MCK = 780 fh (fh: horizontal scanning frequency of the image sensor 101) = 12.3 MHz. Further, the horizontal synchronization signal H and the vertical synchronization signal V generated in the camera signal processing circuit 104 are supplied to the timing controller 107. A drive pulse generated by the CCD drive circuit 109 of the timing controller 107 is supplied to the image sensor 101. The drive pulse includes a vertical drive pulse, a horizontal drive pulse, a read pulse, and the like.

  FIG. 2 shows an example of the camera signal processing circuit 104. Here, a configuration in the case of including an automatic aperture control circuit is shown. For simplicity, the defect compensation circuit, automatic focus control circuit, and automatic white balance correction circuit are not shown. A 10-bit width digital imaging signal from the A / D converter 103 is supplied to the arithmetic circuit 112 via the digital clamp circuit 111. When the image sensor has a three primary color filter, the arithmetic circuit 112 adds or subtracts the three primary color signals to generate a luminance signal component and a color difference signal component.

  The luminance signal component is supplied to the luminance signal processing circuit 113 and the contour correction circuit 114, and the color difference signal component is supplied to the color signal processing circuit 116. The luminance signal processing circuit 113 includes a γ correction circuit and the like. The contour correction signal generated by the contour correction circuit 114 is added to the output signal of the luminance signal processing circuit 113 by the addition circuit 115. A luminance signal Y is obtained from the adder circuit 115. The color signal processing circuit 116 includes a γ correction circuit, a HUE, a gain adjustment circuit, and the like. Color difference signals Cr and Cb are generated from the color signal processing circuit 116. A component signal composed of Y, Cr, and Cb is supplied to the multiplexer 117. The multiplexer 117 combines these signals as described later, and a multiplexed component signal is generated at the output.

  A timing / synchronization signal generation circuit 118 is provided, and a horizontal synchronization signal H, a vertical synchronization signal V, a clock, and a timing signal are generated from this circuit 118 from a 3MCK clock. Reference numeral 119 denotes a serial I / O for an interface between the microcomputer 105 and the camera signal processing circuit 104, and reference numeral 120 denotes a detection / accumulation circuit. The luminance signal component formed by the arithmetic circuit 112 is detected and supplied to the accumulation circuit 120. In the case of aperture control, the imaging screen is divided into a plurality of areas, and imaging signals are accumulated for each area. The accumulated data of each area is detected and output from the accumulation circuit 120 to the serial I / O 119.

  The microcomputer 105 receives the accumulated data through the serial I / O 119, and the microcomputer 105 performs a weighting operation on the accumulated data, an operation for obtaining a sum of weighted data in each area, an aperture control signal generation, and the like. The generated aperture control signal drives the aperture control ring drive motor of the lens system 100 to control the timing controller 107 and the electronic volume 106. An electronic shutter (exposure time) is controlled by the timing controller 107, and a gain is controlled by the electronic volume 106. In addition, a control signal is supplied from the microcomputer 105 to the detection and accumulation circuit 120 through the serial I / O 119, and the pattern of area division is controlled.

  The multiplexer 117 for multiplexing component signals of the (411) method will be described in more detail. As shown in FIG. 3, the multiplexer 117 receives an 8-bit width luminance signal Y and a color difference signal C synchronized with the clock MCK and is synchronized with 3 / 2MCK (a clock having a frequency 3/2 times that of the clock MCK). An 8-bit wide multiplexed component signal is generated. FIG. 4 shows an exemplary configuration of the multiplexer 117. The multiplexer 117 includes an input selector 121 that selects one of the luminance signal Y and the color signal C, a shift register 122 to which the input selector 121 is supplied as a serial input, a register 123 to which a parallel output of the shift register 122 is loaded, The output selector 124 sequentially selects data loaded in the register 123 and the register 125 connected to the output selector 124. Each register is 8 bits wide.

FIG. 5 is a timing chart showing the operation of the multiplexer 117 described above. 3MCK is a clock three times the frequency of the clock MCK. The luminance data Y and the color signal C are synchronized with the clock MCK. Since it is a component signal of (411) system, one sample of red color difference data (for example, Cr ₀ ) and one sample of luminance data (for example, Y ₀ , Y ₁ , Y ₂ , Y ₃ ) Corresponding to blue color difference data (for example, Cb ₀ ).

The input selector 121 is controlled so that luminance data is selected at the high level of the select pulse and color data is selected at the low level. The shift register 122 is supplied with 3/2 MCK as a clock, takes in the data selected by the input selector 121, and shifts in series. As shown in the figure, the output Q ₀ of the first-stage register of the shift register 122 changes as Y ₋₁ , Y ₀ , Cr ₀ , Y ₁ , Y ₂ , Cb ₀ , Y ₃ ,.

  The output of the shift register 122 is loaded in parallel to the register 123 with a 1/4 MCK clock timing. The quarter MCK clock period is six times the 3/2 MCK period. The phase of the 1/4 MCK clock is selected so that a total of 6 samples of luminance data and color difference data related to each other are transferred from the shift register 122 to the register 123.

The output selector 124 sequentially selects Y ₀ , Y ₁ , Y ₂ , Y ₃ , Cr, and Cb in order from the register 123 in synchronization with the clock (3 / 2MCK), and the register 125 selects the selected sample. take in. Therefore, multiplexed component signals are generated from the register 125 such that Y ₀ , Y ₁ , Y ₂ , Y ₃ , Cr, and Cb are arranged in this order.

  The multiplexer 117 described above converts the data sampling clock frequency from MCK to 3/2 MCK of 1.5 times the frequency, thereby converting the data into an 8-bit multiplexed component signal. In the case where the multiplexer 117 is not provided, the camera signal processing circuit 104 outputs (8 × 2 = 16 bits) width data (luminance signal Y and color signal C). In that case, crosstalk between two data buses occurs, crosstalk increases due to an increase in the substrate wiring area, memory size increases due to an increase in the memory data width, Various problems such as an increase in power consumption of the memory occur. By providing the multiplexer 117 described above on the output side of the signal processing circuit 104, the occurrence of these problems can be prevented.

  Returning to FIG. 1, an embodiment of the present invention will be further described. The component signals multiplexed as described above from the camera signal processing circuit 104 are supplied to the data switcher 130. The data switcher 130 is connected to the output point a connected to the output of the camera signal processing circuit 104, the input point b connected to the conversion circuit 134 for converting the component signal into the three primary color signals, and the recording / reproducing data bus 140. And an input / output point c. The state of the data switcher 130 is controlled by mode switching signals 131, 132, 133 generated based on user key operations and the like. The microcomputer 105 in FIG. 1 is provided mainly for controlling the camera unit. Although not shown, the microcomputer 105 is provided for controlling the recording / reproducing operation and for controlling the entire apparatus. Communication between microcomputers is performed.

  The three primary color signals R, G, and B generated by the conversion circuit 134 are supplied to a television display device such as a liquid crystal display 135, and a captured image is displayed on the liquid crystal display 135. The liquid crystal display 135 displays a color image using a non-interlace method with a 1/60 second period. A random accessible memory such as a DRAM (dynamic random access memory) 141 and a data compression encoder / decoder such as a JPEG (Joint Photographic Experts Group) encoder / decoder 142 are connected to the recording / reproducing data bus 140. High efficiency encoding other than JPEG may be used. A recording medium such as a flash memory 143 and an interface 144 are connected to the encoder / decoder 142. The operation of the DRAM 141 is controlled by an address signal and a control signal supplied from the memory controller 145.

  The encoder / decoder 142 compresses the data amount to about 1/10 by encoding of JPEG, that is, adaptive DCT (Discrete Cosine Transform). A DRAM 141 is provided for processing such as blocking in JPEG. The flash memory 143 is a semiconductor memory that retains stored contents even when the power is turned off, and can be erased and rewritten electrically collectively for the entire memory or for each divided area. As the recording medium, a medium such as a semiconductor memory other than the flash memory may be used. Further, an interface may be provided to supply the compressed still image data to a personal computer as necessary. In one embodiment of the present invention, recording means encoding an imaging signal and writing it in the flash memory 143, and reproduction means reading data in the flash memory 143 and decoding read data.

  One embodiment of the present invention described above will be described in more detail. In this embodiment, five types of operations are possible depending on the connection state of the data switcher 130. This includes a monitoring mode, a first recording mode, a second recording mode, a first reproduction mode, and a second reproduction mode. These modes are set by mode switching signals 131, 132, 133. The mode switching signals 131, 132, 133 are generated from a recording / reproducing system control microcomputer (not shown). A mode switching signal may be generated by the microcomputer 105. In the monitoring mode, the imaging screen is displayed on the liquid crystal display 135. In the first recording mode, a desired captured image is written into the DRAM 141. In the second recording mode, the image data stored in the DRAM 141 is compressed and written to the flash memory 143. In the first reproduction mode, the data stored in the flash memory 143 is read, and the read data is decoded and written into the DRAM 141. In the second reproduction mode, data in the DRAM 141 is read and displayed on the liquid crystal display 135.

  FIG. 6 shows the connection in the monitoring mode in which the output point a and the input point b of the data switcher 130 are connected. The monitoring mode is set when the mode switching signal 131 becomes active. In the monitoring mode, the microcomputer 105 controls the CCD drive circuit 109 of the timing controller 107 to operate the image sensor 101 in the line thinning mode. A line which is not read out is generated from the image pickup element 101, and an image pickup signal is read out at a period of 1/60 second.

  In the monitoring mode, the output signal of the signal processing circuit 104 is supplied to the conversion circuit 134 via the data switcher 130, and the three primary color signals output from the conversion circuit 134 are supplied to the liquid crystal display 135 and displayed. Since the image sensor 101 operates in the line thinning mode, the liquid crystal display 135 can perform non-interlaced display with a 1/60 second period. By looking at the display on the liquid crystal display 135, the angle of view can be adjusted and the still image to be recorded can be determined. Due to the line decimation mode, the vertical resolution is degraded compared to when recording, but this is not a problem for the purpose of monitoring captured images, which is also equivalent to a CCD imaging camera that performs field accumulation. In the line thinning mode, the followability to movement is improved for high-speed reading. Accordingly, the response of automatic control such as automatic focus adjustment and automatic aperture adjustment is improved, and it becomes easy to monitor a moving image.

  In the monitoring mode, the DRAM 141, the encoder / decoder 142, and the flash memory 143 connected to the data bus indicated by the broken line are not operated. In order to save power consumption, it is preferable that the power supply to these non-operating circuits is turned off or the supply of clocks necessary for the operation is stopped. In other modes described below, the buses for circuits that do not operate are indicated by broken lines, and the power supply to circuits that do not operate is turned off.

  FIG. 7 shows a mode for recording a still image, that is, a connection in the first recording mode in which the output point a and the input / output point c of the data switcher 130 are connected. The first recording mode is set when the mode switching signal 132 becomes active. In the first recording mode, the microcomputer 105 controls the CCD drive circuit 109 of the timing controller 107 to operate the image sensor 101 in the full frame readout mode. From the image sensor 101, all pixels, for example, 320,000 pixels are read out, and an image pickup signal is read out at a 1/30 second period.

  The imaging signal is processed by the camera signal processing circuit 104 and written to the DRAM 141 through the output point a and the input / output point c of the data switcher 130 and the recording / reproducing data bus 140. The memory controller 145 sets the DRAM 141 to a write state and supplies a write address to the DRAM 141. The memory controller 145 is controlled by a recording / reproducing system control microcomputer (not shown). One still image data is written in the DRAM 141. In the first recording mode in which 1/30 second image data is written, an image cannot be displayed on the liquid crystal display 135. In order to minimize the time during which no image is displayed, when writing is completed, the process proceeds to the next second recording mode.

  When the writing of one image data to the DRAM 141 is completed, the data switcher 130 enters the second recording mode in which the output point a and the input point b are connected as shown in FIG. The second recording mode is set when the mode switching signal 131 becomes active. In this mode, image data is read from the DRAM 141. The read data is supplied to the encoder / decoder 142 via the bus 140. The encoder / decoder 142 compresses data read from the DRAM 141 by, for example, JPEG. In addition, the compressed data is written into the flash memory 143. In this way, the captured image is compressed and recorded.

  In the second recording mode, the image sensor 101 is operated in the line thinning mode, and the signal read from the image sensor 101 at a high speed is processed by the camera signal processing circuit 104 in the same manner as in the monitoring mode. The signal is supplied to the liquid crystal display 135 through the data switcher 130 and the conversion circuit 134, and an image is displayed. As a result, the time during which the image display disappears during recording can be minimized.

  In the reproduction mode, the image data written in the flash memory 143 is reproduced and displayed on the liquid crystal display 135. FIG. 9 shows a state of the first reproduction mode in which the output point a and the input point b of the data switcher 130 are connected and the image pickup signal is displayed on the liquid crystal display 135. The first reproduction mode is set when the mode switching signal 131 becomes active. In this mode, data is read from the flash memory 143 and the read data is supplied to the encoder / decoder 142.

  Data is decoded by the encoder / decoder 142 to generate image data. The DRAM 141 is controlled to write this image data. In this case, the memory controller 145 controls the write address of the DRAM 141 so that the decoded data is written to the DRAM 141 with the same data arrangement as that in the first recording mode. A similar data array may be realized by address control at the time of reading. This relationship is because when the digital image signal read from the DRAM 141 is supplied to the liquid crystal display 135 via the conversion circuit 134 and displayed on the liquid crystal display 135, the same configuration as that used in the monitoring mode is used. Is necessary for. In the first reproduction mode, the image sensor 101 is driven in the line thinning mode, and a captured image of the image sensor 101 is displayed on the liquid crystal display 135.

  When the decoded data is written to the DRAM 141, the second reproduction mode shown in FIG. 10 is entered. In the second playback mode, the input / output point c and the input point b of the data switcher 130 are connected. The second reproduction mode is set when the mode switching signal 133 becomes active. The DRAM 141 is set in a read state. Then, read data of the DRAM 141 is supplied to the liquid crystal display 135 via the recording / reproducing data bus 140, the data switcher 130, and the conversion circuit 134. Therefore, an image corresponding to the data recorded in the flash memory 143 can be viewed on the liquid crystal display 135. In this case, the data recorded in the flash memory 143 is not full-line data but full-frame data. Therefore, line thinning similar to the case where the image sensor 101 is driven in the line thinning mode is realized by address control by the memory controller 145. Thereby, the read data of the DRAM 141 can be reproduced by the liquid crystal display 135.

  In this way, the still image data stored in the flash memory 143 can be reproduced and viewed on the liquid crystal display 135. The number of still images that can be recorded is determined by the storage capacity of the flash memory 143, the data compression method, and the like. The flash memory 143 is preferably configured as an IC card. Of course, a recording medium other than the flash memory may be used. Furthermore, recording data may be transmitted to an external personal computer via an interface provided as necessary, or recording data may be stored in an external storage device.

  An example of the solid-state image sensor 101 described above will be described below. FIG. 11 schematically shows an example of a solid-state image sensor, for example, a CCD image sensor 1. In this example, an interline method is adopted, and a signal charge from the photosensor 2 provided between the photosensors (for example, photodiodes) 2 two-dimensionally arranged in the image area and the photosensor 2 is horizontal CCD (horizontal). A vertical CCD (vertical transfer unit) 3 for transferring to a transfer unit 4, and a buffer amplifier 5 connected to the horizontal CCD 4. Imaging light that has passed through an array of color filters, which will be described later, is incident on the photosensor 2. One photo sensor 2 and one bit in the vertical CCD 3 correspond to each other, and signal charges from the photo sensor 2 are read to the vertical CCD 3 without mixing, and signals of all pixels are sequentially transferred to the horizontal CCD 4. It is possible. Then, by driving the horizontal CCD 4, the signal is transferred to the floating diffusion area, sequentially converted into a voltage, and output through the buffer amplifier 5.

A plan view of a unit pixel of the image sensor 1 is shown in FIG. 12, and a structure of the vertical CCD 3 is shown in FIG. The vertical CCD 3 has, for example, a three-layer electrode three-phase drive configuration. In FIG. 12, 6 is a transfer channel of the vertical CCD 3, 7 is a channel stopper for separating pixels and between the pixel and the transfer channel, and 8, 9 and 10 are transfer gates of the vertical CCD 3, respectively. The transfer gate 9 also serves as a read gate. In FIG. 12, illustration of the light shielding film and the like is omitted. As shown in FIG. 13, the transfer gates 8, 9, and 10 are formed by processing the first, second, and third polycrystalline silicon electrodes. Vertical drive pulses φV ₁ , φV ₂ , and φV ₃ are applied to these transfer gates 8, 9, and 10, respectively.

When a signal is read from the photo sensor 2 to the vertical CCD 3, a bias voltage (read pulse) higher than the high level of the vertical transfer clock φV ₂ is applied to the transfer gate adjacent to the photo sensor 2, that is, the transfer gate 9 also serving as a read gate. Applied). When a read pulse is supplied to the gate 9, one pixel corresponds to one bit of the vertical CCD 3, so that signal charges are read from all the photosensors 2 to the vertical CCD 3. The horizontal CCD 5 outputs data for one line by the transfer clocks φH ₁ and φH ₂ . As the horizontal CCD 5, for example, a composite channel horizontal CCD structure can be adopted. In that case, the output unit has a two-channel configuration.

  The CCD image pickup device described above is suitable for electronic still cameras and image capture because it can sequentially output signals of all pixels. However, the output time of one screen (from the upper end to the lower end of the screen) is doubled compared to an image sensor for video cameras having the same number of pixels that performs interlaced output. In this example, as described above, as a monitor signal and an imaging signal for automatic control such as automatic focus control, the number of horizontal lines is reduced to output an imaging signal for one screen at high speed. In addition, in the case of this line thinning, the color sequence in the vertical direction defined by the color filter arrangement is not disturbed. On the other hand, when a captured image is taken into the flash memory, a full frame imaging signal (an imaging signal in which the number of lines is not thinned) is output. Even in the case of line thinning, since the color sequence is the same as that in the case of a full frame, the problem that the signal processing circuit becomes complicated can be avoided.

  In the above-described image pickup device capable of reading all pixels, in order to thin out the number of lines, two wirings for the transfer gate (second polycrystalline silicon) 9 contributing to reading of the signal charges from the photosensor 2 are used. It is possible by dividing. The repetition period of the color sequence is represented by N. FIG. 14 shows an example in the case of (N = 2).

  As the arrangement of the color filters of the single-plate CCD image sensor, R (filter that passes red), G (filter that passes green), and B (filter that passes blue) are arranged as shown in FIG. 15A (Bayer method) )It has been known. A high-sensitivity G filter is arranged in half of the pixels. Also, a complementary color checkered color filter shown in FIG. 15B is known. In FIG. 15B, Ye, Cy, and Mg are yellow, cyan, and magenta filters, respectively. The complementary color filter shown in FIG. 15B can be increased in resolution as compared with the primary color filter, and is therefore often used in video cameras. On the other hand, the primary color filter shown in FIG. 15A is excellent in terms of color reproducibility and is often employed in an electronic still camera.

  As the image sensor in the present invention, any of a single-plate image sensor having a primary color filter and a single-plate image sensor having a complementary color filter may be used. Further, although not shown in the drawing, the image pickup device includes an image pickup device having a G filter and an image pickup device having an array of R and B filters, and the positional relationship between the two image pickup devices is a pixel in the horizontal direction or in the horizontal and vertical directions. You may use the image pick-up element (what is called a space picture element shift system) of the system shifted only 1/2 of the pitch.

In the arrangement of FIG. 15A, the repetition period N of the color sequence in the vertical direction is (N = 2), and the arrangement of FIG. 15B is (N = 4). FIG. 14 is a schematic diagram showing (N = 2) one row of the photosensors 2 in the vertical direction, the vertical CCDs 3 and the gate wirings of the gates of the vertical CCDs 3 with respect to a part of one column. Among the photosensors 2, the one provided with a hatched portion in the upper left corner corresponds to one color filter, for example, a G filter, and the one not provided with the hatched portion corresponds to another color filter, for example, a B filter. As described above, the vertical CCD 3 is of the three-layer electrode, three-phase drive type, and has a 3-bit gate adjacent to the aperture pixel of the image sensor. The vertical CCD 3 includes a repeating unit A and a repeating unit B. The repeating unit A includes gates 21, 22, and 23, and the repeating unit B includes gates 31, 32, and 33. Gates 22 and 32 are transfer and read gates. Reference numerals 41, 42, 42 ′, and 43 denote bus wirings to which drive pulses φV ₁ , φV ₂ , φV ₂ ′, and φV ₃ for vertical transfer are respectively supplied.

Gates 21 and 31 are connected to bus line 41, and gates 23 and 33 are connected to bus line 43. Drive pulses φV ₁ and φV ₃ are supplied to the bus lines 41 and 43, respectively. For the drive pulse φV ₂ , two buses 42 and 42 ′ are provided. The repeat unit A indicates that the transfer / read gate 22 is connected to the bus 42, and the repeat unit B indicates that the transfer / read gate 32 is connected to the bus 42 '. In FIG. 14, for simplification, the bus line is drawn only on one side, but it is normal to drive the both sides by arranging the bus line on both sides.

  In the above-described imaging device, for line thinning, a range of A × m (bits) in which repeating units A are arranged m (m = 1, 2, 3,...) And repeating units B are arranged N × a. A range of B × N × a (bits) is alternately formed in the vertical direction. The example shown in FIG. 14 is a case of (N = 2, m = 3, a = 2). Although the values of m and a can be arbitrarily selected, even if m and a are large values, it is necessary that (m + N × a) is smaller than the number of effective pixels.

  In the imaging device described above, in the first operation mode, that is, in the full frame operation in which the signals of all the pixels are read out, signals are read from the photosensor 2 to both the repeating units A and B of the vertical CCD 3. For this purpose, a read pulse is applied to both gates 22 and 32 through bus lines 42 and 42 '. In this case, color signals are output in a color sequence corresponding to the order of arrangement of the color filters, for example, a sequence of G, B, G, B,.

  On the other hand, in the second operation mode, that is, in the line thinning operation, the read pulse is applied only to the gate 22 of the repeating unit A through the bus wiring 42. Therefore, a signal is read from the range of A × m (bit), and no signal is read from the range of B × N × a (bit). In the example of FIG. 14, a signal is generated from the (m = 3) line, and no signal is generated from the (N × a = 4) line. Since the number of lines to be thinned is an integer multiple of N, the color sequence corresponding to the order of the color signals of the imaging output in the case of line thinning is kept in the same relation as full frame reading.

FIG. 16 shows the timing when the image sensor is driven, and FIG. 16A shows the timing when full frame reading is performed. In each horizontal blanking period, the three-phase drive pulses φV ₁ , φV ₂ , φV ₂ ′, and φV ₃ are the gates 21, 22, and 23 of the repeating unit A and the gates 31, 32, and 33 of the repeating unit B of the vertical CCD _3. Are supplied respectively. A read pulse is also applied to both gates 22 and 32. Thereby, signal charges are read out from all the photosensors to the vertical CCD 3. As shown in the detailed timing chart of FIG. 16B, the driving pulses φV ₁ , φV ₂ , φV ₂ ′, and φV ₃ generated in the horizontal blanking period are three-phase, and one line shift is performed depending on the line shift period. Made. When reading out a full frame, one line shift is performed within each horizontal blanking period.

  On the other hand, in the case of line thinning readout, a readout pulse is applied only to the gate 22 of the repeating unit A as shown in FIG. 16C. Thereby, signal charges are read out only from the photosensor adjacent to the repeating unit A. In the case of line thinning, no signal charge is read out in the thinned line, and no signal is generated. This non-signal period can be removed by repeating the line shift operation a plurality of times, as will be described later.

  FIG. 17A is a schematic diagram of the potential of the channel 6 of the vertical CCD 3 in the case of (m = 1, a = 1). The direction from the right side to the left horizontal CCD 4 in the drawing is the vertical transfer direction. The channel 6 includes a packet 51 including a signal charge Qs and an empty packet 52 during the line thinning operation. In order to output the signal charge Qs from each line, the number of line shifts is increased by the empty packet 52, whereby the signal charge and the non-signal are mixed in the horizontal CCD 4 and the non-signal period is removed. The number of line shifts performed within each horizontal blanking period may be selected so as to satisfy the following relationship.

1 (: number of packets including signal charge Qs to be output) + X (number of packets not including signal charge Qs in front) and 1 + X + (N × a) (: packets not including signal charge Qs in back) Accordingly, in the case of (X = 0), only the signal charge is transferred to the horizontal CCD 4, and in the case of (X ≠ 0), the packet including the signal charge and one or more signal charges are included. No packet is transferred to the horizontal CCD 4.

  Under the above-described conditions, signal charges can be transferred to the horizontal CCD 4 and a non-signal line can be compressed. Actually, the charge of the empty packet is not 0, and unnecessary signal charges Qn such as a smear signal and a dark signal are included. If the number of line shifts performed in each horizontal blanking period is different, the number of times unnecessary signal charge Qn is added differs, so that the amount of unnecessary signal included varies from line to line. As a result, image quality degradation such as line crawl and color shift may occur.

  In order to solve this problem, the number of line shifts performed in each horizontal blanking period may be constant. In the case of a limited condition, that is, (m = 1 or m = 2), the number of line shifts of the vertical CCD 3 is set to ((N × a / m) +1), whereby the signal charge Qs of each line is set. The number of packets not including the signal charge Qs added to can be made constant. As a result, the above-described image quality deterioration can be prevented.

  FIG. 17B is a schematic diagram of the potential of the channel 6 of the vertical CCD 3 in the case of (N = 2, m = 1, a = 1). In this example, (N × a / m = 2), and by setting the number of line shifts to three, the number of packets not including the signal charge Qs added in each line can be made constant. FIG. 17C shows the case of (N = 2, m = 2, a = 1). In this case, (N × a / m = 1), and the number of line shifts may be two. Further, even when m> 2, there is no problem if the level of the smear signal or the dark signal can be sufficiently reduced.

  The above-described CCD image pickup device can reduce the number of lines. Therefore, by selecting the value of the number m of repeating units A arranged in the vertical CCD 3 and the value N × a of repeating units B, the value of a one-field television can be obtained. The number of lines of the output imaging signal can be suppressed to the number of horizontal scanning lines or less. Several examples of the number of output lines will be described by taking the case of a Bayer color filter array (N = 2) as an example.

As shown in FIG. 18, when the present invention is applied to a VGA (Video Graphics Array) compatible image sensor having an effective pixel count (vertical × horizontal) of (480 × 640), (a = 1, m = 2). Therefore, in the line thinning mode, the number of output lines can be reduced to a half of 240 lines. As shown in FIG. 19, in an image sensor with the number of effective pixels (768 × 1024), by setting (m = 1, a = 1), the number of output lines can be 256 lines. As shown in FIG. 20, in an imaging device with the number of effective pixels (1024 × 1280), by setting (m = 1, a ₁ = 1, a ₂ = 2), the number of output lines can be 256 lines. a ₁ and a ₂ are used alternately.

  In any of the cases shown in FIGS. 18, 19 and 20, the number of output lines can be made smaller than the number of lines per field (262.5) of the NTSC system, for example. Therefore, it is possible to output the image signal in the line thinning mode at a higher speed while maintaining the same relationship between the color sequence and the angle of view as in the full frame readout mode. Thereby, an imaging screen can be displayed on the liquid crystal monitor without using a VRAM or a frame memory. Note that the angle of view is an angle at which the range reflected on the image sensor when taking a picture is centered on the optical axis of the lens.

The specific configuration of the image sensor in the above-described embodiment is merely an example, and other solid-state image sensors can be used in the present invention. For example, the vertical CCD may have a structure of a two-layer electrode four-phase drive, an image sensor other than the interline system, and a solid-state image sensor using other than the CCD. Furthermore, as a mode for driving the solid-state imaging device, a third operation mode in which the read pulse φV ₂ ′ is applied and the read pulse φV ₂ is not applied may be set.

  In addition, the present invention is not limited to the image sensor having the above-described structure, and an image sensor that can select an all-pixel readout mode and a mode in which the number of readout pixels is reduced can be used.

It is a block diagram which shows the structure of one Example of this invention. It is a block diagram of an example of the camera signal processing circuit in one Example of this invention. It is a block diagram of the part of the multiplexer in a camera signal processing circuit. It is a block diagram of an example of a multiplexer. It is a timing chart which shows operation | movement of a multiplexer. It is a block diagram which shows the connection relation of the monitoring mode of one Example of this invention. FIG. 3 is a block diagram showing a connection relationship in a first recording mode according to an embodiment of the present invention. FIG. 6 is a block diagram showing a connection relationship in a second recording mode according to an embodiment of the present invention. It is a block diagram which shows the connection relation of the 1st reproduction | regeneration mode of one Example of this invention. It is a block diagram which shows the connection relation of the 2nd reproduction | regeneration mode of one Example of this invention. It is a basic diagram which shows schematic structure of an example of the image pick-up element which can be used for this invention. It is an enlarged plan view of a 1-pixel portion of an example of an image sensor. It is a basic diagram which shows the structure of vertical CCD of an example of an image pick-up element. It is a basic diagram which shows the bus wiring of 1 vertical line of an example of an image pick-up element. It is a basic diagram which shows an example of the arrangement | sequence of the color filter used for an example of an image pick-up element, and another example. It is a timing chart of the drive pulse for driving an example of an image sensor. It is a basic diagram which shows typically the potential of vertical CCD in an example of an image sensor. It is a basic diagram which shows a specific example of an image pick-up element. It is a basic diagram which shows the other specific example of an image pick-up element. It is a basic diagram which shows other specific example of an image pick-up element. It is a basic diagram used for description of the conventional image sensor. It is a basic diagram used for description of the image pick-up element proposed previously. It is a basic diagram which shows the relationship between the output of an image pick-up element, and the display of a liquid crystal monitor. It is a block diagram which shows the structure in the case of supplying the imaging signal generated from the image pick-up element to a liquid crystal monitor.

Explanation of symbols

2 Photosensor 3 Vertical CCD
4 Horizontal CCD
6 Vertical CCD channel 101 Image sensor 104 Camera signal processing circuit 105 Microcomputer 107 Timing controller 130 Data switcher 135 Liquid crystal display 141 DRAM
142 Encoder / Decoder 143 Flash Memory

Claims (3)

A plurality of photosensors arranged in a matrix in which light is incident through a plurality of color filters that are repeated in a vertical direction with N (N is a natural number) pixel cycles;
A vertical transfer unit that transfers the charges read from the plurality of photosensors without mixing the charges from the photosensors connected in the vertical direction;
A signal supply unit for transferring charges accumulated in the plurality of photosensors to the vertical transfer unit;
The plurality of photosensors include a first photosensor group continuous in the vertical direction with m (m is a natural number) and a second continuous in the vertical direction having a number (a is a natural number) times the pixel period N. The photo sensor group is configured by being alternately arranged in the vertical direction,
The signal supply unit includes a first signal supply unit for transferring charges accumulated in the first photosensor group to the vertical transfer unit, and a charge accumulated in the second photosensor group. A solid-state imaging device, wherein a second signal supply unit for transferring to a vertical transfer unit is provided independently of each other . The solid-state imaging device according to claim 1,
The color filters in the vertical direction of the color filters arranged corresponding to the respective photosensors of the first photosensor group have the photosensors of the plurality of photosensors configured by the first and second photosensors. A solid-state imaging device having the same color order in the vertical direction of the color filters arranged corresponding to the above. First photosensors arranged in a matrix and receiving m (m is a natural number) continuous vertical light beams that are incident through a plurality of color filters repeated in a vertical direction with N (N is a natural number) pixel period. A plurality of photosensors configured by alternately arranging a group and a second photosensor group that is continuous in the vertical direction, which is a number (a is a natural number) times the pixel period N, The charges read from the first photosensor group are transferred from the first signal supply unit to the vertical transfer unit that transfers the charges from the photosensors connected in the vertical direction without mixing, and the second photosensor Solid-state imaging characterized in that charges read from a sensor group are transferred to a vertical transfer unit from a second signal supply unit provided independently of the first signal supply unit. How to control elements .

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