JP3942699B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor device manufactured using a semiconductor thin film and a configuration of a manufacturing method thereof. Specifically, the present invention relates to a structure of a bottom gate type thin film transistor (TFT) typified by an inverted stagger type.
[0002]
Note that in this specification, a semiconductor device includes all devices that can function using semiconductor characteristics. That is, TFTs, electro-optical devices, semiconductor circuits, electronic devices, and the like described in this specification are all included in the category of semiconductor devices.
[0003]
[Prior art]
In recent years, the demand for active matrix liquid crystal display devices has increased rapidly, and a technique for forming a thin film transistor (hereinafter abbreviated as TFT) with a semiconductor thin film formed on a glass or quartz substrate has been urgently required. The TFT is used as a switching element for image display.
[0004]
TFTs formed in units of hundreds of thousands on the same substrate must exhibit predetermined electrical characteristics according to the function of the electric circuit to be formed. As an electrical characteristic of such a TFT, there is a parameter called a threshold voltage (threshold voltage: Vth).
[0005]
The threshold voltage is defined as a voltage at which an inversion layer is formed in the channel portion of the TFT. That is, it can be considered as a voltage at which a TFT in an off state switches to an on state. Therefore, it can be said that the higher the threshold voltage, the higher the operating voltage of the TFT.
[0006]
There is a problem that this threshold voltage changes due to various external factors. For example, contamination impurities in the active layer, fixed charges and movable charges of the gate insulating film, interface states at the interface of the active layer / gate insulating film, work function difference between the gate electrode and the active layer, and the like. In this case, contamination impurities in the active layer and movable charges in the gate insulating film can be eliminated by cleaning the process, but fixed charges, interface states, work function differences, etc. are determined by the element material. Therefore, it cannot be easily changed.
[0007]
As a result of such external factors, the threshold voltage may shift to the plus side or to the minus side. For example, NTFT has a problem that if it is shifted to the minus side, a current flows (referred to as a normally-on state) in spite of being in an off state (a state in which no gate voltage is applied).
[0008]
A technique called channel dope is known as means for solving such a problem. Channel doping is a technique for adjusting a desired threshold voltage by forcibly shifting the threshold voltage by adding an impurity of a predetermined concentration into the active layer.
[0009]
Impurities used for channel doping include group 13 elements B (boron), In (indium), 15 elements P (phosphorus), As (arsenic), Sb (antimony), and the like.
[0010]
[Problems to be solved by the invention]
It is an object of the present invention to provide a technique for channel doping a bottom gate type TFT (typically an inverted stagger type TFT). It is another object of the present invention to provide a semiconductor device including a plurality of bottom-gate TFTs using the present invention and a manufacturing method thereof.
[0011]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
A semiconductor device including a plurality of bottom gate TFTs formed on a substrate having an insulating surface in a configuration,
Among the plurality of bottom gate TFTs, an impurity element for controlling a threshold voltage is intentionally included in at least a channel formation region of a TFT operating in an N channel type,
The concentration of the impurity element in the channel formation region decreases as it approaches the interface between the channel formation region and the gate insulating film in contact with the channel formation region.
[0012]
In addition, the configuration of other inventions is as follows:
A method for manufacturing a semiconductor device including a plurality of bottom gate TFTs formed on a substrate having an insulating surface.
Forming an amorphous silicon film;
Irradiating the amorphous silicon film with laser light or strong light having the same intensity as the laser light to obtain a crystalline silicon film;
Adding an impurity element for controlling a threshold voltage to the whole surface or a part of the crystalline silicon film;
Activating the impurity element;
It is characterized by including.
[0013]
In addition, the configuration of other inventions is as follows:
A method for manufacturing a semiconductor device including a plurality of bottom gate TFTs formed on a substrate having an insulating surface.
Forming an amorphous silicon film;
Adding an impurity element for controlling a threshold voltage to the whole surface or a part of the amorphous silicon film;
Activating the impurity element simultaneously with the step of irradiating the amorphous silicon film with laser light or strong light having the same intensity as the laser light to obtain a crystalline silicon film;
It is characterized by including.
[0014]
In addition, the configuration of other inventions is as follows:
A method for manufacturing a semiconductor device including a plurality of bottom gate TFTs formed on a substrate having an insulating surface.
Forming an amorphous silicon film;
Holding or adding a catalytic element for promoting crystallization of the amorphous silicon film over the entire surface or a part of the amorphous silicon film;
Transforming the whole or part of the amorphous silicon film into a crystalline silicon film by a first heat treatment;
Adding an impurity element for selectively controlling a threshold voltage with respect to the crystalline silicon film;
Selectively introducing an element selected from Group 15 into the crystalline silicon film;
Activating the impurity element for controlling the threshold voltage at the same time gettering the catalyst element in the region where the element selected from the group 15 is introduced by the second heat treatment;
It is characterized by including.
[0015]
The present invention having the above-described configuration will be described in detail with the embodiments described below.
[0016]
【Example】
[Example 1]
An example in which a CMOS circuit in which NTFT (N-channel TFT) and PTFT (P-channel TFT) are complementarily combined using the present invention will be described. In this embodiment, an example in which boron, which is a group 13 element, is added only to NTFT.
[0017]
First, a base film 102 made of a silicon oxide film is provided on a glass substrate 101, and gate electrodes 103 and 104 are formed thereon. In this embodiment, a chromium film having a thickness of 200 to 400 nm is used as the gate electrodes 103 and 104. However, an aluminum alloy, tantalum, tungsten, molybdenum, a silicon film imparted with conductivity, or the like may be used.
[0018]
Next, a gate insulating film 105 is formed on the gate electrodes 103 and 104 to a thickness of 100 to 200 nm. As the gate insulating film 105, a silicon oxide film, a silicon nitride film, or a stacked film of a silicon oxide film and a silicon nitride film is used. An anodized film obtained by anodizing a gate electrode can also be used as a gate insulating film.
[0019]
Next, an amorphous silicon film 106 is formed to a thickness of 10 to 75 nm (preferably 15 to 45 nm). In addition to amorphous silicon films, semiconductor thin films containing silicon as the main component (eg Si _x Ge _1-x (0 <X The silicon-germanium compound represented by <1) can be used.
[0020]
When the state of FIG. 1A is obtained in this way, laser light or strong light having the same intensity as the laser light is irradiated to crystallize the amorphous silicon film 106. As the laser light, excimer laser light is preferable. As the excimer laser, a pulse laser using KrF, ArF, or XeCl as a light source may be used.
[0021]
As strong light having the same intensity as laser light, strong light from a halogen lamp or a metal halide lamp, or strong light from an infrared light or an ultraviolet light lamp can be used.
[0022]
In this embodiment, excimer laser light processed into a linear shape is scanned from one end to the other end of the substrate, and the entire surface of the amorphous silicon film 106 is crystallized. At this time, sweep speed of laser beam is 1.2mm / s, processing temperature is room temperature, pulse frequency is 30Hz, laser energy is 300 ~ 315mJ / cm ² And (Fig. 1 (B))
[0023]
Thus, a crystalline silicon film 107 is obtained as shown in FIG. Next, a buffer layer 108 made of a silicon oxide film is formed thereon with a thickness of 50 to 200 nm (preferably 100 to 150 nm).
[0024]
Then, a region to be a PTFT is concealed with a resist mask 109, and boron is added by an ion implantation (ion plantation) method (with mass separation) or an ion doping method (without mass separation). The boron-containing region 110 is formed by this channel doping process. Instead of boron, a group 13 element such as indium may be added. (Figure 1 (C))
[0025]
At this time, the acceleration voltage is selected from 5 to 80 keV (typically 10 to 30 keV), and the dose is 1 × 10 ¹² ~ 1 × 10 ¹⁷ atoms / cm ² (Preferably 1 × 10 ¹³ ~ 1 × 10 ¹⁶ atoms / cm ² ). In this example, the acceleration voltage is 30 keV and the dose is 5 × 10. ¹³ atoms / cm ² And
[0026]
At this time, since the crystalline silicon film 107 is very thin, if direct ion implantation is performed, the crystallinity is destroyed due to a great damage. In addition, when ion implantation is performed on a very thin film, it is very difficult to control the concentration of impurities.
[0027]
However, in this embodiment, through doping is performed through the buffer layer 108 described above, damage to the crystalline silicon film 107 during ion implantation can be suppressed. In addition, since the thick buffer layer 108 exists on the crystalline silicon film 107, the impurity concentration added to the crystalline silicon film 107 can be easily controlled.
[0028]
Further, the boron concentration profile in the crystalline silicon film formed by ion implantation is adjusted so that the boron concentration is lowered at the portion where the channel is formed (near the interface where the channel formation region and the gate insulating film are in contact). It is desirable. This effect will be described later.
[0029]
When the impurity element addition step is completed as described above, the buffer layer 108 and the resist mask 109 are removed, and then active layers 111 and 112 are formed by patterning. Thereafter, excimer laser light is irradiated to recover the damage received in the ion implantation process and activate the added boron. (Figure 1 (D))
[0030]
Next, resist masks 113 and 114 are formed by performing backside exposure using the gate electrodes 103 and 104 as a mask. Then, an impurity element imparting N-type (typically phosphorus or arsenic) is added to add 1 × 10 ¹⁷ ~ 5 × 10 ¹⁸ atoms / cm ^Three About low concentration impurity regions 115 to 118 are formed. (Fig. 2 (A))
[0031]
Next, after removing the resist masks 113 and 114, patterning is performed again to form resist masks 119 and 120. At this time, the PTFT is completely covered. Then, the impurity element which imparts N-type again has a higher concentration (1 × 10 10 than in the case of FIG. ¹⁹ ~ 1 × 10 ²⁰ atoms / cm ^Three The source region 121 and the drain region 122 of the NTFT are formed.
[0032]
At this time, in the regions indicated by 123 and 124, the above-described low-concentration impurity regions remain as they are and function as LDD regions (Light Doped Drain). Further, a region indicated by 125 is a channel formation region. (Fig. 2 (B))
[0033]
Next, after removing the resist masks 119 and 120, resist masks 126 and 127 are formed so as to completely cover the NTFT.
[0034]
Then, an impurity element imparting P-type (typically boron or indium) is added at 1 × 10 ¹⁹ ~ 1 × 10 ²⁰ atoms / cm ^Three The source region 128 and the drain region 129 of the PTFT are formed by adding so as to have a concentration of about. A region indicated by 130 is a channel formation region. (Fig. 2 (C))
[0035]
Next, after removing the resist masks 126 and 127, the excimer laser light is irradiated to recover the damage at the time of ion implantation and to activate the added impurities. (Fig. 2 (D))
[0036]
When the laser annealing is finished, an interlayer insulating film 131 is formed to a thickness of 300 to 500 nm. The interlayer insulating film 131 is composed of a silicon oxide film, a silicon nitride film, an organic resin film, or a laminated film thereof.
[0037]
Then, source electrodes 132 and 133 and a drain electrode 134 made of a metal thin film are formed thereon. As the metal thin film, aluminum, tantalum, titanium, tungsten, molybdenum, or a laminated film thereof may be used. The film thickness may be 100 to 300 nm. (Figure 2 (E))
[0038]
Finally, the whole is subjected to heat treatment at 350 ° C. for about 2 hours in a hydrogen atmosphere, and the dangling bonds in the film (particularly in the channel formation region) are terminated with hydrogen. Through the above steps, a CMOS circuit having a structure as shown in FIG.
[0039]
Note that when the manufacturing process of this embodiment is followed, the NTFT has an LDD structure, but the PTFT does not have an LDD structure. However, this embodiment is an embodiment of the present invention, and the structure to which the present invention can be applied is not limited to this embodiment.
[0040]
In other words, the present invention can be applied to all reverse stagger type TFTs configured by known means. In this embodiment, a CMOS circuit is described as an example, but it is needless to say that the present invention can be applied to a circuit constituted by only a single element of NTFT or PTFT.
[0041]
Here, the significance of lowering the boron concentration in the portion where the channel is formed in the channel doping step will be described.
[0042]
When a large amount of an impurity element for controlling the threshold voltage is present in the channel, majority carriers (electrons or holes) collide with the impurity and are scattered. This impurity scattering of carriers is not preferable because it causes a reduction in field effect mobility (mobility) that governs the operating speed of TFT characteristics.
[0043]
In the present invention, since impurities such as boron are added just from the back side of the part where the channel is formed, it is possible to reduce the impurity concentration of the part where the channel is formed using the gradient of the concentration profile. is there. In other words, the impurity concentration of boron or the like in the channel formation region has a concentration gradient that decreases as it approaches the interface between the channel formation region and the gate insulating film.
[0044]
Therefore, in the channel formation region, near the surface far from the substrate, the concentration of the impurity element is 1 × 10 ¹⁷ ~ 1 × 10 ²⁰ atoms / cm ^Three However, the concentration decreases toward the interface with the gate insulating film, and it is about 1/10 or less near the interface (typically 1 × 10 ¹⁶ ~ 5 × 10 ¹⁸ atoms / cm ^Three ).
[0045]
Such adjustment of the concentration gradient is controlled by ion implantation conditions, but the buffer layer provided at the time of ion implantation facilitates such precise concentration control.
[0046]
In this way, by controlling the threshold voltage while avoiding impurity scattering as much as possible, it is possible to manufacture a TFT that can be driven at a low operating voltage and has high mobility.
[0047]
[Example 2]
In this embodiment, an example in which the order of the impurity element addition step and the crystallization step for controlling the threshold voltage is switched in the first embodiment will be described.
[0048]
In FIG. 3A, 301 is a glass substrate, 302 is a base film, 303 and 304 are gate electrodes made of a tantalum film, 305 is a gate insulating film made of a laminated film in which a thin silicon nitride film is provided on a silicon oxide film, Reference numeral 306 denotes an amorphous silicon film. (Fig. 3 (A))
[0049]
Next, a buffer layer 307 and a resist mask 308 are provided, and boron is added by an ion implantation method. The injection conditions may be according to Example 1. In this way, a boron-containing region 309 is formed. 3 The state (B) is obtained.
[0050]
Next, after removing the buffer layer 307 and the resist mask 308, excimer laser light is irradiated as shown in FIG. Excimer laser light irradiation conditions may be in accordance with the first embodiment.
[0051]
Through this step, the amorphous silicon film 306 is crystallized, and a crystalline silicon film 309 is obtained. At the same time, the boron added by the aforementioned ion implantation is activated.
[0052]
Then, the crystalline silicon film 309 is patterned into an island shape to obtain active layers 310 and 311. If the subsequent steps are performed in accordance with Embodiment 1, a CMOS circuit having a structure as shown in FIG. 2E can be manufactured.
[0053]
Example 3
In this embodiment, an example in which a catalyst element (typically nickel) that promotes crystallization is used for crystallization of an amorphous silicon film is shown.
[0054]
4A, 401 is a glass substrate, 402 is a base film, 403 and 404 are gate electrodes made of a chromium film, 405 is a gate insulating film, and 406 is an amorphous silicon film. Since these details have already been described in the first embodiment, they will be omitted.
[0055]
In this embodiment, a film containing nickel (hereinafter referred to as a nickel-containing layer) 407 is formed on the amorphous silicon film 406. As a method for forming the nickel-containing layer 407, a technique described in Japanese Patent Laid-Open No. 7-130652 (particularly, Example 1) by the present inventors may be used. (Fig. 4 (A))
[0056]
In addition to nickel, the catalytic element is cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), gold (Au), germanium (Ge), lead (Pb). Etc. can be used.
[0057]
In the above publication, an example in which the catalyst element addition step is performed by a spin coating method is shown, but an ion implantation method or a plasma doping method can also be used. In this case, since the occupied area of the added region can be reduced and the growth distance of the lateral growth region can be easily controlled, this is an effective technique for configuring a miniaturized circuit.
[0058]
Next, after the catalyst element addition step is completed, after hydrogen removal at 500 ° C. for about 1 hour, a temperature of 500 to 700 ° C. (typically 550 to 650 ° C.) in an inert atmosphere, hydrogen atmosphere or oxygen atmosphere Then, the amorphous silicon film 406 is crystallized by applying heat treatment (furnace annealing) for 4 to 24 hours. In this embodiment, a heat treatment is performed at 550 ° C. for 4 hours in a nitrogen atmosphere to obtain a crystalline silicon film 408. (Fig. 4 (B))
[0059]
Next, a buffer layer 409 and a resist mask 410 are provided, and boron is added only to a region to be NTFT. The addition method and conditions may follow the conditions shown in Example 1. By this step, a boron-containing region 411 is formed. (Fig. 4 (C))
[0060]
Next, the buffer layer 409 and the resist mask 410 are removed, and active layers 412 and 413 are formed by patterning. Thereafter, excimer laser light is irradiated to recover damage when boron is added, improve crystallinity (such as crystallization of a slightly remaining amorphous component), and activate boron. (Fig. 4 (D))
[0061]
In this embodiment, the laser beam is irradiated after the crystalline silicon film 408 is processed into an island shape. However, the active layer is formed by processing into an island shape after the laser beam irradiation. May be.
[0062]
Then, if the subsequent steps are in accordance with Embodiment 1, a CMOS circuit having a structure as shown in FIG. 2E can be manufactured.
[0063]
Example 4
In this embodiment, an example in which the amorphous silicon film is crystallized by means different from that in Embodiment 3 will be described. Specifically, crystallization is performed using the technique described in JP-A-8-78329.
[0064]
5A, reference numeral 501 is a glass substrate, 502 is a base film, 503 and 504 are gate electrodes, 505 is a gate insulating film, and 506 is an amorphous silicon film. These details may be according to the first embodiment.
[0065]
In this embodiment, a mask insulating film 507 having a plurality of openings is provided on the amorphous silicon film 506, and a nickel-containing layer 508 is formed thereon. That is, the nickel-containing layer 508 is in contact with the amorphous silicon film 506 only in the opening provided in the mask insulating film 507. Note that as the mask insulating film 507, a silicon oxide film with a thickness of 50 to 200 nm is preferably used. (Fig. 5 (A))
[0066]
Next, after the catalyst element addition process is completed, after hydrogen removal at 450 ° C. for about 1 hour, a temperature of 500 to 700 ° C. (typically 550 to 650 ° C.) in an inert atmosphere, hydrogen atmosphere or oxygen atmosphere Then, the amorphous silicon film 506 is crystallized by applying heat treatment for 4 to 24 hours. In this embodiment, heat treatment is performed in a nitrogen atmosphere at 570 ° C. for 14 hours.
[0067]
At this time, crystallization of the amorphous silicon film 506 proceeds preferentially from the nuclei generated in the nickel-added regions 509 and 510, and crystal regions 511 and 512 grown substantially parallel to the substrate surface of the substrate 501. Is formed. (Fig. 5 (B))
[0068]
The inventors refer to the crystal regions 511 and 512 as lateral growth regions. The lateral growth regions 511 and 512 are advantageous in that they are excellent in overall crystallinity because individual rod-like or flat rod-like crystals are gathered in a relatively aligned state.
[0069]
When the crystalline silicon films (lateral growth regions) 511 and 512 are thus obtained, a resist mask 513 is formed and a boron addition step is performed to form a boron-containing region 514. (Fig. 5 (C))
[0070]
In this embodiment, the mask insulating film 507 used in the catalyst element addition step is used as a buffer layer in the boron addition step. Thereby, the process can be simplified.
[0071]
When the state of FIG. 5C is thus obtained, active layers 515 and 516 consisting only of the lateral growth regions 511 and 512 are formed. When forming the active layers 515 and 516, the nickel-added regions 509 and 510 are preferably completely removed.
[0072]
Next, the excimer laser light is irradiated to recover damage caused by boron addition to the active layers 515 and 516, improve crystallinity, and activate boron. If the subsequent steps are in accordance with Embodiment 1, a CMOS circuit having the structure shown in FIG. 2E can be manufactured.
[0073]
Example 5
In this embodiment, an example in which a step for removing the catalytic element used for crystallization by gettering in Embodiment 3 is added will be described. Specifically, the gettering effect by an element selected from the group 15 is used for gettering of the catalyst element (nickel). As elements selected from Group 15, P (phosphorus), N (nitrogen), As (arsenic), Sb (antimony), and Bi (bismuth) can be used. This shows the case of using phosphorus.
[0074]
First, the state shown in FIG. Then, after removing the buffer layer 409 and the resist mask 410, a resist mask 601 having a plurality of openings is newly formed. This opening is formed at a position where a region that will not be used (removed) later as an active layer is exposed.
[0075]
Next, phosphorus is added using the resist mask 601 as a mask. This adding step uses an ion implantation method or an ion doping method. The addition conditions are RF power 20W, acceleration voltage 5-30keV (typically 10keV) and phosphorus dose 1 × 10 ¹³ atoms / cm ² Or more (preferably 5 × 10 ¹³ ~ 5 × 10 ¹⁵ atoms / cm ² ).
[0076]
As a standard of the phosphorus concentration to be added, a concentration higher by one digit or more than the nickel concentration contained in the crystalline silicon film 408 is preferably added. In the process of the third embodiment, about 1 × 10 6 is formed in the crystalline silicon film 408. ¹⁹ atoms / cm ^Three In that case, 1 × 10 ²⁰ atoms / cm ^Three It is preferable to add a certain amount of phosphorus.
[0077]
Thus, regions doped with phosphorus (gettering regions) 602 to 604 are formed inside the crystalline silicon film 408. (Fig. 6 (A))
[0078]
Next, after the resist mask 601 is removed, heat treatment for gettering nickel is performed. By this heat treatment, nickel contained in the gettering regions 605 and 606 is captured by the gettering regions 602 to 604 as indicated by arrows. (Fig. 6 (B))
[0079]
This heat treatment may be furnace annealing in an inert atmosphere, a hydrogen atmosphere, an oxidizing atmosphere, or an oxidizing atmosphere containing a halogen element. The treatment temperature may be 400 to 700 ° C. (preferably 550 to 650 ° C.), and the treatment time may be 2 hours or more (preferably 4 to 12 hours). The higher the processing temperature is, the shorter the time is required and the higher the gettering effect is. However, considering the heat resistance of the glass substrate, it is desirable to set it to 650 ° C. or lower.
[0080]
Further, boron is added to the gettering region 605 that later becomes NTFT in order to control the threshold voltage, but recovery of damage and activation of boron at the time of boron addition are simultaneously performed by the furnace annealing. It is. If the temperature is within the above temperature range, boron diffusion is very small, which is not a problem.
[0081]
When nickel is gettered in the gettering regions 602 to 604 in this manner, the crystalline silicon film is patterned to form active layers 607 and 608 including only gettering regions 605 and 606. At this time, since the gettering regions 602 to 604 and the vicinity thereof contain nickel in a high concentration, it is desirable to completely remove them without using them for the active layer.
[0082]
The nickel concentration in the active layers 607 and 608 obtained by the gettering process is 5 × 10 5. ¹⁷ atoms / cm ^Three It has been confirmed by SIMS (mass secondary ion analysis) that it is reduced to the following. (The concentration in this specification is defined by the minimum value of the SIMS measurement value.)
[0083]
Currently 5 × 10 due to the detection limit ¹⁷ atoms / cm ^Three Only known below, but in practice at least 1x10 ¹⁴ atoms / cm ^Three I think that it has reached to the extent. Experimentally, the nickel concentration is 5 × 10 ¹⁷ atoms / cm ^Three It has been found that the following will not affect TFT characteristics.
[0084]
The state shown in FIG. 6C is obtained as described above. Thereafter, in the same manner as in the third embodiment, if the steps shown in the first embodiment are followed, a CMOS circuit having a structure as shown in FIG. 2E can be manufactured.
[0085]
Note that this embodiment can be easily applied not only to the case of the third embodiment but also to the case where the crystallization means shown in the fourth embodiment is used. In that case, the mask insulating film 507 used for nickel addition can be used not only as a mask at the time of boron addition but also as a mask at the time of phosphorus addition shown in this embodiment. In that case, the process can be greatly simplified.
[0086]
In this embodiment, an example in which an ion implantation method or an ion doping method is used as a means for adding phosphorus is shown. An annealing in an atmosphere containing phosphorus (vapor phase method), a getter into an insulating film containing phosphorus. A ring (solid phase method) may be used.
[0087]
Example 6
In this embodiment, an example of manufacturing an inverted staggered TFT having a structure different from that of Embodiment 1 is shown. FIG. 7 is used for the description.
[0088]
First, the state shown in FIG. Then, channel stoppers 701 and 702 are formed on the active layers 111 and 112. As the channel stoppers 701 and 702, a silicon nitride film or a silicon oxide film having a thickness of 30 to 150 nm can be used. (Fig. 7 (A))
[0089]
Next, a crystalline silicon film (hereinafter abbreviated as an N-type conductive film) 703 having N-type conductivity is formed, and a metal thin film 704 is formed thereon. For the N-type conductive film 703, a polycrystalline or microcrystalline silicon film to which phosphorus is added is used. Further, the metal thin film 704 may be the same as the metal thin film constituting the source / drain electrodes in the first embodiment. (Fig. 7 (B))
[0090]
Note that it is preferable to continuously form the N-type conductive film 703 and the metal thin film 704 because a very good ohmic contact can be realized.
[0091]
Next, the metal thin film 704 is first etched to cut off necessary portions. Then, the N-type conductive film 703 is etched in a self-aligning manner using the metal thin film 704 as a mask. At this time, the channel stoppers 701 and 702 function as etching stoppers.
[0092]
Thus, NTFT source electrodes 705 and 706, PTFT source electrodes 707 and 708, and NTFT and PTFT common drain electrodes 709 and 710 are formed. A passivation film made of a silicon nitride film or an organic resin film may be provided on these electrodes. As described above, the CMOS circuit having the structure shown in FIG.
[0093]
Note that the reverse stagger type TFT using the channel stopper is not limited to this embodiment. The present invention can be easily applied to other types of structures.
[0094]
Example 7
In this embodiment, an example in which an inverted stagger type TFT having a structure different from those in Embodiments 1 and 6 is shown. FIG. 8 is used for the description.
[0095]
First, the state shown in FIG. Then, an N-type conductive film 801 is formed on the active layers 111 and 112, and a metal thin film is formed thereon. 802 Form. Since these thin films have been described in Example 6, their description is omitted here. (Fig. 8 (A))
[0096]
Next, the metal thin film 802 is etched to cut off necessary portions, and then the N-type conductive film 801 is etched in a self-aligning manner. At this time, the N-type conductive film 801 and the lower active layers 111 and 112 cannot be selected, so that etching proceeds into the active layers 111 and 112.
[0097]
Therefore, only this portion has a thin active layer, and this thinned portion functions as an effective channel formation region.
[0098]
Thus, NTFT source electrodes 803 and 804, PTFT source electrodes 805 and 806, and NTFT and PTFT common drain electrodes 807 and 808 are formed. Finally, a silicon nitride film 809 is formed as a passivation film. 8 ( B The CMOS circuit having the structure shown in FIG.
[0099]
Note that in the case where a peripheral driver circuit and a pixel matrix circuit are formed over the same substrate as in an active matrix liquid crystal display device, for example, an organic resin film may be provided instead of the silicon nitride film 809. In such a case, the organic resin film functions as a passivation film. The same applies to Example 6.
[0100]
Further, in the case of the structure of this embodiment, the N-type conductive film 801 comes into contact with the subsequent channel formation region at the stage shown in FIG. At this time, boron added to the active layer 111 and phosphorus in the N-type conductive film 801 mutually diffuse and cancel each other, so that the channel formation region becomes substantially intrinsic or is inverted to N-type. There may be a problem that a desired threshold voltage cannot be obtained.
[0101]
When such a problem occurs, boron having a concentration higher than the phosphorus concentration contained in the N-type conductive film 801 is added in the channel doping step (the step of adding boron to control the threshold voltage). You should do it. In this way, even if they cancel each other, the absolute amount of boron is larger, so that the P-type can be maintained. Of course, it is necessary to perform channel dope so that a desired threshold voltage can be obtained in anticipation of the finally remaining boron concentration.
[0102]
The present invention can be easily applied to an inverted stagger type TFT having a structure other than that shown in this embodiment.
[0103]
Example 8
In Examples 1 to 7, an example in which the buffer layer is used in the channel doping process is shown. However, a configuration in which the buffer layer is not used is possible if the boron addition conditions are optimized. In that case, the damage to the silicon film when it is added increases, but it is not a problem as long as it can be recovered by subsequent furnace annealing or laser annealing.
[0104]
Example 9
In the configurations shown in the first to seventh embodiments, an example in which boron is added only to NTFT in manufacturing a CMOS circuit is shown, but it goes without saying that it may be added to both NTFT and PTFT.
[0105]
In order to control the threshold voltage in Examples 1 to 7, boron (which may be indium) selected from the group 13 is added to force the threshold voltage shifted to the minus side to the plus side. This is because the control is performed so that a desired threshold voltage is indicated. Therefore, if it is necessary to shift the PTFT to the plus side, it is naturally effective to add boron to the PTFT.
[0106]
Similarly, it is also possible to apply the present invention only to PTFT in manufacturing a CMOS circuit.
[0107]
Example 10
In Examples 1 to 7, a group 13 element is used to shift the threshold voltage to the plus side. However, when it is necessary to shift the threshold voltage to the minus side, the channel doping impurity element is selected from group 15 The element used (phosphorus, arsenic or antimony) may be used.
[0108]
In this case, for example, the concentration profile of phosphorus when phosphorus is ion-implanted is different from the concentration profile of boron. Therefore, it is necessary to experimentally obtain optimum values for the dose and other various conditions.
[0109]
However, when combined with the gettering by phosphorus of the fifth embodiment, the gettering effect cannot be expected so much because the structure of this embodiment also contains phosphorus in the channel formation region.
[0110]
Example 11
In the structure shown in Examples 1-7, the activation of the impurity after a channel dope process has shown the example by irradiation of an excimer laser beam. In the present invention, lamp annealing represented by RTA (rapid thermal annealing) can be used instead of laser annealing.
[0111]
When RTA treatment is performed, the thin film can be annealed without causing deformation of the glass substrate by performing treatment at a temperature of 500 to 1150 ° C. (preferably 800 to 1000 ° C.) for several seconds. For this reason, the throughput is remarkably improved.
[0112]
Of course, the impurity may be activated by furnace annealing at about 500 to 600 ° C., but RTA treatment is effective for improving productivity.
[0113]
Example 12
In this embodiment, an example in which a circuit is formed on a glass substrate using the semiconductor device having the structure shown in Embodiments 1 to 11 to manufacture an electro-optical device will be described. Typically, a liquid crystal display device, an EL (electroluminescence) display device, an EC (electrochromic) display device, an image sensor, a CCD, or the like can be manufactured.
[0114]
Note that in this specification, an electro-optical device is defined as a device that converts an electrical signal into an optical signal or vice versa.
[0115]
FIG. 9A shows a liquid crystal display device (liquid crystal module). Reference numeral 11 denotes an active matrix substrate, which includes a pixel matrix circuit 12, a source side driving circuit 13, a gate side driving circuit 14, and a logic circuit 15 which are formed of a TFT of the present invention on a glass substrate.
[0116]
The source side drive circuit 13 is mainly composed of a shift register circuit, a sampling circuit, a buffer circuit, a level shifter circuit, and the like. The gate side drive circuit 14 is mainly composed of a shift register circuit, a buffer circuit, and the like. The logic circuit 15 includes all circuits that perform various signal processing, and includes a clock generation circuit, a memory circuit, an arithmetic circuit, a signal conversion circuit, and the like.
[0117]
A liquid crystal layer (not shown) is sealed between the active matrix substrate 11 configured as described above and the counter substrate 16 by a sealing material. In addition, the active matrix substrate 11 and the counter substrate 16 are bonded so that all end faces are aligned except for one side, and the counter substrate 16 is removed so that a part of the active matrix substrate 11 is exposed on one side. Yes.
[0118]
In this area, terminals for transmitting signals from the outside to the source / gate side drive circuits 13 and 14 and the logic circuit 15 are exposed, and this area becomes an area for connecting an FPC (flexible printed circuit) 17.
[0119]
FIG. 9B shows a simplified circuit configuration of the source side driver circuit 13. Reference numeral 18 denotes a shift register circuit, and a plurality of inverter circuits (CMOS circuits) 19 form a flip-flop circuit.
[0120]
A sampling circuit 21 is assembled by a plurality of analog switches 22 with the buffer circuit 20 interposed therebetween.
[0121]
Since the threshold voltage is adjusted by the effect of channel doping, the present invention can easily cope with a low operating voltage. Further, since carrier scattering due to impurities is very small in the channel portion, high mobility can be realized even though the threshold voltage is controlled.
[0122]
Therefore, the TFT of the present invention is effective in constructing the logic circuit 15 and the shift register circuit 18 that require a low operating voltage and a high operating speed.
[0123]
Further, since the characteristic balance of the CMOS circuit is corrected by controlling the threshold voltage, it is also suitable for configuring a circuit in which it is important to equalize the characteristic balance between NTFT and PTFT like the analog switch 22.
[0124]
Example 13
The electro-optical device shown in Example 12 is used as a display of various electronic devices. Note that the electronic apparatus described in this embodiment is defined as a product on which an electro-optical device typified by a liquid crystal module is mounted.
[0125]
Examples of such electronic devices include a video camera, a still camera, a projector, a projection TV, a head mounted display, a car navigation, a personal computer (including a notebook type), a portable information terminal (a mobile computer, a mobile phone, etc.). . An example of them is shown in FIG.
[0126]
FIG. 10A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, an operation switch 2005, and an antenna 2006. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and the like.
[0127]
FIG. 10B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the audio input unit 2103, and the image receiving unit 2106.
[0128]
FIG. 10C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the image receiving unit 2203, the display device 2205, and the like.
[0129]
FIG. 10D illustrates a head mounted display, which includes a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to the display device 2302.
[0130]
FIG. 10E shows a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403.
[0131]
FIG. 10F illustrates a front projector, which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention can be applied to the display device 2503.
[0132]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. In addition, it can also be used for electric billboards, advertising announcement displays, and the like.
[0133]
【The invention's effect】
By utilizing the present invention, the threshold voltage of the bottom gate type TFT can be effectively controlled. In addition, various electro-optical devices and electronic devices can be realized by using such a semiconductor device.
[Brief description of the drawings]
FIGS. 1A to 1C illustrate a manufacturing process of a thin film transistor. FIGS.
FIGS. 2A and 2B illustrate a manufacturing process of a thin film transistor. FIGS.
FIG. 3 illustrates a manufacturing process of a thin film transistor.
4A and 4B illustrate a manufacturing process of a thin film transistor.
FIGS. 5A and 5B illustrate a manufacturing process of a thin film transistor. FIGS.
6A and 6B illustrate a manufacturing process of a thin film transistor.
FIGS. 7A to 7C illustrate a manufacturing process of a thin film transistor. FIGS.
FIG. 8 illustrates a manufacturing process of a thin film transistor.
FIG. 9 is a diagram illustrating a configuration of an electro-optical device.
FIG 10 illustrates a structure of an electronic device.
[Explanation of symbols]
101 glass substrate
102 Base film
103, 104 Gate electrode
105 Gate insulation film
106 Amorphous silicon film
107 crystalline silicon film
108 Buffer layer
109 resist mask
110 Boron-containing region
111, 112 active layer

Claims (13)

On a substrate having an insulation surface, forming a first gate electrode and second gate electrode,
Forming a gate insulating film covering the first gate electrode and the second gate electrode;
Forming an amorphous silicon film on the gate insulating film;
Forming a first mask having an opening on the amorphous silicon film;
In contact with the amorphous silicon film in the opening, N i, Co, Fe, Pd, Pt, Cu, to form a layer having at least one element selected from Au, the amorphous by the heat treatment Crystallizing the porous silicon film to form a crystalline silicon film,
Adding a group 13 element to a region of the crystalline silicon film on the first gate electrode by doping through the first mask ;
The crystalline silicon film is patterned to form a first island-like crystalline silicon film on the first gate electrode and a second island-like crystalline silicon film on the second gate electrode And
One of the first island-like crystalline silicon film, applying the on the first region of the gate electrode to form a second mask, N-type in the first island-like crystalline silicon film By adding an impurity element to form an N-channel bottom gate thin film transistor,
Wherein among the second island-like crystalline silicon film, applying the on the second region on the gate electrode to form a third mask, P-type in the second island-like crystalline silicon film A method for manufacturing a semiconductor device, wherein a p-channel bottom-gate thin film transistor is formed by adding an impurity element to be added. Forming a first gate electrode and a second gate electrode on a substrate having an insulating surface;
Forming a gate insulating film covering the first gate electrode and the second gate electrode;
Forming an amorphous silicon film on the gate insulating film;
Forming a first mask having an opening on the amorphous silicon film;
A layer having at least one element selected from Ni, Co, Fe, Pd, Pt, Cu, and Au is formed in contact with the amorphous silicon film in the opening, and the amorphous is formed by heat treatment. Crystallizing the silicon film to form a crystalline silicon film,
Adding a group 13 element to a region of the crystalline silicon film on the first gate electrode by doping through the first mask;
The group 13 element added to the crystalline silicon film is activated by laser light irradiation or RTA,
The crystalline silicon film is patterned to form a first island-like crystalline silicon film on the first gate electrode and a second island-like crystalline silicon film on the second gate electrode And
A second mask is formed on a region of the first island-like crystalline silicon film on the first gate electrode, and an N-type is imparted to the first island-like crystalline silicon film. By adding an impurity element to form an N-channel bottom gate thin film transistor,
A third mask is formed on a region of the second island-shaped crystalline silicon film on the second gate electrode, and a P-type is imparted to the second island-shaped crystalline silicon film. A method for manufacturing a semiconductor device, wherein a p-channel bottom-gate thin film transistor is formed by adding an impurity element to be added. Forming a first gate electrode and a second gate electrode on a substrate having an insulating surface;
Forming a gate insulating film covering the first gate electrode and the second gate electrode;
Forming an amorphous silicon film on the gate insulating film;
Forming a first mask having an opening on the amorphous silicon film;
A layer having at least one element selected from Ni, Co, Fe, Pd, Pt, Cu, and Au is formed in contact with the amorphous silicon film in the opening, and the amorphous is formed by heat treatment. Crystallizing the silicon film to form a crystalline silicon film,
Of the crystalline silicon film, the first gate is doped by doping through the first mask. A group 13 element is added to the region on the electrode,
The crystalline silicon film is patterned so as to remove a region in contact with the layer in the opening, and a first island-shaped crystalline silicon film and the second gate are formed on the first gate electrode. Forming a second island-like crystalline silicon film on the electrode;
A second mask is formed on a region of the first island-like crystalline silicon film on the first gate electrode, and an N-type is imparted to the first island-like crystalline silicon film. By adding an impurity element to form an N-channel bottom gate thin film transistor,
A third mask is formed on a region of the second island-shaped crystalline silicon film on the second gate electrode, and a P-type is imparted to the second island-shaped crystalline silicon film. A method for manufacturing a semiconductor device, wherein a p-channel bottom-gate thin film transistor is formed by adding an impurity element to be added. Forming a first gate electrode and a second gate electrode on a substrate having an insulating surface;
Forming a gate insulating film covering the first gate electrode and the second gate electrode;
Forming an amorphous silicon film on the gate insulating film;
Forming a first mask having an opening on the amorphous silicon film;
A layer containing at least one element selected from Ni, Co, Fe, Pd, Pt, Cu, and Au is formed in contact with the amorphous silicon film in the opening, and the first heat treatment Crystallizing the amorphous silicon film to form a crystalline silicon film,
Adding a group 13 element to a region of the crystalline silicon film on the first gate electrode by doping through the first mask;
At least one selected from the group consisting of Ni, Co, Fe, Pd, Pt, Cu, and Au is added by adding a group 15 element to a region exposed in the opening of the crystalline silicon film and performing a second heat treatment. Gettering elements into the region,
The crystalline silicon film is patterned so as to remove the region of the crystalline silicon film, and a first island-shaped crystalline silicon film and the second gate electrode are formed on the first gate electrode. A second island-like crystalline silicon film is formed thereon;
A second mask is formed on a region of the first island-like crystalline silicon film on the first gate electrode, and an N-type is imparted to the first island-like crystalline silicon film. By adding an impurity element to form an N-channel bottom gate thin film transistor,
A third mask is formed on a region of the second island-shaped crystalline silicon film on the second gate electrode, and a P-type is imparted to the second island-shaped crystalline silicon film. A method for manufacturing a semiconductor device, wherein a p-channel bottom-gate thin film transistor is formed by adding an impurity element to be added. Forming a first gate electrode and a second gate electrode on a substrate having an insulating surface;
Forming a gate insulating film covering the first gate electrode and the second gate electrode;
Forming an amorphous silicon film on the gate insulating film;
Forming a first mask having an opening on the amorphous silicon film;
A layer containing at least one element selected from Ni, Co, Fe, Pd, Pt, Cu, and Au is formed in contact with the amorphous silicon film in the opening, and the first heat treatment Crystallizing the amorphous silicon film to form a crystalline silicon film,
Adding a group 13 element to a region of the crystalline silicon film on the first gate electrode by doping through the first mask;
At least one selected from the group consisting of Ni, Co, Fe, Pd, Pt, Cu, and Au is added by adding a group 15 element to a region exposed in the opening of the crystalline silicon film and performing a second heat treatment. Activating the group 13 element simultaneously with gettering the element into the region,
The crystalline silicon film is patterned so as to remove the region of the crystalline silicon film, and a first island-shaped crystalline silicon film and the second gate electrode are formed on the first gate electrode. A second island-like crystalline silicon film is formed thereon;
A second mask is formed on a region of the first island-like crystalline silicon film on the first gate electrode, and an N-type is imparted to the first island-like crystalline silicon film. By adding an impurity element to form an N-channel bottom gate thin film transistor,
A third mask is formed on a region of the second island-shaped crystalline silicon film on the second gate electrode, and a P-type is imparted to the second island-shaped crystalline silicon film. A method for manufacturing a semiconductor device, wherein a p-channel bottom-gate thin film transistor is formed by adding an impurity element to be added. Any one to Oite of claims 1 to 3, the method for manufacturing a semiconductor device, wherein the heat treatment is carried out at a temperature range of 550 to 650 ° C.. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the first heat treatment is performed in a temperature range of 550 to 650 ° C. 6. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the second heat treatment is performed in a temperature range of 550 to 650 ° C. 6. 9. The method for manufacturing a semiconductor device according to claim 4, wherein the group 15 element is phosphorus. 10. The method for manufacturing a semiconductor device according to claim 1, wherein the group 13 element is boron. Any one to Oite of claims 1 to 10, wherein the addition of the Group 13 element in the region on the first gate electrode, the row at a dose of ^{1 × 10 12 ~1 × 10 17} atoms / cm 2 A method for manufacturing a semiconductor device. In any one of claims 1 to 11 Oite, the addition of the first of the group 13 element in the region on the gate electrode, the semiconductor device characterized in that it is performed by an ion implantation method or an ion doping method Manufacturing method. In any one of claims 1 to 12, wherein the method for manufacturing a semiconductor device a first mask, characterized in that formed to a thickness of 5 0 ~20 0 nm.

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