JP3833659B2 - Calibration method for semiconductor test equipment - Google Patents

Description

  The present invention relates to a semiconductor test apparatus calibration method for adjusting operation timings of drivers and comparators in pin electronics of a semiconductor test apparatus.

  The pin electronics of the semiconductor test apparatus includes a driver that applies a signal to the device under measurement and a comparator that determines the logic of the signal output from the device under measurement corresponding to this signal. The driver performs a signal output operation in synchronization with the input clock signal. The comparator performs a determination operation synchronized with the input strobe signal.

  By the way, in the initial state of the semiconductor test equipment, the time length of the signal path for each input / output pin of the device under test varies. End up. For this reason, timing calibration is performed before various tests are performed on the device under measurement.

  FIG. 73 is a diagram showing a conventional configuration for performing timing calibration of a semiconductor test apparatus. In FIG. 73, the semiconductor test apparatus main body 90 is connected to the socket board 94 via a dedicated cable 93 provided on the performance board 92. For example, when various tests are performed on a device under measurement having a BGA (Ball Grid Array) type package, a socket board 94 having a large number of pogo pins on the surface is used. The test board 96 is used to facilitate the operation of bringing the probe 99 drawn out from the reference driver / comparator (DR / CP) section 98 into contact with these pogo pins provided on the surface of the socket boat 94. The pad provided on each of the front and back surfaces is electrically connected inside.

  FIG. 74 is an electrical layout diagram of the conventional configuration shown in FIG. The semiconductor test apparatus main body 90 includes a plurality of sets of drivers and comparators. Each set of drivers and comparators is connected to a common device socket end via a performance board (PB) 92 and a socket board (SB) 94. It is connected. In FIG. 74, the test board 96 is omitted.

  75, 76, and 77 are diagrams showing an outline of conventional timing calibration. As shown in FIG. 75, in the initial state of the semiconductor test apparatus, the phases of the clock signals CLK1 to CLKn and the strobe signals STB1 to STBn input to the n drivers DR1 to DRn and the n comparators CP1 to CPn, respectively. (Skew) is off.

  First, the probe 99 of the reference driver / comparator unit 98 is connected to one of the device socket ends via the test board 96, and the phase of the strobe signal STB1 (comparison by the comparator CP1) is detected at the rising timing of the reference driver signal (reference DR). The operation timing is matched (FIG. 76). Next, after making the phase of the reference comparator signal (reference CP) coincide with the rising timing of the output signal of the reference driver, it is output from the driver DR1 at the output timing of the reference comparator signal (comparison operation timing by the reference comparator). The phase of CLK1 of the clock signal input to the driver DR1 is matched so that the rising timings of the signals coincide with each other (FIG. 77). Such a timing calibration operation is performed for each device socket end.

  By the way, in the timing calibration method of the conventional semiconductor test apparatus described above, in order to correct the timing at the end of the device socket, the movement of the probe 99 provided in the reference driver / comparator unit 98 and the contact of the tip portion thereof are performed. It must be repeated, and a special device is required to automate this operation. Although it is conceivable that this work is performed by a dedicated robot, such a robot is generally expensive, and in many cases it is not easy to handle in order to ensure high positioning accuracy, and the work content becomes complicated. was there. Further, the probe 99 can be manually aligned without using a robot. However, if the device under test has a large number of pins or the number of devices under test to be tested simultaneously, the probe 99 The number of repetitions of 99 movements and contacts also becomes enormous, and there is a problem that the work time until the timing calibration is completed increases.

  The present invention was created in view of the above points, and an object of the present invention is to provide a semiconductor test apparatus calibration method capable of reducing cost, simplifying work contents, and shortening work time. It is in.

  In order to solve the above-described problems, a semiconductor test apparatus calibration method according to the present invention includes a driver that performs a signal generation operation synchronized with a clock signal and a comparator that performs a comparison operation synchronized with a strobe signal. In order to perform timing calibration of the apparatus, the apparatus includes the first to third steps. In the first step, each of the plurality of drivers and each of the plurality of comparators are in a one-to-one correspondence, and one of the clock signals and the strobe signal corresponding to each other is used as a reference. The other phase is adjusted. In the second step, a relative phase difference between clock signals corresponding to each of the plurality of drivers or a relative phase difference between strobe signals corresponding to each of the plurality of comparators is acquired. In the third step, the phases of the plurality of clock signals and the plurality of strobe signals are adjusted based on the relative phase difference. Costs are eliminated as there is no need for a dedicated reference driver / comparator unit, a probe connected to it, or a dedicated robot to automate the movement and contact of the probe, just to perform timing calibration. Can be significantly reduced.

  In particular, the phase adjustment performed in the first step described above is such that the timing at which the comparison operation is performed by the comparator in accordance with the strobe signal coincides with the timing at which the signal output from the driver and input to the comparator changes. In addition, it is desirable to change the phase of the clock signal. Alternatively, in the phase adjustment performed in the first step described above, the timing at which the comparison operation is performed by the comparator in accordance with the strobe signal matches the timing at which the signal output from the driver and input to the comparator changes. In addition, it is desirable to change the phase of the strobe signal. In addition, the acquisition of the phase difference performed in the second step described above is performed for either one of the clock signal and the strobe signal corresponding to each other in a state where the combination of the driver and the comparator in the first step is changed. It is desirable to measure by measuring the other phase difference with reference to. By changing the phase of the clock signal or strobe signal while observing the result of the comparison operation by the comparator, it is possible to easily adjust the phase and measure the relative phase difference.

  Further, it is desirable that a delay element for changing the phase of the signal is inserted in each of the clock signal supply path to the driver and the strobe signal supply path to the comparator. By individually varying the delay amount of each delay element, the respective phases of the clock signal and the strobe signal corresponding to each device socket end can be adjusted to arbitrary values.

  In the first step described above, the first calibration in which the output terminal of the corresponding one driver and the input terminal of the one comparator are connected to each of the short connection points via the wiring having the same time length. It is desirable that this be performed using an operation board. In the second step described above, the output terminal of the corresponding one driver and the input terminal of the one comparator are connected to each of the short connection points via a wiring having an equal time length. It is desirable to use a second calibration board having a different combination of calibration board and wiring. The phase adjustment between the clock signal and the strobe signal and the measurement of the phase difference between the strobe signals or the phase difference between the clock signals can be performed by using the first calibration board or the second calibration board. Therefore, the work content can be simplified as compared with the conventional method in which the phase of the clock signal or strobe signal is adjusted for each device socket end using a probe.

  Moreover, it is desirable to have the 4th step which replace | exchanges a 1st calibration board for a 2nd calibration board between the 1st step mentioned above and a 2nd step. The mechanical work is merely replacement of the first calibration board with the second calibration board, and the work time in the entire timing calibration can be greatly reduced.

  Further, in the first step described above, the third calibration in which the output terminal of the corresponding one driver and the input terminal of the one comparator are connected to each of the short connection points via the wiring having the same time length. In the second step, the output terminal of one corresponding driver and the input terminal of one comparator are connected to each of the short connection points via wires of equal time length. As described above, it is desirable to switch the wiring state of the third calibration board. By using the third calibration board capable of switching the wiring content, the replacement work of the calibration board becomes unnecessary, so that the entire work time can be further reduced.

  Further, the above-described third calibration board includes a plurality of changeover switches for switching the wiring state, and the operations of the first and second steps are performed by switching the connection state of these changeover switches. It is desirable. Thereby, the wiring state of the third calibration board can be easily switched.

  Further, instead of using the various calibration boards described above, a calibration device or a calibration wafer having the same wiring may be used. In particular, the replacement work can be automated by exchanging the calibration device using a handler.

  The semiconductor test apparatus calibration method of the present invention includes a timing test for a semiconductor test apparatus including a driver that performs a signal generation operation synchronized with a clock signal and a comparator that performs a comparison operation synchronized with a strobe signal. In order to perform, it is comprised including the 1st-3rd step. In the first step, a plurality of drivers and a plurality of comparators are output from a plurality of drivers and input to the comparators for each group in a state where m groups are divided so that at least one of them is included in two or more. The phase of the clock signal and the phase of the strobe signal are adjusted by matching the timing at which the generated signal changes with the timing at which the comparison operation is performed by the plurality of comparators. In the second step, relative phase differences between clock signals corresponding to drivers or strobe signals corresponding to comparators are acquired for different groups. In the third step, the phase of the clock signal corresponding to the driver included in each of the plurality of groups and the phase of the strobe signal corresponding to the comparator are adjusted based on the relative phase difference. Costs are eliminated as there is no need for a dedicated reference driver / comparator unit, a probe connected to it, or a dedicated robot to automate the movement and contact of the probe, just to perform timing calibration. Can be significantly reduced. Further, by performing the calibration operation in units of groups, adjustment errors within the groups can be averaged, so that calibration errors caused by variations in measurement results can be reduced.

  Further, it is desirable that a delay element for changing the phase of the signal is inserted in each of the clock signal supply path to the driver and the strobe signal supply path to the comparator. By individually varying the delay amount of each delay element, the respective phases of the clock signal and the strobe signal can be adjusted to arbitrary values, and the phase adjustment of these signals becomes easy.

  In the first step described above, the first calibration board in which the output terminal of the driver and the input terminal of the comparator are connected via a common first short connection point for each of the plurality of groups. It is desirable to be used. In the second step, the output terminal of the driver included in one group and the input terminal of the comparator included in the other group are connected via a common second short connection point. It is desirable to use a calibration board. Since the calibration operation is performed by exchanging the first and second calibration boards, the work contents are compared with the conventional method in which the phases of the clock signal and the strobe signal are individually adjusted using the probe. Simplification is possible.

  In addition, the wiring length of the wiring connecting the driver and the first and second short connection points and the wiring length connecting the comparator and the first and second short connection points are all set to be the same. Is desirable. Thereby, all clock signals and strobe signals can be adjusted under the same conditions, and a calibration operation can be performed by observing the output of the comparator.

  In addition, it is desirable to have a fourth step of replacing the first calibration board with the second calibration board between the first step and the second step described above. The mechanical work is merely replacement of the first calibration board with the second calibration board, and the work time in the entire timing calibration can be greatly reduced.

  The first step described above uses a third calibration board in which the output terminals of the drivers included in each group and the input terminals of the comparators are connected via wirings having the same time length for all groups. In the second step, the output terminals of the drivers included in one group and the input terminals of the comparators included in the other group are connected to each other through wiring having the same time length. As described above, it is desirable to switch the wiring state of the third calibration board. By using the third calibration board capable of switching the wiring content, the replacement work of the calibration board becomes unnecessary, so that the entire work time can be further reduced.

  Further, the above-described third calibration board includes a plurality of changeover switches for switching the wiring state, and the operations of the first and second steps are performed by switching the connection state of these changeover switches. It is desirable. Thereby, the wiring state of the third calibration board can be easily switched.

  Further, instead of using the various calibration boards described above, a calibration device or a calibration wafer having the same wiring may be used. In particular, the replacement work can be automated by exchanging the calibration device using a handler.

  The semiconductor test apparatus calibration method of the present invention includes a timing test for a semiconductor test apparatus including a driver that performs a signal generation operation synchronized with a clock signal and a comparator that performs a comparison operation synchronized with a strobe signal. In order to perform, it is comprised including the 1st-3rd step. In the first step, a strobe signal corresponding to a common comparator is used with a single comparator as a common comparator in a state where m groupings are performed so that at least one of a plurality of drivers and a plurality of comparators is included. As a reference, the phase of the clock signal corresponding to the common driver in the group is adjusted with one driver included in each group as the common driver in the group. In the second step, in each of the m groups, the phase of the strobe signal corresponding to the comparator included in the same group is adjusted with reference to the clock signal corresponding to the common driver in the group. In the third step, in each of the m groups, the phase of the clock signal corresponding to the driver included in the same group is adjusted with reference to the phase of the strobe signal corresponding to an arbitrary comparator.

  Alternatively, the semiconductor test apparatus calibration method according to the present invention performs timing calibration of a semiconductor test apparatus including a driver that performs a signal generation operation synchronized with a clock signal and a comparator that performs a comparison operation synchronized with a strobe signal. In order to perform, it is comprised including the 1st-3rd step. In the first step, a clock signal corresponding to a common driver with a single driver as a common driver in a state where m groupings are performed so that at least one of a plurality of drivers and a plurality of comparators is included. As a reference, the phase of the strobe signal corresponding to the intra-group common comparator is adjusted by using one comparator included in each group as the intra-group common comparator. In the second step, in each of the m groups, the phase of the clock signal corresponding to the driver included in the same group is adjusted with reference to the strobe signal corresponding to the intra-group common comparator. In the third step, in each of the m groups, the phase of the strobe signal corresponding to the comparator included in the same group is adjusted with reference to the phase of the clock signal corresponding to an arbitrary driver.

  Costs are eliminated as there is no need for a dedicated reference driver / comparator unit, a probe connected to it, or a dedicated robot to automate the movement and contact of the probe, just to perform timing calibration. Can be significantly reduced. In addition, the adjustment work in the second and third steps can be performed in parallel for each group, and work efficiency can be improved and work time can be shortened.

  The phase adjustment performed in each of the first to third steps described above includes a timing for performing a comparison operation by the comparator according to the strobe signal, and a timing for changing a signal output from each of the drivers and input to the comparator. It is desirable to change the phase of the clock signal or strobe signal so as to match. By changing the phase of the clock signal or strobe signal while observing the result of the comparison operation by the comparator, it is possible to easily adjust the phase and measure the relative phase difference.

  Further, it is desirable that a delay element for changing the phase of the signal is inserted in each of the clock signal supply path to the driver and the strobe signal supply path to the comparator. By individually varying the delay amount of each delay element, the respective phases of the clock signal and the strobe signal can be adjusted to arbitrary values, and the phase alignment of these signals becomes easy.

  In addition, the first step described above is performed using a first calibration board in which the input terminal of the common comparator and the output terminal of the in-group common driver are connected via a common first short connection point. It is desirable that Alternatively, the first step described above is performed using a first calibration board in which the output terminal of the common driver and the input terminal of the intra-group common comparator are connected via a common first short connection point. It is desirable that In the second and third steps described above, the second calibration in which the output terminal of the driver and the input terminal of the comparator are connected via a common second short connection point for each of the plurality of groups. It is desirable that this be performed using an operation board. Since the calibration operation is performed by exchanging the first and second calibration boards, the work contents are compared with the conventional method in which the phases of the clock signal and the strobe signal are individually adjusted using the probe. Simplification is possible.

  In addition, the wiring length of the wiring connecting the driver and the first and second short connection points and the wiring length connecting the comparator and the first and second short connection points are all set to be the same. Is desirable. Thereby, all clock signals and strobe signals can be adjusted under the same conditions, and a calibration operation can be performed by observing the output of the comparator.

  In addition, it is desirable to have a fourth step of replacing the first calibration board with the second calibration board between the first step and the second step described above. The mechanical work is merely replacement of the first calibration board with the second calibration board, and the work time in the entire timing calibration can be greatly reduced.

  In the first step described above, the input terminal of the common comparator and the output terminal of the in-group common driver included in each of the m groups are connected to each other through wires having the same time length. The third calibration board is used, and the second and third steps are performed through wiring in which the output ends of the drivers included in each group and the input ends of the comparators have the same time length for all groups. It is desirable that the connection is performed by switching the wiring state of the third calibration board so as to be connected. Alternatively, in the first step described above, the output terminal of the common driver and the input terminal of the intra-group common comparator included in each of the m groups are connected via wires having the same time length for all the groups. The third calibration board is used, and the second and third steps are performed through wiring in which the output ends of the drivers included in each group and the input ends of the comparators have the same time length for all groups. It is desirable that the connection is performed by switching the wiring state of the third calibration board so as to be connected. By using the third calibration board capable of switching the wiring content, the replacement work of the calibration board becomes unnecessary, so that the entire work time can be further reduced.

  The above-described third calibration board includes a plurality of changeover switches for switching the wiring state. By switching the connection state of these changeover switches, the first, second, and third steps are switched. It is desirable to perform the operation. Thereby, the wiring state of the third calibration board can be easily switched.

  Further, instead of using the various calibration boards described above, a calibration device or a calibration wafer having the same wiring may be used. In particular, the replacement work can be automated by exchanging the calibration device using a handler.

  The semiconductor test apparatus calibration method of the present invention includes a timing test for a semiconductor test apparatus including a driver that performs a signal generation operation synchronized with a clock signal and a comparator that performs a comparison operation synchronized with a strobe signal. In order to carry out, it is comprised including the 1st and 2nd step. In the first step, the phase of the strobe signal corresponding to each of the plurality of comparators is adjusted with reference to the clock signal corresponding to one driver. In the second step, the phase of the clock signal corresponding to each of the plurality of drivers is adjusted with reference to the one strobe signal for which the phase adjustment has been completed in the first step.

  Alternatively, the semiconductor test apparatus calibration method according to the present invention performs timing calibration of a semiconductor test apparatus including a driver that performs a signal generation operation synchronized with a clock signal and a comparator that performs a comparison operation synchronized with a strobe signal. In order to carry out, it is comprised including the 1st and 2nd step. In the first step, the phase of the clock signal corresponding to each of the plurality of drivers is adjusted with reference to the strobe signal corresponding to one comparator. In the second step, the phase of the strobe signal corresponding to each of the plurality of comparators is adjusted with reference to the one clock signal for which the phase adjustment has been completed in the first step.

  Costs are eliminated as there is no need for a dedicated reference driver / comparator unit, a probe connected to it, or a dedicated robot to automate the movement and contact of the probe, just to perform timing calibration. Can be significantly reduced.

  In addition, the phase adjustment performed in each of the first and second steps described above changes the timing at which the comparison operation is performed by the comparator in accordance with the strobe signal, and the signal output from each of the drivers and input to the comparator. It is desirable to change the phase of the clock signal or strobe signal so that the timing matches. By changing the phase of the clock signal or strobe signal while observing the result of the comparison operation by the comparator, it is possible to easily adjust the phase and measure the relative phase difference.

  Further, it is desirable that a delay element for changing the phase of the signal is inserted in each of the clock signal supply path to the driver and the strobe signal supply path to the comparator. By individually varying the delay amount of each delay element, the respective phases of the clock signal and the strobe signal can be adjusted to arbitrary values, and the phase alignment of these signals becomes easy.

  Further, the first step described above includes a plurality of first calibration boards in which the output terminal of one driver and the input terminals of the plurality of comparators are separately connected via the first short connection point. It is desirable to be used. Alternatively, the first step described above includes a plurality of first calibration boards in which output terminals of a plurality of drivers and input terminals of one comparator are separately connected via a first short connection point. It is desirable to be used. In the second step described above, each of the plurality of drivers corresponds to each of the plurality of comparators, and the second calibration board in which the output terminal of the corresponding driver is connected to the input terminal of the comparator. It is desirable to be performed using. Since the calibration operation is performed by exchanging the first and second calibration boards, the work contents are compared with the conventional method in which the phases of the clock signal and the strobe signal are individually adjusted using the probe. Simplification is possible.

  In addition, the wiring length of the wiring connecting the driver and the first and second short connection points and the wiring length connecting the comparator and the first and second short connection points are all set to be the same. Is desirable. Thereby, all clock signals and strobe signals can be adjusted under the same conditions, and a calibration operation can be performed by observing the output of the comparator.

  Further, instead of using the various calibration boards described above, a calibration device or a calibration wafer having the same wiring may be used. In particular, the replacement work can be automated by exchanging the calibration device using a handler.

  Hereinafter, a semiconductor test apparatus calibration method according to an embodiment to which the present invention is applied will be described in detail.

[First Embodiment]
FIG. 1 is a diagram illustrating an overall configuration of a semiconductor test apparatus that is a target of timing calibration performed in the first embodiment. The semiconductor test apparatus includes a semiconductor test apparatus main body 10 and a workstation (WS) 40 in order to perform a predetermined test on a device under measurement (not shown).

  The workstation 40 controls a whole series of test operations such as a function test and a timing calibration operation, and realizes an interface with the user.

  The semiconductor test apparatus main body 10 performs various tests on the device under measurement by executing a predetermined test program transferred from the workstation 40. In addition, the semiconductor test apparatus main body 10 performs timing calibration by executing a dedicated program transferred from the workstation 40. For this purpose, the semiconductor test apparatus body 10 includes a tester control unit (TP) 12, a timing generator (TG) 14, a pattern generator (PG) 16, a data selector (DS) 18, a format control unit (FC) 20, Pin electronics 22 are provided.

  The tester control unit 12 is connected to each component such as the timing generator 14 via a bus, and executes various test operations on each component by executing a test program transferred from the workstation 40. And control necessary for calibration operation.

  The timing generator 14 sets a basic period of the test operation and generates various timing edges included in the set basic period. The pattern generator 16 generates pattern data to be input to each pin of the device under measurement. The data selector 18 associates various pattern data output from the pattern generator 16 with each pin of the device under measurement that inputs the pattern data. The format control unit 20 performs waveform control on the device under measurement based on the pattern data generated by the pattern generator 16 and selected by the data selector 18 and the timing edge generated by the timing generator 14.

  The pin electronics 22 is used to establish a physical interface with the device under measurement, and is actually measured based on the clock signal CLK and strobe signal STB generated by the waveform control of the format control unit 20. Generates signals that are input to and output from the device. For this purpose, the pin electronics 22 includes n drivers DR1 to DRn and n comparators CP1 to CPn.

  The driver DR1 performs a signal generation operation in synchronization with the clock signal CLK1 output from the format control unit 20, and changes the output signal from a low level to a high level when the clock signal CLK1 rises. Similarly, the drivers DR2 to DRn perform a signal generation operation synchronized with each of the input clock signals CLK2 to CLKn, and change the output signal from the low level to the high level when the corresponding clock signal rises. Let

  In this embodiment (the same applies to other embodiments), the output signal of the driver changes in the same way as the clock signal, that is, the output signal of the driver rises in synchronization with the rising edge of the clock signal. The driver output signal also falls in synchronization with the falling edge of the driver, but conversely, the driver output signal falls in synchronization with the rising edge of the clock signal, and the driver output synchronizes with the falling edge of the clock signal. The signal may rise.

  The comparator CP1 performs a comparison operation in synchronization with the strobe signal STB1 output from the format control unit 20, and determines the logic of the signal input from the corresponding pin of the device under test when the strobe signal STB1 is input. . Similarly, the comparators CP2 to CPn perform comparison operations synchronized with the input strobe signals STB2 to STBn, respectively, and signals input from the corresponding pins of the device under test at the time when the corresponding strobe signals are input. Determine the logic of.

  In addition, when the comparison operation synchronized with the strobe signal is performed by the comparator, the comparison operation by the comparator is performed in synchronization with the rising edge of the strobe signal, and the comparison operation by the comparator is synchronized with the falling edge of the strobe signal. However, in this embodiment (the same applies to the other embodiments), there is no essential difference in relation to the present invention, so either comparison timing may be adopted.

  The driver DR1 and the comparator CP1 described above make one set and correspond to one input / output pin of the device under measurement. Further, the driver DR2 and the comparator CP2 form a set and correspond to different input / output pins. In this way, a set of drivers and comparators are provided corresponding to the input / output pins of the device under measurement.

  Further, a performance board 30 is mounted on the semiconductor test apparatus body 10, and the pin electronics 22 described above is connected to the calibration board 50 </ b> A (or 50 </ b> B) via the performance board 30.

  The calibration boards 50A and 50B are provided with special internal wiring for performing timing calibration, and are different from each other.

  FIG. 2 is a diagram illustrating a wiring state of one calibration board 50A. In FIG. 2, two terminals 1a and 1b are connected in common with a short connection point (device socket end) 1c, and the wiring lengths (time lengths) converted into signal delay times are the same. Is set. The two terminals 2a and 2b are connected in common with the short connection point 2c, and the wiring lengths converted to the signal delay time are set to be the same. Similarly, the two terminals na and nb are connected in common with the short connection point nc, and the wiring lengths converted to the signal delay time are set to be the same. Furthermore, each wiring length mentioned above is set to the same length about all the short connection points.

  FIG. 3 is a diagram illustrating a wiring state of the other calibration board 50B. In FIG. 3, two terminals 1a and nb are connected in common with the short connection point 1c, and the wiring lengths converted to signal delay times are set to be the same. Further, the two terminals 2a and 1b are connected in common with the short connection point 2c, and the wiring lengths converted to signal delay times are set to be the same. Similarly, the two terminals na and 2b are connected in common with the short connection point nc, and the wiring lengths converted to the signal delay time are set to be the same. Furthermore, each wiring length mentioned above is set to the same length about all the short connection points of two types of calibration boards 50A and 50B.

  The semiconductor test apparatus according to the present embodiment has such a configuration. Next, a calibration operation using the same will be described.

  FIG. 4 is a flowchart showing the calibration operation procedure of the present embodiment. After one calibration board 50A is set on the performance board 30 (step 100), the tester control unit 12 sets the phase of the clock signal for each short connection point of the calibration board 50A with reference to the strobe signal. Adjust (step 101).

  In step 101 described above, the level of the output signal when the strobe signal is output (rises) and the comparison operation by the comparator is performed is observed while gradually changing the rising timing of the clock signal, and the output signal of the comparator is observed. The phase of the clock signal is adjusted by obtaining the phase of the clock signal when the level is just inverted.

  FIG. 5 is a diagram showing a state in which a calibration board (CB) 50 </ b> A is set on the semiconductor test apparatus body 10 via the performance board (PB) 30. In FIG. 5, Tx1 to Txn are delay times caused by wiring from the output end of each driver to the terminal of the calibration board 50A, and Ty1 to Tyn are caused by wiring from the terminal of the calibration board 50A to the input end of each comparator. The delay time Ta represents the delay time caused by each wiring in the calibration board 50A. For example, Tx1 to Txn and Ty1 to Tyn are all set to the same value.

  As shown in FIG. 5, a delay element T is provided in a path through which the clock signal is supplied to each of the drivers DR1 to DRn in order to adjust the phase (change timing) of the clock signal. By varying the element constant of each delay element T, the phase of the clock signal for each driver DR1 to DRn can be arbitrarily and independently adjusted. Similarly, a delay element T is provided in the path through which the strobe signal is supplied to each of the comparators CP1 to CPn in order to adjust the phase of the strobe signal. By varying the element constant of each delay element T, the phase (change timing) of the strobe signal for each of the comparators CP1 to CPn can be arbitrarily and independently adjusted.

  In the present embodiment and each of the second and subsequent embodiments, the case where the wiring length from each terminal of the calibration board to the output end of the driver and the input end of the comparator is all the same is described. The wiring lengths may be different and the difference between the wiring lengths may be adjusted by the delay element T described above.

  FIG. 6 is a diagram showing an outline of the operation of adjusting the phase of the clock signal performed in step 101 described above. FIG. 7 is a diagram showing details of the phase adjustment operation of the clock signal shown in FIG. In FIG. 7, “DR”, “short connection point”, and “CP” shown corresponding to each clock signal indicate the timing at which a signal output from the driver corresponding to each clock signal passes or arrives. ing. For example, paying attention to the clock signal CLK1, a signal is output from the driver DR1 corresponding to the clock signal CLK1 at a timing indicated by “DR”. This signal reaches the short connection point (device socket end) at the timing indicated by “short connection point”, and further reaches the comparator CP1 at the timing indicated by “CP”. Note that FIG. 6 focuses on the timing indicated by “CP” in FIG. 7, and other portions are omitted.

  First, the tester control unit 12 pays attention to the short connection point 1c, and fixes the phase of the strobe signal STB1 input to the comparator CP1 (timing for performing the comparison operation) and the phase of the clock signal CLK1 input to the driver DR1. Is adjusted to rise when a signal output from the driver DR1 corresponding to the clock signal CLK1 is input to the comparator CP1 via the short connection point 1c and the terminal 1b. Next, the tester control unit 12 pays attention to the short connection point 2c, and fixes the phase of the strobe signal STB2 input to the comparator CP2 (timing for performing the comparison operation) in the clock signal CLK2 input to the driver DR2. The phase is varied so that the signal output from the driver DR2 corresponding to the clock signal CLK2 is adjusted to rise when it is input to the comparator CP2 via the short connection point 2c and the terminal 2b. As described above, the tester control unit 12 pays attention to each of the short connection points nc, and the phase of the strobe signal STBi input to the comparator CPi (i = 1, 2,..., N) (timing for performing the comparison operation). Is fixed, the phase of the clock signal CLKi input to the driver DRi is varied, and the signal output from the driver DRi corresponding to the clock signal CLKi is output to the comparator CPi via the short connection point ic and the terminal ib. Adjust to stand up when input to.

  When the phase adjustment of the clock signals CLK1 to CLKn corresponding to all the short connection points 1c to nc is completed using one calibration board 50A in this way, the other calibration board 50B is set next. (Step 102). Note that the setting of the calibration boards 50A and 50B in Steps 100 and 102 may be performed manually, or the work may be automated using a dedicated robot or the like.

  FIG. 8 is a diagram illustrating a state in which the calibration board 50 </ b> B is set in the semiconductor test apparatus main body 10.

  Next, the tester control unit 12 acquires the phase difference of the strobe signal by measurement for each short connection point of the calibration board 50B (step 103).

  FIG. 9 is a diagram showing an outline of the strobe signal phase difference obtaining operation performed in step 103. First, the tester control unit 12 pays attention to the short connection point 1c of the calibration board 50B and uses the phase of the clock signal CLK1 input to the driver DR1 as a reference (more precisely, from the driver DR1 corresponding to the clock signal CLK1). The phase difference Tn of the strobe signal STBn input to the comparator CPn is measured based on the timing at which the output signal rises at the input terminal of the comparator CPn. This measurement can be performed by scanning the phase of the strobe signal STBn within a predetermined range with the phase of the clock signal CLK1 fixed. Specifically, the output timing of the strobe signal STBn is fixed in a state where the rising timing of the signal output from the driver DR1 corresponding to the clock signal CLK1 and input to the comparator CPn via the short connection point 1c is fixed. The level is changed little by little until the level of the output signal of the comparator CPn is inverted. The amount of change when the phase of the strobe signal STBn is changed in this way corresponds to the phase difference Tn of the strobe signal STBn to be measured.

  Next, the tester control unit 12 pays attention to the short connection point 2c of the calibration board 50B, and uses the phase of the clock signal CLK2 input to the driver DR2 as a reference, the phase difference T1 of the strobe signal STB1 input to the comparator CP1. Measure. As described above, the tester control unit 12 pays attention to each of the calibration board 50B up to the short connection point nc, and inputs it to each driver DRi (i = 1, 2,..., N) corresponding to the next adjacent group. The phase difference Tj of the strobe signal STBj input to the comparator CPj (j = n, 1, 2,..., N−1) is measured with reference to the phase of the clock signal CLKi.

  In this way, the relative phase difference of all the strobe signals STB1 to STBn is acquired using the other calibration board 50B.

  Next, the tester control unit 12 determines the correction value of the strobe signal using the acquired phase difference between the strobe signals STB1 to STBn (step 104). Specifically, in the phase difference acquisition operation of each strobe signal in step 103, the relative deviation of the phase of the two strobe signals input to the two comparators corresponding to each of the two adjacent short connection points can be found. Therefore, by using the phase of the strobe signal input to the comparator corresponding to a short connection point as a reference, the phase of the strobe signal input to another comparator is matched with the phase of the strobe signal serving as the reference. Necessary correction values can be determined. Thereafter, the tester control unit 12 performs phase correction of the strobe signals STB1 to STBn input to the comparators CP1 to CPn using the determined correction value (step 105).

  FIG. 10 is a diagram showing an outline of the strobe signal correction value determination operation and the correction operation performed in steps 104 and 105. For example, when the phase difference of the strobe signal STB2 when the phase (output timing) of the strobe signal STB1 is used as a reference is T1, the tester control unit 12 shifts the phase of the strobe signal STB2 by T1. The phase of STB2 is matched with the phase of strobe signal STB1. Thereby, the timing of the comparison operation of the comparator CP1 synchronized with the strobe signal STB1 and the timing of the comparison operation of the comparator CP2 synchronized with the strobe signal STB2 can be matched.

  Similarly, when the phase difference of the strobe signal STBn with respect to the phase (output timing) of the strobe signal STB1 is T1 + T2, the tester control unit 12 shifts the strobe signal STBn by T1 + T2, thereby shifting this strobe signal STBn. The phase of the signal STBn is matched with the phase of the strobe signal STB1. In this way, it is possible to match the timings of the comparison operations of all the comparators.

  Next, the tester control unit 12 corrects the phase of the clock signals CLK1 to CLKn input to the drivers DR1 to DRn (step 106). This correction is performed using the correction value of the phase of the strobe signal input to the comparator corresponding to each driver.

  FIG. 11 is a diagram showing an outline of the operation of correcting the phase of the clock signal performed in step 106. First, the tester control unit 12 corrects the phase of the clock signal CLK2 corresponding to the strobe signal STB2 so as to match the phase of the strobe signal STB2 that has been corrected in Step 105. Similarly, the tester control unit 12 corrects each phase up to the corresponding clock signal CLKn so as to match each phase up to the strobe signal STBn. In this way, it is possible to make the timings at which the signals output from the drivers rise in synchronism with the rising edges of the clock signals.

  As described above, in the semiconductor test apparatus according to the present embodiment, the operation of adjusting the phase of the clock signal based on the strobe signal is performed for each socket device end by first using one calibration board 50A. Is called. Next, by using the other calibration board 50B, after the phase difference between two strobe signals at adjacent short connection points is measured, the clock signal and the strobe signal corresponding to one of the short connection points are used as a reference. Thus, phase correction of other strobe signals and clock signals is performed. Therefore, in the calibration operation of the semiconductor test apparatus according to the present embodiment, it is not necessary to contact the probe at each short connection point, and only the calibration boards 50A and 50B are set. The work content can be simplified. In addition, there is no need for a special configuration such as a separate reference driver / comparator unit for calibration operation or a dedicated robot that repeats contact and movement of the probe, and a significant cost reduction can be achieved. Further, since the operation that involves mechanical movement until the calibration operation is completed is only the set of the calibration boards 50A and 50B, the probe movement and contact are repeated as many times as the number of short connection points as in the prior art. Compared to the above, the working time can be greatly reduced.

  In the above-described embodiment, first, one calibration board 50A is used to adjust the phase of the clock signal based on each strobe signal. On the contrary, the phase of each clock signal is adjusted. You may make it adjust the phase of a strobe signal on the basis. Further, after adjusting the phase of the strobe signal using the other calibration board 50B (step 105 in FIG. 4), the phase of the clock signal was adjusted (step 106 in FIG. 4), but this order is changed. Also good.

[Second Embodiment]
In the above-described embodiment, the calibration operation is performed by using the two types of calibration boards 50A and 50B in order. You may make it save the effort of replacement | exchange using a board.

  FIGS. 12 and 13 are diagrams showing the configuration of the calibration board 50C of the second embodiment having the functions of two types of calibration boards 50A and 50B having different wiring contents. A state of being connected via the board 30 is shown. The calibration board 50C shown in these figures includes two changeover switches corresponding to each short connection point.

  Specifically, a changeover switch 1e is provided near the short connection point 1c, and a changeover switch 1d is provided near the terminal 1b corresponding to the comparator CP1, corresponding to the short connection point 1c. By switching the changeover switch 1d, the terminal 1b can be selectively connected to one of the short connection points 1c and 2c. Further, by switching the changeover switch 1e, it is possible to selectively realize a state in which the short connection point 1c is commonly connected to the terminals 1a and 1b and a state in which the short connection point 1c is commonly connected to the terminals 1a and nb. it can. The same applies to the other change-over switches 2d and the like. Note that the wiring length between each of the short connection points 1c to nc and each of the terminals 1a, 1b, etc. is set so that the signal delay times are all equal.

  As shown in FIGS. 12 and 13, the wiring contents of the two types of calibration boards 50A and 50B can be selectively realized by switching each changeover switch 1d and the like. Therefore, the calibration board 50C is used to perform the calibration operation by switching each changeover switch, so that the work of replacing the calibration board becomes unnecessary, and further simplification of work contents, cost reduction, and reduction of work time can be achieved. It becomes possible.

[Third Embodiment]
By the way, in each of the above-described embodiments, the calibration operation is performed by combining one driver and one comparator. However, a plurality of drivers and comparators are combined to form a group, and each group is a unit. A calibration operation may be performed as follows.

  FIG. 14 is a diagram showing a wiring state of one calibration board 150A used for performing the calibration operation in the present embodiment. The device socket ends 1g to mg as m short connection points shown in FIG. 14 correspond to the short connection points 1c to nc of the calibration board 50A shown in FIG. The short connection point is drawn in the calibration board 150A for convenience of illustration. However, in the calibration board 50A shown in FIG. 2 and the calibration board 150A shown in FIG. 14, focusing on only the calibration operation, each short connection point does not necessarily have to be exposed to the outside. As illustrated in FIG. 14, each short connection point 1 g or the like may be buried in the calibration board.

  In FIG. 14, a predetermined number (for example, three) of n terminals 1a to na to which n drivers DR1 to DRn are respectively connected together form m groups. The first group (group 1) includes terminals 1a to 3a corresponding to the drivers DR1 to DR3, respectively, and these are commonly connected to one short connection point 1g. The second group (group 2) includes terminals 4a to 6a corresponding to the drivers DR4 to DR6, respectively, and these are commonly connected to one short connection point 2g. The same applies to the other terminals, and the m-th group (group m) includes terminals (n-2) a to na corresponding to the drivers DRn-2 to DRn, respectively. Commonly connected to the connection point mg.

  Similarly, a predetermined number of n terminals 1b to nb to which n comparators CP1 to CPn are connected form a group of m. The first group includes terminals 1b to 3b corresponding to the comparators CP1 to CP3, respectively, and these are commonly connected to one short connection point 1g. The second group includes terminals 4b to 6b corresponding to the comparators CP4 to CP6, respectively, and these are commonly connected to one short connection point 2g. The same applies to the other terminals, and the m-th group (group m) includes terminals (n-2) b to nb corresponding to the comparators CPn-2 to CPn, respectively. Commonly connected to the connection point mg.

  In this way, a total of six terminals corresponding to the three drivers and the three comparators are connected to each of the short connection points 1g to mg. The wiring connecting each terminal and the short connection point is set so that all the wiring lengths (time lengths) converted into signal delay times are the same.

  FIG. 15 is a diagram showing a wiring state of the other calibration board 150B used for performing the calibration operation in the present embodiment.

  The calibration board 150B shown in FIG. 15 differs from the calibration board 150A shown in FIG. 14 only in the correspondence between each of the short connection points 1g to mg and the terminals 1a to na connected to each driver. ing. Specifically, the terminals 1a to 3a corresponding to the drivers DR1 to DR3 included in the first group are commonly connected to the short connection point mg included in the mth group. The terminals 4a to 6a corresponding to the drivers DR4 to DR6 included in the second group are commonly connected to the short connection point 1g. Thus, the correspondence between the terminals corresponding to each driver and the short connection point is set so as to be shifted by one group. Also in this calibration board 150B, the wiring connecting each terminal and the short connection point is set so that all wiring lengths (time lengths) converted into signal delay times are the same. That is, the wiring lengths of the wirings connecting the terminals included in the two calibration boards 150A and 150B and the short connection points are all set to the same length.

  The calibration boards 150A and 150B of the present embodiment have such a configuration. Next, a calibration operation using these will be described. In addition to the calibration boards 150A and 150B, the semiconductor test apparatus main body 10, the performance board 30, the workstation 40, and the like described in the first embodiment are used.

  FIG. 16 is a diagram illustrating an initial state of the clock signal and the strobe signal in the semiconductor test apparatus 10 before performing the calibration operation. In FIG. 16, attention is paid to the timing at which the signals output from the drivers reach the comparators, as in FIG. 6 used in the first embodiment. As shown in FIG. 16, in the initial state, the timing at which the signals output from the drivers corresponding to the clock signals CLK1 to CLKn rise and input to the comparators rise, and the strobe signals STB1 to STBn are input to the comparators. Timing is not consistent.

  FIG. 17 is a flowchart showing the calibration operation procedure of the present embodiment. After one calibration board 150A is set on the performance board 30 (step 200), the tester control unit 12 sets each strobe signal for each group of the calibration board 150A with reference to an arbitrary clock signal. The phase is adjusted (step 201).

  As described above, in this specification, when adjusting the phase of the clock signal or the strobe signal, attention is paid to the operation of the comparator when the signal generated by the driver according to the clock signal is input to the comparator. ing. Therefore, adjusting the phase of each strobe signal with reference to an arbitrary clock signal in step 201 means that the clock signal is input to an arbitrary driver of each group, and the signal output from this driver has a short connection point. When the signal is input to each comparator in the same group via the same timing, the timing at which the comparison operation is performed by the comparator coincides with the timing at which the input signal rises.

  FIG. 18 is a diagram illustrating a driver and a comparator that perform input / output of signals corresponding to step 201. In FIG. 18, a driver or a comparator whose operation is enabled is hatched. As shown in FIG. 18, for example, in the group 1, the operation of the driver DR1 to which the clock signal CLK1 is input becomes valid, and the signal output from the driver DR1 is input via the short connection point 1g. Each operation of the two comparators CP1 to CP3 becomes effective. The same applies to other groups, and a detailed description thereof will be omitted.

  FIG. 19 is a diagram showing an outline of the phase adjustment operation of the strobe signal performed in step 201. First, the tester control unit 12 pays attention to the group 1 and inputs to each of the three comparators CP1 to CP3 through a state where the phase of the clock signal CLK1 input to the driver DR1 is fixed, that is, via the short connection point 1g. In a state in which the timing at which the generated signal rises is fixed, each phase of the strobe signals STB1 to STB3 is varied to search for a position where the output level of each of the comparators CP1 to CP3 is inverted. The phases of the strobe signals STB1 to STB3 are adjusted. Next, the tester control unit 12 pays attention to the group 2 in a state where the phase of the clock signal CLK4 input to the driver DR4 is fixed, that is, to each of the three comparators CP4 to CP6 via the short connection point 2g. With the timing at which the input signal rises fixed, the phase of the strobe signals STB4 to STB6 is varied to search for a position where the output level of each of the comparators CP4 to CP6 is inverted, and the clock signal CLK4 is used as a reference. The phases of the strobe signals STB4 to STB6 are adjusted. In this way, the tester control unit 12 pays attention to each group, and with the phase of the clock signal input to an arbitrary driver fixed, the phase of the strobe signal is varied to change the output level of each of the three comparators. By searching for the position where the signal is inverted, the phase of each strobe signal is adjusted with reference to the clock signal.

  In this way, the phase adjustment of the strobe signal is performed for each group. However, the phase of the clock signal corresponding to each group used for this phase adjustment (the timing at which the signal corresponding to each clock signal rises at the input end of each comparator) does not match each other. The phases of the different strobe signals do not match each other. Further, the order of the groups for performing the phase adjustment of the strobe signal is not necessarily performed in order from the group 1, and may be performed in an arbitrary order or in parallel.

  Next, the tester control unit 12 adjusts the phase of each clock signal for each group of the calibration board 150A with reference to an arbitrary strobe signal (step 202). Here, adjusting the phase of each clock signal based on an arbitrary strobe signal means that the phase of the signal output from each driver rises with the phase of the strobe signal input to one of the comparators fixed. This is nothing but adjusting the phase of each clock signal so that the timing coincides with the timing of the comparison operation performed by this comparator.

  FIG. 20 is a diagram illustrating a driver and a comparator that perform input / output of signals corresponding to step 202. As shown in FIG. 20, for example, in group 1, the operations of the three drivers DR1 to DR3 are enabled, and the output signals of these drivers DR1 to DR3 are selectively input via the short connection point 1g. The operation of the comparator CP1 becomes effective. The same applies to other groups, and a detailed description thereof will be omitted.

  FIG. 21 is a diagram showing an outline of the phase adjustment operation of the clock signal performed in step 202. First, the tester control unit 12 pays attention to the group 1 from the driver DR2 in a state where the phase of the strobe signal STB1 input to the comparator CP1 is fixed, that is, in a state where the timing of the comparison operation performed by the comparator CP1 is fixed. The phase of the clock signal CLK2 is adjusted so that the timing at which the signal output and input to the comparator CP1 rises coincides with the comparison timing of the comparator CP1. When the phase adjustment corresponding to the driver DR2 is completed, the phase adjustment of the clock signal CLK3 is similarly performed for the driver DR3. Next, the tester control unit 12 pays attention to the group 2 in a state where the phase of the strobe signal STB4 input to the comparator CP4 is fixed, that is, in a state where the timing of the comparison operation performed by the comparator CP4 is fixed. The phase of the clock signal CLK5 is adjusted so that the timing at which the signal output from the input to the comparator CP4 rises coincides with the comparison timing of the comparator CP4. When the phase adjustment corresponding to the driver DR5 is completed, the phase adjustment of the clock signal CLK6 is similarly performed for the driver DR6. As described above, the tester control unit 12 pays attention to each group and changes the phase of the clock signal input to each driver while fixing the phase of the strobe signal input to an arbitrary comparator. The phase of each clock signal is adjusted by making the timing at which the respective outputs rise coincide with the timing at which the comparison operation is performed by the comparator.

  In this way, the phase of the clock signal is adjusted for each group. However, since the phases of the strobe signals of each group used for this phase adjustment do not match each other, at this stage, the phases of the clock signals of different groups do not match each other. Further, the order of the groups for performing the phase adjustment of the strobe signal is not necessarily performed in order from the group 1, and may be performed in an arbitrary order or in parallel.

  As described above, when the operation of adjusting the phases of the clock signal and the strobe signal corresponding to all the drivers and comparators included in each group is completed for each group using one calibration board 150A, One calibration board 150B is set (step 203). Note that the setting of the calibration boards 150A and 150B in Steps 200 and 203 can be performed manually, or the work can be automated using a dedicated robot or the like.

  Next, the tester control unit 12 acquires, for each group, the phase difference of each strobe signal corresponding to the comparator included in the group by measurement with reference to the clock signal corresponding to an arbitrary driver (step 204). ). Thereby, the phase difference of the strobe signal between each group is obtained.

  FIG. 22 is a diagram illustrating a driver and a comparator that perform input / output of signals corresponding to step 204. As shown in FIG. 22, for example, in group 1, the operations of the three comparators CP1 to CP3 are enabled, and in order to measure the phase differences of the strobe signals STB1 to STB3 corresponding to these three comparators CP1 to CP3, 2 is activated. The same applies to other groups, and a detailed description thereof will be omitted.

  FIG. 23 is a diagram showing an outline of the phase difference measurement operation of the strobe signal performed in step 204. First, the tester control unit 12 measures the phase difference T1 between the strobe signals STB1 to STB3 corresponding to the comparators CP1 to CP3 included in the group 1 with reference to the clock signal CLK4 corresponding to the driver DR4 included in the group 2. To do. Specifically, the clock signal corresponding to the driver DR4 in a state where the phases of the strobe signals STB1 to STB3 input to the comparators CP1 to CP3 are fixed, that is, the timing of the comparison operation of the three comparators CP1 to CP3 is fixed. By changing the phase of CLK4 and searching for a position where the outputs of the comparators CP1 to CP3 are inverted, the amount of change in the phase of the clock signal CLK4 is measured as the phase difference T1. Next, the tester control unit 12 measures the phase difference between the strobe signals STB4 to STB6 corresponding to the comparators CP4 to CP6 included in the group 2 with reference to the clock signal CLK7 corresponding to the driver DR7 included in the group 3. To do. As described above, the tester control unit 12 measures the phase difference of the strobe signals corresponding to the comparators included in each group with reference to the clock signals corresponding to the drivers included in different groups. Thereby, it is possible to know the phase shift of the strobe signal between the groups.

  In the above description, the phase of the clock signal is varied, but conversely, the phase of the strobe signal may be varied while the phase of the clock signal is fixed. Further, the phases of the strobe signals corresponding to the comparators included in each group should be matched by the phase adjustment in step 201 described above, but there may be variations in actual measurement. Therefore, it is desirable to obtain the averaged phase difference for each group by averaging the phase difference values measured for each of the three strobe signals for each group. Alternatively, the phase difference of each strobe signal may be obtained and averaged based on a clock signal corresponding to another driver in the same group. For example, the clock signals CLK5 and CLK6 may be used when measuring the phase difference T1 shown in FIG. By averaging the measurement results in this way, it is possible to reduce calibration errors caused by variations in the measurement results, and improve measurement accuracy by making the measurement errors uniform in the measurement work performed after the calibration operation. Is possible.

  Next, the correction value of each strobe signal is determined using the acquired phase difference of the strobe signal between each group (step 205). Specifically, in the phase difference acquisition operation of the strobe signal between each group in step 204, the relative phase difference between the two adjacent groups is known, so the phase of the strobe signal corresponding to one group As a reference, it is possible to determine a correction value necessary for making the phase of the strobe signal corresponding to the other group coincide with the phase of the reference strobe signal.

  Thereafter, the tester control unit 12 corrects the phase of the strobe signal corresponding to each group using the determined correction value (step 206).

  FIG. 24 is a diagram showing an outline of the phase correction of the strobe signal performed in step 206. For example, the tester control unit 12 sets the phases of the strobe signals STB4 to STB6 corresponding to the comparators CP4 to CP6 included in the group 2 to the phases of the strobe signals STB1 to STB3 corresponding to the comparators CP1 to CP3 included in the group 1, respectively. By correcting only the correction value T1 obtained in step 206, the phases of these strobe signals STB1 to STB6 are matched. In this way, the tester control unit 12 can match the phases of all the strobe signals by correcting the phase of the strobe signals corresponding to the comparators of each group using the correction value obtained in step 206.

  Next, the tester control unit 12 corrects the phase of the clock signals CLK1 to CLKn input to the drivers DR1 to DRn (step 207). This correction is performed based on the phase of the strobe signal corresponding to an arbitrary comparator in each group.

  FIG. 25 is a diagram illustrating a driver and a comparator that perform input / output of signals corresponding to step 207. As shown in FIG. 25, for example, in group 1, the operations of the three drivers DR1 to DR3 are enabled, and in order to perform phase correction of the clock signals CLK1 to CLK3 corresponding to these three drivers DR1 to DR3, the group m The operation of the comparator CPn-2 included in is enabled. The same applies to other groups, and a detailed description thereof will be omitted.

  FIG. 26 is a diagram showing an outline of the clock signal correction operation performed in step 207. For example, the tester control unit 12 performs phase correction of the clock signals CLK4 to CLK6 corresponding to each of the three drivers DR4 to DR6 included in the group 2 with reference to the strobe signal corresponding to the comparator CP1 in the group 1. In this way, the tester control unit 12 performs phase correction on the basis of the strobe signals corresponding to arbitrary comparators included in different groups, with respect to the phases of the clock signals corresponding to the three drivers included in each group. As a result, the phases of all the clock signals and the strobe signals coincide.

  As described above, in the semiconductor test apparatus according to the present embodiment using the calibration boards 150A and 150B, the clock signal and the strobe signal are adjusted for each group by first using one calibration board 150A. . Next, by using the other calibration board 150B, the phase difference of the strobe signal between the groups is measured, and the phase difference of the strobe signal and the phase difference of the clock signal between the groups based on the measured phase difference. A phase correction operation is performed to eliminate. Therefore, in the calibration operation of the semiconductor test apparatus of this embodiment, it is not necessary to contact the probe for each device socket end, and only the calibration boards 150A and 150B are set. The work content can be simplified. In addition, there is no need for a special configuration such as a reference driver / comparator unit or a dedicated robot that repeats contact and movement of the probe for the calibration operation, and a significant cost reduction can be achieved. In addition, since the operation with mechanical movement until the calibration operation is completed is only the setting of the calibration boards 150A and 150B, the movement and contact of the probe is repeated as many times as the number of the device socket ends as in the past. Compared to the above, the working time can be greatly reduced. Furthermore, by dividing the drivers and comparators into multiple groups and using phase difference data measured for each group, it is possible to reduce calibration errors caused by variations in measurement results. The measurement accuracy can be improved by making the measurement error uniform in the actual measurement work.

  In the embodiment described above, in steps 201 and 202 shown in FIG. 17, the phase of each strobe signal is first adjusted based on an arbitrary clock signal, and then the phase of each clock signal is adjusted. However, first, the phase of each clock signal may be adjusted based on an arbitrary strobe signal, and then the phase of each strobe signal may be adjusted.

  In step 204 shown in FIG. 17, the phase difference of each strobe signal is acquired with reference to an arbitrary clock signal. However, the phase difference of each clock signal is acquired with reference to an arbitrary strobe signal. You may do it.

  Further, after adjusting the phase of the strobe signal using the calibration board 150B (step 206 in FIG. 17), the phase of the clock signal is adjusted (step 207 in FIG. 17), but this order may be changed. .

[Fourth Embodiment]
In the third embodiment described above, the calibration operation is performed by using the two types of calibration boards 150A and 150B in order, but one type having the functions of these two types of calibration boards 150A and 150B. The calibration board may be used to save the labor of replacement.

  27 and 28 are diagrams illustrating a configuration of a calibration board 150C according to the fourth embodiment having the functions of two types of calibration boards 150A and 150B having different wiring contents. The calibration board 150C shown in these figures includes two changeover switches for each group.

  Specifically, the changeover switch 1j is connected in common to the input terminals of the three comparators CP1 to CP3 in the vicinity of the terminal 1f commonly connected to the output terminals of the three drivers DR1 to DR3 corresponding to the group 1. A selector switch 1k is provided in the vicinity of the terminal 1h. Similarly, group 2 is provided with two changeover switches 2j, 2k,..., Group m is provided with changeover switches mj, mk.

  By switching the changeover switch 1j, the output terminals of the three drivers DR1 to DR3 corresponding to the group 1 are connected to the input terminal sides of the three comparators CP1 to CP3 corresponding to the same group 1, and the three corresponding to the group m. The comparators CPn-2 to CPn can be selectively connected to any one of the input end sides. The same applies to the other changeover switches, and two connection states can be selectively realized. Note that the wiring length of the wiring connecting the output terminal of each driver and the input terminal of each comparator is set so that all signal delay times are equal regardless of the state of each changeover switch.

  As shown in FIGS. 27 and 28, the wiring contents of the two types of calibration boards 150A and 150B can be selectively realized by switching the selector switches 1j and 1k. Therefore, the calibration board 150C is used to perform the calibration operation by switching each changeover switch, thereby eliminating the need for replacing the calibration board, further simplifying the work content, reducing costs, and reducing the work time. It becomes possible.

[Fifth Embodiment]
Next, a calibration method for the semiconductor test apparatus according to the fifth embodiment using a calibration board having different wiring contents from those of the above-described embodiments will be described.

  FIG. 29 is a diagram showing a wiring state of one calibration board 250A. Note that the short connection point (device socket end) e shown in FIG. 29 is drawn in the calibration board 250A for convenience of illustration.

  In FIG. 29, n terminals 1a to na to which n drivers DR1 to DRn are respectively connected together form a predetermined number (for example, 3) of m terminals as a group. The first group (group 1) includes terminals 1a to 3a corresponding to the drivers DR1 to DR3, respectively, and only the terminal 1a is commonly connected to the short connection point e. The second group (group 2) includes terminals 4a to 6a corresponding to the drivers DR4 to DR6, respectively, and only the terminal 4a is commonly connected to the short connection point e. The same applies to the other terminals, and the m-th group (group m) includes terminals (n-2) a to na corresponding to the drivers DRn-2 to DRn, respectively. n-2) Only a is commonly connected to the short connection point e.

  Similarly, a predetermined number of n terminals 1b to nb to which n comparators CP1 to CPn are connected form a group of m. The first group includes terminals 1b to 3b corresponding to the comparators CP1 to CP3, respectively, and only the terminal 1b is connected to the short connection point e. The second group includes terminals 4b to 6b corresponding to the comparators CP4 to CP6, respectively. The same applies to the other terminals, and the mth group (group m) includes terminals (n-2) b to nb corresponding to the comparators CPn-2 to CPn, respectively.

  Thus, the only short connection point e provided on the calibration board 250A is a terminal corresponding to one of the three drivers included in each group (this driver is referred to as “common driver in group”). And a terminal corresponding to one of the three comparators included in group 1 (this comparator is referred to as a “common comparator”). The wiring connecting each terminal and the short connection point e is set so that the wiring lengths (time lengths) converted into signal delay times are all the same.

  FIG. 30 is a diagram illustrating a wiring state of the other calibration board 250B. Similarly to the short connection point e shown in FIG. 29, m short connection points 1g to mg shown in FIG. 30 are drawn in the calibration board 250B for convenience of illustration. However, since each short connection point does not necessarily have to be exposed to the outside, each short connection point 1g or the like may be buried in the calibration board as shown in FIG. The other calibration board 250B shown in FIG. 30 has the same wiring as the calibration board 150A shown in FIG. 14, and the description of the wiring state is omitted.

  The calibration boards 250A and 250B of the present embodiment have such a configuration, and a calibration operation using them will now be described. It is assumed that the clock signal and the strobe signal in the semiconductor test apparatus main body 10 before the calibration operation are in the initial state shown in FIG. 16, for example.

  FIG. 31 is a flowchart showing the calibration operation procedure of the present embodiment. After one calibration board 250A is set on the performance board 30 (step 300), the tester control unit 12 is included in each group based on the strobe signal STB1 corresponding to the comparator CP1 of the calibration board 250A. The phase of each clock signal CLK1, CLK4,..., CLKn-2 corresponding to one driver (common driver in group) DR1, DR4,..., DRn-2 is adjusted (step 301).

  In step 301 described above, since it is necessary to adjust the phase of the clock signal CLK1 or the like based on the strobe signal STB1, the comparator when the strobe signal STB1 is output (rises) and the comparison operation by the comparator CP1 is performed. The level of the output signal of CP1 is observed while gradually changing the rising timing of the clock signal CLK1, etc., and the phase of the clock signal CLK1 when the level of the output signal of the comparator CP1 is just inverted is obtained. Phase adjustment of CLK1 and the like is performed. This operation is sequentially performed for each of the clock signals CLK1, CLK4,.

  FIG. 32 is a diagram illustrating a driver and a comparator that perform input / output of signals corresponding to step 301. In FIG. 32, the driver or the comparator whose operation is valid is hatched. As shown in FIG. 32, in the group 1, the operation of the driver DR1 to which the clock signal CLK1 is input becomes valid, and the signal output from the driver DR1 is input via the short connection point e. Is enabled. In other groups, the operation of one driver to which a clock signal is input is valid. For example, in the group 2, the operation of the driver DR4 is enabled, and in the group m, the operation of the driver DRn-2 is enabled.

  FIG. 33 is a diagram showing an outline of the phase adjustment operation of the clock signal performed in step 301. First, the tester control unit 12 pays attention to the driver DR1 of the group 1 in a state where the phase of the strobe signal STB1 input to the comparator CP1 is fixed, that is, in a state where the timing for performing the comparison operation by the comparator CP1 is fixed. The phase of the clock signal CLK1 is adjusted by changing the phase of the signal CLK1 and searching for a position where the output level of the comparator CP1 is inverted. Next, the tester control unit 12 pays attention to the driver DR4 of the group 2 and changes the phase of the clock signal CLK4 in a state where the phase of the strobe signal STB1 input to the comparator CP1 is fixed, and the output level of the comparator CP1. The phase of the clock signal CLK4 is adjusted by searching for the position where the signal is inverted. As described above, the tester control unit 12 pays attention to one driver included in each group, and fixes the phase of the strobe signal STB1 input to the comparator CP1 and the phase of the clock signal input to each driver. The phase of each clock signal is adjusted by searching for the position where the level of the output of the comparator CP1 is varied and is inverted.

  In this way, the operation of adjusting the phase of one clock signal for each group with reference to the common strobe signal STB1 is performed. Note that the order of the groups for adjusting the phase of the clock signal is not necessarily the order from the group 1, and may be performed in any order.

  In this way, using one calibration board 250A, for each group, the clock signal input to one common driver included in each group is based on the strobe signal STB1 input to the common comparator CP1. When the adjustment operation is completed, the other calibration board 250B is set (step 302). Note that the setting of the calibration boards 250A and 250B in Steps 300 and 302 can be performed manually, or the work can be automated using a dedicated robot or the like.

  Next, the tester control unit 12 adjusts the phase of each strobe signal for each group of the calibration board 250B with reference to the clock signal whose phase adjustment has been completed (step 303).

  FIG. 34 is a diagram illustrating a driver and a comparator that perform input / output of signals corresponding to step 303. As shown in FIG. 34, in group 1, the operation of the driver DR1 to which the clock signal CLK1 is input becomes effective, and two comparators to which the signal output from the driver DR1 is input via the short connection point 1g Each operation of CP2 and CP3 becomes effective. In the group 2, the operation of the driver DR4 to which the clock signal CLK4 is input becomes effective, and each of the three comparators CP4 to CP6 to which the signal output from the driver DR4 is input via the short connection point 2g. The operation is enabled. The other groups are basically the same as those in group 2 and will not be described in detail.

  FIG. 35 is a diagram showing an outline of the phase adjustment operation of the strobe signal performed in step 303. First, the tester control unit 12 pays attention to the group 1, in a state where the phase of the clock signal CLK1 input to the driver DR1 is fixed, that is, input to each of the two comparators CP2 and CP3 via the short connection point 1g. In a state where the timing at which the generated signal rises is fixed, the phase of the strobe signals STB2 and STB3 is varied to find the position where the output level of each of the comparators CP2 and CP3 is inverted. The phases of the strobe signals STB2 and STB3 are adjusted. Next, the tester control unit 12 pays attention to the group 2 in a state where the phase of the clock signal CLK4 input to the driver DR4 is fixed, that is, to each of the three comparators CP4 to CP6 via the short connection point 2g. With the timing at which the input signal rises fixed, the phase of the strobe signals STB4 to STB6 is varied to search for a position where the output level of each of the comparators CP4 to CP6 is inverted, thereby making the clock signal CLK4 a reference. The phases of the strobe signals STB4 to STB6 are matched. For groups 3 to m, as in group 2, the tester control unit 12 changes the phase of the strobe signal for each group while changing the phase of the one clock signal whose phase adjustment is completed. By searching for a position where the output level of each comparator is inverted, the phase of each strobe signal is matched based on one clock signal.

  In this way, the phase adjustment of the strobe signal is performed for each group. Note that the order of the groups for adjusting the phase of the strobe signal is not necessarily the order from the group 1, and may be performed in an arbitrary order or in parallel.

  Next, the tester control unit 12 adjusts the phase of each clock signal for each group with reference to an arbitrary strobe signal (step 304).

  FIG. 36 is a diagram illustrating a driver and a comparator that perform input / output of signals corresponding to step 304. As shown in FIG. 36, for example, the operations of the drivers DR2 and DR3 to which the two clock signals CLK2 and CLK3 that have not been phase-matched in the group 1 are input become valid, and the outputs from the drivers DR2 and DR3 are output. The operation of the comparator CP1 to which the signal to be input is input via the short connection point 1g becomes effective. The same applies to other groups, and a detailed description thereof will be omitted.

  FIG. 37 is a diagram showing an outline of the phase adjustment operation of the clock signal performed in step 304. First, the tester control unit 12 pays attention to the group 1 from the driver DR2 in a state where the phase of the strobe signal STB1 input to the comparator CP1 is fixed, that is, in a state where the timing of the comparison operation performed by the comparator CP1 is fixed. The phase of the clock signal CLK2 is adjusted so that the timing at which the output signal rises coincides with the comparison timing of the comparator CP1. When the phase adjustment corresponding to the driver DR2 is completed, the phase adjustment of the clock signal CLK3 is similarly performed for the driver DR3. Next, the tester control unit 12 pays attention to the group 2 in a state where the phase of the strobe signal STB4 input to the comparator CP4 is fixed, that is, in a state where the timing of the comparison operation performed by the comparator CP4 is fixed. The phase of the clock signal CLK5 is adjusted so that the timing at which the signal output from the signal rises matches the comparison timing of the comparator CP4. When the phase adjustment corresponding to the driver DR5 is completed, the phase adjustment of the clock signal CLK6 is similarly performed for the driver DR6. In this way, the tester control unit 12 focuses on each group and adjusts the phase of the clock signal input to each driver by changing the phase of the strobe signal input to an arbitrary comparator. The phase of each clock signal is adjusted by matching the timing at which the output of each of the two drivers that are not finished coincides with the timing at which the comparison operation is performed by the comparator.

  In the above description, in group 1, the comparator CP1 is a common comparator, but any of the other comparators CP2 and CP3 may be a common comparator. The same applies to the other groups.

  In this way, a series of calibration operations for adjusting the phases of all clock signals and strobe signals is completed.

  As described above, in the semiconductor test apparatus according to the present embodiment, by first using one calibration board 250A, the phase of the clock signal input to one common driver in each group is changed to the common comparator CP1. The adjustment operation is performed with reference to the strobe signal STB1 input to. Next, by using the other calibration board 250B, the phase adjustment of each strobe signal is performed for each group with reference to the clock signal for which the phase adjustment has been completed, and then any strobe for which the phase adjustment has been completed is performed. Using the signal as a reference, the phase adjustment of the remaining clock signals that have not been completed in phase adjustment is performed. Therefore, in the calibration operation of the semiconductor test apparatus of this embodiment, it is not necessary to contact the probe for each device socket end, and only the calibration boards 250A and 250B are set. The work content can be simplified. In addition, there is no need for a special configuration such as a separate reference driver / comparator unit for calibration operation or a dedicated robot that repeats contact and movement of the probe, and a significant cost reduction can be achieved. Furthermore, since the operation that involves mechanical movement until the calibration operation is completed is only the set of calibration boards 250A and 250B, the movement and contact of the probe is repeated as many times as the number of device socket ends as in the prior art. Compared to the above, the working time can be greatly reduced.

[Sixth Embodiment]
In the fifth embodiment described above, the calibration board 250A in which m drivers DR1, DR4,..., DRn-2 belonging to each group and one comparator CP1 are connected to the short connection point e is used. Further, as shown in FIG. 38, one driver (common driver) DR1 and m number of comparators (common comparators in groups) CP1, CP4,..., CPn-2 belonging to each group are connected to the short connection point e. A calibration board 250C may be used.

  FIG. 39 is a flowchart showing a calibration operation procedure of the present embodiment performed by combining the calibration board 250C shown in FIG. 38 and the calibration board 250B shown in FIG. After one calibration board 250C is set on the performance board 30 (step 400), the tester control unit 12 assigns each group to each group based on the phase of the clock signal CLK1 corresponding to the driver DR1 of the calibration board 250C. The phase of each strobe signal STB1, STB4,..., STBn-2 corresponding to one included comparator CP1, CP4,..., CPn-2 is adjusted (step 401).

  In this way, using one calibration board 250C, with respect to the clock signal CLK1 input to the common driver DR1 for each group, the strobe signal input to the common comparator in one group included in each group. When the operation for adjusting the phase is completed, the other calibration board 250B is set (step 402).

  Next, the tester control unit 12 adjusts the phase of each clock signal for each group of the calibration board 250B with reference to the strobe signal for which phase adjustment has been completed (step 403). Further, the tester control unit 12 adjusts the phase of each strobe signal for each group with reference to an arbitrary clock signal (step 404). In this way, a series of calibration operations for adjusting the phases of all clock signals and strobe signals is completed.

[Seventh Embodiment]
In the fifth and sixth embodiments described above, the calibration operation is performed by using two types of calibration boards in order, but one type of calibration having the functions of these two types of calibration boards. You may make it save the effort of replacement | exchange using a board.

  FIGS. 40 and 41 are diagrams showing a configuration of a calibration board 250D of the seventh embodiment having the functions of two types of calibration boards 250A and 250B having different wiring contents. The calibration board 250D shown in these drawings includes two changeover switches corresponding to the group 1, and one changeover switch corresponding to each of the other groups.

  Specifically, the changeover switch 1j connected to each output end side of the three drivers DR1 to DR3 and the changeover switch connected to each input end side of the three comparators CP1 to CP3 so as to correspond to the group 1 1k is provided. Further, a changeover switch 2j connected to each output end side of the three drivers DR4 to DR6 is provided so as to correspond to the group 2. Similarly, a changeover switch connected to each output terminal side of the three drivers is provided so as to correspond to each of the other groups. By switching the connection state of the changeover switches 1j to mj, 1k provided in the calibration board 250D, the same connection state (FIG. 40) as that of one calibration board 250A shown in FIG. 29 and the other connection state shown in FIG. The same connection state as that of the calibration board 250B (FIG. 41) can be selectively realized. Accordingly, the calibration board 250D is used to perform the calibration operation by switching each changeover switch, thereby eliminating the need for replacing the calibration board, further simplifying the work content, reducing costs, and reducing the work time. It becomes possible.

  42 and 43 are diagrams showing a configuration of a calibration board 250E according to a modified example of the present embodiment having the functions of two types of calibration boards 250C and 250B having different wiring contents. The calibration board 250E shown in these figures includes two changeover switches corresponding to the group 1, and one changeover switch corresponding to each of the other groups.

  Specifically, the changeover switch 1j connected to each output end side of the three drivers DR1 to DR3 and the changeover switch connected to each input end side of the three comparators CP1 to CP3 so as to correspond to the group 1 1k is provided. Further, a changeover switch 2k connected to each input end side of the three comparators CP4 to CP6 is provided so as to correspond to the group 2. Similarly, a changeover switch connected to each input end side of the three comparators is provided so as to correspond to each of the other groups. By switching the connection state of the changeover switches 1j and 1k to mk provided in the calibration board 250E, the same connection state (FIG. 42) as that of one calibration board 250C shown in FIG. 38 and the other connection state shown in FIG. The same connection state as that of the calibration board 250B (FIG. 43) can be selectively realized. Accordingly, the calibration board 250E is used to switch each changeover switch to perform the calibration operation, thereby eliminating the need for replacing the calibration board, further simplifying the work contents, reducing costs, and reducing the work time. It becomes possible.

[Eighth Embodiment]
Next, a calibration method of the semiconductor test apparatus according to the eighth embodiment using another calibration board will be described.

  44 to 48 are diagrams showing wiring states of a calibration board used in the calibration method of the present embodiment. Note that the wiring lengths of the wirings connecting the short connection points 1p, 1q, etc. and the terminals 1a, 1b, etc. shown in these drawings are all set to be the same.

  FIG. 44 is a diagram illustrating a wiring state of the calibration board 350A-1 according to the present embodiment. In the calibration board 350A-1, only the terminal 1a is connected to the short connection point 1p among the n terminals 1a to na to which each of the n drivers DR1 to DRn is connected. Further, only the terminal 1b among the n terminals 1b to nb to which each of the n comparators CP1 to CPn is connected is connected to the short connection point 1p. That is, by using this calibration board 350A-1, the signal output from the driver DR1 is input to the comparator CP1 via the short connection point 1p.

  FIG. 45 is a diagram showing a wiring state of another calibration board 350A-2 of the present embodiment. In the calibration board 350A-2, only the terminal 1a is connected to the short connection point 2p among the n terminals 1a to na to which each of the n drivers DR1 to DRn is connected. Of the n terminals 1b to nb to which each of the n comparators CP1 to CPn is connected, only the terminal 2b is connected to the short connection point 2p. That is, by using this calibration board 350A-2, the signal output from the driver DR1 is input to the comparator CP2 via the short connection point 2p.

  FIG. 46 is a diagram illustrating a wiring state of another calibration board 350A-3 of the present embodiment. In the calibration board 350A-3, only the terminal 1a is connected to the short connection point 3p among the n terminals 1a to na to which each of the n drivers DR1 to DRn is connected. Of the n terminals 1b to nb to which each of the n comparators CP1 to CPn is connected, only the terminal 3b is connected to the short connection point 3p. That is, by using this calibration board 350A-3, the signal output from the driver DR1 is input to the comparator CP3 via the short connection point 3p.

  FIG. 47 is a diagram showing a wiring state of another calibration board 350A-n of the present embodiment. In the calibration board 350A-n, only the terminal 1a is connected to the short connection point np among the n terminals 1a to na to which the n drivers DR1 to DRn are connected. Of the n terminals 1b to nb to which the n comparators CP1 to CPn are connected, only the terminal nb is connected to the short connection point np. That is, by using the calibration board 350A-n, the signal output from the driver DR1 is input to the comparator CPn via the short connection point np.

  In the present embodiment, in order to connect one of the n comparators CP1 to CPn and one driver DR1 via the short connection point in this way, n calibration boards 350A-1 to 350A-n are provided. It is used.

  FIG. 48 is a diagram showing a wiring state of another calibration board 350B of the present embodiment. In this calibration board 350B, the n terminals 1a to na to which the n drivers DR1 to DRn are connected are connected to the short connection points 1q to nq that correspond one-to-one. These short connection points 1q to nq are also connected to each of n comparators CP1 to CPn. As a result, signals output from the drivers DR1 to DRn are input to the comparators CP1 to CPn via the corresponding short connection points 1q to nq, respectively.

  FIG. 49 is a flowchart showing the calibration operation procedure of the present embodiment. After one calibration board (for example, calibration board 350A-1) is set on the performance board 30 (step 500), the tester control unit 12 uses the clock signal CLK1 corresponding to the driver DR1 of the calibration board 350A-1. As a reference, the phase of the strobe signal STB1 corresponding to the comparator CP1 connected to the driver DR1 via the short connection point 1p is adjusted (step 501).

  In step 501, the phase of the strobe signal STB1 is fixed while the phase of the clock signal CLK1 input to the driver DR1 is fixed, that is, the timing at which the signal input to the comparator CP1 rises via the short connection point 1p is fixed. By searching for a position where the output level of the comparator CP1 is inverted by changing the phase, the phase adjustment of the strobe signal STB1 with respect to the clock signal CLK1 is performed.

  Next, the tester control unit 12 determines whether or not an unadjusted strobe signal remains (step 502). If it remains, the process returns to step 501 and the next calibration board (for example, calibration board). The operation after setting 350A-2) is repeated. In this way, by using each of the calibration boards 350A-1 to 350A-n shown in FIGS. 44 to 47, n comparators are obtained based on the clock signal CLK1 input to one driver DR1. The phases of the strobe signals STB1 to STBn input to CP1 to CPn are adjusted.

  In this way, when the phase adjustment of all the strobe signals is completed (No in Step 502), another calibration board 350B is set (Step 503). Note that the setting of the calibration boards 350A-1 to 350A-n and 350B in Steps 500 and 503 can be performed manually, or the work can be automated using a dedicated robot or the like.

  Next, the tester control unit 12 uses the calibration board 350B to adjust the phase of each clock signal with reference to each strobe signal for which phase adjustment has been completed (step 504). As described above, in the calibration board 350B, since the driver DR1 is connected to the comparator CP1 via the short connection point 1q, the phase of the clock signal CLK1 can be adjusted with reference to the strobe signal STB1. Further, since the driver DR2 is connected to the comparator CP2 via the short connection point 2q, the phase of the clock signal CLK2 can be adjusted with reference to the strobe signal STB2. Similarly, since the driver DRn is connected to the comparator CPn via the short connection point nq, the phase of the clock signal CLKn can be adjusted with reference to the strobe signal STBn.

  In this way, a series of calibration operations for adjusting the phases of all the strobe signals and the clock signals are completed.

  In the present embodiment, the phases of the n strobe signals STB1 to STBn are first adjusted with reference to one clock signal CLK1, and then the n clock signals CLK1 to CLK1 are set with reference to the respective strobe signals. The phase of CLKn is adjusted. First, the phase of n clock signals CLK1 to CLKn is adjusted with reference to one strobe signal, and then n strobes with reference to each clock signal. The phases of the signals STB1 to STBn may be adjusted.

  In this embodiment, in order to adjust the phases of the n strobe signals STB1 to STBn on the basis of one clock signal CLK1, each of the n calibration boards 350A-1 to 350A-n is sequentially arranged. However, as shown in FIG. 50, one calibration board 350C is used by using a calibration board 350C in which all n comparators CP1 to CPn are connected to one short connection point. Thus, the phase of each of the strobe signals STB1 to STBn may be adjusted.

  Further, in the present embodiment, the calibration board 250B in which each of the drivers DR1 to DRn and each of the comparators CP1 to CPn corresponds one-to-one is used, but these correspondences are not necessarily one-to-one.

[Ninth Embodiment]
In the above-described eighth embodiment, the calibration operation is performed by sequentially using n + 1 types of calibration boards. However, replacement is performed by using one type of calibration board having the functions of these calibration boards. You may make it save the trouble of.

  FIG. 51 is a diagram illustrating a configuration of a calibration board 350D according to the ninth embodiment having the functions of n + 1 types of calibration boards 350A-1 to 350A-n and 350B having different wiring contents.

  The calibration board 350D shown in this figure includes changeover switches 2r to nr corresponding to the other comparators CP2 to CPn other than the comparator CP1. By switching the connection states of these changeover switches 2r to nr, it is possible to selectively realize the same connection state as that of each of the calibration boards 350A-1 to 350A-n and the same connection state as that of the calibration board 350B. it can. Therefore, by using this calibration board 350D, it is not necessary to replace the calibration board, and further simplification of work contents, cost reduction, and reduction of work time can be realized.

  FIG. 52 is a view showing a modification of the calibration board 350D shown in FIG. When the phase adjustment of each clock signal is first performed with reference to one strobe signal, and then the operation of adjusting the phase of each strobe signal is performed, each switch 2s using the calibration board 350E shown in FIG. The connection state of ˜ns may be switched.

[Other Embodiments]
In each of the above-described embodiments, various calibration boards are set on the performance board 30. In consideration of the actual installation state, a socket board and an IC socket are mounted on the performance board 30, and the calibration board is further mounted thereon. May be set.

  FIG. 53 is a diagram showing a modification in which the installation state of the calibration board is changed. The configuration shown in FIG. 53 is different from the configuration shown in FIG. 5 in that a socket board (SB) 32 and an IC socket 34 are added between the performance board (PB) 30 and the calibration board (CB) 50A. That is, the calibration board 50A and the like are set in a state where the socket board 32 and the IC socket 34 that are actually used for performing various tests on the device under test are mounted. In this case, the wiring length between the output end of each driver and each short connection point and the wiring length between each short connection point and the input end of each comparator become longer. It is possible to perform a calibration operation in the same manner.

  For example, when FIG. 7 is rewritten with the wiring length of the wiring included in the socket board 32 and the IC socket 34 as Tb, the relationship shown in FIG. 54 is obtained. The signal output timing by each driver shown in FIG. 54 and the signal input timing to each comparator are the same as those shown in FIG. It can be seen that timing calibration in the same manner is possible.

  In each of the above-described embodiments, timing calibration is performed using various calibration boards. However, instead of these calibration boards, calibration devices and calibration wafers having the same wiring state are used. May be.

  FIG. 55 is a diagram illustrating a connection state between the calibration device and the semiconductor test apparatus main body. FIG. 56 is a diagram showing an outline of timing calibration using a calibration device. As shown in FIG. 55, the calibration device 450 is set with the performance board (PB) 30, socket board (SB) 32, and IC socket 34 installed in the semiconductor test apparatus body 10. The calibration device 450 has the same external shape and terminal shape as the device under measurement, and the internal wiring state is set to be the same as the calibration board of each embodiment described above. In each of the above-described embodiments, it is necessary to replace the calibration board manually or automatically by a robot as necessary. However, when the calibration device 450 is used, as shown in FIG. The calibration device 450 can be replaced by using the handler 100 that replaces the device under measurement in the semiconductor test. Accordingly, it is possible to reduce the time and effort of replacement compared with the case where manual replacement is performed. In addition, the cost can be reduced by eliminating the need for a dedicated robot as compared with the case of performing automatic replacement using a robot.

  FIG. 57 is a diagram showing a connection state between the calibration wafer and the semiconductor test apparatus main body. FIG. 58 is a diagram showing an outline of timing calibration using a calibration wafer. When a test is performed on a device under test formed on a wafer using a semiconductor test apparatus, a probe card (PC) 36 is attached to the performance board 30 as shown in FIG. The needle 38 that protrudes from the surface is brought into contact with a pad formed on the wafer. Therefore, timing calibration is performed by replacing the wafer on which the device under test is formed with a calibration wafer 550 in which the internal wiring state is set to be the same as the wiring state of the calibration board of each of the above-described embodiments. It becomes possible to do. Further, in each of the above-described embodiments, the calibration board has to be replaced manually or automatically by a robot as necessary. However, when the calibration wafer 550 is used, as shown in FIG. The calibration wafer 550 can be replaced by using the chuck 110 that moves the wafer to be measured in a normal semiconductor test. Accordingly, it is possible to reduce the time and effort of replacement compared with the case where manual replacement is performed. In addition, the cost can be reduced by eliminating the need for a dedicated robot as compared with the case of performing automatic replacement using a robot. In the example shown in FIGS. 57 and 58, the needle 38 on the probe card 36 is of a type that ensures electrical contact between the calibration wafer 550 and the wafer on which the device under test is actually formed. Although the semiconductor test apparatus has been described, electrical contact may be ensured by a method other than the needle 38, for example, via a bump.

  Next, a specific example of the calibration device 450 described above will be described.

  59 and 60 are diagrams illustrating a calibration device that realizes the same wiring state as the calibration board used in the first embodiment described above. One calibration device 450A shown in FIG. 59 has the same wiring as the calibration board 50A shown in FIG. The other calibration device 450B shown in FIG. 60 has the same wiring as that of the calibration board 50B shown in FIG. Note that the terminals and short connection points of the calibration devices 450A and 450B shown in FIGS. 59 and 60 are the same as the corresponding terminals and short connection points in the calibration boards 50A and 50B shown in FIGS. The code | symbol is attached | subjected. By setting these calibration devices 450A and 450B in order, the timing calibration is performed by the same procedure (the operation procedure shown in FIG. 4) as the first embodiment using the calibration boards 50A and 50B. It becomes possible to do.

  61 and 62 are diagrams illustrating a calibration device that realizes the same wiring state as that of the calibration board used in the third embodiment described above. One calibration device 450C shown in FIG. 61 has the same wiring as the calibration board 150A shown in FIG. The other calibration device 450D shown in FIG. 62 has the same wiring as the calibration board 150B shown in FIG. By setting these calibration devices 450C and 450D in order, the timing calibration is performed according to the same procedure (the operation procedure shown in FIG. 17) as the third embodiment using the calibration boards 150A and 150B. It becomes possible to do.

  FIG. 63 is a diagram showing a calibration device that realizes the same wiring state as that of the calibration board used in the fifth embodiment described above. The calibration device 450E shown in FIG. 63 has the same wiring as the calibration board 250A shown in FIG. Note that the wiring state of the calibration board 250B shown in FIG. 30 is the same as the wiring state of the calibration device 450C shown in FIG. 61, so that the calibration device 450C is combined with the calibration device 450E described above. Used. By setting these calibration devices 450E and 450C in order, timing calibration is performed by the same procedure (the operation procedure shown in FIG. 31) as that of the fifth embodiment using the calibration boards 250A and 250B. It becomes possible to do.

  FIGS. 64 to 68 are diagrams showing a calibration device that realizes the same wiring state as that of the calibration board used in the above-described eighth embodiment. The calibration device 450F-1 shown in FIG. 64 has the same wiring as the calibration board 350A-1 shown in FIG. The calibration device 450F-2 shown in FIG. 65 has the same wiring as the calibration board 350A-2 shown in FIG. The calibration device 450F-3 shown in FIG. 66 has the same wiring as the calibration board 350A-3 shown in FIG. The calibration device 450F-n shown in FIG. 67 has the same wiring as the calibration board 350A-n shown in FIG. Further, the calibration device 450G shown in FIG. 68 has the same wiring as the calibration board 350B shown in FIG. By sequentially setting these calibration devices 450F-1 to 450F-n and 450G, the same procedure as that in the eighth embodiment using the calibration boards 350A-1 to 350A-n and 350B (see FIG. 49). It is possible to perform timing calibration according to the operation procedure shown).

  Next, a specific example of the calibration wafer 550 described above will be described.

  FIG. 69 is a diagram showing a calibration wafer that realizes the same wiring state as the calibration board used in the first embodiment described above. Note that the calibration wafer shown in FIG. 69 and the like is for realizing a wiring state similar to that of the calibration board described above, and therefore, it is not always necessary to use a wafer formed of a semiconductor material, such as an epoxy resin. You may make it comprise using cheap materials other than these semiconductor materials.

  The calibration wafer 550A shown in FIG. 69 has the same wiring as the calibration board 50B shown in FIG. 3 and the first area 550A-1 where the same wiring as the calibration board 50A shown in FIG. A second region 550A-2 is included. By bringing the needle 38 of the probe card 36 into contact with the first and second regions 550A-1 and 550A-2 in order, the same procedure as in the first embodiment using the calibration boards 50A and 50B (FIG. It is possible to perform timing calibration according to the operation procedure shown in FIG.

  FIG. 70 is a diagram showing a calibration wafer that realizes the same wiring state as that of the calibration board used in the third embodiment described above. The calibration wafer 550B shown in FIG. 70 has the same wiring as the calibration board 150B shown in FIG. 15 and the first region 550B-1 where the same wiring as the calibration board 150A shown in FIG. 14 is made. A second region 550B-2 is included. By bringing the needle 38 of the probe card 36 into contact with the first and second regions 550B-1 and 550B-2 in order, a procedure similar to that of the third embodiment using the calibration boards 150A and 150B (FIG. It is possible to perform timing calibration according to the operation procedure shown in FIG.

  FIG. 71 is a diagram showing a calibration wafer that realizes the same wiring state as the calibration board used in the fifth embodiment described above. The calibration wafer 550C shown in FIG. 71 has the same wiring as the calibration board 250B shown in FIG. 30 and the first area 550C-1 where the same wiring as the calibration board 250A shown in FIG. 29 is made. A second region 550C-2 is included. By bringing the needle 38 of the probe card 36 into contact with the first and second regions 550C-1 and 550C-2 in order, the same procedure as in the fifth embodiment using the calibration boards 250A and 250B (FIG. The timing calibration according to the operation procedure shown in FIG.

  FIG. 72 is a diagram showing a calibration wafer that realizes the same wiring state as that of the calibration board used in the eighth embodiment described above. The calibration wafer 550D shown in FIG. 72 has the same wiring as the calibration board 350A-2 shown in FIG. 45 and the region 550D-1 shown in FIG. Area 550D-2, the area 550D-3 wired the same as the calibration board 350A-3 shown in FIG. 46, and the area 550D- wired the same as the calibration board 350A-n shown in FIG. n and a region 550D-B in which the same wiring as that of the calibration board 350B shown in FIG. 48 is made. The eighth embodiment using the calibration boards 350A-1 to 350A-n and 350B by bringing the needle 38 of the probe card 36 into contact with the respective regions 550D-1 to 550D-n and 550D-B in order. It is possible to carry out timing calibration by the same procedure (the operation procedure shown in FIG. 49).

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation implementation is possible within the range of the summary of this invention. For example, in the above-described embodiment, the dedicated calibration boards 50A, 50B, 150A, and 150B are used to perform the calibration operation. However, the calibration is performed on the socket board that is used to actually install the device to be measured. Wiring equivalent to 50B, 150A, 150B, and the like may be performed, and the content of the wiring may be changed by appropriately switching the changeover switch during the calibration operation.

  In the above-described embodiment, the case where the output terminal of the driver and the input terminal of the comparator constituting the set are separately connected to the short connection point is considered. However, the output terminal of the driver and the input terminal of the comparator are The present invention can also be applied to the case where the connection is made within the semiconductor test apparatus main body 10 or the performance board 30 and the connection point and the short connection point are connected via a single wiring. However, since the phase correction target by calibration in this case is the range up to the connection point described above, it is necessary to measure in advance the time length of the wiring between this connection point and the short connection point.

It is a figure which shows the whole structure of the semiconductor test apparatus used as the object of timing calibration. It is a figure which shows the wiring state of one calibration board. It is a figure which shows the wiring state of the other calibration board. It is a flowchart which shows the calibration operation | movement procedure of this embodiment. It is a figure which shows the state by which one calibration board (CB) was set to the semiconductor test apparatus main body. FIG. 6 is a diagram showing an outline of a phase alignment operation of a clock signal performed in step 101. FIG. 7 is a diagram showing details of a phase adjustment operation of the clock signal shown in FIG. 6. It is a figure which shows the state by which the other calibration board was set to the semiconductor test apparatus main body. FIG. 10 is a diagram showing an outline of a strobe signal phase difference obtaining operation performed in step 103. It is a figure which shows the outline of the correction value determination operation | movement and correction operation | movement of a strobe signal implemented in step 104,105. 6 is a diagram showing an outline of a phase correction operation of a clock signal performed in step 106. FIG. It is a figure which shows the structure of the calibration board of 2nd Embodiment which has the function of two types of calibration boards from which wiring content differs. It is a figure which shows the structure of the calibration board of 2nd Embodiment which has the function of two types of calibration boards from which wiring content differs. It is a figure which shows the wiring state of one calibration board used in order to perform the calibration operation | movement in 3rd Embodiment. It is a figure which shows the wiring state of the other calibration board used in order to perform the calibration operation | movement in 3rd Embodiment. It is a figure which shows the initial state of a clock signal and a strobe signal in a semiconductor test device before performing a calibration operation. It is a flowchart which shows the calibration operation | movement procedure of 3rd Embodiment. It is a figure which shows the driver and comparator in which signal input / output is performed corresponding to step 201 shown in FIG. FIG. 18 is a diagram illustrating an outline of a phase adjustment operation of a strobe signal performed in step 201 illustrated in FIG. 17. It is a figure which shows the driver and comparator in which signal input / output is performed corresponding to step 202 shown in FIG. FIG. 18 is a diagram showing an outline of a phase adjustment operation of a clock signal performed in step 202 shown in FIG. 17. It is a figure which shows the driver and comparator in which signal input / output is performed corresponding to step 204 shown in FIG. FIG. 18 is a diagram showing an outline of a phase difference measurement operation of a strobe signal performed in step 204 shown in FIG. 17. It is a figure which shows the outline of the phase correction of the strobe signal implemented in step 206 shown in FIG. It is a figure which shows the driver and comparator in which signal input / output is performed corresponding to step 207 shown in FIG. FIG. 18 is a diagram showing an outline of a clock signal correction operation performed in step 207 shown in FIG. 17. It is a figure which shows the structure of the calibration board of 4th Embodiment which has the function of two types of calibration boards from which wiring content differs. It is a figure which shows the structure of the calibration board of 4th Embodiment which has the function of two types of calibration boards from which wiring content differs. It is a figure which shows the wiring state of one calibration board of 5th Embodiment. It is a figure which shows the wiring state of the other calibration board of 5th Embodiment. It is a flowchart which shows the calibration operation | movement procedure of 5th Embodiment. FIG. 32 is a diagram illustrating a driver and a comparator that perform input / output of signals corresponding to step 301 illustrated in FIG. 31. FIG. 32 is a diagram showing an outline of a phase adjustment operation of a clock signal performed in step 301 shown in FIG. 31. FIG. 32 is a diagram illustrating a driver and a comparator that perform input / output of signals corresponding to step 303 illustrated in FIG. 31. FIG. 32 is a diagram showing an outline of a phase adjustment operation of a strobe signal performed in step 303 shown in FIG. 31. FIG. 32 is a diagram showing a driver and a comparator that perform input / output of signals corresponding to step 304 shown in FIG. 31. FIG. 32 is a diagram showing an outline of a phase adjustment operation of a clock signal performed in step 304 shown in FIG. 31. It is a figure which shows the structure of one calibration board of 6th Embodiment. It is a flowchart which shows the calibration operation | movement procedure of 6th Embodiment. It is a figure which shows the structure of the calibration board of 7th Embodiment which has the function of two types of calibration boards from which wiring content differs. It is a figure which shows the structure of the calibration board of 7th Embodiment which has the function of two types of calibration boards from which wiring content differs. It is a figure which shows the structure of the calibration board of the modification which has the function of two types of calibration boards from which wiring content differs. It is a figure which shows the structure of the calibration board of the modification which has the function of two types of calibration boards from which wiring content differs. It is a figure which shows the wiring state of the calibration board used with the calibration method of 8th Embodiment. It is a figure which shows the wiring state of the calibration board used with the calibration method of 8th Embodiment. It is a figure which shows the wiring state of the calibration board used with the calibration method of 8th Embodiment. It is a figure which shows the wiring state of the calibration board used with the calibration method of 8th Embodiment. It is a figure which shows the wiring state of the calibration board used with the calibration method of 8th Embodiment. It is a flowchart which shows the calibration operation | movement procedure of 8th Embodiment. It is a figure which shows the modification of the calibration board of this embodiment. It is a figure which shows the structure of the calibration board of 9th Embodiment which has the function of the n + 1 type calibration board from which wiring content differs. FIG. 52 is a diagram showing a modification of the calibration board shown in FIG. 51. It is a figure which shows the modification which changed the installation state of the calibration board. FIG. 54 is an explanatory diagram of clock signal phase adjustment corresponding to the configuration shown in FIG. 53; It is a figure which shows the connection state between a calibration device and a semiconductor test apparatus main body. It is a figure which shows the outline | summary of the timing calibration using a calibration device. It is a figure which shows the connection state between a calibration wafer and a semiconductor test apparatus main body. It is a figure which shows the outline | summary of the timing calibration using a calibration wafer. It is a figure which shows the calibration device which implement | achieved the same wiring state as the calibration board used in 1st Embodiment. It is a figure which shows the calibration device which implement | achieved the same wiring state as the calibration board used in 1st Embodiment. It is a figure which shows the calibration device which implement | achieved the same wiring state as the calibration board used in 3rd Embodiment. It is a figure which shows the calibration device which implement | achieved the same wiring state as the calibration board used in 3rd Embodiment. It is a figure which shows the calibration device which implement | achieved the same wiring state as the calibration board used in 5th Embodiment. It is a figure which shows the calibration device which implement | achieved the same wiring state as the calibration board used in 8th Embodiment. It is a figure which shows the calibration device which implement | achieved the same wiring state as the calibration board used in 8th Embodiment. It is a figure which shows the calibration device which implement | achieved the same wiring state as the calibration board used in 8th Embodiment. It is a figure which shows the calibration device which implement | achieved the same wiring state as the calibration board used in 8th Embodiment. It is a figure which shows the calibration device which implement | achieved the same wiring state as the calibration board used in 8th Embodiment. It is a figure which shows the calibration wafer which implement | achieved the same wiring state as the calibration board used in 1st Embodiment. It is a figure which shows the calibration wafer which implement | achieved the same wiring state as the calibration board used in 3rd Embodiment. It is a figure which shows the calibration wafer which implement | achieved the same wiring state as the calibration board used in 5th Embodiment. It is a figure which shows the calibration wafer which implement | achieved the same wiring state as the calibration board used in 8th Embodiment. It is a figure which shows the conventional structure which performs timing calibration of a semiconductor test apparatus. FIG. 74 is an electrical layout diagram of the conventional configuration shown in FIG. 73. It is a figure which shows the outline | summary of the conventional timing calibration. It is a figure which shows the outline | summary of the conventional timing calibration. It is a figure which shows the outline | summary of the conventional timing calibration.

Explanation of symbols

10 Semiconductor Test Equipment Body 12 Tester Control Unit (TP)
14 Timing generator (TG)
16 Pattern generator (PG)
18 Data selector (DS)
20 Format controller (FC)
22-pin electronics 30 performance board (PC)
50A, 50B, 50C Calibration board 150A, 150B, 150C Calibration board 250A, 250B, 250C, 250D, 250E Calibration board 350A-1 to 350A-n, 350B, 350C, 350D, 350E Calibration board 450, 450A, 450B, 450C, 450D, 450E, 450F-1 to 450F-n, 450G Calibration device 550, 550A, 550B, 550C, 550D Calibration wear

Claims (16)

In a semiconductor test apparatus calibration method for performing timing calibration of a semiconductor test apparatus including a driver that performs a signal generation operation synchronized with a clock signal and a comparator that performs a comparison operation synchronized with a strobe signal,
In a state where m groupings are performed so that at least one of the plurality of drivers and the plurality of comparators is included in two or more, the one clock driver is used as a common driver and the clock signal corresponding to the common driver is used as a reference. The first step of adjusting the phase of the strobe signal corresponding to the intra-group common comparator as one intra-group comparator as one comparator included in each group,
A second step of adjusting a phase of the clock signal corresponding to the driver included in the same group with reference to the strobe signal corresponding to the intra-group common comparator in each of the m groups;
A third step of adjusting a phase of the strobe signal corresponding to the comparator included in the same group with reference to the phase of the clock signal corresponding to an arbitrary driver in each of the m groups;
A calibration method for a semiconductor testing apparatus, comprising:   The phase adjustment performed in the first step is performed by each of the intra-group common comparators according to the strobe signal, and when the comparison operation is performed by each of the intra-group common comparators. 2. The semiconductor test according to claim 1, wherein the phase of the strobe signal input to each of the plurality of common comparators in the group is varied so that the timing at which the signal to be changed coincides. How to calibrate the device.   The phase adjustment performed in the second step is performed by changing the timing of performing the comparison operation by the intra-group common comparator according to the strobe signal, and the signal output from the driver and input to the intra-group common comparator. The semiconductor test apparatus calibration method according to claim 1, wherein the calibration is performed by changing a phase of the clock signal so that the timing to match is matched.   In the phase adjustment performed in the third step, the timing at which the comparison operation is performed by the comparator according to the strobe signal coincides with the timing at which the signal output from the driver and input to the comparator changes. The semiconductor test apparatus calibration method according to claim 1, wherein the calibration is performed by varying the phase of the strobe signal input to the comparator.   2. The semiconductor test apparatus according to claim 1, wherein a delay element for changing a phase of the signal is inserted in each of the clock signal supply path to the driver and the strobe signal supply path to the comparator. Calibration method.   The first step is performed using a first calibration board in which an output terminal of the common driver and an input terminal of the intra-group common comparator are connected via a common first short connection point. The semiconductor test apparatus calibration method according to claim 1.   In the second and third steps, a second calibration in which the output terminal of the driver and the input terminal of the comparator are connected via a common second short connection point for each of the plurality of groups. 7. The semiconductor test apparatus calibration method according to claim 6, wherein the calibration is performed using a calibration board.   The wiring length of the wiring connecting the driver and the first and second short connection points and the wiring length of the wiring connecting the comparator and the first and second short connection points are all set to be the same. The semiconductor test apparatus calibration method according to claim 7.   8. The method according to claim 7, further comprising a fourth step of replacing the first calibration board with the second calibration board between the first step and the second step. Calibration method for semiconductor test equipment. In the first step, the output terminal of the common driver and the input terminal of the intra-group common comparator included in each of the m groups are connected via wirings having the same time length for all the groups. Using a third calibration board,
In the second and third steps, the output terminals of the drivers and the input terminals of the comparators included in each group are connected to each other via wires having the same time length for all the groups. The semiconductor test apparatus calibration method according to claim 1, wherein the calibration is performed by switching a wiring state of the third calibration board.   The third calibration board includes a plurality of changeover switches for switching the wiring state. By switching the connection state of these changeover switches, the operations of the first, second, and third steps are performed. 11. The semiconductor test apparatus calibration method according to claim 10, wherein the calibration is performed.   The first step is performed using a first calibration device in which an output terminal of the common driver and an input terminal of the intra-group common comparator are connected via a common first short connection point. The semiconductor test apparatus calibration method according to claim 1.   In the second and third steps, a second calibration in which the output terminal of the driver and the input terminal of the comparator are connected via a common second short connection point for each of the plurality of groups. 13. The semiconductor test apparatus calibration method according to claim 12, wherein the calibration method is performed using a calibration device.   Between the first step and the second step, there is provided a fourth step of exchanging the first calibration device with the second calibration device using a handler. A method for calibrating a semiconductor test apparatus according to claim 13. In the first step, the first end in the first calibration wafer in which the output terminal of the common driver and the input terminal of the intra-group common comparator are connected via a common first short connection point. Done with the region,
In the second and third steps, a second calibration in which the output terminal of the driver and the input terminal of the comparator are connected via a common second short connection point for each of the plurality of groups. 2. The semiconductor test apparatus calibration method according to claim 1, wherein the calibration is performed using a second region in the wafer. 16. The semiconductor according to claim 15, wherein the first calibration wafer and the second calibration wafer are the same wafer, and the first and second regions are formed in the wafer. Calibration method for test equipment.

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