JP3818087B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit including a BIST circuit that self-inspects the quality of an internal circuit and a semiconductor inspection method using the same.
[0002]
[Prior art]
In the prior art, in the PASS / FAIL determination of the BIST circuit, both the FAIL flag and the END flag are observed. The FAIL flag is determined to be FAIL when the signal changes from L to H or from H to L, and the END flag is determined to be FAIL if the signal does not change at a predetermined position.
[0003]
In this determination method, whether the BIST circuit has entered the test mode cannot be observed with the FAIL flag and the END flag. That is, as shown in the timing chart of FIG. 5, when the BIST circuit does not enter the test mode, the FAIL flag does not change, and the test cannot be completed unless the test is performed up to the predetermined END flag position.
[0004]
Further, when the BIST circuit can perform a plurality of types of tests, the setting state (algorithm, pattern) that defines the plurality of types of operations cannot be observed from the outside, so that if there is an undetected failure in the BIST circuit, Even if an attempt is made to change the setting state (algorithm, pattern) that defines the operation of the circuit, the intended state may not be achieved, and there is a possibility that the test will not be performed correctly (test items may be leaked).
[0005]
[Problems to be solved by the invention]
In the BIST test, a test circuit is incorporated in the LSI to self-inspect the quality. However, the conventional configuration has a possibility of generating unnecessary test time and leaking test items.
[0006]
When arranged, it has the following two problems.
(1) When the BIST test mode is not entered due to a circuit failure or a BIST test mode setting failure, the FAIL flag does not change, and therefore, there is a problem that the test is not completed unless the position reaches a predetermined END flag.
(2) If there is an undetected fault circuit in the BIST circuit, the test setting state may be different from the intended one, and the test may not be performed correctly, and all necessary test items have not been performed. there were.
[0007]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device and a semiconductor inspection method that solve the above-mentioned conventional problems.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the semiconductor inspection apparatus of the present invention takes the following means.
[0009]
First, a BIST state detection circuit that detects that the BIST circuit has entered the test mode is provided. Thereby, the signal of the BIST state detection circuit is output as an external signal, and when the test mode is not entered, the test can be terminated.
[0010]
Second, a delay adjustment circuit is provided that changes the external output timing of the BIST state detection flag according to a setting state that defines the operation of the BIST. Thereby, when there is an undetected failure in the BIST and the test is not correctly performed due to the influence, the chip can be determined as a defective product.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
[0012]
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device of the present invention.
[0013]
The BIST circuit 1 includes a pattern generation circuit 2 that generates a test target pattern in a semiconductor circuit, a mode setting circuit 3 that sets test contents to be tested, and a comparison circuit 4 that compares test results.
[0014]
The test by the BIST circuit 1 is to generate a test pattern in the pattern generation circuit 2 in order to perform the test specified by the mode setting circuit 3, and to self-test the test target circuit 6 inside the semiconductor circuit to be tested, The comparison value is compared by the comparison circuit 4 and the inspection device 7 is made to recognize the determination result.
[0015]
The BIST state detection circuit 5 detects the BIST state of the BIST circuit 1, detects whether or not the test mode is in effect, and outputs the result to the outside (inspection apparatus 7). Specifically, the BIST state detection circuit 5 observes the signal of the BIST setting register 9 in the BIST circuit 1.
[0016]
FIG. 3 is a timing chart showing the state of the BIST state detection flag configured as described above.
[0017]
When the BIST circuit 1 enters the test mode, the BIST state detection circuit 5 recognizes that the BIST circuit 1 is in the test mode, and outputs the BIST state detection flag 13 (H level) to the outside (inspection apparatus 7). If the BIST circuit 1 is not in the test mode, the BIST test is terminated.
[0018]
That is, after the test by the BIST circuit 1 is started, if the BIST circuit 1 is not in the test mode (if the state detection flag is not output at H level), the test is terminated before the predetermined END flag is set, and useless Inspection is possible without using a long inspection time.
[0019]
(Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to the drawings.
[0020]
FIG. 2 is a block diagram showing the configuration of the semiconductor integrated circuit device of the present invention.
[0021]
The operations of the BIST circuit 1 and the BIST state detection circuit 5 are the same as in the first embodiment, and the feature of this embodiment is that a function for changing the timing of outputting the BIST state detection flag 8 to the outside (inspection apparatus 7) is added. There is.
[0022]
When the BIST circuit 1 has specifications that allow a plurality of types of tests, the BIST mode setting register 10 is set so as to define the operation of the BIST circuit 1 according to the type of test. The BIST state detection circuit 5 observes the signal of the BIST mode setting register 10, delays the signal by the delay adjustment circuit 11 in the BIST state detection circuit 5 according to the signal state, and outputs the BIST state detection signal flag 8 Change the timing.
[0023]
Then, the inspection device 7 determines which type of test the BIST circuit is currently performing by referring to the output timing, and terminates the test of the device if the desired test is not performed.
[0024]
That is, as shown in FIG. 4, when there are three different test setting states, the output start position of the BIST state detection flag 8 is set to 14, 15, 16 in accordance with the state set in the BIST mode setting register 10. By changing to, it is possible to make the inspection circuit recognize the current test setting state.
[0025]
For example, in the case of a memory BIST test, 14 in FIG. 4 is assigned to the march test table, 15 is assigned to the back of the memory march test, and 16 is assigned to the checker test. Can be recognized.
[0026]
As a result, “If there is a circuit failure in the memory BIST circuit, the value of the BIST setting register may not change, and the same pattern is generated from the pattern generator for different tests of the memory (front, back, etc.). Since the same test is generated twice, one of the tests becomes an uninspected item, which can cause a market failure. ”
[0027]
【The invention's effect】
By providing a BIST state detection circuit, the present invention makes it easy to determine whether a FAIL has occurred without entering the BIST state or has failed due to a failure of an internal circuit, and does not enter the BIST state during a mass production test. In the case of FAIL, the BIST test can be stopped, and an excellent semiconductor inspection that can save useless inspection time can be realized.
[0028]
Further, by changing the output start timing of the BIST state detection flag in accordance with the setting state that defines the operation of BIST, it is possible to make the test circuit recognize the currently performed test setting state. As a result, when there is an undetected failure in the BIST and the test is not correctly performed due to the influence, the chip can be determined as a defective product.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 4 is a timing chart showing a state of a BIST state detection flag in Embodiment 2 of the present invention. FIG. 5 is a timing chart showing a state of a flag in a conventional BIST circuit. [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 BIST circuit 2 Pattern generation circuit 3 Mode setting circuit 4 Comparison circuit 5 BIST state detection circuit 6 Test object circuit (internal circuit)
7 Inspection Device 8 BIST State Detection Flag 9 BIST State Setting Register 10 BIST Mode Setting Register 11 Delay Adjustment Circuit

Claims (1)

A semiconductor integrated circuit device having a BIST circuit for self-inspecting the quality of an internal circuit, wherein the BIST state detection circuit detects whether the BIST circuit is in a test mode and outputs a detection flag to the outside, and the BIST circuit If is a plurality of types of tests, depending on the type of test, the semiconductor integrated circuit device characterized by comprising a timing adjustment circuit for changing a timing for outputting the detection flag.

Images