JP3810679B2 - Clock recovery circuit and clock data recovery circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock recovery circuit that regenerates a clock so as to be synchronized with received data, and a clock / data recovery circuit including the clock recovery circuit.
[0002]
[Prior art]
Today, with the spread of local area networks and the Internet, the transmission capacity and transmission speed in data communication are steadily increasing.
[0003]
Data exchange between devices (hereinafter referred to as “nodes”) that perform data communication is generally performed in accordance with a predetermined interface standard. Various interface standards such as USB (universal serial bus), SSA (serial storage architecture), Ethernet (trademark), IEEE (institute of electrical and electronics engineers) 1394, fiber channel, etc. are known. .
[0004]
In many interface standards, data is transmitted under a predetermined frequency. The node that has received the transmission data can theoretically decode the reception data by synchronizing with the reception data using a clock having the same frequency as the frequency predetermined by the interface standard.
[0005]
However, the frequency of the internal clock of each node takes a unique value for each node. For example, even between nodes having the same clock frequency nominal value, there is a maximum error of about ± 100 ppm in the frequency of the clock generated by these nodes. In addition, the received data inevitably includes jitter.
[0006]
For this reason, in a node that exchanges data at a high speed, processing for enabling the content of received data to be decoded at its own clock frequency is performed prior to decoding of received data. This process differs depending on under what standard the data to be transmitted is encoded.
[0007]
For example, in standards such as Gigabit Ethernet, IEEE 1394b, and fiber channel, data is encoded and transmitted serially under the 8B10B encoding method. In this encoding method, 2-bit redundant data is added to continuous 8-bit data and converted to 10-bit data.
[0008]
A node that has received data created under the 8B10B encoding scheme first removes jitter in the received data using a clock / data recovery circuit.
[0009]
FIG. 13 schematically shows an example of a clock / data recovery circuit (hereinafter abbreviated as “CDR circuit”). The CDR circuit 200 shown in the figure includes a phase-locked loop circuit (hereinafter abbreviated as “PLL circuit”) 10 and a plurality of clocks Φ1 to Φn (n is an integer of 2 or more) supplied from the PLL circuit 10. .), A multiplexer 120 that outputs one clock Φx (x represents an integer of 1 to n) as a recovered clock Cr, a feedback circuit 130 for the multiplexer 120, a recovered clock Cr, and reception A reproduction data generator 50 for receiving reproduction data D and generating reproduction data;
[0010]
The PLL circuit 10 includes a plurality of clocks Φ1 to Φn having the same frequency and shifted by a constant phase by a voltage controlled oscillator (VCO) 11, for example, 10-phase clocks Φ1 to Φ1 whose phases are shifted by 1/10 of one cycle. Φ10 is generated. In order to maintain the frequency of each of the clocks Φ1 to Φn at a predetermined frequency, a part of the output from the voltage controlled oscillator 11 is supplied to the frequency divider 12 and is divided under a predetermined frequency division ratio to obtain a phase. Supplied to the frequency detector 13;
[0011]
The phase / frequency detector 13 detects, for example, the phase and frequency of the reference clock Cf supplied from the original oscillation and the phase and frequency of the signal supplied from the frequency divider 12, and based on the difference between these, Generate a signal. This signal is supplied to a loop filter 14 having a charge pump and converted into a DC voltage signal. This DC voltage signal becomes a control signal for the voltage controlled oscillator 11.
[0012]
Each of the clocks Φ <b> 1 to Φn generated by the voltage controlled oscillator 11 is supplied to the multiplexer 120. The multiplexer 120 selects one clock from the clocks Φ1 to Φn based on the control signal S supplied from the feedback circuit 130, and outputs this as the reproduction clock Cr.
[0013]
The feedback circuit 130 includes a phase detector 32, a digital filter 34, and a control device 136.
[0014]
The phase detector 32 detects, for example, a time lag between the rising edge of the recovered clock Cr and the change in state of the received data D (the rising or falling edge of the signal), that is, the phase difference between the recovered clock CR and the received data D. Generate an output signal. In the data created under the 8B10B encoding method, the same bit information does not continue five or more, so the phase of the received data D can be easily detected.
[0015]
The digital filter 34 integrates signals from the phase detector 33. When this integrated value is equal to or greater than a predetermined value, the control device 136 generates a control signal S and feedback-controls the multiplexer 120 in a direction in which the phase of the recovered clock Cr matches the phase of the received data D.
[0016]
For example, when the phase of the recovered clock Cr is delayed with respect to the phase of the received data D, the control device 136 supplies the control signal S indicating that the phase of the recovered clock Cr is delayed to the multiplexer 120, and the advanced phase. The multiplexer 120 is controlled so that a clock having the signal is output as the reproduction clock Cr. The frequency of the reproduction clock Cr is matched with the frequency of the reception data D by sequentially changing the phase of the reproduction clock Cr stepwise.
[0017]
The PLL circuit 10, the multiplexer 120, and the feedback circuit 130 constitute a clock recovery circuit 140.
[0018]
The reproduction data generator 50 receives the reproduction clock Cr and the reception data D, and latches the reception data D according to the reproduction clock Cr, thereby generating reproduction data (retimed data) Dr.
[0019]
The clock itself generated by the PLL circuit 10 in the CDR circuit 200 described above has a clock frequency that is unique to the node itself that received the data. As described above, the clock frequency and the clock frequency of the node on the data transmission side differ from each other by about ± 100 ppm at the maximum.
[0020]
However, by making the phase of the recovered clock Cr coincide with the phase of the received data D by the clock recovery operation, the recovered clock CR becomes a frequency that matches the clock frequency of the other party (the node on the data transmission side). Therefore, the reception data D can be accurately latched by the reproduction data generator 50, and jitter can be removed from the reception data D.
[0021]
The reception data D from which the jitter has been removed, that is, the reproduction data Dr is then written in, for example, a first-in first-out (FIFO) buffer in synchronization with the reproduction clock Cr.
[0022]
The node on the receiving side reads and decodes the reproduction data Dr written in the FIFO buffer in synchronization with its own internal clock.
[0023]
[Problems to be solved by the invention]
FIG. 14 shows a specific configuration of the multiplexer 120 shown in FIG. The multiplexer 120 shown in the figure includes ten switching elements SW1 to SW10 and a buffer 22 electrically connected to one end of these switching elements SW1 to SW10.
[0024]
Clocks having different phases are supplied to the other ends of the switching elements SW1 to SW10 one by one. Further, control signals SA to SJ are supplied from the control device 136 to these switching elements SW1 to SW10. One control signal corresponds to one switching element.
[0025]
The multiplexer 120 is controlled in operation by the control signals SA to SJ, selects one clock from the 10-phase clocks Φ1 to Φ10, and outputs this clock as the reproduction clock Cr.
[0026]
The multiplexer 120 supplies the reproduction clock Cr to the control device 136 in addition to supplying the reproduction clock Cr to the phase detector 32 and the reproduction data generator 50.
[0027]
The control device 136 is supplied with the reproduction clock Cr, and can switch the levels of the control signals SA to SJ according to the signal from the digital filter 34 when the reproduction clock Cr falls. The clock output as the reproduction clock Cr can be switched. However, the operations of the switching elements SW1 to SW10 are actually switched after a predetermined delay time has elapsed.
[0028]
This delay time depends on the parasitic capacitance at the junction C shown in FIG. As the parasitic capacitance increases, the waveform of the clock at the junction C becomes a dull waveform and the delay time increases. Further, when the clock waveform becomes dull, jitter is likely to occur in the recovered clock.
[0029]
With the recent increase in transmission capacity and transmission speed, the clock frequency is also gradually increasing. Further, the jitter tolerance required for the clock / data recovery circuit is becoming stricter, and accordingly, it is desired to generate a recovered clock using a clock recovery circuit having a higher phase resolution.
[0030]
In order to increase the phase resolution of the clock recovery circuit, it is necessary to increase the number of phases of the clock generated by the PLL circuit 10. As the number of clock phases increases, the parasitic capacitance at the junction C described above increases and the delay time described above also increases. An increase in the delay time hinders smooth switching of the reproduction clock Cr.
[0031]
FIG. 15 schematically shows a state in which the clock output as the reproduction clock Cr cannot be smoothly switched from the clock Φ5 to the clock Φ6.
[0032]
As described above, the switching operation of the reproduction clock Cr is started when the control device 136 receiving the supply of the reproduction clock Cr detects the fall of the reproduction clock Cr at a certain time. In the illustrated example, at time t1, an operation for switching the reproduction clock Cr from the clock Φ5 to the clock Φ6 is started.
[0033]
When the control device 136 starts the switching operation of the reproduction clock Cr at time t1, the switching elements SW5 and SW6 are actually switched at time t2. The time is delayed by a time corresponding to the time difference between time t2 and time t1.
[0034]
Based on the phase of the clock Φ5 supplied to the multiplexer 120, the delay time until the switching elements SW5 and SW6 are actually switched is further increased. That is, the phase of the recovered clock Cr is delayed by a time corresponding to the time difference between the time t1 and the time t0 from the phase of the clock Φ5 that is the basis of the phase due to the parasitic capacitance described above. The delay time until SW6 is actually switched is a time corresponding to the time difference between time t2 and time t0.
[0035]
If the delay time until the switching elements SW5 and SW6 are actually switched becomes longer, the switching elements SW5 and SW6 are switched when the clock Φ5 is at the high level and the clock Φ6 is at the low level as shown in the example in the figure. Become. As a result, problems such as glitches occur in the recovered clock Cr. The reproduction clock Cr cannot be switched smoothly.
[0036]
In order to smoothly switch the reproduction clock Cr, it is necessary to strictly control the switching timing, and accordingly, it is difficult to increase the clock frequency.
[0037]
An object of the present invention is to provide a clock recovery circuit that can easily shorten a delay time of a circuit and easily obtain a reproduction clock with small jitter.
[0038]
An object of the present invention is to provide a clock and data recovery circuit that can easily shorten the delay time of the circuit and can easily obtain a recovered clock with small jitter.
[0039]
[Means for Solving the Problems]
According to one aspect of the present invention, each of the plurality of signal selection circuits can selectively output one signal from a plurality of input signals, and the plurality of signal selection circuits includes at least two signal selection circuits. A hierarchical structure is formed with the signal selection circuit as the first stage and one signal selection circuit as the last stage, and one input signal is selected from a plurality of input signals supplied to the first stage to generate a reproduction clock. A regenerated clock generator capable of generating a plurality of clocks having the same frequency and a phase shifted by a fixed value, and outputting the plurality of clocks in parallel to the first stage, received data, and the regenerated clock The phase of the received data is compared with the phase of the recovered clock, and the recovered clock generator is set in a direction in which the phase of the recovered clock matches the phase of the received data. In a clock recovery circuit having a feedback circuit for feedback control, when the regenerated clock generator changes a selection state of a signal to be output, only one of the plurality of signal selection circuits forming a hierarchical structure is formed. A clock recovery circuit characterized by changing a selection state of the signal selection circuit is provided.
[0040]
According to another aspect of the present invention, each of the plurality of signal selection circuits can selectively output one signal from a plurality of input signals, and the plurality of signal selection circuits includes at least two signal selection circuits. A hierarchical structure is formed with one signal selection circuit as the first stage and one signal selection circuit as the last stage, and one input signal is selected from a plurality of input signals supplied to the first stage to generate a reproduction clock. A regenerated clock generator capable of generating a plurality of clocks having the same frequency and a phase shifted by a constant value, and outputting the plurality of clocks in parallel to the first stage, received data and the regenerated clock The phase of the received data is compared with the phase of the recovered clock, and the phase of the recovered clock is adjusted to match the phase of the received data. In a clock and data recovery circuit comprising a feedback circuit for feedback control, and a reproduction data generator capable of receiving the reception data and the reproduction clock and supplying the reception data in synchronization with the reproduction clock, The reproduction clock generator changes a selection state of a signal selection circuit of only one stage among the plurality of signal selection circuits forming a hierarchical structure when changing a selection state of an output signal. A clock and data recovery circuit is provided.
[0041]
By using the regenerative clock generator having the hierarchical structure described above, it becomes easy to suppress the dullness of the waveform of the clock output from each signal selection circuit.
[0042]
For example, when the above hierarchical structure is formed using three signal selection circuits, the first stage is constituted by two signal selection circuits. When one clock is selected from among the 10-phase clocks as the reproduction clock, each signal selection circuit constituting the first stage has only to be supplied with a 5-phase clock. It is only necessary to have one switching element. Therefore, the parasitic capacitance at the output terminal of each signal selection circuit can be easily made smaller than the parasitic capacitance at the junction C shown in FIG. Dullness of the waveform of the clock output from each signal selection circuit can be easily suppressed.
[0043]
As a result, the clock delay time in the regenerative clock generator can be easily shortened. In addition, it is easy to suppress the occurrence of jitter in the recovered clock. Even if the timing of switching the reproduction clock is not strictly controlled, it becomes easy to smoothly switch the reproduction clock, so that it is easy to increase the clock frequency.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 schematically shows a clock recovery circuit and a CDR circuit according to the first embodiment.
[0045]
The clock recovery circuit 40 shown in the figure is significantly different from the clock recovery circuit 140 shown in FIG. 13 in that the clock recovery circuit 40 includes a regenerated clock generator 20 instead of the multiplexer 120 shown in FIGS. Accordingly, the functions of the control device 36 and the feedback circuit 30 are also slightly different from those of the control device 136 and the feedback circuit 130 shown in FIG. The illustrated CDR circuit 100 has the same configuration as the CDR circuit 200 shown in FIG. 13 except that the clock recovery circuit 40 is different from the clock recovery circuit 140 shown in FIG.
[0046]
Among the constituent elements shown in FIG. 1, those common to the constituent elements shown in FIG. 13 or FIG. 14 are assigned the same reference numerals as those used in FIG. 13 or FIG.
[0047]
In the CDR circuit 100 shown in FIG. 1, clocks φ1 to φn (n represents an integer of 2 or more) having a predetermined number of phases are generated by the voltage controlled oscillator 11 constituting the PLL circuit 10. The frequencies of the clocks φ1 to φn can be the same as or different from the frequencies of the clocks φ1 to φn generated by the CDR circuit 200 shown in FIG. When the frequency of the clocks φ1 to φn is different from the frequency of the clocks φ1 to φn, the frequency dividing rate of the frequency divider 12 shown in FIG. 1 is different from the frequency dividing rate of the frequency divider 12 shown in FIG. Value.
[0048]
These clocks φ1 to φn are supplied to the reproduction clock generator 20 in parallel. The regenerative clock generator 20 receives the clocks φ1 to φn and the control signal S from the control device 36, and receives a predetermined clock φx (x represents one integer among 1 to n). Is output as a reproduction clock Cr. The configuration of the regenerated clock generator 20 will be described in detail later with reference to FIG.
[0049]
The PLL circuit 10, the recovered clock generator 20, and the feedback circuit 30 constitute a clock recovery circuit 40.
[0050]
The CDR circuit 100 includes a reproduction data generator 50, similar to the CDR circuit 200 shown in FIG. The reproduction data generator 50 latches the received data D according to the reproduction clock Cr, thereby generating reproduction data (retimed data) Dr.
[0051]
Hereinafter, the configuration of the voltage-controlled oscillator 11 and the configuration of the regenerative clock generator 20 will be described in detail by taking as an example the case where the voltage-controlled oscillator 11 generates 10-phase clocks φ1 to φ10. First, the configuration of the voltage controlled oscillator 11 will be described with reference to FIG.
[0052]
FIG. 2 schematically shows the voltage controlled oscillator 11. In the voltage controlled oscillator 11 shown in the figure, five differential inverters 11A to 11E constitute a five-stage differential inverter array IA. The individual differential inverters 11A to 11E receive a control signal (DC voltage signal) CV from the loop filter 14 having the charge pump shown in FIG.
[0053]
The first-stage differential inverter 11A receives the inverted output Os5 and the non-inverted output Es5 from the final-stage differential inverter 11E, and supplies the inverted output Os1 and the non-inverted output Es1 to the second-stage differential inverter 11B. The differential inverter 11B supplies the inverted output Os2 and the non-inverted output Es2 to the third-stage differential inverter 11C, and the differential inverter 11C supplies the inverted output Os3 and the non-inverted output Es3 to the fourth-stage differential inverter 11D. Supply. The final-stage differential inverter 11E receives the inverted output Os4 and the non-inverted output Es4 from the fourth-stage differential inverter 11D, and generates the above-described inverted output Os5 and non-inverted output Es5.
[0054]
A total of ten conversion circuits 11a to 11j are arranged corresponding to two differential inverters 11A to 11E in each stage.
[0055]
One of the two conversion circuits corresponding to one differential inverter receives the inverted output from the corresponding differential inverter at the inverted input terminal (−), and receives the non-inverted output at the non-inverted input terminal (+). Then, a predetermined clock is generated. The other conversion circuit receives the inverted output from the corresponding differential inverter at the non-inverted input terminal (+) and the non-inverted output at the inverted input terminal (−), and generates a predetermined clock. These two conversion circuits generate clocks with opposite phases.
[0056]
Since the illustrated voltage controlled oscillator 11 includes ten conversion circuits 11a to 11j, it generates 10-phase clocks φ1 to φ10 whose phases are shifted by 1/10 of one cycle, and these clocks φ1 to φ10. Can be output in parallel.
[0057]
FIG. 3 is a timing chart showing the relationship between the differential outputs from the differential inverters 11A, 11B, and 11E and the outputs from the conversion circuits 11a to 11j.
[0058]
As shown in the figure, the non-inverted output Es1 and the inverted output Os1 from the differential inverter 11A have a period T corresponding to the time difference between time t2 and time t1. The differential outputs from the other differential inverters 11B to 11E have the same period T. From the differential inverter 11A to the differential inverter 11E, the phase of each differential output is delayed by T / 5 from the differential output from the previous differential inverter.
[0059]
Since the differential output from the differential inverter has the period T, each of the clocks φ1 to φ10 output from the conversion circuits 11a to 11j also has the period T.
[0060]
From one conversion circuit, one clock that rises below the period T in synchronization with the time when the waveforms of the differential outputs from the differential inverter corresponding to the conversion circuit cross each other, and this clock is opposite Phase clock. In FIG. 3, the time when the waveforms of the differential outputs Os2 and Es2 from the differential inverter 11B cross each other is indicated by t3, and the time when the waveforms of the differential outputs Os5 and Es5 from the differential inverter 11E cross each other is indicated by t4. Show.
[0061]
Since the phase of the differential output of each of the differential inverters 11A to 11E is delayed by T / 5 from the differential output from the differential inverter in the previous stage, the phases of the two clocks output from the individual conversion circuits are also It is delayed by T / 5 from the clock output from the preceding conversion circuit.
[0062]
When the clocks φ1 to φ10 shown in FIG. 2 are arranged in this order, the phases are shifted by T / 10 from the clock φ1 to the clock φ10. That is, 10-phase clocks φ1 to φ10 whose phases are shifted by T / 10 can be generated by the voltage controlled oscillator 11 shown in FIG.
[0063]
Next, the configuration of the regenerated clock generator 20 that receives the supply of these clocks φ1 to φ10 will be described.
[0064]
FIG. 4 schematically shows the configuration of the regenerative clock generator 20. As shown in the figure, the reproduction clock generator 20 includes three signal selection circuits SS1 to SS3. These signal selection circuits SS1 to SS3 form a two-stage hierarchical structure with the signal selection circuit SS3 as the final stage.
[0065]
The signal selection circuit SS1 has five switching elements SW1 to SW5. One end of each of these switching elements SW1 to SW5 is electrically connected to each other, and five phases of clocks φ1 to φ5 are supplied to each other end from the voltage controlled oscillator 11 one by one.
[0066]
The operations of the switching elements SW1 to SW5 are controlled by the control signals Sa to Se supplied from the control device 36, and only one of the clocks φ1 to φ5 is output from the junction A1. The control signals Sa, Sb, Sc, Sd, and Se correspond in this order from the switching element SW1 to the switching element SW5.
[0067]
The signal selection circuit SS2 has five switching elements SW6 to SW10. One end of each of these switching elements SW6 to SW10 is electrically connected to each other, and the other end of each of the switching elements SW6 to SW10 is supplied with five-phase clocks φ6 to φ10 from the voltage controlled oscillator 11 one by one.
[0068]
The operations of the switching elements SW6 to SW10 are controlled by the control signals Sa to Se supplied from the control device 36, and only one of the clocks φ6 to φ10 is output from the junction A2. The control signals Sa, Sb, Sc, Sd, and Se correspond in this order from the switching element SW6 to the switching element SW10.
[0069]
The switching elements SW1 to SW10 are divided into five groups depending on which control signal is used for on / off control. Each group is constituted by two switching circuits corresponding to two clocks having opposite phases, that is, two clocks whose phases are shifted from each other by a half of one cycle.
[0070]
Since one control signal corresponds to one switching element in the signal selection circuit SS1 and one switching element in the signal selection circuit SS2, one control signal corresponds to one of the signal selection circuits SS1 and SS2. When a clock is selected, one clock is always selected also in the other signal selection circuit.
[0071]
The signal selection circuit SS3 includes two switching elements SW11 to SW12. The output of the signal selection circuit SS1 is supplied from the junction point A1 to one end of the switching element SW11. The output of the signal selection circuit SS2 is supplied from the junction point A2 to one end of the switching element SW12. The other ends of the switching elements SW11 to SW12 are electrically connected to each other at a junction point A3.
[0072]
The operation of the switching element SW11 is controlled by the control signal S0 supplied from the control device 36, and the operation of the switching element SW12 is controlled by the control signal S1 supplied from the control device 36, so that one of the signal selection circuits SS1 and SS2 The output from one side is output from the junction point A3.
[0073]
The output from the signal selection circuit SS3 is supplied to the buffer 22. The output signal of the buffer 22 becomes the reproduction clock Cr. In addition to being supplied to the phase detector 32 and the reproduction data generator 50, the reproduction clock Cr is also supplied to the control device 36 as described above.
[0074]
FIG. 5 shows the relationship between the levels of the control signals Sa to Se and S0 to S1 supplied from the control device 36 to the reproduction clock generator 20 and the clock selected as the reproduction clock Cr by the reproduction clock generator 20. It is a state transition diagram. In the following description, it is assumed that when the control signals Sa to Se and S0 to S1 are at a high level, the switching element that receives the supply of the control signal is closed.
[0075]
In the figure, two control signals that become high level when one clock is selected as the reproduction clock Cr by the reproduction clock generator 20 are shown in one circle. When the reproduction clock Cr is generated, any one of the control signals Sa to Se and one of the control signals S0 and S1 are at a high level, and the other control signals are all at a low level.
[0076]
For example, when both the control signals Sa and S0 are set to the high level and all other control signals are set to the low level, the clock φ1 is selected as the reproduction clock. A clock having a waveform corresponding to the clock φ1 is output as the reproduction clock Cr.
[0077]
When the control signal S0 is set to the high level and the control signals Sa to Se are sequentially set to the high level in this order, the clocks φ1 to φ5 are sequentially selected in this order. Similarly, when the control signal S1 is set to the high level and the control signals Sa to Se are sequentially set to the high level in this order, the clocks φ6 to φ10 are sequentially selected in this order. In either case, the phase of the reproduction clock Cr is sequentially delayed.
[0078]
On the other hand, when the control signal S0 is set to the high level and the control signals Sa to Se are sequentially set to the high level in the reverse order, the clocks φ1 to φ5 are sequentially selected in the reverse order. Similarly, when the control signal S1 is set to the high level and the control signals Sa to Se are sequentially set to the high level in the reverse order, the clocks φ6 to φ10 are sequentially selected in the reverse order. In either case, the phase of the reproduction clock Cr advances sequentially.
[0079]
For example, when the clock φ6 is selected after the clock φ5, or when the clock φ5 is selected after the clock φ6, the levels of two predetermined control signals in the control signals Sa to Se are changed. It is necessary to change the levels of the control signals S0 and S1. The same applies when the clock φ10 is selected after the clock φ1 and when the clock φ1 is selected after the clock φ10.
[0080]
In the regenerated clock generator 20 having the above-described configuration, the five-phase clocks φ1 to φ5 or φ6 to φ10 may be supplied to the signal selection circuits SS1 and SS2 constituting the first stage of the hierarchical structure. The parasitic capacitance at the junction point A1 in the signal selection circuit SS1 and the parasitic capacitance at the junction point A2 in the signal selection circuit SS2 can be easily made smaller than the parasitic capacitance at the junction point C shown in FIG. It is possible to easily suppress the dullness of the waveform of the clock output from the individual signal selection circuits SS1 and SS2. The dullness of the waveform of the clock input to the buffer 22 can be easily suppressed.
[0081]
As a result, in the clock recovery circuit 40 and the CDR circuit 100 provided with the reproduction clock generator 20, the clock delay time in the reproduction clock generator 20 can be easily shortened, and the reproduction clock Cr can be jittered. It becomes easy to suppress the occurrence of. Even if the timing of switching the reproduction clock Cr is not strictly controlled, it is easy to smoothly switch the reproduction clock Cr, and therefore it is easy to increase the clock frequency.
[0082]
Next, a clock recovery circuit and a CDR circuit according to the second embodiment will be described.
[0083]
The clock recovery circuit and the CDR circuit according to this embodiment have the same configuration as the clock recovery circuit 40 and the CDR circuit 100 according to the first embodiment, except for the mode of supplying the clock to the reproduction clock generator. Here, only the mode of supplying the clock to the regenerative clock generator and the effect of taking the mode will be described in detail, and the description of the other configurations will be omitted.
[0084]
FIG. 6 schematically shows the configuration of the regenerated clock generator 20A in the clock recovery circuit and the CDR circuit according to this embodiment.
[0085]
As is clear from the comparison with FIG. 4, the regenerated clock generator 20A is supplied with clocks φ6 to φ10 in the reverse order from the switching element SW6 to the switching element SW10 in the signal selection circuit SS2. . Each of the switching elements SW1 to SW10 included in the first stage is divided into five groups depending on which control signal of the control signals Sa to Se is supplied. Each group is (2m-1) / 10 (m is an integer equal to or greater than 1) of the period T of the clocks φ1 to φ10, and a different value corresponds to each group. The maximum value of m is the same as the number of groups. 2) It is composed of two switching elements corresponding to clocks shifted by one.
[0086]
Except for this point, the recovered clock generator 20A has the same configuration as the recovered clock generator 20 shown in FIG. In FIG. 6, the same reference numerals as those used in FIG. 4 are given to the respective components except for the regenerated clock generator 20A.
[0087]
The clock recovery circuit and CDR circuit of this embodiment having the regenerated clock generator 20A shown in the figure have the same effects as the clock recovery circuit or CDR circuit of the first embodiment. Furthermore, it is possible to reliably prevent the error transition described below.
[0088]
Here, “error transition” in this specification means that a clock different from a desired clock is temporarily selected and output as the reproduction clock Cr. First, error transition will be specifically described with reference to FIG.
[0089]
FIG. 7 schematically shows a state when the reproduction clock Cr is switched from the clock φ5 to the clock φ6 in the reproduction clock generator 20 shown in FIG.
[0090]
As shown in the figure, the recovered clock Cr output from the recovered clock generator 20 is delayed from the clock φ5 supplied to the recovered clock generator 20 by a time corresponding to the time difference between time t11 and time t10. ing.
[0091]
When the control device 36 starts the operation to switch the clock output as the reproduction clock Cr from the clock φ5 to the clock φ6 at time t11, the switching elements SW5, SW6, SW11, SW12 are actually switched at time t12. The time is delayed by a time corresponding to the time difference between time t12 and time t11.
[0092]
At time t12, the switching element SW5 is opened by the control signal Se, and the switching element SW6 is closed by the control signal Sa. Further, the switching element SW11 is opened by the control signal S0, and the switching element SW12 is closed by the control signal S1.
[0093]
At this time, if switching of the switching elements SW11 and SW12 occurs prior to switching of the switching elements SW5 and SW6, since the switching element SW10 is also closed when the switching element SW5 is closed, the clock φ10 is used as the reproduction clock Cr. Temporarily selected, and thereafter clock φ6 is selected as the reproduction clock Cr. That is, an error transition occurs. This error transition is indicated by a broken arrow Er1 in FIG.
[0094]
On the other hand, in the reproduction clock generator 20A shown in FIG. 6, the reproduction clock Cr is switched as shown in FIG.
[0095]
FIG. 8 shows the relationship between the levels of the control signals Sa to Se and S0 to S1 supplied from the control device 36 to the reproduction clock generator 20A and the clock selected as the reproduction clock Cr by the reproduction clock generator 20A. It is a state transition diagram. In the following description, it is assumed that when the control signals Sa to Se and S0 to S1 are at a high level, the switching element that receives the supply of the control signal is closed.
[0096]
Also in the figure, as in FIG. 5, two control signals that are at a high level when one clock is selected as the reproduction clock Cr by the reproduction clock generator 20A are described in one circle. When the reproduction clock Cr is generated, any one of the control signals Sa to Se and one of the control signals S0 and S1 are at a high level, and the other control signals are all at a low level.
[0097]
As is apparent from FIG. 8, by providing the signal selection circuit SS2 with the above-described configuration, the final stage (signal selection circuit SS3) and the first stage (signal selection) of the hierarchical structure formed by the signal selection circuits SS1 to SS3 are formed. By switching the switching element only in one of the stages of the circuits SS1 to SS2), it becomes possible to switch the reproduction clock Cr to the next reproduction clock Cr. Error transition can be prevented. A desired clock can be reliably selected as the reproduction clock Cr.
[0098]
Next, a clock recovery circuit and a CDR circuit according to the third embodiment will be described.
[0099]
The clock recovery circuit and the CDR circuit according to the present embodiment are (i) that 18-phase clocks φ1 to φ18 are generated by the PLL circuit 10 (voltage controlled oscillator 11), and (ii) seven signals in the regenerative clock generator. The selection circuits SS1 to SS6 and SS10 form a two-stage hierarchical structure, and (iii) the control device 36 supplies the control signals Sa to Sc and S0 to S5 to the reproduction clock generator. This is greatly different from the clock recovery circuit 40 and the CDR circuit 100 according to the embodiment.
[0100]
The configuration excluding these differences is the same as that of the clock recovery circuit 40 and the CDR circuit 100 according to the first embodiment. Here, only the configuration of the regenerative clock generator will be described in detail, and description of other configurations will be omitted.
[0101]
FIG. 9 schematically shows a configuration of the regenerated clock generator 20B in the clock recovery circuit and the CDR circuit according to this embodiment.
[0102]
Six signal selection circuits SS1 to SS6 constitute the first stage of the hierarchical structure, and one signal selection circuit SS10 constitutes the final stage of the hierarchical structure. The clock selected by the signal selection circuit SS10 is supplied to the buffer 22, and is output as the reproduction clock Cr.
[0103]
In the regenerated clock generator 20B, 18-phase clocks φ1 to φ18 are supplied to the six signal selection circuits SS1 to SS6 constituting the first stage of the hierarchical structure. The phases of these clocks φ1 to φ18 are delayed by 1/18 of the period T of the clocks φ1 to φ18 in this order from the clock φ1 to the clock 18. Three clocks are sequentially supplied from the signal selection circuit SS1 to the signal selection circuit SS6 to the individual signal selection circuits SS1 to SS6 in order from the clock with the advanced phase.
[0104]
Each signal selection circuit SS1 to SS6 has three switching elements, and one clock is supplied to one switching element. The 18 switching elements SW1 to SW18 included in the first stage are divided into first to third groups depending on which control signal of the control signals Sa to Sc is turned on / off.
[0105]
Each group includes six switching elements corresponding to two sets of clocks whose phases are shifted by (2 × 18/6) · T / 18, respectively, where T is the period of the clocks φ1 to φ18. These six switching elements are selected one by one from the signal selection circuits SS1 to SS6.
[0106]
The first group is composed of six switching elements including switching elements SW1 and SW18, and is supplied with a control signal Sa. The second group is composed of six switching elements including switching elements SW2 and SW17, and receives a control signal Sb. The remaining six switching elements form a third group. The third group is supplied with the control signal Sc.
[0107]
Each of the signal selection circuits SS1 to SS6 selects one clock from the supplied clocks and outputs this clock to the signal selection circuit SS10 at the final stage.
[0108]
The signal selection circuit SS10 has six switching elements SW21 to SW26. One clock is supplied to each of the switching elements SW21 to SW26. These switching elements SW21 to SW26 are on / off controlled by separate control signals S0 to S5, respectively. Only one of the control signals S0 to S5 is supplied to one switching element.
[0109]
The signal selection circuit SS10 selects one clock from the supplied six clocks and outputs this clock to the buffer 22. The output signal of the buffer 22 becomes the reproduction clock Cr.
[0110]
The clock recovery circuit and CDR circuit of this embodiment having the regenerated clock generator 20B shown in the figure have the same effects as the clock recovery circuit or CDR circuit of the second embodiment.
[0111]
Next, a clock recovery circuit and a CDR circuit according to the fourth embodiment will be described.
[0112]
The clock recovery circuit and the CDR circuit according to the present embodiment are: (i) the four signal selection circuits SS1 to SS3 and SS10 in the reproduction clock generator form a two-stage hierarchical structure; and (ii) the control device 36. Is different from the clock recovery circuit and the CDR circuit according to the second embodiment in that the control signals Sa to Sf and S0 to S2 are supplied to the reproduction clock generator.
[0113]
The configuration excluding these differences is the same as that of the clock recovery circuit and the CDR circuit according to the second embodiment. Here, only the configuration of the regenerative clock generator will be described in detail, and description of other configurations will be omitted.
[0114]
FIG. 10 schematically shows a configuration of a regenerated clock generator 20C in the clock recovery circuit and the CDR circuit according to this embodiment.
[0115]
In the regenerated clock generator 20C, the first stage of the hierarchical structure is configured by three signal selection circuits SS1 to SS3 each having six switching elements. Eighteen switching elements SW1 to SW18 are included in the first stage.
[0116]
These 18 switching elements SW1 to SW18 are divided into first to sixth groups depending on which control signal among the control signals Sa to Sf is on / off controlled. If the period of the clocks φ1 to φ18 supplied to the first stage is T, each group includes three switching elements corresponding to three clocks whose phases are shifted by T / 18. These three switching elements are selected one by one from the signal selection circuits SS1 to SS3.
[0117]
A group including the switching element SW1 receiving the supply of the clock φ1 whose phase is most advanced is defined as a first group, and a group including the switching element SW18 receiving the supply of the clock φ18 whose phase is most delayed is a sixth group. Then, the control signals Sa to Sf correspond one by one in this order from the first group to the sixth group.
[0118]
Each signal selection circuit SS1 to SS3 selects one clock from the supplied clocks, and outputs this clock to the signal selection circuit SS10 in the final stage.
[0119]
The signal selection circuit SS10 includes three switching elements SW21 to SW23. One clock is supplied to each of the switching elements SW21 to SW23. These switching elements SW21 to SW26 are on / off controlled by separate control signals S0 to S2. Only one of the control signals S0 to S2 is supplied to one switching element.
[0120]
The signal selection circuit SS10 selects one clock from the supplied three clocks and outputs this clock to the buffer 22. The output signal of the buffer 22 becomes the reproduction clock Cr.
[0121]
The clock recovery circuit and CDR circuit of this embodiment having the regenerated clock generator 20C shown in the figure have the same effects as the clock recovery circuit or CDR circuit of the second embodiment.
[0122]
Next, a clock recovery circuit and a CDR circuit according to a fifth embodiment will be described.
[0123]
The clock recovery circuit and the CDR circuit according to the present embodiment are (i) the nine signal selection circuits SS1 to SS6, SS10 to SS11, and SS15 in the reproduction clock generator form a three-stage hierarchical structure, and ( iii) It differs greatly from the clock recovery circuit and the CDR circuit according to the third embodiment in that the control device 36 supplies the control signals Sa to Sc, S10 to S12, and S0 to S1 to the reproduction clock generator.
[0124]
The configuration excluding these differences is the same as that of the clock recovery circuit and CDR circuit according to the third embodiment. Here, only the configuration of the regenerative clock generator will be described in detail, and description of other configurations will be omitted.
[0125]
FIG. 11 schematically shows the configuration of the regenerated clock generator 20D in the clock recovery circuit and the CDR circuit according to this embodiment.
[0126]
In the regenerated clock generator 20D, the first stage of the hierarchical structure is configured by six signal selection circuits SS1 to SS6 each having three switching elements. The configuration of the first stage and the supply form of the clocks φ1 to φ18 to the first stage are the same as those of the clock recovery circuit and the CDR circuit according to the third embodiment.
[0127]
The second stage of the hierarchical structure is composed of two signal selection circuits SS10 to SS11. One clock is supplied from each of the signal selection circuits SS1 to SS3 to the signal selection circuit SS10, and one clock is supplied from each of the signal selection circuits SS4 to SS6 to the signal selection circuit SS11.
[0128]
Each signal selection circuit SS10 to SS11 has three switching elements, and one clock is supplied to one switching element. The six switching elements SW21 to SW26 included in the second stage are divided into three groups depending on which of the control signals S10 to S12 is controlled to be turned on / off. Each group includes two switching elements. One control signal is supplied to one group.
[0129]
The switching element SW21 to which the clock with the most advanced phase among the clocks supplied to the signal selection circuit SS10 is supplied is the switching to which the clock with the most delayed phase is supplied among the clocks supplied to the signal selection circuit SS11. A group is formed together with the element SW26. The switching element SW23 to which the clock having the most delayed phase among the clocks supplied to the signal selection circuit SS10 is switched is supplied with the clock having the most advanced phase among the clocks supplied to the signal selection circuit SS11. A group is formed together with the element SW24.
[0130]
The signal selection circuits SS10 to SS11 select one clock from two clocks supplied to each, and output these clocks to the final stage.
[0131]
The signal selection circuit SS15 configuring the final stage is configured in the same manner as the signal selection circuit SS3 illustrated in FIG. 4 or FIG. The signal selection circuit SS15 selects one clock from the two supplied clocks and outputs this clock to the buffer 22. The output signal of the buffer 22 becomes the reproduction clock Cr.
[0132]
The clock recovery circuit and CDR circuit of this embodiment having the regenerated clock generator 20D shown in the figure have the same effects as the clock recovery circuit or CDR circuit of the second embodiment. Error transition can be reliably prevented in the first stage of the hierarchical structure constituted by nine signal selection circuits SS1 to SS6, SS10 to SS11, and SS15, and error transition can also be reliably prevented in the second stage. Can do.
[0133]
Next, a clock recovery circuit and a CDR circuit according to the sixth embodiment will be described.
[0134]
The clock recovery circuit and the CDR circuit according to the present embodiment are: (i) the seven signal selection circuits SS1 to SS4, SS10 to SS11, and SS15 in the reproduction clock generator form a three-stage hierarchical structure; iii) The control device 36 supplies five control signals Sa to Se to the first stage signal selection circuits SS1 to SS4, and supplies two control signals S10 to S11 to the second stage signal selection circuits SS10 to SS11. This is very different from the clock recovery circuit and CDR circuit according to the fifth embodiment.
[0135]
The configuration excluding these differences is the same as that of the clock recovery circuit and CDR circuit according to the fifth embodiment. Here, only the configuration of the regenerative clock generator will be described in detail, and description of other configurations will be omitted.
[0136]
FIG. 12 schematically shows a configuration of the regenerated clock generator 20E in the clock recovery circuit and the CDR circuit according to this embodiment.
[0137]
In this reproduction clock generator 20E, four signal selection circuits SS1 to SS4 constitute the first stage of the hierarchical structure. Five clocks φ1 to φ5 are supplied to the signal selection circuit SS1, and four clocks φ6 to φ9 are supplied to the signal selection circuit SS2. In addition, four clocks φ10 to φ13 are supplied to the signal selection circuit SS3, and five clocks φ14 to φ18 are supplied to the signal selection circuit SS4.
[0138]
Each of the signal selection circuits SS1 to SS4 has the same number of switching elements as the number of clocks to be supplied, and one clock is supplied to one switching element. The 18 switching elements SW1 to SW18 included in the first stage are divided into first to fifth groups depending on which control signal of the control signals Sa to Se is turned on / off.
[0139]
The first group includes a switching element SW1 to which a clock φ1 is supplied and a switching element SW18 to which a clock φ18 is supplied, and receives a control signal Sa.
[0140]
In the second to fifth groups, when the period of the clocks φ1 to φ18 is T, four switching elements corresponding to two sets of clocks whose phases are shifted by (2 × 16/4) · T / 18 respectively. including. The control signals Sb to Se correspond one by one in this order from the second group to the fifth group.
[0141]
Each signal selection circuit SS1 to SS4 selects one clock from the supplied clocks and outputs this clock to the second stage.
[0142]
The second stage of the hierarchical structure is composed of two signal selection circuits SS10 to SS11. One clock is supplied from each of the signal selection circuits SS1 to SS2 to the signal selection circuit SS10, and one clock is supplied from each of the signal selection circuits SS3 to SS4 to the signal selection circuit SS11.
[0143]
Each of the signal selection circuits SS10 to SS11 has two switching elements, and one clock is supplied to one switching element. The four switching elements SW21 to SW24 included in the second stage are divided into two groups according to which of the control signals S10 to S11 is controlled to be turned on / off.
[0144]
Among the two clocks supplied to the signal selection circuit SS10, the switching element SW21 to which the clock with the phase advanced is supplied has the other clock whose phase is delayed among the clocks supplied to the signal selection circuit SS11. One group is formed together with the supplied switching element SW24. The remaining switching elements SW22 and SW23 constitute the other group.
[0145]
The signal selection circuits SS10 to SS11 select one clock from two clocks supplied to each, and output these clocks to the final stage.
[0146]
The signal selection circuit SS15 constituting the final stage is configured similarly to the signal selection circuit SS15 shown in FIG. The signal selection circuit SS15 selects one clock from the two supplied clocks and outputs this clock to the buffer 22. The output signal of the buffer 22 becomes the reproduction clock Cr.
[0147]
The clock recovery circuit and CDR circuit of this embodiment having the regenerated clock generator 20C shown in the figure have the same effects as the clock recovery circuit or CDR circuit of the second embodiment.
[0148]
Although the clock recovery circuit and the CDR circuit according to the embodiments have been described above, the present invention is not limited to the above-described embodiments.
[0149]
For example, the oscillator that generates the clock is preferably a voltage controlled oscillator constituting a PLL circuit, but is not limited to this voltage controlled oscillator. When a PLL circuit is used, the PLL circuit can be configured to generate a plurality of types of clocks having different frequencies.
[0150]
The number of clock phases generated by the oscillator can be less than 10 phases or more than 10 phases depending on the intended use of the clock recovery circuit or CDR circuit.
[0151]
The number of stages in the hierarchical structure formed by the signal selection circuit in the regenerative clock generator can be set to a desired number of 2 or more, but it is preferable that this number be smaller. The number of signal selection circuits constituting the first stage can be appropriately selected according to the number of clock phases generated by the oscillator, the number of stages of the hierarchical structure formed by the signal selection circuit, and the like.
[0152]
A clock is supplied to each signal selection circuit constituting the first stage so that the phase of the clock in each signal selection circuit is shifted by a certain value.
[0153]
It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like are possible.
[0154]
【The invention's effect】
As described above, according to the present invention, it is easy to shorten the delay time of the clock recovery circuit and the clock / data recovery circuit, and it is easy to obtain a reproduction clock with small jitter. It becomes easy to provide a clock recovery circuit or a clock data recovery circuit that can easily cope with an increase in data transmission capacity and transmission speed.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a clock recovery circuit and a clock / data recovery circuit according to a first embodiment;
FIG. 2 is a schematic diagram illustrating an example of a voltage controlled oscillator illustrated in FIG. 1;
3 is a timing chart showing a relationship between an output from the differential inverter shown in FIG. 2 and an output from each conversion circuit shown in FIG.
4 is a schematic diagram showing an example of a regenerated clock generator shown in FIG.
5 is a state transition diagram showing the relationship between the level of a control signal supplied to the recovered clock generator shown in FIG. 4 and a clock selected as a recovered clock by the recovered clock generator. FIG.
FIG. 6 is a schematic diagram showing a recovered clock generator in a clock recovery circuit and a CDR circuit according to a second embodiment.
7 is a timing chart schematically showing an example of switching of a reproduction clock by the reproduction clock generator shown in FIG.
8 is a state transition diagram showing the relationship between the level of a control signal supplied to the reproduction clock generator shown in FIG. 6 and a clock selected as the reproduction clock Cr by the reproduction clock generator.
FIG. 9 is a schematic diagram showing a recovered clock generator in a clock recovery circuit and a CDR circuit according to a third embodiment.
FIG. 10 is a schematic diagram showing a recovered clock generator in a clock recovery circuit and a CDR circuit according to a fourth embodiment.
FIG. 11 is a schematic diagram showing a recovered clock generator in a clock recovery circuit and a CDR circuit according to a fifth embodiment.
FIG. 12 is a schematic diagram showing a recovered clock generator in a clock recovery circuit and a CDR circuit according to a sixth embodiment.
FIG. 13 is a schematic diagram showing an example of a conventional clock and data recovery circuit.
14 is a schematic diagram showing an example of a multiplexer in the clock / data recovery circuit shown in FIG. 13; FIG.
FIG. 15 is a timing chart schematically showing a state when the reproduction clock cannot be switched smoothly by the multiplexer shown in FIG. 14;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... PLL circuit, 11 ... Voltage control oscillator, 20, 20A, 20B, 20C, 20D, 20E ... Reproduction clock generator, 30 ... Feedback circuit, 36 ... Control device, 40 ... Clock recovery circuit, 50 ... Reproduction data generator , 100... Clock / data recovery circuit, φ1 to φn, φ1 to φ18, clock, SS1 to SS6, SS10 to SS11, SS15, signal selection circuit, SW1 to SW18, SW21 to SW26, SW31 to SW32, switching element, Sa to Sf, S0 to S5, S10 to S11 ... control signal, Cr ... reproduction clock, Dr ... reproduction data.

Claims (3)

Each has a plurality of signal selection circuits capable of selectively outputting one signal from a plurality of input signals, and the plurality of signal selection circuits have at least two signal selection circuits as the first stage, A regenerative clock generator capable of generating a regenerative clock by selecting a single input signal from a plurality of input signals supplied to the first stage, forming a hierarchical structure with the signal selection circuit as the final stage;
An oscillator capable of generating a plurality of clocks having the same frequency and a phase shifted by a constant value, and outputting the plurality of clocks in parallel to the first stage;
Receiving the received data and the recovered clock, the phase of the received data is compared with the phase of the recovered clock, and the recovered clock generator is in a direction in which the phase of the recovered clock matches the phase of the received data In a clock recovery circuit having a feedback circuit for performing feedback control ,
The reproduction clock generator changes a selection state of a signal selection circuit of only one stage among the plurality of signal selection circuits forming a hierarchical structure when changing a selection state of an output signal. Clock recovery circuit.   The reproduction clock generator includes a state in which a first clock input to one first signal selection circuit in the first stage is selected as a reproduction clock, and another second signal in the first stage. 2. The state in which the second clock input to the selection circuit and selected from the first clock and the second clock whose phase is shifted by a certain value is selected as a reproduction clock by the signal selection circuit subsequent to the first stage. Clock recovery circuit.   Each has a plurality of signal selection circuits capable of selectively outputting one signal from a plurality of input signals, and the plurality of signal selection circuits have at least two signal selection circuits as the first stage, A regenerative clock generator capable of generating a regenerative clock by selecting a single input signal from a plurality of input signals supplied to the first stage, forming a hierarchical structure with the signal selection circuit as the final stage;
  An oscillator capable of generating a plurality of clocks having the same frequency and a phase shifted by a constant value, and outputting the plurality of clocks in parallel to the first stage;
  Receiving the received data and the recovered clock, the phase of the received data is compared with the phase of the recovered clock, and the recovered clock generator is in a direction in which the phase of the recovered clock matches the phase of the received data A feedback circuit for feedback control;
  A reproduction data generator capable of receiving the reception data and the reproduction clock and outputting the reception data in synchronization with the reproduction clock;
In the clock and data recovery circuit having
  The reproduction clock generator changes a selection state of a signal selection circuit of only one stage among the plurality of signal selection circuits forming a hierarchical structure when changing a selection state of an output signal. Clock and data recovery circuit.

Images