JP3808633B2 - FSK receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an FSK (Frequency Shift Keying) receiver, and more particularly to a quaternary FSK demodulating circuit used for an FSK digital radio receiver or the like.
[0002]
[Prior art]
Conventionally, an FSK receiver is known from, for example, Japanese Patent Laid-Open No. 9-214570.
FIG. 4 is a block diagram showing such a conventional FSK receiver.
This FSK receiver includes an antenna 30 that receives an FSK modulated wave signal, a local oscillator (VCO) 1 that outputs a local oscillation frequency that is the same frequency as the carrier of the FSK modulated wave signal, and a local oscillation frequency from the VCO 1. , A phase shifter 2 that changes the phase by 90 degrees, a mixer circuit 3a on the in-phase component (hereinafter referred to as I phase) side that mixes the FSK modulated wave signal from the antenna 30 and the local oscillation frequency from the VCO 1, and the FSK from the antenna 30. A mixer circuit 3b on the quadrature component (hereinafter referred to as Q phase) side for mixing the modulated wave signal and the local oscillation frequency phased 90 degrees by the phase shifter 2 is provided.
[0003]
In addition, this FSK receiver receives the I-phase low-pass filter 4a and the Q-phase low-pass filter 4b that output the I-phase and Q-phase, which are baseband signals by cutting high frequencies, and the I-phase is input and digitized. An I-phase comparator circuit 5a that outputs an I-phase comparator signal, a Q-phase comparator circuit 5b that inputs a Q-phase and outputs a 1-bit digitized Q-phase comparator signal, and receives an I-phase comparator signal to smooth the waveform The I-phase moving average circuit 6a for outputting the I-phase moving average signal, the Q-phase moving average circuit 6b for inputting the Q-phase comparator signal to smooth the waveform and outputting the Q-phase moving average signal, and the I-phase moving A phase angle detector 7 that receives the average signal and the Q-phase moving average signal, detects a phase angle by calculation of tan ⁻¹ Q / I, and outputs a phase angle signal.
[0004]
Furthermore, this FSK receiver detects a change point of a symbol sent from a base station by inputting a differentiator 8 that differentiates a phase angle signal and outputs a differential signal, and inputs an I-phase comparator signal and a Q-phase comparator signal. A phase detection circuit 12 for outputting a symbol change signal, a synchronization circuit 13 for inputting the symbol change signal and outputting a synchronization signal synchronized with a symbol transmitted from the base station, and a differential signal and a synchronization signal. An integral discharge circuit 10a that integrates the differential signal and discharges for each symbol in accordance with the synchronization signal, and outputs an integral discharge signal that means that the integral value in the positive direction is positive rotation and the integral value in the negative direction is negative rotation. With.
[0005]
Furthermore, this FSK receiver takes the absolute value of the differential signal and outputs the absolute value signal. The FSK receiver inputs the absolute value signal and the synchronizing signal, integrates the absolute value signal, and matches the synchronizing signal. An integrated discharge circuit 10b that discharges each symbol and outputs an integrated discharge signal that takes an absolute value, an integrated discharge signal, and an integrated discharge signal that takes an absolute value are input to perform quaternary determination, and a quaternary determination signal is output. And a quaternary determination circuit 11 for outputting.
[0006]
The operation of the conventional FSK receiver will be described below.
This description will be made according to the FLEX-TD system, which is an advanced radio paging standard as an example.
First, the frequency shift of the FLEX-TD system will be briefly described.
In the binary FSK system, the frequency shift is +4.8 kHz for 1-bit value “1” and −4.8 kHz for “0”.
In the case of the 4-level FSK system, the frequency shift is +4.8 kHz for the 2-bit value “10”, +1.6 kHz for “11”, −1.6 kHz for “01”, “00”. Is -4.8 kHz.
[0007]
The antenna 30 receives an FSK modulated wave signal.
The VCO 1 outputs a local oscillation frequency that is the same frequency as the carrier of the FSK modulated wave signal.
The phase shifter 2 inputs the local oscillation frequency, shifts the phase by 90 degrees, and outputs the local oscillation frequency shifted by 90 degrees.
In the I-phase mixer circuit 3a, a carrier signal and a local frequency are input and mixed, and an I-phase mixer signal is output.
In the Q-phase mixer circuit 3b, the local oscillation frequency whose phase is shifted by 90 degrees is input from the FSK modulated wave signal, mixing is performed, and a Q-phase mixer signal is output.
[0008]
As shown in FIG. 5, the I-phase low-pass filter 4a receives an I-phase mixer signal, removes high-frequency components, and outputs an I-phase (a) that is a baseband signal. The Q-phase low-pass filter 4b receives the Q-phase mixer signal, removes high-frequency components, and outputs the Q-phase (b) that is a baseband signal.
The I-phase (a) and Q-phase (b) waveforms are input to the I-phase comparator circuit 5a and the Q-phase comparator circuit 5b, respectively.
[0009]
The I-phase comparator circuit 5a receives the I-phase (a) signal, digitizes it by 1 bit, and outputs the I-phase comparator signal (c). Similarly, in the Q-phase comparator circuit 5b, the Q-phase (b) signal is input, digitized by 1 bit, and the (d) Q-phase comparator signal is output.
[0010]
The I-phase moving average circuit 6a receives the I-phase comparator signal, shapes the waveform, and outputs the I-phase moving average signal (e). The waveform shaping described here will be described with reference to FIG. 5 as an example using a 3-bit counter.
First, an I-phase comparator signal is input to the I-phase moving average circuit 6a. If the I phase is “1”, the counter value is increased, and if the counter value reaches the maximum, the counter value is stopped so as not to overflow. If the I phase is “0”, the counter value is decreased, and if the counter value is minimized, the counter value is stopped so as not to overflow.
[0011]
The I-phase moving average signal (I-phase smoothed signal) in FIG. 3 is an analog view of the signal output in the above operation. Since a 3-bit counter is used, it is stepped at 8 levels. In FIG. 5, the staircase shape is represented as an I-phase moving average signal (e) by an oblique line for convenience.
The Q-phase moving average circuit 6b performs the same operation as the I-phase moving average circuit 6a. A Q-phase comparator signal is input, the waveform is shaped, and the Q-phase moving average signal (f) is output.
[0012]
The phase angle detector 7 receives the I-phase moving average signal and the Q-phase moving average signal, detects the phase angle by calculating tan ⁻¹ Q / I, and outputs the phase angle signal (g). The actual diagonal line of the phase angle signal is a digital value that is stepped, but here it is an oblique straight line for convenience.
[0013]
The differentiator 8 differentiates the phase angle signal (g) and outputs a differentiated signal (h). The phase detection circuit 12 accurately captures the change point of the symbol sent from the base station from the I-phase comparator output and the Q-phase comparator output, and outputs a symbol change signal.
[0014]
The synchronization circuit 13 inputs the symbol change signal and outputs a synchronization signal synchronized with the symbol transmitted from the base station.
In the integral discharge circuit 10a, the differential signal is input and integrated, and the integral discharge signal (i) is output by the integral discharge circuit that discharges in accordance with the synchronization signal (symbol change). The diagonal line of the actual integrated discharge signal is a digital value and has a staircase shape, but here it is an oblique straight line for convenience.
[0015]
In the absolute value circuit 9, the differential signal is input to perform the absolute value calculation, the negative component of the differential signal is folded back to the positive side, and the absolute value signal (j) is output.
In the integral discharge circuit 10b, an absolute value signal is input and integrated, and an integral discharge circuit (k) that takes an absolute value is output in an integral discharge circuit that discharges in accordance with a synchronization signal (symbol change). The diagonal line of the actual integrated discharge signal is a digital value and has a staircase shape, but here it is an oblique straight line for convenience.
[0016]
In the quaternary determination circuit 11, an integrated discharge signal obtained by taking the absolute value of the integrated discharge signal is input and compared with a threshold value to perform quaternary determination, and +4.8 kHz, +1.6 kHz, −1.6 kHz, −4 Outputs a data quaternary determination signal of 10, 11, 01, 00 corresponding to .8 kHz.
[0017]
[Problems to be solved by the invention]
In the conventional FSK receiver, the I phase and the Q phase, which are usually 90 degrees out of phase, may change at the same time due to noise mixed in the received signal.
The operation of the FSK receiver in this case is as shown in the timing chart of FIG.
(1) The comparator signals (a) and (b) in which the I phase and the Q phase are changed simultaneously are input.
(2) The digital value shown in (c) and (d) is converted by a moving average circuit.
(3) When the ROM table of FIG. 7 is used for the phase angle detection circuit, the digital value shown in (e) is output.
(4) When this digital value is differentiated and a differential signal is output, in the case of digital processing in which the MSB (most significant bit) indicates a sign, 00H (H indicates a hexadecimal number) or a negative minimum as shown in (f) It becomes a digital value of 80H meaning the value.
That is, when the I phase and the Q phase change simultaneously, there is a problem that both positive rotation (increase in phase) and negative rotation (decrease in phase) are demodulated as negative rotation.
[0018]
In order to solve the above-mentioned problems, the present invention is provided with an I-phase and Q-phase simultaneous change detector, and detects that the I-phase and Q-phase rise simultaneously, thereby correcting the output of the differentiator to 00H. The purpose is to improve the sensitivity by canceling the output signal of the differentiator when the I-phase and Q-phase change at the same time and eliminating the erroneous determination that the data that is originally positive rotation is negative rotation. And
[0019]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention is an I homologous phase component obtained by mixing an FSK modulated wave signal with the same frequency, the same phase as the carrier, and a local oscillation frequency that is 90 degrees out of phase with the carrier, By obtaining and integrating a 1-bit digitized signal from the Q-phase quadrature component, a moving average signal is obtained to detect their phase angle, and a differential signal of this phase angle signal is integrated and sent from the base station. Obtained by integrating the integrated discharge signal obtained by discharging in accordance with the timing of the symbol and the absolute value of the differential signal of the phase angle signal, and discharging in accordance with the timing of the symbol sent from the base station. In the FSK receiver configured to perform quaternary determination based on the absolute value integrated discharge signal obtained,
A detection circuit (delay circuit 21a, 21b, exclusive OR circuit 22a, 22b, logical product circuit 23, delay circuit 25) for detecting a case where the I homologous phase component and the Q phase orthogonal component change simultaneously; and the detection When a detector detects that the I homologous phase component and the Q phase quadrature component have changed simultaneously, a cancel value setting device (selector 24) sets the value of the differential signal for obtaining the integrated discharge signal as a cancel value. ).
[0020]
In the embodiment of the present invention, as shown in FIG. 1, an antenna 30 that receives an FSK (Frequency Shift Keying) modulated wave signal, and a local oscillation frequency that is the same frequency as the carrier of the FSK modulated wave signal are output. The local oscillation unit VCO1 that performs the phase shifter 2 that changes the phase of the local oscillation frequency output by the local oscillation unit VCO1, and an I homologous phase component that mixes the FSK modulated wave signal with the local oscillation frequency (hereinafter referred to as I phase). ) Side mixer circuit 3a, QSK quadrature component (hereinafter referred to as Q phase) side mixer circuit 3b that mixes the local oscillation frequency whose phase is changed by 90 degrees with the FSK modulated wave signal, and a high frequency cut base I-phase low-pass filter 4a and Q-phase low-pass filter 4b that output band signal I-phase and Q-phase, and I-phase input An I-phase comparator circuit 5a for outputting a 1-bit digitized I-phase comparator signal, a Q-phase comparator circuit 5b for inputting a Q-phase and outputting a 1-bit digitized Q-phase comparator signal, and an I-phase comparator signal The I-phase moving average circuit 6a for smoothing the waveform and outputting the I-phase moving average signal, and the Q-phase moving average for smoothing the waveform and outputting the Q-phase moving average signal by inputting the Q-phase comparator signal A circuit 6b, a phase angle detector 7 that inputs an I-phase moving average signal and a Q-phase moving average signal, detects a phase angle by calculation of tan ⁻¹ Q / I, and outputs a phase angle signal; and a phase angle signal Is differentiated, and a differential signal is output, an I-phase comparator signal is input and delayed for a predetermined time, an I-phase delay circuit 21a that outputs an I-phase delay signal, and a Q-phase comparator signal is input and constant. Q-phase delay circuit 21b that outputs a Q-phase delay signal, an I-phase delay signal, and an I-phase comparator signal are input to perform an exclusive OR operation, and an I-phase exclusive OR signal is output. An I-phase exclusive OR circuit 22a, a Q-phase delay signal, and a Q-phase comparator signal are input to perform an exclusive-OR operation, and a Q-phase exclusive OR circuit 22b that outputs a Q-phase exclusive OR signal , An I-phase exclusive OR signal and a Q-phase exclusive OR signal are input to perform an AND operation and output an AND signal, and an AND signal is input to a differentiator. The delay circuit 25 delays the logical product signal in synchronization with the output of 8 and outputs a delay signal, and inputs the delay signal and the differential signal. When the delay signal is zero, the differential signal is 1 and the delay signal is 1 Selector 24 which outputs 00H at the time of the I phase comparator A phase detection circuit 12 for detecting a change point of a symbol sent from a base station by inputting a data signal and a Q-phase comparator signal and outputting a symbol change signal, and a symbol change signal being inputted and sent from the base station Synchronizing circuit 13 for outputting a synchronizing signal synchronized with a coming symbol, and integrating discharging circuit for inputting a differential signal and a synchronizing signal, integrating the differential signal, discharging each symbol according to the synchronizing signal, and outputting an integrated discharging signal 10a and 10b, and a quaternary determination circuit 11 that inputs an integrated discharge signal, performs quaternary determination, and outputs a quaternary determination signal.
[0021]
According to such a configuration, the detection circuit (delay circuit 21a, 21b, exclusive OR circuit 22a, 22b, logical product circuit 23, delay circuit) that detects the case where the I homologous phase component and the Q phase quadrature component change simultaneously. The circuit 25) and the cancel value setter (selector) constitute an erroneous determination prevention circuit 40, which prevents erroneous determination of positive rotation data as negative rotation data when the I phase and the Q phase change simultaneously. And sensitivity can be improved.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments will be described with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment.
In the block diagram shown in FIG. 1, the configuration from the antenna 30, the local oscillator 1 to the differentiator 8 is the same as that of the prior art shown in FIG.
[0023]
In the embodiment, the newly added misjudgment prevention circuit 40 receives the I-phase delay signal 21a, which outputs the I-phase delay signal by inputting the I-phase comparator signal, delays it for a predetermined time, and the Q-phase comparator signal. Q phase delay circuit 21b that inputs and delays for a certain time and outputs a Q phase delay signal, an I phase delay signal, and an I phase comparator signal are input to perform an exclusive OR operation, and an I phase exclusive Q phase that outputs an I-phase exclusive OR signal by inputting an I-phase exclusive OR circuit 22a that outputs a logical sum signal, a Q-phase delay signal, and a Q-phase comparator signal and performs an exclusive OR operation. And an exclusive OR circuit 22b.
[0024]
The erroneous determination prevention circuit 40 receives an I-phase exclusive OR signal and a Q-phase exclusive OR signal, performs an AND operation, and outputs an AND signal. When the product signal is input, the logical product signal is delayed in accordance with the output of the differentiator 8, the delay circuit 25 outputs the delay signal, the delay signal and the differential signal are input, and the delay signal is 0 And a selector 24 that outputs a differential signal and outputs 00H when the delay signal is 1.
[0025]
The FSK receiver receives the I-phase comparator signal and the Q-phase comparator signal, detects the change point of the symbol sent from the base station, and outputs the symbol change signal, and the symbol change signal. A synchronization circuit 13 that inputs and outputs a synchronization signal synchronized with a symbol sent from the base station, inputs a differential signal and a synchronization signal, integrates the differential signal, and discharges each symbol according to the synchronization signal. And an integrated discharge circuit 10a for outputting an integrated discharge signal.
[0026]
Furthermore, this FSK receiver inputs the differential signal and performs the absolute value calculation, and outputs the absolute value signal 9 and the absolute value signal and the synchronization signal to input the integral of the absolute value signal. An integrated discharge circuit 10b that discharges every symbol in accordance with the synchronization signal and outputs an integrated discharge signal that takes an absolute value, and inputs an integrated discharge signal that takes the integrated discharge signal and the absolute value, performs quaternary determination, and outputs four values. It comprises a quaternary determination circuit 11 that outputs a determination signal.
[0027]
Hereinafter, the operation of the embodiment will be described mainly focusing on the erroneous determination prevention circuit 40. The operations of the antenna 30 and the local oscillation unit 1 to the differentiator 8 are the same as those described in the related art, and thus description thereof is omitted here.
[0028]
The I-phase delay circuit 21a delays the I-phase comparator signal for a predetermined time and outputs an I-phase delay signal. The I-phase exclusive OR circuit 22a performs an exclusive-OR operation on the I-phase delay signal and the I-phase comparator signal. When the I-phase comparator signal (a) in FIG. A logical sum (EXOR) signal (c) is output.
[0029]
That is, the I-phase exclusive OR circuit 22a detects that the I-phase has changed between the I-phase delay circuit 21a and the I-phase exclusive OR circuit 22a, and normally outputs 0, and the I-phase comparator When the signal changes from 0 to 1, or from 1 to 0, 1 is output.
[0030]
The Q-phase delay circuit 21b delays the Q-phase comparator signal for a predetermined time and outputs a Q-phase delay signal. The Q-phase exclusive OR circuit 22b performs an exclusive-OR operation on the Q-phase delay signal and the Q-phase comparator signal. When the Q-phase comparator signal (b) in FIG. A logical sum (EXOR) signal (d) is output.
[0031]
That is, the Q-phase exclusive OR circuit 22b detects that the Q-phase has changed between the Q-phase delay circuit 21b and the Q-phase exclusive OR circuit 22b, and normally outputs 0, and the Q-phase comparator When the signal changes from 0 to 1, or from 1 to 0, 1 is output.
[0032]
A logical product (AND) circuit 23 inputs an I-phase exclusive OR (EXOR) signal and a Q-phase exclusive OR (EXOR) signal and outputs a logical product (and) signal (e). That is, the AND signal is a signal indicating that the I phase has changed at the same time, and normally outputs 0, and outputs 1 when the I phase and the Q phase change simultaneously.
[0033]
The delay circuit 25 delays the delays generated by the moving average circuits 6a and 6b, the phase angle detector 7 and the differentiation circuit 8 so as to cancel the data to be canceled of the differential signal, and takes the timing. And the delay signal (f) which took the timing is output.
[0034]
In the selector 24, the delayed signal (f) with timing and the differential signal are input, and when the delayed signal with timing is 0, the differential signal is output, and when the timing signal is 1, the digital value is 00H. The select signal (g) is output.
[0035]
The phase detection circuit 12 accurately captures the change point of the symbol sent from the base station from the I-phase comparator output and the Q-phase comparator output, and outputs a symbol change signal.
The synchronization circuit 13 inputs a symbol change signal and outputs a synchronization signal synchronized with a symbol transmitted from the base station.
[0036]
In the integral discharge circuit 10a, the differential signal and the synchronization signal are input and integrated, and the integral discharge circuit that discharges in accordance with the synchronization signal (symbol change) outputs the integral discharge signal. The diagonal line of the actual integrated discharge signal is a digital value and has a staircase shape, but here it is an oblique straight line for convenience.
[0037]
In the absolute value circuit 9, the differential signal is input and the absolute value is calculated, the negative component of the differential signal is folded back to the positive side, and the absolute value signal is output.
In the integral discharge circuit 10b, an absolute value signal and a synchronization signal are input and integrated, and further, an integral discharge circuit that discharges in accordance with the synchronization signal (change in symbol) outputs an integral discharge signal that takes an absolute value. . The diagonal line of the actual integrated discharge signal is a digital value and has a staircase shape, but here it is an oblique straight line for convenience.
[0038]
The quaternary determination circuit 11 inputs an integrated discharge signal and an integrated discharge signal obtained as an absolute value, compares the threshold value with each other, performs quaternary determination, and +4.8 kHz, +1.6 kHz, −1.6 kHz, − A data quaternary determination signal of 10, 11, 01, 00 corresponding to 4.8 kHz is output.
[0039]
【The invention's effect】
As described above in detail, according to the present invention, a detection circuit that detects a case where the I homologous phase component and the Q phase quadrature component are changed simultaneously, and the detector uses the detector to detect the I homologous phase component and the Q phase quadrature component. And a cancel value setter for setting the value of the differential signal for obtaining the integrated discharge signal to a cancel value when it is detected that the change is simultaneously changed. It is possible to eliminate the erroneous determination that the operation is performed, and the sensitivity can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the embodiment of the present invention.
FIG. 3 is a timing chart showing an I-phase moving average signal (I-phase smoothed signal).
FIG. 4 is a block diagram showing a conventional FSK receiver.
FIG. 5 is a timing chart showing the operation of the prior art.
FIG. 6 is a timing chart for illustrating the operation of the prior art.
FIG. 7 is a diagram illustrating a ROM table of a phase angle detection circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Local oscillation part 2 Phaser 3a, 3b Mixer circuit 4a, 4b Low pass filter 5a, 5b Comparator 6a, 6b Moving average circuit 7 Phase angle detector 8 Differentiator 9 Absolute value circuit 10a, 10b Integral discharge circuit 11 Four value judgment circuit 12 phase detection circuit 13 synchronization circuit 21a, 21b, 25 delay circuit 22a, 22b exclusive OR circuit 23 AND circuit 40 erroneous determination prevention circuit

Claims (1)

A 1-bit digitized signal is obtained from the I homologous phase component and Q phase quadrature component obtained by mixing the FSK modulated wave signal with the local oscillation frequency that is the same frequency and phase as the carrier and 90 degrees out of phase. Integration to obtain a moving average signal, detect their phase angle, integrate the differential signal of this phase angle signal, and discharge at the timing of the symbol sent from the base station Based on the discharge signal and the absolute value of the differential signal of the phase angle signal and integrating, the four-value determination is made based on the absolute value integrated discharge signal obtained by discharging in accordance with the timing of the symbol sent from the base station. In the FSK receiver designed to perform
A detection circuit for detecting the case where the I homologous phase component and the Q phase quadrature component are changed simultaneously, and when the detector detects that the I homologous phase component and the Q phase quadrature component are changed simultaneously, An FSK receiver comprising: a cancel value setter that sets a value of a differential signal for obtaining the integrated discharge signal as a cancel value.

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