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JP3881079B2 - Semiconductor integrated circuit element - Google Patents

Semiconductor integrated circuit element Download PDF

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Publication number
JP3881079B2
JP3881079B2 JP06090597A JP6090597A JP3881079B2 JP 3881079 B2 JP3881079 B2 JP 3881079B2 JP 06090597 A JP06090597 A JP 06090597A JP 6090597 A JP6090597 A JP 6090597A JP 3881079 B2 JP3881079 B2 JP 3881079B2
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mos transistor
source
circuit
semiconductor integrated
current
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JPH10256606A (en
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俊幸 岡安
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Advantest Corp
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Advantest Corp
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Priority to TW087103652A priority patent/TW391062B/en
Priority to US09/041,960 priority patent/US6396610B1/en
Priority to KR1019980008618A priority patent/KR100271432B1/en
Priority to DE19811296A priority patent/DE19811296A1/en
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/78Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
    • H03K17/785Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling field-effect transistor switches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Led Devices (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
  • Light Receiving Elements (AREA)
  • Optical Communication System (AREA)
  • Electronic Switches (AREA)

Description

【0001】
【発明の属する技術分野】
この発明は例えば装置間を光伝送路によって接続し、光信号を授受して装置を動作させるような場合に用いて好適な半導体集積回路素子に関する。
【0002】
【従来の技術】
装置間において、信号の授受速度を高速化するために光信号を用いる場合がある。従来は図12に示すように送信側装置Aから受信側装置Bに光信号でデータを伝送する場合は、送信側装置Aに発光素子11と発光素子駆動回路12を設け、この発光素子駆動回路12に信号源となる集積回路素子13から駆動信号を与え、その駆動信号を発光素子11で光信号に変換し、その光信号を光ファイバから成る光伝送路14で伝送する方式が採られる。
【0003】
受信側装置Bには受光素子15と、光電流検出回路16と、送られて来た信号を取り込んで処理する半導体集積回路素子17とが設けられ、送信側装置A側から送られて来た信号を受け取って信号を処理する動作を行う。
【0004】
【発明が解決しようとする課題】
従来は半導体集積回路素子13及び17の他に、発光素子駆動回路12と光電流検出回路16を別にして設けているため、この発光素子駆動回路12と光電流検出回路16を格納するためにスペースを要し、また電力消費量も多くなる欠点がある。特に装置AとBの間で数100〜数1000チャンネルに及ぶチャンネル数で光伝送路を設ける場合には、これらの発光素子駆動回路12と光電流検出回路16を格納するためのスペースも大きくなり、装置AとBを小型化する上で障害になる。
【0005】
この発明の目的は装置間のチャンネル数が多くても発光素子駆動回路及び光電流検出回路を格納するスペースを小さくし、且つ駆動回路、検出回路と信号処理を行う集積回路とを一体化することによって、これらの間の信号伝送に係る電力を無くすことにより電力消費量も小さくできる機能を備えた半導体集積回路を提供しようとするものである。
【0006】
【課題を解決するための手段】
この発明の半導体集積回路素子は光電流検出回路であり、他端が受光素子の受光素子接続端子とされる第1定電流源の一端が一方の電源に接続され、ソースが他方の電源に接続される第1のMOSトランジスタのドレインとゲートが第1定電流源の他端に接続され、第1のMOSトランジスタと同極性の第2のMOSトランジスタが、そのゲートを第1のMOSトランジスタのゲートに接続し、そのソースが他方の電源に接続されて第1のMOSトランジスタとカレントミラー回路を構成する
【0007】
第2のMOSトランジスタと極性の異なる第3のMOSトランジスタのゲートとドレインが第2のMOSトランンジスタのドレインに接続され、ソースが一方の電源に接続され、第3のMOSトランジスタと同極性の第4のMOSトランジスタが、そのゲートを第3のMOSトランジスタのゲートに接続されて第3のMOSトランジスタとカレントミラー回路を構成する。
【0008】
この発明の構成によれば、信号源となる半導体集積回路素子或いは信号処理回路を構成する半導体集積回路素子の内部に光電流検出回路を組み込んだ構造としたから、半導体集積回路素子に設けた受光素子接続端子に受光素子を接続するだけでよい。
【0009】
従って半導体集積回路素子と受光素子の部品だけで構成できるため、占有スペースを小さくすることができる。また、光電流検出回路を半導体集積回路の特にCMOS構造の半導体集積回路に形成することはより消費電力を小さくできる利点が得られる。
【0010】
【発明の実施の形態】
図1にこの発明の概念を説明するための構成図を示す。この例では、装置Aから装置Bに光信号を伝送し、装置B側で受信した信号を処理する場合を示す。
このため送信側装置Aには、この発明による半導体集積回路素子20と発光素子11とが設けられ、受信機装置Bには受光素子15と、この発明による半導体集積回路素子30とが設けられる。装置AとBの間には光コネクタ14Aと14Bを介して、例えば光ファイバで構成される光伝送路14が接続される。
【0011】
送信側装置Aに設けられるこの発明による半導体集積回路素子20には、受信側装置Bに伝送すべき信号を発生する信号源回路21と発光素子駆動回路22とが同一の半導体チップ内に形成される。更に、半導体集積回路素子20には、発光素子駆動回路22の出力端子に接続された発光素子接続端子23が設けられる。従って発光素子11は、この発光素子接続端子23と電源端子24との間に接続することにより配線が完了する。
【0012】
装置B側では受光素子15と、この発明による半導体集積回路素子30とが設けられる。この発明による半導体集積回路素子30は信号処理回路31と、光電流検出回路32と、受光素子接続端子33とを有し、信号処理回路31と光電流検出回路32とが同一半導体チップ内に形成される。受光素子15は受光素子接続端子33と電源端子34の間に接続され配線が完了する。
【0013】
図1に示す送信側装置Aに設けた半導体集積回路素子20は、この出願の請求項1で提案する半導体集積回路素子の構成を具備し、受信側装置Bに設けた半導体集積回路素子30がこの出願の請求項3で提案する半導体集積回路素子の構成を具備するものである。
図2は半導体集積回路素子20と30に設ける発光素子駆動回路22と光電流検出回路32の回路構造を具体的に示す。一般に半導体集積回路はCMOS構造により構成される。従って、発光素子駆動回路22と光電流検出回路32をCMOSによって構成した場合を示す。
【0014】
図2に示す発光素子駆動回路22は電界効果トランジスタ(以下単にトランジスタと称す)Q11とQ12を差動接続し、発光素子が消光状態となるためにはトランジスタQ11をオンに、またトランジスタQ12をオフの状態に維持させる。トランジスタQ12のドレインは発光素子接続端子23に接続される。トランジスタQ11とQ12のゲートには信号源回路21から差動的に変化する信号が与えられる。この結果、トランジスタQ11がオフに反転するのと同時にトランジスタQ12がオンとなり、発光素子11に駆動電流を流し発光させる。
【0015】
このように、差動回路によって発光素子11を駆動させることにより、トランジスタQ11に流れていた電流が、トランジスタQ12に切替わるだけの動作で発光素子11を発光させるから、発光素子11に流れる電流の立ち上がりが速く、高速動作が期待できる。なお、発光素子接続端子23に接続した定電流回路25は発光素子11に一定のバイアス電流を流すために設けた定電流回路である。つまり、発光素子11が例えばレーザダイオードの場合は、レーザダイオードに発光閾値近くの電流をバイアス電流として流しておき、トランジスタQ1に電流を流すことによって発光量を変化させるための回路である。
【0016】
受信装置B側に設けた光電流検出回路32も同様にCMOS回路によって構成される。トランジスタQ21,Q22と、Q23,Q24及びQ25,Q26はそれぞれカレントミラー回路を構成している。この光電流検出回路32の特徴は、入力インピーダンスが極力小さくなるように構成している点である。つまり、入力インピーダンスを低くすることにより受光素子15のアノード・カソード間に存在する容量C1と、受光素子接続端子33と共通電位点との間に存在する浮遊容量C2による影響を軽減し、高速動作を可能とした回路構成としたものである。
【0017】
この回路は電流比較回路として動作し、基準電流Ithと、トランジスタQ21を流れる電流I1 =(光電流Iin+バイアス電流Ibias)とを比較することによって出力端子OUTからパルス信号Pを出力する。つまり、図3Aに示すようにトランジスタQ13を流れる電流I1 =(光電流Iin+Ibias)が基準電流Ithを越えると、出力端子OUTの電位は上昇し、出力端子OUTに図3Cに示すパルスPが出力される。尚、カレントミラーの比率は1として説明したが、必要に応じて倍率を設けることもできる。
【0018】
また、この図2に示す光電流検出回路32は使用するトランジスタQ21〜Q26の中のPチャンネル型(Q23,Q24)とNチャンネル型(Q21,Q22,Q25,Q26)の特性に製造偏差、或いは環境温度変動により相対的にずれを生じた場合に、タイミング精度に影響を受けることが少なくなるように、回路を極力対称形に構成している。この結果、定電流のIth及びIbiasを流す電流源のペア性及びトランジスタQ21,Q22によって構成されるカレントミラーとトランジスタQ25,Q26によって構成されるカレントミラーのペア性はよく、製造偏差や環境温度変動によっても、これらのレシオ特性は保たれる。よって無調整で歩留まりがよく、動作環境に対して安定に精度を保つことができる。
【0019】
図4乃至図7に発光素子駆動回路22の変形例を示す。図4は図2に示した発光素子駆動回路22と比較して構成を簡素化した実施例を示す。この実施例ではトランジスタQ11は電流スイッチとして動作し、トランジスタQ12はトランジスタQ12を流れる駆動電流の値を任意の値に設定するための可変抵抗器として動作する。
【0020】
トランジスタQ11は発光素子11を発光させるときだけオンとなり、発光素子11に電流を流す。このため、図2に示す発光素子駆動回路22より電力消費量を少なくできる利点が得られる。
図5に示す発光素子駆動回路22は電源電圧を低くしたい場合に有効な回路例である。つまり、この図5に示す回路では、電源電圧+Vと−Vとの間に発光素子11とトランジスタQ14を直列接続とし、発光素子11とトランジスタQ14から成る直列回路に電源電圧+Vと−Vを印加する構造としたもので、図4と比較すれば明らかなようにトランジスタQ14に印加できる電圧を高く採ることができ、高速動作に適している。
【0021】
図6は図4と図5の特徴とする点を組合せた回路構造とした例である。図7は最も単純な回路構造とした例である。この回路はCMOS回路のインバータによって簡単に駆動できる特徴を有し、更にIC内において占有面積を少なくできる利点もあり、多チャンネル化の場合に適している。
図8乃至図10に光電流検出回路32の変形実施例を示す。図8に示す光電流検出回路32は図2に示した電流検出回路を簡略化した回路例である。この図8の場合も、トランジスタQ21に流れる電流I1 =(Iin+Ibias)が基準電流Ithより大きくなると、出力端子OUTにパルスPを出力する。
【0022】
図9の例ではIC内に抵抗を形成できる場合の例である。トランジスタQ21及びQ22は入力インピーダンスを下げることによって受光素子15に形成される容量及び浮遊容量等により動作速度が劣化することを防ぐことを目的としたゲート接地回路である。トランジスタQ25,Q26は抵抗に置き換えることができる。トランジスタQ25,Q26を抵抗とした場合は、出力振幅は小さくなるが、動作を高速化することができ、差動出力を得ることができる。この図9の場合も、トランジスタQ21を流れる電流I1 =(Iin+Ibias)が基準電流Ithより大きくなると、Pチャンネル型トランジスタQ24の電流が増加し、その電流の増加によって出力端子OUTにパルスPを出力する。
【0023】
図10は図2,図8,図9で用いた基準電流Ithの代わりに、基準電圧Vthを用いた場合を示す。この図10に示す回路では、受光によって入力電流Iinが増加し、抵抗器Rd1に発生する電圧Vd1が基準電圧Vthより下がると、トランジスタQ22の電流が減少し、代わってトランジスタQ23の電流I2 が増加し、この電流I2 の増加により出力端子OUTにパルスPを出力する。トランジスタQ24とQ25は図9の場合と同様に抵抗としてもよい。
【0024】
図11は半導体集積回路素子に発光素子駆動回路22と、光電流検出回路32の双方を備えた場合の実施例を示す。40は発光素子駆動回路22と光電流検出回路32の双方を備えた半導体集積回路素子を示す。
この半導体集積回路素子40にはそれぞれに発光素子接続端子23と、受光素子接続端子33と、発光素子駆動回路22,光電流検出回路32を具備し、各発光素子接続端子23に発光素子11を接続し、受光素子接続端子33に受光素子15を接続し、発光素子11と受光素子15の間は光ファイバのような光伝送路14が接続されて、信号の授受を行う。
【0025】
各半導体集積回路素子40に発光素子接続端子23と受光素子接続端子33を例えば数100チャンネル分ずつ備えた半導体集積回路素子を用意することにより、この半導体集積回路素子を数個用意すればIC試験装置の例えば主試験装置とテストヘッド間の信号の伝送に利用することができる。
【0026】
【発明の効果】
以上説明したように、この発明によれば半導体集積回路素子の内部に発光素子駆動回路22,電流検出回路32をそれぞれ収納した構成としたから、半導体集積回路素子の外部に別体でこれらの回路22及び32を設ける必要がない。よって、多チャンネルの信号の授受を光信号で行うように構成する場合に適用することにより、装置の小型化と、低電力化がはかられる利点が得られる。
【図面の簡単な説明】
【図1】この発明の一実施例を説明するためのブロック図。
【図2】図1に示した実施例の要部の具体例を示す接続図。
【図3】図2に示した具体的回路の動作を説明するための波形図。
【図4】図2に示した発光素子駆動回路の変形例を示す接続図。
【図5】図4と同様の接続図。
【図6】図4と同様の接続図。
【図7】図4と同様の接続図。
【図8】図2に示した電流検出回路の変形例を示す接続図。
【図9】図8と同様の接続図。
【図10】図8と同様の接続図。
【図11】半導体集積回路素子に発光素子駆動回路と電流検出回路の双方を備えた場合の構成例を説明するためのブロック図。
【図12】
従来の技術を説明するためのブロック図。
【符号の説明】
A 送信側装置
B 受信側装置
11 発光素子
14 光伝送路
15 受光素子
20 半導体集積回路素子
21 信号源回路
22 発光素子駆動回路
23 発光素子接続端子
30 半導体集積回路素子
31 信号処理回路
32 光電流検出回路
33 受光素子接続端子
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit element suitable for use when, for example, devices are connected by an optical transmission line and an optical signal is exchanged to operate the device.
[0002]
[Prior art]
In some cases, an optical signal is used in order to increase the signal transmission / reception speed between apparatuses. Conventionally, as shown in FIG. 12, when data is transmitted as an optical signal from the transmission side apparatus A to the reception side apparatus B, the light emitting element 11 and the light emitting element driving circuit 12 are provided in the transmission side apparatus A, and this light emitting element driving circuit is provided. 12, a drive signal is given from an integrated circuit element 13 serving as a signal source, the drive signal is converted into an optical signal by the light emitting element 11, and the optical signal is transmitted through an optical transmission line 14 made of an optical fiber.
[0003]
The receiving side device B is provided with a light receiving element 15, a photocurrent detection circuit 16, and a semiconductor integrated circuit element 17 for receiving and processing the transmitted signal, and sent from the transmitting side device A side. An operation of receiving a signal and processing the signal is performed.
[0004]
[Problems to be solved by the invention]
Conventionally, in addition to the semiconductor integrated circuit elements 13 and 17, the light emitting element driving circuit 12 and the photocurrent detection circuit 16 are provided separately. In order to store the light emitting element driving circuit 12 and the photocurrent detection circuit 16. There is a disadvantage that it requires space and power consumption is increased. In particular, when an optical transmission line is provided between the devices A and B with a number of channels ranging from several hundred to several thousand channels, a space for storing the light emitting element driving circuit 12 and the photocurrent detection circuit 16 becomes large. This is an obstacle to downsizing the devices A and B.
[0005]
The object of the present invention is to reduce the space for storing the light emitting element driving circuit and the photocurrent detection circuit even if the number of channels between the devices is large, and to integrate the driving circuit, the detection circuit and the integrated circuit for signal processing. Accordingly, an object of the present invention is to provide a semiconductor integrated circuit having a function of reducing the power consumption by eliminating the power related to signal transmission between them.
[0006]
[Means for Solving the Problems]
The semiconductor integrated circuit element of the present invention is a photocurrent detection circuit, one end of a first constant current source whose other end is a light receiving element connection terminal of the light receiving element is connected to one power source, and the source is connected to the other power source The drain and gate of the first MOS transistor are connected to the other end of the first constant current source, and the second MOS transistor having the same polarity as the first MOS transistor has its gate connected to the gate of the first MOS transistor. And the source thereof is connected to the other power supply to form a current mirror circuit with the first MOS transistor .
[0007]
The gate and drain of a third MOS transistor having a polarity different from that of the second MOS transistor are connected to the drain of the second MOS transistor, the source is connected to one power source, and the same polarity as that of the third MOS transistor. Four MOS transistors have their gates connected to the gate of the third MOS transistor to form a current mirror circuit with the third MOS transistor.
[0008]
According to this structure, because the internal incorporating photocurrent detection circuit to the structure of a semiconductor integrated circuit elements constituting the semiconductor integrated circuit device or the signal processing circuit comprising a signal source, received provided in the semiconductor integrated circuit device it is only necessary to connect the light receiving element to an optical element connection terminal.
[0009]
Accordingly, since the semiconductor integrated circuit element and the light receiving element can be configured only with parts, the occupied space can be reduced. Furthermore, an advantage particularly capable of reducing power consumption more be formed on the semiconductor integrated circuit of CMOS structure of the semiconductor integrated circuit photocurrent detection circuit is obtained.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram for explaining the concept of the present invention. In this example, an optical signal is transmitted from the device A to the device B, and the signal received on the device B side is processed.
For this reason, the transmitting apparatus A is provided with the semiconductor integrated circuit element 20 and the light emitting element 11 according to the present invention, and the receiver apparatus B is provided with the light receiving element 15 and the semiconductor integrated circuit element 30 according to the present invention. Between the apparatuses A and B, an optical transmission line 14 made of, for example, an optical fiber is connected via optical connectors 14A and 14B.
[0011]
In the semiconductor integrated circuit element 20 according to the present invention provided in the transmission side apparatus A, a signal source circuit 21 for generating a signal to be transmitted to the reception side apparatus B and a light emitting element driving circuit 22 are formed in the same semiconductor chip. The Further, the semiconductor integrated circuit element 20 is provided with a light emitting element connection terminal 23 connected to the output terminal of the light emitting element driving circuit 22. Therefore, the wiring of the light emitting element 11 is completed by connecting between the light emitting element connection terminal 23 and the power supply terminal 24.
[0012]
On the device B side, a light receiving element 15 and a semiconductor integrated circuit element 30 according to the present invention are provided. The semiconductor integrated circuit element 30 according to the present invention has a signal processing circuit 31, a photocurrent detection circuit 32, and a light receiving element connection terminal 33. The signal processing circuit 31 and the photocurrent detection circuit 32 are formed in the same semiconductor chip. Is done. The light receiving element 15 is connected between the light receiving element connection terminal 33 and the power supply terminal 34 to complete the wiring.
[0013]
The semiconductor integrated circuit element 20 provided in the transmission side apparatus A shown in FIG. 1 has the configuration of the semiconductor integrated circuit element proposed in claim 1 of this application, and the semiconductor integrated circuit element 30 provided in the reception side apparatus B includes The semiconductor integrated circuit device proposed in claim 3 of this application is provided.
FIG. 2 specifically shows the circuit structure of the light emitting element driving circuit 22 and the photocurrent detection circuit 32 provided in the semiconductor integrated circuit elements 20 and 30. In general, a semiconductor integrated circuit has a CMOS structure. Therefore, the case where the light emitting element driving circuit 22 and the photocurrent detection circuit 32 are constituted by CMOS is shown.
[0014]
The light emitting element driving circuit 22 shown in FIG. 2 connects field effect transistors (hereinafter simply referred to as transistors) Q11 and Q12 in a differential manner, and the transistor Q11 is turned on and the transistor Q12 is turned off in order for the light emitting element to be in the extinction state. To maintain the state. The drain of the transistor Q12 is connected to the light emitting element connection terminal 23. A differentially changing signal is applied from the signal source circuit 21 to the gates of the transistors Q11 and Q12. As a result, the transistor Q12 is turned on at the same time as the transistor Q11 is turned off, and a driving current is supplied to the light emitting element 11 to emit light.
[0015]
In this manner, by driving the light emitting element 11 by the differential circuit, the current flowing in the transistor Q11 causes the light emitting element 11 to emit light by simply switching to the transistor Q12. Fast start-up and high-speed operation can be expected. The constant current circuit 25 connected to the light emitting element connection terminal 23 is a constant current circuit provided to allow a constant bias current to flow through the light emitting element 11. That is, when the light emitting element 11 is, for example, a laser diode, this is a circuit for causing the current near the light emission threshold to flow through the laser diode as a bias current and changing the light emission amount by flowing the current through the transistor Q1.
[0016]
Similarly, the photocurrent detection circuit 32 provided on the receiving device B side is also constituted by a CMOS circuit. Transistors Q21 and Q22, Q23 and Q24, and Q25 and Q26 each constitute a current mirror circuit. The feature of the photocurrent detection circuit 32 is that the input impedance is configured to be as small as possible. That is, by reducing the input impedance, the influence of the capacitance C1 existing between the anode and the cathode of the light receiving element 15 and the stray capacitance C2 existing between the light receiving element connection terminal 33 and the common potential point is reduced, and high speed operation is achieved. This is a circuit configuration that enables the above.
[0017]
This circuit operates as a current comparison circuit, and outputs the pulse signal P from the output terminal OUT by comparing the reference current I th with the current I 1 flowing through the transistor Q21 = (photocurrent I in + bias current I bias ). To do. That is, as shown in FIG. 3A, when the current I 1 flowing through the transistor Q13 = (photocurrent I in + I bias ) exceeds the reference current I th , the potential of the output terminal OUT rises, and the output terminal OUT is shown in FIG. 3C. A pulse P is output. Although the ratio of the current mirror has been described as 1, the magnification can be provided as necessary.
[0018]
Further, the photocurrent detection circuit 32 shown in FIG. 2 has a manufacturing deviation in the characteristics of the P channel type (Q23, Q24) and the N channel type (Q21, Q22, Q25, Q26) in the transistors Q21 to Q26 used. The circuit is configured as symmetrically as possible so that it is less affected by timing accuracy when a relative deviation occurs due to environmental temperature fluctuations. As a result, the pair property of the current source that flows the constant currents I th and I bias and the pair property of the current mirror composed of the transistors Q21 and Q22 and the current mirror composed of the transistors Q25 and Q26 are good, and manufacturing deviation and environment These ratio characteristics are maintained even by temperature fluctuations. Therefore, no adjustment is required, the yield is good, and the accuracy can be stably maintained with respect to the operating environment.
[0019]
4 to 7 show modification examples of the light emitting element driving circuit 22. FIG. 4 shows an embodiment in which the configuration is simplified as compared with the light emitting element driving circuit 22 shown in FIG. In this embodiment, the transistor Q11 operates as a current switch, and the transistor Q12 operates as a variable resistor for setting the value of the drive current flowing through the transistor Q12 to an arbitrary value.
[0020]
The transistor Q11 is turned on only when the light emitting element 11 emits light, and a current flows through the light emitting element 11. Therefore, an advantage that the power consumption can be reduced as compared with the light emitting element driving circuit 22 shown in FIG.
The light emitting element driving circuit 22 shown in FIG. 5 is an effective circuit example when it is desired to lower the power supply voltage. That is, in the circuit shown in FIG. 5, the light emitting element 11 and the transistor Q14 are connected in series between the power supply voltages + V and −V, and the power supply voltages + V and −V are applied to the series circuit including the light emitting element 11 and the transistor Q14. As can be seen from a comparison with FIG. 4, the voltage that can be applied to the transistor Q14 can be made high, which is suitable for high-speed operation.
[0021]
FIG. 6 shows an example of a circuit structure in which the characteristic points of FIGS. 4 and 5 are combined. FIG. 7 shows an example of the simplest circuit structure. This circuit has a feature that it can be easily driven by an inverter of a CMOS circuit, and further has an advantage that an occupied area can be reduced in the IC, and is suitable for the case of multi-channeling.
8 to 10 show modified embodiments of the photocurrent detection circuit 32. FIG. A photocurrent detection circuit 32 shown in FIG. 8 is a circuit example in which the current detection circuit shown in FIG. 2 is simplified. Also in the case of FIG. 8, when the current I 1 = (I in + I bias ) flowing through the transistor Q21 becomes larger than the reference current I th , the pulse P is output to the output terminal OUT.
[0022]
The example in FIG. 9 is an example in which a resistor can be formed in the IC. Transistors Q21 and Q22 are grounded gate circuits for the purpose of preventing the operating speed from being deteriorated due to the capacitance formed in the light receiving element 15, the stray capacitance, etc. by lowering the input impedance. Transistors Q25 and Q26 can be replaced by resistors. When the transistors Q25 and Q26 are resistors, the output amplitude is small, but the operation can be speeded up and a differential output can be obtained. Also in the case of FIG. 9, when the current I 1 = (I in + I bias ) flowing through the transistor Q21 becomes larger than the reference current I th, the current of the P-channel transistor Q24 increases, and the current increases to the output terminal OUT. The pulse P is output.
[0023]
FIG. 10 shows a case where the reference voltage V th is used instead of the reference current I th used in FIGS. In the circuit shown in FIG. 10, the input current I in is increased by the light, the voltage Vd1 generated in the resistor Rd1 falls below the reference voltage V th, decreases the current of the transistor Q22 is, the transistor Q23 instead current I 2 increases, and a pulse P is output to the output terminal OUT due to the increase in the current I 2 . The transistors Q24 and Q25 may be resistors as in the case of FIG.
[0024]
FIG. 11 shows an embodiment in which a semiconductor integrated circuit element is provided with both a light emitting element driving circuit 22 and a photocurrent detection circuit 32. Reference numeral 40 denotes a semiconductor integrated circuit element including both the light emitting element driving circuit 22 and the photocurrent detection circuit 32.
Each of the semiconductor integrated circuit elements 40 includes a light emitting element connection terminal 23, a light receiving element connection terminal 33, a light emitting element drive circuit 22, and a photocurrent detection circuit 32, and the light emitting element 11 is connected to each light emitting element connection terminal 23. The light receiving element 15 is connected to the light receiving element connection terminal 33, and an optical transmission line 14 such as an optical fiber is connected between the light emitting element 11 and the light receiving element 15 to exchange signals.
[0025]
By preparing semiconductor integrated circuit elements each having, for example, several hundred channels of light emitting element connection terminals 23 and light receiving element connection terminals 33 in each semiconductor integrated circuit element 40, an IC test can be performed by preparing several semiconductor integrated circuit elements. It can be used for transmission of signals between the main test device and the test head of the device.
[0026]
【The invention's effect】
As described above, according to the present invention, since the light emitting element driving circuit 22 and the current detection circuit 32 are respectively housed in the semiconductor integrated circuit element, these circuits are separately provided outside the semiconductor integrated circuit element. There is no need to provide 22 and 32. Therefore, by applying to a configuration in which transmission / reception of multi-channel signals is performed using an optical signal, there is an advantage that the apparatus can be reduced in size and power can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining an embodiment of the present invention.
FIG. 2 is a connection diagram showing a specific example of a main part of the embodiment shown in FIG.
3 is a waveform diagram for explaining the operation of the specific circuit shown in FIG. 2;
4 is a connection diagram illustrating a modification of the light-emitting element driving circuit shown in FIG. 2;
5 is a connection diagram similar to FIG.
6 is a connection diagram similar to FIG.
7 is a connection diagram similar to FIG.
FIG. 8 is a connection diagram showing a modification of the current detection circuit shown in FIG. 2;
9 is a connection diagram similar to FIG.
10 is a connection diagram similar to FIG.
FIG. 11 is a block diagram for explaining a configuration example in the case where a semiconductor integrated circuit element is provided with both a light emitting element driving circuit and a current detection circuit.
FIG.
The block diagram for demonstrating the prior art.
[Explanation of symbols]
A Transmission side device B Reception side device 11 Light emitting element 14 Optical transmission line 15 Light receiving element 20 Semiconductor integrated circuit element 21 Signal source circuit 22 Light emitting element drive circuit 23 Light emitting element connection terminal 30 Semiconductor integrated circuit element 31 Signal processing circuit 32 Photocurrent detection Circuit 33 light receiving element connection terminal

Claims (3)

一端が一方の電源に接続され、他端が受光素子接続端子とされる第1定電流源と、
上記第1定電流源の他端にドレインとゲートが接続され、ソースが他方の電源に接続される第1のMOSトランジスタと、
上記第1のMOSトランジスタのゲートにゲートが接続され、ソースが上記他方の電源に接続され、上記第1のMOSトランジスタと同極性でこの第1のMOSトランジスタとカレントミラー回路を構成する第2のMOSトランジスタと、
上記第2のMOSトランジスタのドレインにドレインとゲートが接続され、ソースが上記一方の電源に接続され、上記第2のMOSトランジスタと極性の異なる第3のMOSトランジスタと、
上記第3のMOSトランジスタと同極性でこの第3のMOSトランジスタのゲートにゲートが接続され、この第3のMOSトランジスタとカレントミラー回路を構成する第4のMOSトランジスタと、
を具備し、上記第1のMOSトランジスタに流れる上記第1定電流源の電流に上記受光素子からの光電流が重畳された電流と、基準電流I th とを比較してパルス信号を得る光電流検出回路を構成したことを特徴とする半導体集積回路素子。
A first constant current source having one end connected to one power source and the other end serving as a light receiving element connection terminal;
A first MOS transistor having a drain and a gate connected to the other end of the first constant current source and a source connected to the other power supply;
A gate is connected to the gate of the first MOS transistor, a source is connected to the other power supply, and the second MOS transistor has the same polarity as the first MOS transistor and forms a current mirror circuit with the first MOS transistor. A MOS transistor;
A drain and a gate connected to the drain of the second MOS transistor, a source connected to the one power source, a third MOS transistor having a polarity different from that of the second MOS transistor;
A fourth MOS transistor having the same polarity as the third MOS transistor and having a gate connected to the gate of the third MOS transistor, and forming a current mirror circuit with the third MOS transistor;
Comprising a photoelectric current obtained with current optical current is superimposed from the first flowing through the MOS transistor of the first said light receiving element to the current of the constant current source, a pulse signal by comparing the reference current I th A semiconductor integrated circuit element comprising a detection circuit .
一端が一方の電源に接続され、他端が受光素子接続端子とされる第1定電流源と、
上記第1定電流源の他端にソースが接続され、ドレインが第1の抵抗を介して他方の電源に接続され、ゲートにバイアス電圧Vbが印加される第1のMOSトランジスタと、
上記第1のMOSトランジスタのドレインの電圧と基準電圧V th との差動で動作する差動回路と、
を具備した光電流検出回路を構成したことを特徴とする半導体集積回路素子。
A first constant current source having one end connected to one power source and the other end serving as a light receiving element connection terminal;
A first MOS transistor having a source connected to the other end of the first constant current source, a drain connected to the other power source via a first resistor, and a bias voltage Vb applied to the gate;
A differential circuit that operates differentially between a drain voltage of the first MOS transistor and a reference voltage Vth ;
A semiconductor integrated circuit device comprising a photocurrent detection circuit comprising:
請求項2に記載の半導体集積回路素子において、
一端が上記一方の電源に接続され、他端が第2のMOSトランジスタのソースに接続される第2定電流源と、
上記第2定電流源の他端にソースが接続され、ゲートには上記バイアス電圧Vbが印加され、ドレインが第2の抵抗を介して上記他方の電源に接続される上記第2のMOSトランジスタと、
を具備し、上記第2のMOSトランジスタのドレイン電圧が上記基準電圧V th を構成していることを特徴とする半導体集積回路素子。
The semiconductor integrated circuit device according to claim 2,
A second constant current source having one end connected to the one power source and the other end connected to the source of the second MOS transistor;
A source connected to the other end of the second constant current source, a bias voltage Vb applied to the gate, and a drain connected to the other power source via a second resistor; ,
And the drain voltage of the second MOS transistor constitutes the reference voltage Vth .
JP06090597A 1997-03-14 1997-03-14 Semiconductor integrated circuit element Expired - Fee Related JP3881079B2 (en)

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JP06090597A JP3881079B2 (en) 1997-03-14 1997-03-14 Semiconductor integrated circuit element
TW087103652A TW391062B (en) 1997-03-14 1998-03-12 Semiconductor integrated circuit
US09/041,960 US6396610B1 (en) 1997-03-14 1998-03-13 Semiconductor integrated circuit
KR1019980008618A KR100271432B1 (en) 1997-03-14 1998-03-14 Semiconductor integrated circuit
DE19811296A DE19811296A1 (en) 1997-03-14 1998-03-16 Integrated semiconductor circuit for optical signal transmission for IC tester

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