JP3880492B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a word line structure of a cell transistor in a DRAM (Dynamic Random Access Memory) and its operation, and in particular, a disturb failure occurring as a disturbing effect of a miniaturized circuit structure, and an adjacent word line after reflow. The present invention relates to a semiconductor memory device capable of preventing reflow deterioration in an adjacent word potential mode in which an information holding time varies depending on a potential.
[0002]
[Prior art]
Conventionally, a typical memory cell in a DRAM as this type of semiconductor memory device is composed of two elements, a charge storage capacitor and a charge input / output MOSFET (metal oxide semiconductor / field effect transistor).
[0003]
For example, as shown in the layout diagram of FIG. 10, there is a structure in which two word lines (WL) 102 are arranged on one active region 101 (see, for example, Patent Document 1).
[0004]
As shown in FIG. 11, one cell transistor in this structure has one word line (WL) as a gate (G) and one bit line (BL) orthogonal to the word line (WL). The MOSFET connects the source (S) and the capacitor (C) to the drain (D).
[0005]
On the other hand, along with the high integration of DRAM memory cells, the amount of information charges is drastically reduced, and data destruction of the memory cells occurs. In order to suppress the occurrence of defects due to this, FRAM (ferroelectric RAM) in which a ferroelectric material is introduced into a parallel plate capacitor is introduced. In this FRAM, in the switch operation using the bistable polarization state for the memory logic using the bistable state of the ferroelectric polarization, there is a problem in reliability such as fatigue deterioration due to a decrease in polarization amount and imprint deterioration due to polarization habit. .
[0006]
In order to solve such a problem, there has also been proposed an FRAM in which a CMOS transistor is formed as a second transistor as shown in FIG. 12 and a second word line WL2 orthogonal to the word line WL1 is provided (for example, Patent Document 2).
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-9261 (FIG. 2)
[0008]
[Patent Document 2]
Japanese Patent Laying-Open No. 2002-94024 (FIG. 7)
[0009]
[Problems to be solved by the invention]
In the above-described conventional semiconductor memory device, the DRAM cell structure described above has a width Fw of the word line 102 of the memory cell at present when the half pitch of the minimum feature size portion as shown in FIG. Is the above-mentioned dimension F or less. When miniaturization is advanced with such a structure and the width of the word line is reduced, there are the following problems.
[0010]
First, the first problem is that the information holding time is shortened.
[0011]
The reason is as follows. As the cell size is reduced and the width of the word line is reduced, the threshold voltage Vth of the cell transistor is significantly reduced. In order to prevent this, it is necessary to increase the substrate concentration, but this increases the junction electric field. When the junction electric field increases in this way, the junction leakage current due to the junction electric field increases. Therefore, as shown in FIG. 13, as the width of the word line is reduced, the information holding time is shortened.
[0012]
The second problem is an increase in disturbance to cells. If the substrate concentration is increased in order to avoid this, a write failure occurs, and it becomes difficult to take measures against a disturb failure and a write failure at the same time. As a result, the device performance cannot be achieved.
[0013]
The reason is as follows. As cell miniaturization proceeds, variations in word line processing dimensions become a major factor in variations in threshold voltage Vth, which increases disturb failures. In order to avoid this, it is necessary to increase the substrate concentration. However, when the substrate concentration is increased, the variation of the threshold voltage Vth further increases. Further, when the substrate concentration is increased, the variation toward the high threshold voltage Vth side increases, so that the number of insufficiently written bits increases and a write failure occurs. That is, it is difficult to take measures against disturb failure and write failure at the same time.
[0014]
The third problem is that reflow degradation increases. A phenomenon in which junction leakage increases after reflow due to thermal stress during IR (infrared) reflow and shortens the information retention time is called reflow deterioration.
[0015]
The reason is as follows. As cell miniaturization proceeds, adjacent word lines running in parallel approach the diffusion region, and the junction electric field on the adjacent word line side increases. If there is a defect on the adjacent word line side in this state, the junction leakage current increases due to the stress from the STI (shallow trench isolation) structure and the stress from the package. Since the stress from this package increases due to thermal stress during IR reflow, junction leakage increases after reflow and shortens the information retention time. Such reflow deterioration can be avoided by increasing the potential of the adjacent word line, and is called reflow deterioration in the adjacent word potential mode. As described above, the increase in junction leakage current on the adjacent word line side increases the reflow deterioration in the adjacent word potential mode.
[0016]
An object of the present invention is to solve such a problem, a disturb failure that occurs as a disturbing effect of a miniaturized circuit structure, and an adjacent word potential mode in which an information retention time varies depending on the adjacent word line potential after reflow It is an object of the present invention to provide a semiconductor memory device that can prevent reflow degradation.
[0017]
[Means for Solving the Problems]
In a semiconductor memory device according to the present invention, one memory cell connected to one bit line in a DRAM has one capacitor and two MOSFETs as transistors. The two transistors have two word lines each composed of a separate gate electrode orthogonal to the bit line, and are sandwiched between the diffusion layer connected to the bit line and the gate electrode, and are common to both. Each of the diffusion layer and the diffusion layer connected to the capacitor is formed in a source / drain region and connected in series.
[0018]
Specifically, in this semiconductor memory device, one memory cell connected to one bit line includes a first word line composed of a first gate electrode and a second word line composed of a second gate electrode. Is orthogonal to the bit line, and has one capacitor and the following two transistors formed in a MOSFET.
[0019]
The first transistor includes a diffusion layer formed by the first gate electrode and connected to the bit line and a diffusion layer sandwiched between the first gate electrode and the second gate electrode. It is said. The second transistor is formed of a second gate electrode, and the diffusion layer sandwiched between the second gate electrode and the first gate electrode and the diffusion layer connected to the capacitor are used as source / drain regions. .
[0020]
In this way, the two transistors have a series-connected structure in which the diffusion layer sandwiched between the two gate electrodes is the common source / drain.
[0021]
Further, at the time of writing / reading, an “on” voltage (Vpp) is applied to the two gates to turn the two transistors “on”. When holding information, an “off” voltage (0 V) is applied to the first gate, and an intermediate voltage between the “on” voltage and the “off” voltage (for example, Vpp / 2) is applied to the second gate. Apply.
[0022]
As a result, the channel leak at the time of holding information is extremely reduced as compared with the case of the conventional single gate electrode, and therefore the probability of a disturb failure is extremely reduced. In addition, the transistor having the second gate electrode is in a depleted state, and the electric field at the capacitor side junction at the end of the second gate electrode can be reduced. As a result, the deterioration of the information retention characteristics due to the junction leak accelerated by the electric field is reduced. Therefore, the deterioration of the information retention characteristic which is a problem when the adjacent word line is “zero” V after the reflow, that is, the reflow deterioration becomes a problem because the second gate electrode becomes the nearest word line on the adjacent word line side. Disappear. In this way, reflow deterioration depending on the adjacent word line potential is avoided.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0024]
FIG. 1 is a diagram showing an embodiment of a planar layout of a memory cell portion according to the present invention.
[0025]
In the semiconductor memory device shown in FIG. 1, four word lines 2 orthogonal to the length direction of the active region 1 are arranged on one active region 1. Accordingly, one memory cell in the region 8 corresponding to one bit has a structure having two word lines 2. That is, a cell transistor having a first gate 3 and a second gate 4 having substantially the same dimensions on the active region 1 is formed. The first transistor having the first gate 3 uses the diffusion layer 5 at the bit line side junction and the diffusion layer 6 at the second gate side junction as source / drain regions, and has a second gate 4. The two-transistor uses the diffusion layer 7 at the capacitor side junction and the diffusion layer 6 at the first gate side junction as the source / drain regions. That is, between the first gate 3 and the second gate 4, there is a source / drain diffusion layer 6 common to the first gate 3 and the second gate 4, and this diffusion layer 6 is used as a common source / drain region. The first transistor and the second transistor are connected in series (see FIG. 8).
[0026]
Here, the minimum processing line width F is set to 0.15 μm, the width Fc of each of the first gate 3 and the second gate 4, the distance between the first gate 3 and the second gate 4, and the first gate 3 is adjacent to this. The distance between the first gate 3, the distance between the second gate 4 and the adjacent second gate 4, and the width Fa of the active region 1 are 0.15 μm of “F”, and the length of the active region 1 is A memory cell having a size 9 times that of “F” was formed.
[0027]
FIG. 2 is a cross-sectional view taken along line AA in the one-bit corresponding region 8 surrounded by a broken line shown in FIG. The 1-bit corresponding area 8 indicates the size of 1 bit, and this cross-sectional structure will be described with reference to FIG.
[0028]
In the p-type well layer 10, a shallow trench isolation layer 11 having a depth of 250 nm in which a silicon oxide film is embedded is formed. Further, threshold voltage control layers 12 and 13 having different substrate concentrations are formed on the substrate surface side where the p-type well layer 10 is formed. One threshold voltage control layer 12 having a low substrate concentration is formed in a portion where the second gate 4 is formed. The other threshold voltage control layer 13 having a high substrate concentration is formed in a portion where the first gate 3 is formed. The gate oxide film 14 is the same for the first gate 3 and the second gate 4.
[0029]
A first transistor using the first gate 3 as a gate electrode and the diffusion layer 5 and diffusion layer 6 of the bit line side portion 18 as a source / drain, and a diffusion layer 7 and diffusion of a capacitor side portion 19 using the second gate 4 as a gate electrode One MOSFET is constituted by two MOSFETs with the second transistor using the layer 6 as a source / drain. Each of the diffusion layers 5 and 7 may have a structure in which deep diffusion layers 20 and 21 are formed in deeper portions.
[0030]
Next, a process flow for achieving the structure shown in FIG. 2 will be described with reference to FIGS. In addition, drawing is a schematic diagram and does not correspond with the reduced scale of the dimension demonstrated. Also, the peripheral circuit portion is omitted because it is not necessary for the description of the present invention.
[0031]
First, as shown in FIG. 3, the substrate includes a p-type well layer 10 having a retrograde boron concentration distribution, and a shallow groove element isolation layer 11 having an element isolation width of 0.15 μm and a depth of 0.25 μm. Is formed. Specific boron concentration distribution is about 1 × ¹⁰ 17 ^{cm -3} to a depth of approximately the depth 250nm from the surface of the substrate consisted deeper than partial and 3 × ¹⁰ 17 ^{cm -3} approximately to a depth of about 750nm .
[0032]
Next, as shown in FIG. 4, boron is introduced into the entire active region, and the threshold voltage control layer 12 is formed so as to have a peak concentration of 6 × 10 ¹⁷ cm ⁻³ at a depth of about 50 nm. .
[0033]
Thereafter, as shown in FIG. 5, boron is introduced into the central portion of the active region, and the threshold voltage control layer 13 is formed so as to have a peak concentration of 1.5 × 10 ¹⁸ cm ⁻³ at a depth of about 30 nm. Is done.
[0034]
Next, as shown in FIG. 6, a gate oxide film 14 having a thickness of 7 nm is formed, a gate electrode made of polycrystalline silicon having a thickness of 70 nm and tungsten silicide having a thickness of 120 nm, the first gate 3 and the second gate. A gate 4 is formed. A silicon nitride film 15 for gate processing is formed on the first gate 3 and the second gate 4.
[0035]
Next, as shown in FIG. 7, after the gate side surface oxidation process (not shown), phosphorus is introduced into the source / drain portions, and the peak concentration is about 2 × 10 ¹⁸ cm ⁻³ at a depth of about 25 nm. Diffusion layers 5, 6, and 7 are formed so that
[0036]
Thereafter, as shown in FIG. 2, sidewalls 16 are formed on the side surfaces of the first gate 3 and the second gate 4, and bit line connection is performed on the diffusion layer 5 by depositing an interlayer insulating film 17 and contact processing. A contact hole 18 for connecting a capacitor and a contact hole 19 for connecting a capacitor are formed on the diffusion layer 7. After the contact holes 18 and 19 are formed, phosphorous is introduced from the contact holes 18 and 19 to a portion deeper than the diffusion layers 5 and 7, thereby ^achieving a peak concentration of 1 × 10 ¹⁸ cm ⁻³ at a depth of about 50 nm. Such diffusion layers 20 and 21 are formed.
[0037]
Thereafter, a polysilicon plug is formed in the contact hole by a normal method, the bit line is connected to the bit line side plug, and the capacitor base electrode is connected to the capacitor side plug. A capacitor film is formed on the capacitor base electrode to form a capacitor.
[0038]
Next, with reference to FIGS. 8 and 9 together with FIG. 2, operation functions in writing and reading and holding information in the above structure will be described.
[0039]
First, as shown in FIG. 8, one first transistor has a first gate 3 as a gate G1, a bit line (BL) side junction diffusion layer 5 as a source S1, and a second gate side junction diffusion layer. 6 is the drain D1. In the other second transistor, the second gate 4 is the gate G2, the capacitor (C) side junction diffusion layer 7 is the drain D2, and the first gate side junction diffusion layer 6 is the source S2. That is, the diffusion layer 6 is used for the common drain D1 and source S2 for the first transistor and the second transistor, and the first transistor and the second transistor are connected in series. Accordingly, the bit line BL is connected to the source S1, and the drain D2 is connected to the capacitor C through the first and second transistors in series.
[0040]
The gates G1 and G2 are connected to the word lines WL1 and WL2 that are orthogonal to the bit line BL, respectively, and the voltage applied to each of the gates G1 and WL2 can be independently controlled.
[0041]
As shown in FIG. 9, in writing and reading, an on voltage (Vpp) is applied to the two gates G1 and G2 to turn on both the first transistor and the second transistor. When holding information, an off voltage (0 V) is applied to the gate G1, and an intermediate voltage (for example, Vpp / 2) between the on voltage and the off voltage is applied to the gate G2.
[0042]
As a result, the channel leak at the time of information retention is extremely reduced as compared with the conventional case of one gate electrode, and therefore the probability of a disturb failure is extremely reduced. The second transistor having the gate G2 is in a depleted state, and the electric field at the capacitor side junction at the end of the gate G2 can be reduced. As a result, the deterioration of the information retention characteristics due to the junction leak accelerated by the electric field is reduced. Therefore, the deterioration of the information retention characteristic that becomes a problem when the adjacent word line becomes 0 V after reflow, that is, the reflow deterioration is a problem because the closest word line WL2 by the gate G2 is arranged in the middle on the adjacent word line WL1 side. No longer. In this way, reflow degradation depending on the adjacent word line potential is avoided.
[0043]
The potentials of the gate G1 and the gate G2 were operated as shown in FIG.
[0044]
First, the threshold voltage Vth of the first transistor having the gate G1 was 1V, and the threshold voltage Vth of the second transistor having the gate G2 was 0.5V.
[0045]
At the time of writing and reading, an ON voltage (Vpp = 3.6 V) was applied to the two gates G1 and G2 to turn on both the first transistor and the second transistor. When holding information, 0V is applied to the gate G1 to turn off the first transistor, while the gate G2 is set to 0V and an intermediate voltage “1.8V” of “Vpp = 3.6V”. The second transistor was turned on from the depletion state by applying. At this time, the ON voltage Vpp and the intermediate potential are applied almost alternately to the gate G2 on the adjacent word line WL1 side.
[0046]
At the time of writing and reading, an on voltage (Vpp) is applied to the two gates to turn on both the first transistor and the second transistor. In this case, since the second transistor having the gate G2 is arranged in series with the first transistor having the gate G1, there is a concern about a decrease in on-current. However, the second transistor having the gate G2 can obtain a sufficient on-current because the threshold voltage Vth is low. For this reason, there is almost no influence on the on-current limited by the first transistor having the gate G1.
[0047]
On the other hand, when holding information, 0 V was applied to the gate G1 to turn off the first transistor, and an intermediate voltage between 0 V and the on-voltage Vpp was applied to the gate G2. In this case, the channel current of the second transistor having the gate G2 is about “1/10” of the normal on-current. As a result, the total channel current of the first transistor and the second transistor was about “1/10” of the channel current in the case of only the first transistor having the gate G1. Usually, the channel current being “1/10” corresponds to the threshold voltage Vth being increased by about 90 mV. Therefore, if the variation σ of the threshold voltage Vth is about 90 mV, the probability of causing information leakage due to channel current, that is, disturb failure can be reduced by σ. The probability of a conventional disturb failure is about 10 ^−7. From this probability, in this embodiment, the probability of a disturb failure can be reduced by σ, so that it can be reduced to about 10 ⁻⁹ .
[0048]
In the case of information retention, the information retention characteristic may be deteriorated by a junction leakage current affected by the junction electric field between the capacitor side diffusion layer and the p-type well layer. In particular, when the stress in the vicinity of the bonding position increases due to thermal stress during reflow, the electric field is equivalently increased as the band cap becomes narrower. Therefore, the junction leakage current further increases, and the information retention characteristics are likely to deteriorate. This phenomenon is called reflow deterioration. In this case, since the substrate concentration of the second transistor having the gate G2 is low, the junction electric field is very small. As a result, information retention characteristics are improved. The reflow deterioration rate is reduced by the improvement in the information retention characteristic. In addition, when the junction electric field is small, the influence of the narrowing of the band gap due to stress is small, so the reflow deterioration rate is lowered.
[0049]
Further, the ON voltage Vpp and the intermediate potential are applied almost alternately to the gate G2 on the adjacent word line side. The junction electric field is easily affected by the potential of the gate with which the diffusion layer is in contact. Compared with the case where the gate potential is 0 V and the intermediate voltage between 0 V and the on voltage Vpp, the junction electric field is intermediate between 0 V and the on voltage Vpp. The voltage is smaller. As a result, since the gate in contact with the capacitor-side diffusion layer is the gate G2, the reflow deterioration rate is lowered because the junction electric field is small. As a result, it was possible to substantially avoid the deterioration of the information retention characteristic that becomes a problem when the adjacent word line is 0 V after reflow. In this example, the reflow deterioration rate of 260 degrees Celsius could be reduced to the conventional “1/5” reflow deterioration rate.
[0050]
In the above description, the width of the second gate has been described as the dimension F in the same manner as the first gate, but a dimension smaller than the dimension F may be used. When the size is smaller than the dimension F, the cell size can be reduced accordingly.
[0051]
Further, when the potential of the second gate was made lower than that in the above embodiment, the probability of disturb failure could be further reduced. However, since the junction electric field is increased, the reflow deterioration rate is increased compared to the case of the above example. Further, when the potential of the second gate was made higher than that in the above example, the probability of disturb failure was higher than in the above example, but the reflow deterioration rate was smaller than that in the above example.
[0052]
As described above, by selecting the potential at the second gate at the time of holding information, it is possible to cope with both cases where there are many disturbance failures and cases where there is much reflow degradation.
[0053]
Further, as described above, the channel impurity concentration immediately below the first gate electrode is set higher than the impurity concentration immediately below the second gate electrode in order to maintain the information retention characteristic, and the second transistor has a lower impurity concentration to prevent reflow deterioration. The threshold voltage is set to approximately “½” of the threshold voltage applied to the first transistor.
[0054]
In the above description, the boosted voltage “Vpp” is applied to each of the first gate electrode and the second gate electrode at the time of data writing and reading of the memory cell, and at the time of holding information, While the voltage “zero” is applied to the electrode and the voltage “Vpp / 2” is applied to the electrode of the second gate, the voltage “zero” is applied to the first gate electrode and the second An intermediate voltage from “zero” to “Vpp” may be applied to the gate electrode.
[0055]
【The invention's effect】
As described above, according to the present invention, the disturb failure which is a problem in the miniaturization of the DRAM and the deterioration in which the information holding time varies depending on the adjacent word line potential after reflow, that is, in the adjacent word potential mode. In addition to measures against reflow deterioration, the information retention time can be increased. As a result, in addition to reducing power consumption, a highly reliable memory cell can be obtained.
[0056]
The reason is that in the memory cell, a second transistor is further formed between one transistor and one capacitor and inserted in series, and the second word line comprising the second gate electrode in the second transistor. This is because a structure is provided in parallel with the main first word line.
[0057]
With this structure, the channel impurity concentration immediately below the gate electrode in the two transistors, the threshold voltage of the two transistors, or the voltage applied to the gate electrode in the two transistors can be changed so as to obtain the optimum effect. Because.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of a layout in a memory cell according to the present invention.
FIG. 2 is a diagram showing an embodiment of an AA cross section in the memory cell of FIG. 1;
FIG. 3 is a diagram showing an embodiment of an initial process result for obtaining the structure of FIG. 2;
4 is a diagram illustrating one embodiment of a process result subsequent to FIG. 3 to obtain the structure of FIG. 2;
FIG. 5 is a diagram showing an embodiment of a process result subsequent to FIG. 4 to obtain the structure of FIG. 2;
6 is a diagram illustrating an embodiment of a process result subsequent to FIG. 5 to obtain the structure of FIG.
7 is a diagram showing an embodiment of process results in the process of proceeding to FIG. 2 following FIG. 6 in order to obtain the structure of FIG. 2;
FIG. 8 is a diagram showing an embodiment of an equivalent circuit in the memory cell of FIG. 1;
9 is a diagram showing one embodiment for applying an applied voltage at the gate during operation of the memory cell circuit of FIG. 8;
FIG. 10 is a diagram showing an example of a layout in a conventional memory cell.
11 is a diagram showing an example of an equivalent circuit in the memory cell of FIG. 10;
12 is a diagram showing an example of a layout in a conventional memory cell different from FIG.
FIG. 13 is a diagram showing a relationship between a conventional word line width and information retention characteristics.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Active region 2 Word line 3 1st gate 4 2nd gate 5, 6, 7, 20, 21 Diffusion layer 8 1 bit corresponding | compatible region 10 P-type well layer 11 Shallow groove element isolation layers 12, 13 Threshold voltage control layer 14 Gate oxide film 15 Silicon nitride film 16 Side wall 17 Interlayer insulating films 18 and 19 Contact hole

Claims (4)

  In a DRAM (dynamic random access memory) composed of a plurality of memory cells, each of the memory cells connected to one bit line has one capacitor and two transistors, and the two The transistor has two word lines each having a gate electrode orthogonal to the bit line, a diffusion layer connected to the bit line, and a diffusion common to the transistor sandwiched between the gate electrodes. A semiconductor memory device having a structure in which a layer and a diffusion layer connected to the capacitor are provided as source / drain regions for the two gate electrodes, respectively, and are connected in series. A first word line in a DRAM, in which one memory cell connected to one bit line has one capacitor, a first transistor and a second transistor, and includes a first gate electrode And a second word line composed of a second gate electrode perpendicular to the bit line,
The first transistor includes a diffusion layer formed by the first gate electrode and connected to a bit line and a diffusion layer sandwiched between the first gate electrode and the second gate electrode. The second transistor is formed by a second gate electrode, and a diffusion layer sandwiched between the second gate electrode and the first gate electrode and a diffusion layer connected to the capacitor are respectively provided. A semiconductor memory device having a structure including a second transistor serving as a source / drain region.   3. The semiconductor memory device according to claim 2, wherein a channel impurity concentration immediately below the first gate electrode is higher than an impurity concentration immediately below the second gate electrode. 3. The threshold voltage of the second transistor according to claim 2, wherein the threshold voltage of the second transistor is set to substantially “½” of the threshold voltage applied to the first transistor by controlling the channel impurity concentration. A semiconductor memory device.

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