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JP3878897B2 - Semiconductor element storage package and semiconductor device - Google Patents

Semiconductor element storage package and semiconductor device Download PDF

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JP3878897B2
JP3878897B2 JP2002277371A JP2002277371A JP3878897B2 JP 3878897 B2 JP3878897 B2 JP 3878897B2 JP 2002277371 A JP2002277371 A JP 2002277371A JP 2002277371 A JP2002277371 A JP 2002277371A JP 3878897 B2 JP3878897 B2 JP 3878897B2
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JP2004146392A (en
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久直 堀川
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子を収容するための半導体素子収納用パッケージおよび半導体装置に関する。
【０００２】
【従来の技術】
従来の半導体素子収納用パッケージ（以下、半導体パッケージともいう）およびその半導体パッケージに半導体素子を気密封止して成る半導体装置の一例を図３および図４（ａ），（ｂ）に示す。これらの図において、101は基体、103は枠体、104は蓋体であり、これらの基体101、枠体103および蓋体104とから基本的に構成される半導体パッケージに半導体素子102を気密に収容して半導体装置105となる。
【０００３】
基体101は、アルミナ（Ａｌ2Ｏ3）質焼結体（セラミックス），ムライト（３Ａｌ2Ｏ3・２ＳｉＯ2）質焼結体等のセラミックス、ガラスセラミックス等の無機材料、四ふっ化エチレン樹脂（ポリテトラフルオロエチレン；ＰＴＦＥ），四ふっ化エチレン・エチレン共重合樹脂（テトラフルオロエチレン−エチレン共重合樹脂；ＥＴＦＥ），四ふっ化エチレン・パーフルオロアルコキシエチレン共重合樹脂（テトラフルオロエチレン−パーフルオロアルキルビニルエーテル共重合樹脂；ＰＦＡ）等のフッ素樹脂，ガラスエポキシ樹脂，ポリイミド等の樹脂系材料等の電気絶縁材料から成り、上側主面に半導体素子102を収納し載置するための凹部101ａを有し、凹部101ａ内の半導体素子102の載置部101ｂの周囲には電極パッド106が設けられている。
【０００４】
また、基体101の上側主面の凹部101ａの周囲には、鉄（Ｆｅ）−ニッケル（Ｎｉ）合金や鉄−ニッケル−コバルト（Ｃｏ）合金等の金属等からなる枠体103が接合されている。この枠体103は、蓋体104を基体101に強固に接合するためのものであり、その下面が基体101にろう材等を介して接合されている。この枠体103の上面に、凹部101aを塞ぐようにして蓋体104をハンダ108を介して接合することにより凹部101ａに収納された半導体素子102が気密封止される。
【０００５】
半導体素子102は、基体101に形成された凹部101ａの底面の載置部101ｂに樹脂接着剤等で接着されるとともに、その電極（図示せず）が金やアルミニウム等から成るボンディングワイヤ107を介して基体101に形成された電極パッド106に電気的に接続されている（例えば、下記の特許文献１参照）。
【０００６】
【特許文献１】
特開平６−３４９９６１号公報
【０００７】
【発明が解決しようとする課題】
しかしながら、上記従来の半導体パッケージおよび半導体装置においては、蓋体104はハンダ108を介して枠体103に接合されているが、封止時の蓋体104を上方から押圧する圧力、温度条件および炉内の雰囲気等の影響により、枠体103と蓋体104とを接合する際にハンダ108の一部が凹部101ａ内へと流れ込む場合があり、流れ込んだハンダ108が凹部101ａ内に設けられた電極パッド106にまで至り、例えば電極パッド106同士が電気的な短絡を起こすという問題点があった。
【０００８】
また、蓋体104は枠体103にハンダ108で固定されるまでは枠体103の上面に載置されているだけであり、枠体103に対する位置が不安定である。このため、枠体103に対し蓋体104がずれて固定されてしまい、気密性が損なわれるという問題点があった。
【０００９】
さらに、蓋体104には、枠体103に固定された後に基体101内に収納された半導体素子102の駆動による発熱や環境温度の変化によって起きる熱応力、また半導体装置105の置かれる環境の気圧変化による応力等が加わる。その際、蓋体104と枠体103との接合部であるハンダ108に大きな応力が加わるため、この接合部が破壊され、半導体装置105の気密性が破れるという問題点もあった。特に、基体101に収納される半導体素子102が大型になるにつれ、半導体素子102が載置される基体101の凹部101ａも大きくなる。その結果、凹部101ａを取り囲む枠体103と、これに接合される蓋体104も大きくなる。その結果、蓋体104の受ける応力も大きくなり、上記のような問題点がより顕著にあらわれる傾向にある。
【００１０】
従って、本発明は上記問題点に鑑みて完成されたものであり、その目的は、蓋体を枠体にハンダで接合する際にハンダの余剰分が基体に形成された電極パッド部に流れ込んで電気的な短絡を起こすことを防ぐとともに、蓋体と枠体の位置決めを確実に行え、また蓋体が枠体に接合された後に蓋体に加わる応力を緩和することのできる半導体パッケージおよび半導体装置を提供することにある。
【００１１】
【課題を解決するための手段】
本発明の半導体素子収納用パッケージは、上側主面に半導体素子を載置する載置部が設けられているとともに前記上側主面の前記載置部の周囲に電極パッドが形成された基体と、該基体の前記上側主面の外周部に前記載置部および前記電極パッドを囲繞するように取着された枠体と、該枠体の上面に下方に向けて略全周にわたって形成された、前記枠体の上面側の開口よりも前記枠体の下面側の開口が大きい複数の穴と、該複数の穴のそれぞれに嵌着させるための前記穴の深さよりも短い突起が下面の外周部に複数形成された蓋体とを具備することを特徴とする。
【００１２】
本発明の半導体素子収納用パッケージは、基体の上側主面の外周部に載置部および電極パッドを囲繞するように取着された枠体と、枠体の上面に下方に向けて略全周にわたって形成された複数の穴と、複数の穴のそれぞれに嵌着させるための穴の深さよりも短い突起が下面の外周部に複数形成された蓋体とを具備していることから、蓋体と枠体とを接合するためのハンダに余剰分が発生しても、ハンダのほとんどは枠体に設けられた穴に流れ込み、蓋体と枠体との接合部から溢れて基体の電極パッド部へ流れ込むのを防ぐことができる。
【００１３】
また、蓋体を枠体に載置する際の位置決めが確実に行なえる。さらに、枠体に設けた穴に蓋体の突起を嵌着させることで、蓋体と枠体との接合面積を大きくすることができ、穴と突起との接合面により蓋体と枠体とを接合するハンダにかかる応力を大幅に緩和することができる。その結果、蓋体と枠体との接合部のハンダの破壊が発生するのを抑制することができる。従って、蓋体と枠体との高い接合信頼性を得ることができる。
【００１５】
本発明の半導体素子収納用パッケージは、複数の穴は枠体の上面側の開口よりも枠体の下面側の開口が大きいことから、蓋体と枠体とを接合するハンダの接合面積および体積を大きくすることができる。その結果、蓋体と枠体との接合部のハンダに破壊が発生するのをより一層効果的に抑制することができ、蓋体と枠体との高い接合信頼性をより確実に得ることができる。
【００１６】
また、穴内のハンダは下側の体積が大きくなっているため、基体と枠体との接合強度が向上する。さらに、蓋体と枠体とは突起およびハンダで接合されるため、それらの接合強度は基体と枠体との接合強度よりも大きいが、基体と枠体との接合強度が向上することから、枠体の上下の接合強度が略同じになるとともに枠体の全周で接合強度が略同じになる。その結果、枠体の接合部に局所的に接合強度の劣化した部位が生じることがなくなり、枠体の接合性がより良好になる。
【００１７】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、前記基体の前記上側主面の前記載置部に載置固定されるとともに前記電極パッドに電気的に接続された半導体素子と、前記枠体の前記穴に前記蓋体の前記突起を嵌着させることにより前記枠体の上面に設置された前記蓋体とを具備したことを特徴とする。
【００１８】
本発明の半導体装置は、上記の構成により、上記本発明の半導体素子収納用パッケージを用いた信頼性の高いものとなる。
【００１９】
【発明の実施の形態】
本発明の半導体素子収納用パッケージおよび半導体装置について以下に詳細に説明する。図１および図３（ａ），（ｂ）は、それぞれ本発明の半導体素子収納用パッケージおよび半導体装置について実施の形態の一例を示し、図１は本発明の半導体素子収納用パッケージを用いた半導体装置の断面図、（ａ）は図１の半導体装置であって蓋体を取り除いたもの（半導体素子収納用パッケージ）の平面図、（ｂ）は図１の半導体装置における蓋体の下面の平面図である。これらの図において、１は基体、２は半導体素子、３は枠体、４は蓋体であり、基体１、枠体３および蓋体４により半導体素子収納用パッケージが基本的に構成される。半導体素子収納用パッケージ内に半導体素子２を収容し枠体３の上面に蓋体４を接合することにより半導体装置５が構成される。
【００２０】
本発明の半導体素子収納用パッケージは、上側主面に半導体素子２を載置する載置部１ｂが設けられているとともに上側主面の載置部１ｂの周囲に電極パッド６が形成された基体１と、基体１の上側主面の外周部に載置部１ｂおよび電極パッド６を囲繞するように取着された枠体３と、枠体３の上面に下方に向けて略全周にわたって形成された、枠体３の上面側の開口よりも枠体３の下面側の開口が大きい複数の穴３ａと、複数の穴３ａのそれぞれに嵌着させるための穴３ａの深さよりも短い突起４ａが下面の外周部に複数形成された蓋体４とを具備する。
【００２１】
本発明の基体１は、アルミナ（Ａｌ2Ｏ3）質焼結体（セラミックス），ムライト（３Ａｌ2Ｏ3・２ＳｉＯ2）質焼結体等のセラミックスやガラスセラミックス等の無機材料、四ふっ化エチレン樹脂（ポリテトラフルオロエチレン；ＰＴＦＥ），四ふっ化エチレン・エチレン共重合樹脂（テトラフルオロエチレン−エチレン共重合樹脂；ＥＴＦＥ），四ふっ化エチレン・パーフルオロアルコキシエチレン共重合樹脂（テトラフルオロエチレン−パーフルオロアルキルビニルエーテル共重合樹脂；ＰＦＡ）等のフッ素樹脂，ガラスエポキシ樹脂，ポリイミド等の樹脂系材料、またはＡｌ，Ｃｕ，Ｆｅ−Ｎｉ−Ｃｏ合金，Ｆｅ−Ｎｉ合金，Ｃｕ−Ｗ合金等の金属材料から成る。
【００２２】
この基体１は上側主面に凹部１ａを有し、凹部１ａ内の載置部１ｂの周囲に電極パッド６が設けられているが、本発明において基体１は凹部１ａのない平板状のものであってもよい。
【００２３】
電極パッド６は、Ａｕ，Ａｌ等から成るボンディングワイヤ７を介して半導体素子２の上面の入出力用の電極に電気的に接続されるものであり、基体１の側面および基体１の下側主面等に形成されたメタライズ層等から成る配線パターンやリード端子等（図示せず）を介して外部電気回路等に電気的に接続される。
【００２４】
また、基板１の上側主面の凹部１ａの底面には、半導体素子２がアクリル系樹脂、エポキシ系樹脂、シリコーン系樹脂、ポリエーテルアミド系樹脂等から成る樹脂接着剤、またはＡｕ−Ｓｉ、Ａｕ−Ｓｎ、Ｓｎ−Ｐｂ半田等から成る接着剤を介して接着される。
【００２５】
基体１の上側主面の凹部１ａの周囲には枠体３が接合されている。この枠体３は、Ｆｅ−Ｎｉ−Ｃｏ合金、Ａｌ，Ｃｕ等の金属、アルミナ質焼結体，窒化アルミニウム（ＡｌＮ）質焼結体，炭化珪素（ＳｉＣ）質焼結体，窒化珪素（Ｓｉ3Ｎ4）質焼結体，ガラスセラミックス等のセラミックス材料等から成る。枠体３の平面視形状は略四角形状等であり、全体形状は例えば高さ約0.3〜３ｍｍ、幅約１〜５ｍｍの直方体状である。枠体３の幅については、封止強度を維持するために極力大きいことがよい。ただし、５ｍｍを超えて大きすぎると、半導体装置５自体の小型化が困難となる。また、枠体３の高さは、ボンディングワイヤ７に接触しないようにするために、ボンディングワイヤ７の最上部よりも高いことがよいが、３ｍｍを超えて高すぎると半導体装置５自体の低背化が困難となる。
【００２６】
枠体３は基体１と蓋体４との間に設置されるため、蓋体４を枠体３に接合固定する際や半導体装置５が外部電気回路基板等に実装される際の熱によって半導体装置５全体が膨張し、基体１、枠体３、蓋体４のそれぞれの間の接合部にストレスが加わり易い。このことから、枠体３は、基体１および蓋体４のそれぞれの熱膨張係数に近い材料を用いるのが好ましい。
【００２７】
枠体３の上面には、Ｓｎ−Ｐｂ共晶ハンダ、Ｓｎ−Ｐｂ系の高温ハンダ、Ａｕ−Ｓｎハンダ等から成るハンダ８を介して蓋体４が接合される。この蓋体４は、Ｆｅ−Ｎｉ−Ｃｏ合金，Ａｌ，Ｃｕ等の金属、アルミナ質焼結体，窒化アルミニウム質焼結体，炭化珪素質焼結体，窒化珪素質焼結体，ガラスセラミックス等のセラミックス材料等から成る。
【００２８】
蓋体４を枠体に３に接合する手法としては、例えば、蓋体４の下面の外周部または枠体３の上面にハンダ８を予め設けておくといった方法がある。
【００２９】
本発明の半導体装置５では、枠体３の上面に下方に向かって略全周にわたって複数の穴３ａを形成し、蓋体４の下面の外周部に穴３ａに嵌着させるための穴３ａの深さよりも短い突起４ａを複数形成して、枠体３の穴３ａに蓋体４の突起４ａを嵌着させて枠体３と蓋体４とを接合させる。これにより、蓋体４と枠体３とを接合するハンダ８に余剰分が発生しても、ハンダ８のほとんどは枠体３の穴３ａに流れ込み、ハンダ８が基体１の凹部１ａ内へ流れ込むのを防ぐことができる。また、穴３ａに突起４ａを嵌着させることで、蓋体４を枠体３に接合する際の位置決めが確実に行える。さらに、蓋体４と枠体３との接合面積を大きくすることができ、穴３ａと突起４ａとの接合面により蓋体４と枠体３とを接合するハンダ８にかかる応力を大幅に緩和することができる。その結果、蓋体４と枠体３との接合部のハンダ８の破壊が発生するのを抑制することができる。従って、蓋体４と枠体３との高い接合信頼性を得ることができる。
【００３０】
また穴３ａは、枠体３の上面側の開口よりも枠体３の下面側の開口が大きいことが必要である。これにより、穴３ａ内のハンダは下側の体積が大きくなるため、基体１と枠体３との接合強度が向上する。さらに、蓋体４と枠体３とは突起４ａおよびハンダ８で接合されるため、それらの接合強度は基体１と枠体３との接合強度よりも大きいが、基体１と枠体３との接合強度が向上することから、枠体３の上下の接合強度が略同じになるとともに枠体３の全周で接合強度が略同じになる。その結果、枠体３の接合部に局所的に接合強度の劣化した部位が生じることがなくなり、枠体３の接合性がより良好になる。
【００３１】
穴３ａは枠体３の上面から下方に向かって厚さ方向の途中まで形成されたものであってもよいし、枠体３の上下面間を貫通する貫通孔であってもよい。
【００３２】
突起４ａの長さは穴３ａの深さよりも短いが、具体的には突起４ａの長さは0.1〜２ｍｍがよい。0.1ｍｍ未満では、蓋体４を枠体３に載置した際に穴３ａから突起４ａがはずれ易くなる。２ｍｍを超えると、穴３ａの深さも２ｍｍ以上となることから、半導体装置５の低背化が困難になる。また、穴３ａの深さは突起４ａの長さよりも0.1〜1.0ｍｍ長ければよい。0.1ｍｍ未満では、ハンダ８が穴３ａから溢れ易くなり、1.0ｍｍを超えると、ハンダ８が枠体３の上面で濡れにくくなる。また、半導体装置５の低背化が困難になる。
【００３３】
また、突起４ａの幅は穴３ａの幅よりも0.05〜0.3ｍｍ小さいことが好ましい。突起４ａの幅と穴３ａの幅との差が0.05ｍｍ未満では、穴３ａに突起４ａを嵌め込むことが困難になる。突起４ａの幅と穴３ａの幅との差が0.3ｍｍを超えると、枠体３上面に蓋体４を載置した際に蓋体４の移動可能範囲が大きくなり、位置決めが困難となる。また突起４ａは、穴３ａの長さと略同じ長さとなるように連続して形成されていることが好ましく、この場合枠体３と蓋体４との接合が強固になる。
【００３４】
さらに突起４ａは、縦断面形状が下側が先細りとされた形状であることがよく、突起４ａを穴３ａに嵌入させることが容易になるとともに突起４ａと穴３ａとの接合部の面積が増大する。また、ハンダ８は穴３ａの両端部で外にはみ出し易いことから、突起４ａの穴３ａの両端部における部位の高さをそれ以外の部位よりも低くすることが好ましい。この場合、穴３ａの両端部でハンダ８が外にはみ出るのを防ぐことができる。
【００３５】
また、枠体３の上面に設けた穴３ａの幅は蓋体４の突起４ａを嵌め込むことができる大きさであり、また穴３ａの深さはハンダ８の余剰分が流れ込むだけの空間ができればよい。穴３ａの幅が大きすぎると、枠体３の上面の穴３ａの両端部の面積が小さくなり、枠体３の上面領域における蓋体４と枠体３との接合面積が減少するため接合信頼性が低下する傾向がある。
【００３６】
また穴３ａは、図３に示すように、枠体３の上面の内側の４辺と略同じ長さで長穴状のものが４つ形成されるのが好ましい。この場合、穴３ａと突起４ａとの接合部の接合面積がほぼ最大になるとともに、接合部における応力緩和効果がほぼ最大になる。さらに複数の穴３ａは、枠体３の上面の略全周にわたって形成されているが、大きな応力が加わり易い枠体３の４隅部で途切れていることがよい。また、穴３ａが貫通孔である場合、穴３ａは少なくとも一箇所で途切れている。穴３ａが途切れずに枠体３の上面の全周にわたって形成されると、枠体３の上面が穴３ａによって内側と外側の２つに分かれてしまうため、基体１に枠体３を接合する際に枠体３の位置決めが難しくなり、接合不良による気密封止の信頼性が低下する恐れがある。
【００３７】
また、穴３ａは、図３に示すように長穴状のものであってもよいし、略円形や略四角形のものを複数形成してもよい。穴３ａは図３に示すような長穴状のものが好ましい。即ち、略円形の穴３ａの場合、枠体３上面の穴３ａの両側の部位が薄くなって枠体３の強度が低下し易いのに対し、長穴状の穴３ａの場合、略円形のものと開口面積が同じであっても枠体３上面の穴３ａの両側の部位が厚くなり、枠体３の強度を保持できるとともに枠体３の強度が全周にわたって略均一になる。また、枠体３と蓋体４との接合部にかかる応力を分散させることができる。
【００３８】
穴３ａが図３のような長穴状のものの場合、穴３ａは枠体３上面の幅方向の中央部に形成されており、穴３ａの幅は枠体３の枠部の上面の幅の１／５〜１／２であることが好ましい。１／５未満では、ハンダ８が穴３ａから溢れ易くなり、１／２を超えると、枠体３の強度が低下して枠体３にクラック等が発生して気密性が破れ易くなる。
【００３９】
【実施例】
本発明の半導体装置の実施例を以下に説明する。
【００４０】
（実施例１）
本発明の半導体装置を以下のように構成した。厚さ1.5ｍｍ×縦20ｍｍ×横20ｍｍの直方体状のアルミナセラミックスから成る基体１の上側主面の載置部１ｂの周囲にＷのメタライズ層から成る電極パッド６を形成し、基体１の上側主面の外周部に載置部１ｂおよび電極パッド６を囲むようにして、縦15ｍｍ、横15ｍｍ、高さ１ｍｍ、枠部の厚さ（枠体３の枠部の上面の幅）が２ｍｍであるＦｅ−Ｎｉ−Ｃｏ合金から成る四角形の枠体３を、Ａｇロウで接合した。
【００４１】
このとき、図３に示した４つの長穴状で貫通孔とされた穴３ａ（深さ１ｍｍ）を枠体３の上面で枠部の中央部に形成した。そして、穴３ａの幅を０．２ｍｍ、０．４ｍｍ、０．６ｍｍ、０．８ｍｍ、１．０ｍｍ、１．２ｍｍと種々の値としたものを各１０個作製した。
【００４２】
そして、載置部１ｂにＬＳＩから成る半導体素子２をエポキシ系樹脂から成る樹脂接着剤で載置固定し、半導体素子２の上面の電極をＡｕから成るボンディングワイヤ７を介して電極パッド６に電気的に接続した。
【００４３】
次に、厚さ0.3ｍｍ×縦15ｍｍ×横15ｍｍのＦｅ−Ｎｉ−Ｃｏ合金から成り、下面の外周部に穴３ａに嵌着される突起４ａが形成された蓋体４を、穴３ａに突起４ａを嵌着させてＳｎ−Ｐｂ共晶ハンダから成るハンダ８を介して接合して、各種半導体装置のサンプルを作製した。このとき、突起４ａの長さを0.3ｍｍとし、また上記各種穴３ａに対して突起４ａの幅がいずれも0.1ｍｍ小さくなるようにした。
【００４４】
そして、上記各種サンプルについて、表１にハンダ８の穴３ａからの溢れの有無、枠体３の強度が低下して枠体３にクラック等が発生して気密性が破れたか否かを調べた結果を示す。
【００４５】
【表１】

Figure 0003878897
【００４６】
表１より、穴３ａの幅が0.2ｍｍのものでは、ハンダ８が穴３ａから溢れ出て電極パッド６同士がショートしたものが３／10発生した。穴３ａの幅が1.2ｍｍのものでは、気密性が破れたものが２／10発生した。これに対して、穴３ａの幅が0.4〜1.0ｍｍのものでは全く問題がなかった。
【００４７】
なお、本発明は上記実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。
【００４８】
【発明の効果】
本発明の半導体収納用パッケージは、上側主面に半導体素子を載置する載置部が設けられているとともに上側主面の載置部の周囲に電極パッドが形成された基体と、基体の上側主面の外周部に載置部および電極パッドを囲繞するように取着された枠体と、枠体の上面に下方に向けて略全周にわたって形成された複数の穴と、複数の穴のそれぞれに嵌着させるための穴の深さよりも短い突起が下面の外周部に複数形成された蓋体とを具備することにより、蓋体と枠体とを接合するためのハンダに余剰分が発生しても、ハンダのほとんどは枠体に設けられた穴に流れ込み、蓋体と枠体との接合部から溢れて基体の電極パッド部へ流れ込むのを防ぐことができる。
【００４９】
また、蓋体を枠体に載置する際の位置決めが確実に行なえる。さらに、枠体に設けた穴に蓋体の突起を嵌着させることで、蓋体と枠体との接合面積を大きくすることができ、穴と突起との接合面により蓋体と枠体とを接合するハンダにかかる応力を大幅に緩和することができる。その結果、蓋体と枠体との接合部のハンダの破壊が発生するのを抑制することができる。従って、蓋体と枠体との高い接合信頼性を得ることができる。
【００５０】
本発明の半導体素子収納用パッケージは、複数の穴は枠体の上面側の開口よりも枠体の下面側の開口が大きいことにより、蓋体と枠体とを接合するハンダの接合面積および体積を大きくすることができる。その結果、蓋体と枠体との接合部のハンダに破壊が発生するのをより一層効果的に抑制することができ、蓋体と枠体との高い接合信頼性をより確実に得ることができる。
【００５１】
また、穴内のハンダは下側の体積が大きくなっているため、基体と枠体との接合強度が向上する。さらに、蓋体と枠体とは突起およびハンダで接合されるため、それらの接合強度は基体と枠体との接合強度よりも大きいが、基体と枠体との接合強度が向上することから、枠体の上下の接合強度が略同じになるとともに枠体の全周で接合強度が略同じになる。その結果、枠体の接合部に局所的に接合強度の劣化した部位が生じることがなくなり、枠体の接合性がより良好になる。
【００５２】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、基体の上側主面の載置部に載置固定されるとともに電極パッドに電気的に接続された半導体素子と、枠体の穴に蓋体の突起を嵌着させることにより枠体の上面に設置された蓋体とを具備したことにより、上記本発明の半導体素子収納用パッケージを用いた信頼性の高いものとなる。
【図面の簡単な説明】
【図１】本発明の半導体装置について実施の形態の一例を示す断面図である。
【図２】本発明の半導体装置について実施の形態の他の例を示す断面図である。
【図３】（ａ）は図１の半導体装置であって蓋体を取り除いたものの平面図、（ｂ）は図１の半導体装置における蓋体の下面の平面図である。
【図４】従来の半導体装置の一例を示す断面図である。
【図５】（ａ）は図４の半導体装置であって蓋体を取り除いたものの平面図、（ｂ）は図４の半導体装置における蓋体の下面の平面図である。
【符号の説明】
１：基体
１ｂ：載置部
２：半導体素子
３：枠体
３ａ：穴
４：蓋体
４ａ：突起
５：半導体装置
６：電極パッド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element housing package and a semiconductor device for housing a semiconductor element.
[0002]
[Prior art]
An example of a conventional semiconductor element housing package (hereinafter also referred to as a semiconductor package) and a semiconductor device in which a semiconductor element is hermetically sealed in the semiconductor package are shown in FIGS. 3 and 4A and 4B. In these drawings, 101 is a base, 103 is a frame, and 104 is a lid. The semiconductor element 102 is hermetically sealed in a semiconductor package basically composed of the base 101, the frame 103, and the lid 104. The semiconductor device 105 is housed.
[0003]
The base 101 is composed of ceramics such as alumina (Al 2 O 3 ) sintered body (ceramics), mullite (3Al 2 O 3 .2SiO 2 ) sintered body, inorganic materials such as glass ceramics, ethylene tetrafluoride resin ( Polytetrafluoroethylene (PTFE), tetrafluoroethylene / ethylene copolymer resin (tetrafluoroethylene-ethylene copolymer resin; ETFE), tetrafluoroethylene / perfluoroalkoxyethylene copolymer resin (tetrafluoroethylene-perfluoroalkyl) It is made of an electrically insulating material such as a fluororesin such as vinyl ether copolymer resin (PFA), a resin-based material such as glass epoxy resin, and polyimide, and has a recess 101a for housing and placing the semiconductor element 102 on the upper main surface. An electrode pad 106 is provided around the mounting portion 101b of the semiconductor element 102 in the recess 101a.
[0004]
A frame 103 made of a metal such as an iron (Fe) -nickel (Ni) alloy or an iron-nickel-cobalt (Co) alloy is joined to the periphery of the recess 101a on the upper main surface of the base 101. . The frame body 103 is for firmly bonding the lid body 104 to the base body 101, and its lower surface is joined to the base body 101 via a brazing material or the like. The semiconductor element 102 accommodated in the recess 101a is hermetically sealed by joining the lid 104 to the upper surface of the frame 103 via the solder 108 so as to close the recess 101a.
[0005]
The semiconductor element 102 is bonded to the mounting portion 101b on the bottom surface of the recess 101a formed in the base 101 with a resin adhesive or the like, and its electrode (not shown) is bonded via a bonding wire 107 made of gold, aluminum, or the like. The electrode pad 106 formed on the base 101 is electrically connected (for example, see Patent Document 1 below).
[0006]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 6-349961
[Problems to be solved by the invention]
However, in the above-described conventional semiconductor package and semiconductor device, the lid body 104 is joined to the frame body 103 via the solder 108, but the pressure, temperature conditions, and furnace for pressing the lid body 104 from above when sealed. In some cases, a part of the solder 108 flows into the recess 101a when the frame 103 and the lid 104 are joined due to the influence of the atmosphere inside the electrode, and the solder 108 that has flowed in is provided in the recess 101a. For example, the electrode pads 106 are electrically short-circuited to the pads 106.
[0008]
Further, the lid 104 is only placed on the upper surface of the frame 103 until it is fixed to the frame 103 with the solder 108, and the position with respect to the frame 103 is unstable. For this reason, there is a problem that the lid 104 is displaced and fixed with respect to the frame 103 and the airtightness is impaired.
[0009]
Furthermore, the lid 104 has a heat stress generated by driving the semiconductor element 102 housed in the base body 101 after being fixed to the frame 103 and a change in environmental temperature, and an atmospheric pressure in which the semiconductor device 105 is placed. Stress due to change is applied. At that time, since a large stress is applied to the solder 108 which is a joint portion between the lid 104 and the frame body 103, the joint portion is broken, and the airtightness of the semiconductor device 105 is broken. In particular, as the semiconductor element 102 accommodated in the base 101 becomes large, the concave portion 101a of the base 101 on which the semiconductor element 102 is placed increases. As a result, the frame 103 surrounding the recess 101a and the lid 104 joined to the frame 103 are also enlarged. As a result, the stress received by the lid 104 also increases, and the above-described problems tend to appear more prominently.
[0010]
Accordingly, the present invention has been completed in view of the above problems, and its purpose is to allow surplus solder to flow into the electrode pad portion formed on the base when the lid is joined to the frame with solder. Semiconductor package and semiconductor device capable of preventing electrical short circuit, reliably positioning lid and frame, and relieving stress applied to lid after lid is joined to frame Is to provide.
[0011]
[Means for Solving the Problems]
The package for housing a semiconductor element of the present invention is provided with a base on which a mounting part for mounting a semiconductor element is provided on the upper main surface and an electrode pad is formed around the mounting part on the upper main surface, A frame body attached to the outer peripheral portion of the upper main surface of the base body so as to surround the placement portion and the electrode pad, and formed on the upper surface of the frame body over substantially the entire periphery downward ; A plurality of holes whose opening on the lower surface side of the frame body is larger than an opening on the upper surface side of the frame body, and a protrusion shorter than the depth of the hole for fitting into each of the plurality of holes is an outer peripheral portion of the lower surface And a plurality of lids formed thereon.
[0012]
The package for housing a semiconductor element according to the present invention includes a frame attached to the outer peripheral portion of the upper main surface of the base so as to surround the mounting portion and the electrode pad, and a substantially entire periphery downward toward the upper surface of the frame. A plurality of holes formed over the plurality of holes, and a cover body in which a plurality of protrusions shorter than the depth of the holes for fitting into each of the plurality of holes are formed on the outer peripheral portion of the lower surface. Even if surplus occurs in the solder for joining the frame and the frame, most of the solder flows into the holes provided in the frame and overflows from the joint between the lid and the frame, and the electrode pad portion of the base body Can be prevented from flowing into.
[0013]
Further, positioning when the lid is placed on the frame can be reliably performed. Furthermore, by fitting the protrusions of the lid body into the holes provided in the frame body, the bonding area between the lid body and the frame body can be increased. It is possible to greatly relieve the stress applied to the solder for joining. As a result, it is possible to suppress breakage of solder at the joint portion between the lid and the frame. Therefore, high joint reliability between the lid and the frame can be obtained.
[0015]
In the package for housing a semiconductor element of the present invention, the plurality of holes have larger openings on the lower surface side of the frame body than the openings on the upper surface side of the frame body, so that the bonding area and volume of the solder for joining the lid body and the frame body Can be increased. As a result, it is possible to more effectively suppress the occurrence of breakage in the solder at the joint between the lid and the frame, and to more reliably obtain high bonding reliability between the lid and the frame. it can.
[0016]
Further, since the solder in the hole has a large volume on the lower side, the bonding strength between the base and the frame is improved. Furthermore, since the lid and the frame are joined by protrusions and solder, their joint strength is greater than the joint strength between the base and the frame, but the joint strength between the base and the frame is improved. The upper and lower joint strengths of the frame body are substantially the same, and the joint strength is substantially the same over the entire circumference of the frame body. As a result, a portion having a locally deteriorated bonding strength is not generated at the joint portion of the frame body, and the bondability of the frame body becomes better.
[0017]
A semiconductor device according to the present invention includes a package for housing a semiconductor element according to the present invention, a semiconductor element mounted and fixed on the mounting portion of the upper main surface of the base body, and electrically connected to the electrode pad. The lid body is provided on the upper surface of the frame body by fitting the projection of the lid body into the hole of the frame body.
[0018]
The semiconductor device of the present invention has high reliability using the semiconductor element storage package of the present invention due to the above-described configuration.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor element storage package and the semiconductor device of the present invention will be described in detail below. FIGS 3 (a), (b), the semiconductor device package for housing and the semiconductor device of the present invention each show an example of embodiment, FIG. 1 is a semiconductor element storage package of the present invention a semiconductor 1A is a cross-sectional view of the device, FIG. 1A is a plan view of the semiconductor device of FIG. 1 with the lid removed (semiconductor element storage package), and FIG. 1B is a plan view of the lower surface of the lid of the semiconductor device of FIG. FIG. In these drawings, 1 is a substrate, 2 a semiconductor element, 3 frame, 4 is lid, the base 1, for housing semiconductor chip package is configured basically by the frame 3 and the lid 4 . The semiconductor device 5 is constructed by joining the lid body 4 housing the semiconductor element 2 to the upper surface of the frame 3 on the semiconductor element storage package in di.
[0020]
For housing a semiconductor element package of the present invention, the electrode pad 6 on the periphery of the upper surface of the mounting portion 1b with mounting portion 1b for mounting the semiconductor element 2 into the upper surface is provided is formed The base body 1, the frame body 3 attached to the outer peripheral portion of the upper main surface of the base body 1 so as to surround the mounting portion 1 b and the electrode pad 6, and the upper surface of the frame body 3 facing downward substantially over the entire circumference. A plurality of formed holes 3a having an opening on the lower surface side of the frame body 3 larger than the opening on the upper surface side of the frame body 3, and a projection shorter than the depth of the hole 3a for fitting into each of the plurality of holes 3a 4a includes a plurality of lids 4 formed on the outer periphery of the lower surface.
[0021]
The substrate 1 of the present invention is made of an inorganic material such as ceramics such as alumina (Al 2 O 3 ) sintered body (ceramics) and mullite (3Al 2 O 3 .2SiO 2 ) sintered body, glass ceramics, and tetrafluoride. Ethylene resin (polytetrafluoroethylene; PTFE), tetrafluoroethylene / ethylene copolymer resin (tetrafluoroethylene-ethylene copolymer resin; ETFE), tetrafluoroethylene / perfluoroalkoxyethylene copolymer resin (tetrafluoroethylene- Perfluoroalkyl vinyl ether copolymer resin (PFA) and other fluororesins, glass epoxy resins, resin materials such as polyimide, or metals such as Al, Cu, Fe-Ni-Co alloys, Fe-Ni alloys, Cu-W alloys Made of material.
[0022]
The base body 1 has a recess 1a on the upper main surface, and an electrode pad 6 is provided around the mounting portion 1b in the recess 1a. In the present invention, the base body 1 is a flat plate having no recess 1a. There may be.
[0023]
The electrode pads 6 are electrically connected to input / output electrodes on the upper surface of the semiconductor element 2 through bonding wires 7 made of Au, Al, and the like. It is electrically connected to an external electric circuit or the like via a wiring pattern made of a metallized layer or the like formed on the surface or the like, a lead terminal or the like (not shown).
[0024]
Further, on the bottom surface of the concave portion 1a on the upper main surface of the substrate 1, a resin adhesive in which the semiconductor element 2 is made of an acrylic resin, an epoxy resin, a silicone resin, a polyether amide resin, or the like, or Au—Si, Au -It adheres via the adhesive agent which consists of Sn, Sn-Pb solder, etc.
[0025]
A frame 3 is joined around the recess 1 a on the upper main surface of the base 1. This frame 3 includes Fe-Ni-Co alloy, metal such as Al, Cu, alumina sintered body, aluminum nitride (AlN) sintered body, silicon carbide (SiC) sintered body, silicon nitride (Si 3 N 4 ) Made of sintered material, ceramic materials such as glass ceramics, etc. The planar view shape of the frame 3 is a substantially rectangular shape or the like, and the overall shape is a rectangular parallelepiped shape having a height of about 0.3 to 3 mm and a width of about 1 to 5 mm, for example. The width of the frame 3 is preferably as large as possible in order to maintain the sealing strength. However, if the size exceeds 5 mm, it is difficult to reduce the size of the semiconductor device 5 itself. Further, the height of the frame 3 is preferably higher than the uppermost part of the bonding wire 7 so as not to contact the bonding wire 7, but if it exceeds 3 mm, the height of the semiconductor device 5 itself is low. It becomes difficult.
[0026]
Since the frame body 3 is installed between the base body 1 and the lid body 4, the semiconductor is generated by heat when the lid body 4 is bonded and fixed to the frame body 3 or when the semiconductor device 5 is mounted on an external electric circuit board or the like. The entire apparatus 5 expands, and stress is easily applied to the joints between the base body 1, the frame body 3, and the lid body 4. For this reason, it is preferable to use a material close to the thermal expansion coefficient of each of the base body 1 and the lid body 4 for the frame body 3.
[0027]
The lid 4 is joined to the upper surface of the frame 3 via a solder 8 made of Sn—Pb eutectic solder, Sn—Pb high temperature solder, Au—Sn solder or the like. The lid 4 is made of an Fe-Ni-Co alloy, a metal such as Al or Cu, an alumina sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a glass ceramic, or the like. Made of ceramic materials.
[0028]
As a method of joining the lid 4 to the frame 3, for example, there is a method in which solder 8 is provided in advance on the outer peripheral portion of the lower surface of the lid 4 or the upper surface of the frame 3.
[0029]
In the semiconductor device 5 of the present invention, a plurality of holes 3a are formed on the upper surface of the frame body 3 over the entire periphery downward, and the holes 3a for fitting into the holes 3a on the outer peripheral portion of the lower surface of the lid body 4 are formed. A plurality of projections 4 a shorter than the depth are formed, and the projection 4 a of the lid 4 is fitted into the hole 3 a of the frame 3 to join the frame 3 and the lid 4. As a result, even if a surplus occurs in the solder 8 that joins the lid 4 and the frame 3, most of the solder 8 flows into the holes 3 a of the frame 3, and the solder 8 flows into the recesses 1 a of the base body 1. Can be prevented. Moreover, the positioning at the time of joining the cover body 4 to the frame body 3 can be reliably performed by fitting the protrusions 4a into the holes 3a. Furthermore, the bonding area between the lid body 4 and the frame body 3 can be increased, and the stress applied to the solder 8 that joins the lid body 4 and the frame body 3 by the joint surface between the hole 3a and the projection 4a is greatly relieved. can do. As a result, it is possible to suppress the breakage of the solder 8 at the joint portion between the lid body 4 and the frame body 3. Therefore, high bonding reliability between the lid 4 and the frame 3 can be obtained.
[0030]
Further, the hole 3 a needs to have a larger opening on the lower surface side of the frame body 3 than an opening on the upper surface side of the frame body 3. Thereby, since the volume in the lower side of the solder in the hole 3a is increased, the bonding strength between the base 1 and the frame 3 is improved. Furthermore, since the lid 4 and the frame 3 are joined by the protrusions 4 a and the solder 8, their joint strength is greater than the joint strength between the base 1 and the frame 3. Since the bonding strength is improved, the upper and lower bonding strengths of the frame body 3 are substantially the same, and the bonding strength is substantially the same all around the frame body 3. As a result, the part where the bonding strength is locally deteriorated does not occur at the joint portion of the frame body 3, and the joining property of the frame body 3 becomes better.
[0031]
The hole 3 a may be formed from the upper surface of the frame body 3 to the middle in the thickness direction downward, or may be a through-hole penetrating between the upper and lower surfaces of the frame body 3.
[0032]
The length of the protrusion 4a is shorter than the depth of the hole 3a. Specifically, the length of the protrusion 4a is preferably 0.1 to 2 mm. If it is less than 0.1 mm, the protrusion 4a is easily detached from the hole 3a when the lid 4 is placed on the frame 3. If it exceeds 2 mm, the depth of the hole 3 a will also be 2 mm or more, so it will be difficult to reduce the height of the semiconductor device 5. Moreover, the depth of the hole 3a should just be 0.1-1.0 mm longer than the length of the processus | protrusion 4a. If it is less than 0.1 mm, the solder 8 tends to overflow from the hole 3 a, and if it exceeds 1.0 mm, the solder 8 is difficult to wet on the upper surface of the frame 3. In addition, it is difficult to reduce the height of the semiconductor device 5.
[0033]
The width of the protrusion 4a is preferably 0.05 to 0.3 mm smaller than the width of the hole 3a. If the difference between the width of the protrusion 4a and the width of the hole 3a is less than 0.05 mm, it is difficult to fit the protrusion 4a into the hole 3a. If the difference between the width of the protrusion 4a and the width of the hole 3a exceeds 0.3 mm, the movable range of the lid 4 becomes large when the lid 4 is placed on the upper surface of the frame 3, and positioning becomes difficult. The protrusion 4a is preferably formed continuously so as to have substantially the same length as the hole 3a. In this case, the joint between the frame 3 and the lid 4 becomes strong.
[0034]
Further, the protrusion 4a preferably has a shape in which the vertical cross section is tapered on the lower side, which makes it easy to fit the protrusion 4a into the hole 3a and increases the area of the joint between the protrusion 4a and the hole 3a. . Further, since the solder 8 easily protrudes at both ends of the hole 3a, it is preferable to make the height of the portion at both ends of the hole 3a of the protrusion 4a lower than the other portions. In this case, it is possible to prevent the solder 8 from protruding at both ends of the hole 3a.
[0035]
Further, the width of the hole 3a provided on the upper surface of the frame body 3 is large enough to fit the protrusion 4a of the lid body 4, and the depth of the hole 3a is enough for the surplus portion of the solder 8 to flow in. I can do it. If the width of the hole 3a is too large, the area of both end portions of the hole 3a on the upper surface of the frame 3 is reduced, and the bonding area between the lid 4 and the frame 3 in the upper surface region of the frame 3 is reduced. Tend to decrease.
[0036]
Further, as shown in FIG. 3, it is preferable that the four holes 3 a having substantially the same length as the four sides on the inner side of the upper surface of the frame body 3 are formed. In this case, the joint area of the joint between the hole 3a and the protrusion 4a is substantially maximized, and the stress relaxation effect at the joint is substantially maximized. Furthermore, although the several hole 3a is formed over substantially the perimeter of the upper surface of the frame 3, it is good to have interrupted at the four corners of the frame 3 where a big stress tends to be added. Moreover, when the hole 3a is a through-hole, the hole 3a is interrupted at least at one place. If the hole 3a is formed over the entire circumference of the upper surface of the frame body 3 without interruption, the upper surface of the frame body 3 is divided into the inner side and the outer side by the hole 3a. At this time, positioning of the frame 3 becomes difficult, and the reliability of hermetic sealing due to poor bonding may be reduced.
[0037]
Further, the hole 3a may be a long hole as shown in FIG. 3 , or a plurality of substantially circular or substantially rectangular holes may be formed. Hole 3a is preferably one elongated hole shape as shown in FIG. That is, in the case of the substantially circular hole 3a, the portions on both sides of the hole 3a on the upper surface of the frame body 3 are thinned and the strength of the frame body 3 tends to be reduced. Even if the opening area is the same as that of the object, the portions on both sides of the hole 3a on the upper surface of the frame 3 are thickened so that the strength of the frame 3 can be maintained and the strength of the frame 3 becomes substantially uniform over the entire circumference. Moreover, the stress concerning the junction part of the frame 3 and the cover body 4 can be disperse | distributed.
[0038]
When the hole 3a is a long hole as shown in FIG. 3 , the hole 3a is formed in the center of the upper surface of the frame 3 in the width direction, and the width of the hole 3a is the width of the upper surface of the frame of the frame 3 It is preferably 1/5 to 1/2. If it is less than 1/5, the solder 8 tends to overflow from the hole 3a, and if it exceeds 1/2, the strength of the frame body 3 decreases, cracks or the like occur in the frame body 3 , and airtightness is easily broken.
[0039]
【Example】
Examples of the semiconductor device of the present invention will be described below.
[0040]
Example 1
The semiconductor device of the present invention was configured as follows. An electrode pad 6 made of a W metallized layer is formed around the mounting portion 1b of the upper main surface of the base body 1 made of a rectangular parallelepiped alumina ceramic having a thickness of 1.5 mm × length 20 mm × width 20 mm. Fe- having a height of 15 mm, a width of 15 mm, a height of 1 mm, and a thickness of the frame portion (the width of the upper surface of the frame portion of the frame body 3) of 2 mm so as to surround the mounting portion 1b and the electrode pad 6 on the outer peripheral portion of the surface A rectangular frame 3 made of a Ni—Co alloy was joined with Ag brazing.
[0041]
At this time, the holes 3a (depth 1 mm) formed as the four long holes and the through holes shown in FIG. 3 were formed on the upper surface of the frame 3 at the center of the frame. Then, 10 holes each having various values such as 0.2 mm, 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, and 1.2 mm were prepared.
[0042]
Then, the semiconductor element 2 made of LSI is placed and fixed on the mounting portion 1b with a resin adhesive made of epoxy resin, and the electrode on the upper surface of the semiconductor element 2 is electrically connected to the electrode pad 6 through the bonding wire 7 made of Au. Connected.
[0043]
Next, the lid body 4 made of a Fe—Ni—Co alloy having a thickness of 0.3 mm × length 15 mm × width 15 mm and having a protrusion 4a fitted in the hole 3a on the outer peripheral portion of the lower surface is projected into the hole 3a. 4a was fitted and joined via solder 8 made of Sn—Pb eutectic solder to prepare various semiconductor device samples. At this time, the length of the protrusion 4a was set to 0.3 mm, and the width of the protrusion 4a was reduced by 0.1 mm with respect to the various holes 3a.
[0044]
And about the said various samples, the presence or absence of the overflow from the hole 3a of the solder | pewter 8 was checked in Table 1, and the strength of the frame 3 fell, the crack etc. generate | occur | produced in the frame 3 , and the airtightness was broken. Results are shown.
[0045]
[Table 1]
Figure 0003878897
[0046]
From Table 1, when the width of the hole 3a is 0.2 mm, 3/10 of the solder 8 overflowed from the hole 3a and the electrode pads 6 were short-circuited. In the case where the width of the hole 3a is 1.2 mm, 2/10 of the broken airtightness occurred. On the other hand, there was no problem at all when the width of the hole 3a was 0.4 to 1.0 mm.
[0047]
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.
[0048]
【The invention's effect】
A semiconductor storage package according to the present invention includes a base on which a mounting portion for mounting a semiconductor element is provided on the upper main surface and an electrode pad is formed around the mounting portion on the upper main surface, and an upper side of the base A frame attached to the outer peripheral portion of the main surface so as to surround the mounting portion and the electrode pad, a plurality of holes formed on the upper surface of the frame downwardly over substantially the entire circumference, and a plurality of holes Providing a lid with a plurality of projections on the outer periphery of the lower surface that are shorter than the depth of the holes for fitting to each other, an excess is generated in the solder for joining the lid and the frame Even so, it is possible to prevent most of the solder from flowing into the holes provided in the frame and overflowing from the joint between the lid and the frame and flowing into the electrode pad portion of the substrate.
[0049]
Further, positioning when the lid is placed on the frame can be reliably performed. Furthermore, by fitting the protrusions of the lid body into the holes provided in the frame body, the bonding area between the lid body and the frame body can be increased. It is possible to greatly relieve the stress applied to the solder for joining. As a result, it is possible to suppress breakage of solder at the joint portion between the lid and the frame. Therefore, high joint reliability between the lid and the frame can be obtained.
[0050]
For housing a semiconductor element package of the present invention, the hole of the double number by the lower surface side of the opening of the frame than the upper surface side of the opening of the frame is large, the solder of the bonding area for bonding the cover member, the frame and The volume can be increased. As a result, it is possible to more effectively suppress the occurrence of breakage in the solder at the joint between the lid and the frame, and to more reliably obtain high bonding reliability between the lid and the frame. it can.
[0051]
Further, since the solder in the hole has a large volume on the lower side, the bonding strength between the base and the frame is improved. Furthermore, since the lid and the frame are joined by protrusions and solder, their joint strength is greater than the joint strength between the base and the frame, but the joint strength between the base and the frame is improved. The upper and lower joint strengths of the frame body are substantially the same, and the joint strength is substantially the same over the entire circumference of the frame body. As a result, a portion having a locally deteriorated bonding strength is not generated at the joint portion of the frame body, and the bondability of the frame body becomes better.
[0052]
A semiconductor device according to the present invention includes a semiconductor element storage package according to the present invention, a semiconductor element mounted and fixed on a mounting portion on an upper main surface of a base, and electrically connected to an electrode pad, and a frame body. By providing the lid mounted on the upper surface of the frame by fitting the projection of the lid into the hole, the semiconductor element storage package of the present invention is highly reliable.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor device of the present invention.
FIG. 2 is a cross-sectional view showing another example of the embodiment of the semiconductor device of the present invention.
3A is a plan view of the semiconductor device of FIG. 1 with a lid removed, and FIG. 3B is a plan view of the lower surface of the lid of the semiconductor device of FIG. 1;
FIG. 4 is a cross-sectional view showing an example of a conventional semiconductor device.
5A is a plan view of the semiconductor device of FIG. 4 with the lid removed, and FIG. 5B is a plan view of the lower surface of the lid of the semiconductor device of FIG. 4;
[Explanation of symbols]
1: Base 1b: Placement part 2: Semiconductor element 3: Frame 3a: Hole 4: Lid 4a: Protrusion 5: Semiconductor device 6: Electrode pad

Claims (2)

上側主面に半導体素子を載置する載置部が設けられているとともに前記上側主面の前記載置部の周囲に電極パッドが形成された基体と、該基体の前記上側主面の外周部に前記載置部および前記電極パッドを囲繞するように取着された枠体と、該枠体の上面に下方に向けて略全周にわたって形成された、前記枠体の上面側の開口よりも前記枠体の下面側の開口が大きい複数の穴と、該複数の穴のそれぞれに嵌着させるための前記穴の深さよりも短い突起が下面の外周部に複数形成された蓋体とを具備することを特徴とする半導体素子収納用パッケージ。A base having a mounting portion for mounting a semiconductor element on the upper main surface and having an electrode pad formed around the mounting portion on the upper main surface, and an outer peripheral portion of the upper main surface of the base A frame body attached so as to surround the mounting portion and the electrode pad, and an opening on the upper surface side of the frame body, which is formed on the upper surface of the frame body and extending substantially downward. A plurality of holes having a large opening on the lower surface side of the frame body, and a lid body in which a plurality of protrusions shorter than the depth of the holes for fitting into each of the plurality of holes are formed on the outer peripheral portion of the lower surface. A package for housing a semiconductor element. 請求項１記載の半導体素子収納用パッケージと、前記基体の前記上側主面の前記載置部に載置固定されるとともに前記電極パッドに電気的に接続された半導体素子と、前記枠体の前記穴に前記蓋体の前記突起を嵌着させることにより前記枠体の上面に設置された前記蓋体とを具備したことを特徴とする半導体装置。A package for housing semiconductor chip according to claim 1 Symbol mounting a semiconductor element electrically connected to the electrode pad while being placed and fixed the mounting section of the upper major surface of the substrate, of the frame A semiconductor device comprising: the lid disposed on an upper surface of the frame body by fitting the protrusion of the lid body into the hole.
JP2002277371A 2002-08-30 2002-09-24 Semiconductor element storage package and semiconductor device Expired - Fee Related JP3878897B2 (en)

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AU2019222263B2 (en) * 2018-02-13 2022-02-24 Tanaka Kikinzoku Kogyo K.K. Sealing lid formed from translucent material
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