JP3877424B2 - Direct spread spectrum communication path detection method and apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a direct spread spectrum communication system using direct sequence code division multiple access (DS-CDMA), and more particularly to path detection in the receiver.
[0002]
[Prior art]
In general, in a wireless receiver in a spread spectrum communication system, a correlation between a received signal and a spread code is detected by a correlator, and demodulation is performed using only the correlation peak. Therefore, a correlation peak appears during one spread code period. It is necessary to get the timing of only points. However, the output from the correlator is buried in noise, and path detection is extremely difficult.
In addition to the direct arrival wave (direct path) generated in the open space transmission path, the delay path also contributes to the improvement of the demodulation characteristics. Therefore, it is necessary to detect the appearance timing of the delay path. A RAKE (rake) receiver is known as a receiver that separates a multipath consisting of a set of direct paths and delay paths, and then synchronizes and combines them. Path detection is also performed for such multipath separation processing. It is essential.
[0003]
Here, a configuration example of a conventional path detection apparatus used for path detection will be described with reference to FIG.
In FIG. 11, reference numerals 101 and 102 denote correlators that obtain a correlation between a received signal and a spreading code that the receiver waits. The correlator 101 is set to an I-phase output obtained by quadrature detection of the received signal and the receiver. The correlator 102 generates a despread output based on the correlation between the Q-phase output obtained by orthogonal detection of the received signal and the spread code set in the receiver.
[0004]
These correlators 101 and 102 are composed of, for example, a matched filter (MF) and each has a circuit configuration as shown in FIG. That is, a register in which delay elements 120 of a predetermined number of samples are connected in series, a spread code generator 121 that generates a spread code, a multiplier 122 that multiplies the output of each delay element 120 and the spread code, and each multiplication And an adder 123 for summing the outputs from the unit 122, and sequentially performing a correlation operation between the received signal and the spread code for each sample.
That is, in the path detection apparatus shown in FIG. 11, if the phases of the spread code in the received signal and the spread code output from the spread code generator 121 match, the correlators 101 and 102 have sharp self-characteristic characteristics unique to the spread code. A correlation peak is detected. When a delay path occurs in the transmission path, the autocorrelation peak is shifted by the delay time of the delay path and appears at the outputs of the correlators 101 and 102.
[0005]
Since these correlator outputs have phase fluctuations due to phase rotation in the transmission path, phase transition of the transmission information signal, etc., the I-phase output of the correlator 101 is squared by the squarer 103, and the Q of the correlator 102 is The phase output is squared by the squarer 104, and these square values are added by the adder 105, thereby eliminating the phase fluctuation component.
The output from the adder 105 is accumulated and averaged by an accumulator comprising an adder 106 and a memory 107 (in this example, a digital memory). That is, since the signal exists constantly but the noise is non-stationary, noise immunity is improved by averaging the accumulated values. Here, the memory 107 has a capacity of a number of words (one word is x bits, x is a value that does not overflow when cumulative addition is performed) that is equal to or greater than one spreading code period (exactly one spreading code period × oversampling number). is necessary.
[0006]
The cumulative average value is input to the maximum value detection circuit 108 and the minimum value detection circuit 109 each time, and the maximum value of the cumulative average value is input to the threshold value generation circuit 110 from the maximum value detection circuit 108. From the minimum value detection circuit 109, the minimum value of the cumulative addition average values is input to the threshold value generation circuit 110.
The threshold value creating circuit 110 creates a threshold value by setting the threshold value between the maximum value and the minimum value, for example, using the input minimum value and maximum value, and compares the threshold values. Input to the instrument 111.
Then, the comparator 111 compares the signal value obtained by the cumulative addition and the threshold value, and if a cumulative addition signal exceeding the threshold value appears, the comparator 111 recognizes it as the arrival path appearance and detects the signal. Is output. The detected path position is used as a path appearance timing (= latch timing) to the demultiplexer in a multipath separation circuit as shown in FIG.
[0007]
[Problems to be solved by the invention]
However, in the above-described conventional path detection device, the level value (sum of square values from the adder 105) input to the memory 107 is expressed by multiple bits, so the number of bits of the numerical value accumulated and stored in the memory 107 is There is a problem that the size of the memory 107 increases considerably.
Also, when the correlation detection of the received signal is realized by an analog method, it is desirable to perform digital processing as much as possible in order to reduce power consumption and speed up the processing. However, the A / D converter is required, so that not only the intended purpose cannot be sufficiently achieved but also the cost is increased.
[0008]
The present invention has been made in view of the above-described conventional circumstances, and an object thereof is to provide a path detection method and apparatus that achieves a reduction in the scale of a memory used for cumulative addition processing.
It is another object of the present invention to provide a path detection method and apparatus that can facilitate digital processing.
[0009]
[Means for Solving the Problems]
The path detection method according to the present invention is implemented in a direct spread spectrum receiver, and each of an I-phase output and a Q-phase output obtained by orthogonal detection of a received signal and a spreading code set in the receiver. A despread output by correlation is generated, and a binary output is generated by comparing the sum of the absolute value or square value of the despread output of I phase and the despread output of Q phase with the first threshold value; The binary output of the portion corresponding to one symbol of the received signal is accumulated over a plurality of symbol times, and the accumulated value is compared with the second threshold value, so that the accumulated value becomes the second threshold in one symbol time. A point exceeding the value is determined as an arrival point of the path.
[0010]
By accumulating binary output in this way, the memory capacity required for the cumulative addition process can be reduced to the conventional 1 bit / x bit, and the signal to be processed is binarized by the comparison process. Therefore, the comparison processing and subsequent steps can be digitally processed without using a multi-value A / D converter.
Here, in the path detection method according to the present invention, the first threshold value and the second threshold value can be set by various methods. For example, a fixed value set in advance to eliminate noise is used. It is preferable to increase the accuracy of path detection by eliminating mixed noise as a value or a value that varies depending on the amount of noise in order to eliminate noise.
[0011]
A path detection apparatus according to the present invention is provided in a direct spread spectrum receiver, and each of an I-phase output and a Q-phase output obtained by orthogonal detection of a received signal and a spread code set in the receiver The de-spread output is generated by the correlator by the correlation with the I-phase, the I-phase de-spread output and the Q-phase de-spread output are summed in absolute value, sum of squares, etc. The sum of the level of the despread output and the level of the Q-phase despread output is generated by the first adder. Then, the sum output from the first adder and the first threshold value are compared by the first comparator, and the comparison result is output as a binary value. The binary output from the first comparison means is cumulatively added by an accumulator having an adder, the cumulative output and the second threshold value are compared by a second comparator, and a comparison result appears as a path. Output as a signal.
Since the signal to be processed is binarized by the first comparator in this way, the subsequent cumulative addition processing can be realized by a memory having a much smaller capacity than the conventional one, and multi-value A / D conversion. Even without using a device, the subsequent processing can be digitally processed.
[0012]
Here, the path detection apparatus according to the present invention can be realized in various modes. For example, the first comparator outputs a comparison result as a binary value having a positive / negative sign, and an accumulator. If the binary output from the first comparison means is added with a sign, the memory capacity required for the cumulative addition process can be further reduced.
Further, in the path detection device according to the present invention, fixed values stored in advance in the memory may be used as the first threshold value or the second threshold value. It is preferable to change the threshold value and the second threshold value so that path detection is performed more effectively and accurately.
[0013]
That is, a first threshold value generator that generates a first threshold value based on the sum output generated by the first adder, and a second threshold value that is generated based on the output from the cumulative adder It is preferable that the path detection device further includes a second threshold value generator.
The first threshold value generator includes, for example, a low-pass filter that generates an average value of the sum output generated by the first adder, and adds a predetermined offset to the average value of the generated sum output. And a DC offset adder for generating the first threshold value. Further, the second threshold value generator includes, for example, a low-pass filter that generates an average value of the output generated by the accumulator, and a second threshold value by adding a predetermined offset to the generated average value. And a DC offset adder for generating
[0014]
The path detection process according to the present invention as described above will be described in more detail with specific examples as follows.
The respective outputs are spread as shown in FIG. 10 by the despreading operation based on the correlation between the quadrature-detected I-phase and Q-phase (in-phase coordinate system and orthogonal coordinate system on the complex plane) and the spreading code of the receiver. It becomes the correlation waveform of the code. FIG. 10 shows an analog method in which the correlator is continuous in time and a digital method in which the correlator is discrete in time, respectively, but even in the analog method, a sample hold circuit is used. It can also be constructed discretely.
[0015]
Then, the absolute value or power value of the I-phase and Q-phase of the correlator output (MF output) is taken, and the sum of these is obtained, and the influence of the phase fluctuation due to the information signal and the transmission path fluctuation is eliminated.
Thereafter, the MF output sum is subjected to binary determination with the first threshold value, and the 1-bit comparison output is output as a sample for one symbol (1 spread code length × oversampling number).
[0016]
Since these comparison outputs are obtained at regular intervals (minimum 1 symbol time), the value is added to the value stored in the memory each time, and the result is stored again in the memory and accumulated. To do. Here, when the symbol rate is larger than the fading speed of the transmission path, the change in the appearance position of the path (arrival wave) within the symbol time unit is extremely slow, so the position where the path appears is every symbol time. Since noise does not change greatly and the occurrence of noise is random, noise suppression is enhanced by accumulating and averaging at each sampling point over a plurality of symbol times.
[0017]
There are various methods for creating the first threshold value, but in the example shown in FIG. 10, it is only necessary to create a threshold value that can ignore other than the peak at the center. For this purpose, for example, the point of level 100 may be fixedly set as the first threshold, or the noise level is measured using an external circuit for measuring the noise level, and a margin is added to the noise level. The value may be the first threshold value.
The sampling point that is compared and determined that the accumulated value of the plurality of symbol periods obtained in this way exceeds the second threshold value is determined as the arrival time position of the path (received incoming wave). For example, if the second threshold value is set to half of the maximum value of the cumulative addition value and a value exceeding the second threshold level is recognized as a path, the appearance of the path can be recognized.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
A path detection method and apparatus according to the present invention will be specifically described based on an embodiment thereof.
FIG. 1 shows a configuration of a multipath separation circuit provided in a direct spread spectrum communication system receiver, and a path detection device described below is used as a path detection circuit 1 of the multipath separation circuit. .
In the figure, 2 is a correlator (MF) for acquiring the correlation between the received spread code and the spread code of the receiver, and 3 is a latch for latching the output of the correlator 2 at the timing given from the demultiplexer 4. This demultiplexer 4 distributes the appearance timings of paths, which are serial data series obtained from the path detection circuit 1, in parallel and inputs them to each latch circuit 3. That is, in this multipath separation circuit, only the peak value at the time when the correlation peak appears in the output of the correlator 2 is required, and no other noise region is required, so only the peak point is extracted from the path detection circuit 1. Are extracted based on the path appearance timing. Note that this multipath separation circuit can handle up to four correlation peaks.
[0019]
FIG. 2 shows a configuration example of the path detection circuit 1 described above.
In FIG. 2, 11 and 12 are correlators for obtaining a correlation between a received signal and a spreading code that the receiver waits for. The correlator 11 is set to an I-phase output obtained by orthogonal detection of the received signal and the receiver. The de-spread output is generated by the correlation with the spread code, and the correlator 12 generates the de-spread output by the correlation between the Q-phase output obtained by orthogonal detection of the received signal and the spread code set in the receiver. .
These correlators 11 and 12 are composed of, for example, a matched filter (MF), and each has a circuit configuration similar to that shown in FIG. The correlators 11 and 12 can be realized in either digital signal processing or analog signal processing.
[0020]
In FIG. 2, reference numerals 13 and 14 denote level detectors for obtaining level values such as amplitude values and power values obtained by removing the influence of phase fluctuations from the despread outputs of the correlators 11 and 12, respectively. Is a first adder that simply adds the levels of Q and Q, and 16 is a first threshold for adjusting the level of the output of the correlator and generating a first threshold value to be provided to the first comparator 17 at the subsequent stage. It is a value creation circuit.
In the illustrated example, the level detectors 13 and 14 convert the despread outputs into absolute values, but the despread outputs may be squared to obtain level values. In this example, the first threshold value creating circuit 16 generates the first threshold value corresponding to the level of the correlator output sum. However, the first threshold value creating circuit 16 sets a certain fixed value suitable for eliminating noise. It may be supplied as a threshold value of 1.
[0021]
The first comparator 17 compares the sum of the I-phase and Q-phase levels with the first threshold value, and makes the comparison result a binary value (1, −1) with a positive / negative sign for the second addition. The second adder 18 adds the binary of the comparison result and the output from the cumulative addition memory 19 with a sign. In the present invention, the first comparator 17 outputs a simple binary value (0, 1), and the second adder 18 simply adds the binary value and the output from the cumulative addition memory 19. May be.
Here, the memory 19 has a capacity for holding an accumulated addition value of at least one spread code period, and the addition result by the second adder 18 is accumulated and averaged over a plurality of symbol times. That is, the output from the second adder 18 is input to the second comparator 20 and is input again to the same write address as the read address of the memory 19, and the second adder 18 and the memory 19 perform cumulative addition. Make up the vessel.
[0022]
The second comparator 20 compares the second threshold value created by the second threshold value creation circuit 21 with the output from the cumulative adder and confirms that a path has been detected by this comparison. Output in binary (1, 0). That is, the binary output of the path detection is input from the path detection circuit 1 shown in FIG. 1 to the demultiplexer 4 as a path appearance timing signal.
Here, the second threshold value creating circuit 21 can have various configurations according to system requirements. For example, when only a path with a high average level is to be detected, a high value is fixed as the second threshold value. If it is desired to detect a low level path, a variation value based on the output from the accumulator is generated as the second threshold value as will be described later. That's fine.
[0023]
The path detection circuit 1 having the above configuration will be described in more detail according to the processing operation.
The I transmission signal and Q transmission signal of the baseband reception signal subjected to quadrature detection are input to the correlators 11 and 12, respectively, and despread as described above. Here, the tap coefficients of the correlators 11 and 12 are given a spread code (referred to as a reference) created by the receiver, and are despread by the correlation with the reference.
The correlators 11 and 12 include a digital type and an analog type, but both can be adopted in the present invention.
[0024]
Level detectors 13, 14 and the first adder 15, converts the despread output from the correlator 11 and 12, for example, I ² of + Q ² square root and I by calculating the ² + Q ² to the amplitude value or power value Thus, the influence of the phase fluctuation that the received signal receives is eliminated. FIG. 3 shows a representative example of the despread output output from the first adder 15, and a high correlation peak is obtained as shown in FIG.
The first threshold value creating circuit 16 creates a fixed level or a fluctuation level using the output from the first adder 15. When creating a fluctuation level, as will be described later, when creating a fixed level, for example, if the correlators 11 and 12 are analog correlators having a full range of 0 to 3 V, the output voltage is Since the operation is performed at the 1.5V center, the first threshold value creating circuit 16 outputs 1.7V as the first threshold value. In this case, it is desirable that the first adder 15 is also an analog system that operates at a 1.5 V center.
[0025]
The first comparator 17 performs level comparison between the first threshold value obtained from the first threshold value creating circuit 16 and the output from the first adder 15, and the comparison result is a signed 2 Output by value.
The second adder 18 adds the binary value of the comparison result and the accumulated value output from the memory 19 with a sign. For example, +1 is added if the output from the first comparator 17 is 1, and -1 is added if the output is 0. Then, the addition result is again input to the same address of the memory 19 to be accumulated and input to the second comparator 20.
[0026]
Here, in the memory 19, the binary output of the comparison result is averaged over a plurality of symbol times. This is because the correlation peak value can be clearly recognized in the example shown in FIG. 3, but the correlation peak value becomes unclear when the noise level increases, and thus the path can be easily recognized by averaging over a plurality of symbol times in this way. It has become.
Since the first comparator 17 performs binary determination, the subsequent stage from the first comparator 17 can be easily replaced with a digital circuit. That is, even if the correlators 11 and 12 to the first comparator 17 are configured in an analog system, the first comparator 17 itself functions as a 1-bit A / D converter. Can be constructed in a digital system without an A / D converter.
[0027]
The output that has been cumulatively averaged as described above is input to the second comparator 20 and subjected to binary determination based on the second threshold value created by the second threshold value creating circuit 21.
FIG. 4 shows the relationship between the second threshold value output from the second threshold value creating circuit 21 and the cumulative addition output from the second adder 18. For example, the cumulative addition output has a second threshold value. The binary determination result is output from the second comparator 20 as a path appearance timing signal, such as 1 when the value exceeds the value and 0 when the value is less than the value.
In FIG. 4, since a two-wave multipath model is assumed as an input signal, a central preceding wave and a subsequent delayed wave are detected in the figure.
[0028]
The second threshold generation circuit 21 can change its configuration according to a system request, and can be set to generate the second threshold as a fixed value or a variation value based on an input.
In order to generate the second threshold value as a fluctuation value as shown in FIG. 4, the second threshold value creating circuit 21 is configured as shown in FIG. 5, for example.
[0029]
That is, in the second threshold value creating circuit 21 having the configuration shown in FIG. 5, the cumulative addition signal from the second adder 18 is compared with the threshold value one sample time before obtained from the memory 23 in the comparator 22. The comparison result is output as 0 and 1. The comparator 22 outputs, for example, a comparison result of 0 when the level of the cumulative addition signal is lower than the threshold, and a comparison result of 1 when the level of the cumulative addition signal is higher than the threshold. Then, the switch 24 operates in response to the comparison result. For example, if it is 0, +1 is added, and if it is 1, -1 is added to the current threshold value by the adder 25, and the addition result is stored in the memory 23. . That is, an LPF in a broad sense is configured.
[0030]
Since the threshold value accumulated in the memory 23 detects the noise floor of the despread output obtained by cumulative averaging (see the thin dotted line in FIG. 9 described later), if a DC offset is given to this level, A value larger than the noise floor is detected as a path (see the thick dotted line in FIG. 9). Therefore, a value obtained by adding this DC offset to the current threshold value by the adder 26 is supplied to the second comparator 20 as the second threshold value.
Depending on the number of oversamplings, even in the above method, there may be many detected values even though there is only one incoming path. In this way, when paths are detected continuously, only the head or rear sample may be set as the path detection position.
[0031]
Next, an example of the configuration in the case where the first threshold value creating circuit 16 creates the first threshold value whose level varies using the output from the first adder 15 will be described in detail.
The first threshold value creating circuit 16 is composed of an LPF circuit 31 and a DC offset adding unit 41.
As shown in FIG. 6, the LPF circuit 31 is a first-order LPF composed of, for example, a resistor 32 and a capacitor 33, and limits the level of the despread signal obtained from the first adder 15. The purpose of the LPF circuit 31 is to measure noise levels other than the peak values (64th and 94th) as seen in the MF output example shown in FIG. Therefore, the larger the time constant RC, the more stable the LPF output level. However, as shown in FIG. 7, the output from the LPF circuit 31 differs from the level corresponding to the MF output.
[0032]
FIG. 8 shows the spectrum before and after input to the LPF circuit 31 obtained by computer simulation with the time constant RC as one symbol period. In the figure, the darker portions are before the input to the LPF circuit 31, and the lighter portions are the output from the LPF circuit 31. As can be seen from the figure, the level attenuation is moderate due to the primary LPF.
FIG. 9 shows signals when the averaged output of the output from the LPF circuit 31 and the MF output (output from the first adder 15) is viewed in time. As can be seen from the figure, the LPF output is an output obtained by averaging the MF output over time.
[0033]
The DC offset adding unit 41 is a part that gives a DC offset to the output from the LPF circuit 31 as described above. Note that the DC offset adder 41 can have the same configuration as that of the DC offset adder 26 of the second threshold value creating circuit 21 shown in FIG. 5, and the output from the LPF circuit 31 (variation based on the input). A predetermined fixed value may be added to (value) and supplied to the first comparator 17 as the second threshold value.
That is, as shown in FIG. 9, the DC offset adding unit 41 gives an appropriate DC offset to the output of the LPF circuit 31 and uses this value as the first threshold value (thick broken line in the figure) for the first comparison. Supply to the vessel 17. Therefore, in the first comparator 17, only the two high-peak paths shown in the central part of FIG. 9 exceed the first threshold value, and the detection signals of these peaks are further recognized as paths through subsequent processing. .
[0034]
【The invention's effect】
As described above in detail, according to the present invention, since the comparison result is output from the first comparator with 1 bit, the memory size for cumulative addition can be greatly reduced as compared with the prior art. Thus, even if the correlation processing is realized in an analog manner, the subsequent processing can be easily digitized without using an A / D converter to speed up processing and reduce power consumption. Can be achieved.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a multipath separation circuit as an application example of a path detection circuit.
FIG. 2 is a diagram illustrating a configuration of a path detection apparatus according to an embodiment of the present invention.
FIG. 3 is a diagram showing an MF output when the transmission path is a two-wave model and Eb / NO indicating a noise level is 100 dB as a representative example of the MF output.
FIG. 4 is a diagram illustrating a relationship between an accumulated output and a second threshold value.
FIG. 5 is a diagram illustrating a configuration of an example of a second threshold value creating circuit.
FIG. 6 is a diagram illustrating a configuration of an example of a primary LPF circuit.
FIG. 7 is a diagram illustrating an output example from an LPF circuit.
FIG. 8 is a diagram showing a spectrum comparison between the input before the LPF circuit and the output from the LPF circuit.
FIG. 9 is a diagram illustrating a relationship between an MF output and an output of an LPF circuit and a first threshold value.
FIG. 10 is a diagram illustrating an example of MF output.
FIG. 11 is a diagram illustrating a configuration of a conventional path detection apparatus.
FIG. 12 is a diagram illustrating a configuration example of a correlator.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Path detection device 11, 12 ... Correlator,
13, 14 ... level detector, 15 ... first adder,
16 ... 1st threshold value generator, 17 ... 1st comparator,
18 ... second adder (cumulative adder), 19 ... memory (cumulative adder),
20 ... second comparator, 21 ... second threshold value generator,
31 ... LPF circuit, 41 ... DC offset adder,

Claims (10)

In a path detection method provided in a direct spread spectrum receiver,
Generating a despread output based on the correlation between each of the I-phase output and the Q-phase output obtained by orthogonal detection of the received signal and the spreading code set in the receiver;
The sum of the absolute values of the I-phase despread output and the Q-phase despread output is compared with the first threshold value to generate a binary output,
The binary output of the portion corresponding to one symbol of the received signal is accumulated over a plurality of symbol times,
A direct spread spectrum characterized in that by comparing and determining the accumulated value with a second threshold value, a point where the accumulated value exceeds the second threshold value during one symbol time is determined as a path arrival point. Path detection method for communication method. In a path detection method provided in a direct spread spectrum receiver,
Generating a despread output based on the correlation between each of the I-phase output and the Q-phase output obtained by orthogonal detection of the received signal and the spreading code set in the receiver;
The sum of square values of the I-phase despread output and the Q-phase despread output is compared with the first threshold value to generate a binary output,
The binary output of the portion corresponding to one symbol of the received signal is accumulated over a plurality of symbol times,
A direct spread spectrum characterized in that by comparing and determining the accumulated value with a second threshold value, a point where the accumulated value exceeds the second threshold value during one symbol time is determined as a path arrival point. Path detection method for communication method. In the path detection method of the direct spread spectrum communication system according to claim 1 or 2,
At least one of the first threshold value and the second threshold value is a fixed value preset in order to eliminate noise, and a path detection method of a direct spread spectrum communication system, characterized in that: In the path detection method of the direct spread spectrum communication system according to claim 1 or 2,
At least one of the first threshold value and the second threshold value is a value that fluctuates depending on the amount of noise in order to eliminate noise. In a path detection device provided in a direct spread spectrum receiver,
A correlator for generating a despread output based on a correlation between each of the I-phase output and the Q-phase output obtained by orthogonal detection of the received signal and a spread code set in the receiver;
A level detector for determining the levels of the I-phase despread output and the Q-phase despread output output from the correlator;
A first adder for generating the sum of the level of the I-phase despread output and the level of the Q-phase despread output determined by the level detector;
A first comparator that compares the sum output from the first adder with a first threshold value and outputs a comparison result in binary;
A storage area having a memory and a second adder of one spread code period or more, and a cumulative adder for accumulating the binary output from the first comparison means;
A second comparator that compares the output from the accumulator with a second threshold value and outputs the comparison result as a path appearance signal;
A direct spread spectrum communication type path detection apparatus. In the direct spread spectrum communication path detection device according to claim 5,
The first comparator outputs the comparison result as a binary value having a positive / negative sign,
The accumulator adds a binary output from the first comparison means with a sign, and is a direct spread spectrum communication type path detection apparatus. In the direct spread spectrum communication path detection device according to claim 5 or 6,
A direct spread spectrum communication type path detection apparatus, further comprising a first threshold value generator for generating a first threshold value based on the sum output generated by the first adder. The direct spread spectrum communication path detection device according to claim 7,
The first threshold value generator includes a low-pass filter that generates an average value of the sum output generated by the first adder, and a first threshold by adding a predetermined offset to the average value of the generated sum output. A direct spread spectrum communication type path detection apparatus comprising: a direct current offset adder for generating a value. In the direct spread spectrum communication path detection device according to any one of claims 5 to 8,
A direct spread spectrum communication type path detection apparatus, further comprising a second threshold value generator for generating a second threshold value based on an output from an accumulator. The direct spread spectrum communication path detection device according to claim 9,
The second threshold value generator includes a low-pass filter that generates an average value of the output generated by the accumulator, and a direct current that generates a second threshold value by adding a predetermined offset to the generated average value. And a direct spread spectrum communication type path detection apparatus.

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