JP3870190B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing method.

  FIG. 27 is a block diagram showing the configuration of the scanner image processing circuit in the conventional image processing apparatus. As an image reading device, an optical element such as a CCD 2010 or CIS 2110 is used, and data according to a predetermined output format for each line unit in the main scanning direction is respectively converted into a CCD interface (I / F) circuit 2000 and a CIS interface (I / F). ) A / D converted by the circuit 2100 and stored in the main memory 2200. In this case, the CCD 2010 outputs data corresponding to R, G, and B in parallel, while the signal output from the CIS 2110 outputs R, G, and B data serially according to the lighting order of the LEDs. Due to the difference in the characteristics of the output data, a dedicated interface circuit is provided, and the read image data is stored in the main memory (SDRAM) 2200 through a predetermined A / D conversion process. .

  In FIG. 27, dedicated line buffers 2400a to 2400d are provided in each image processing block (shading correction (SHD) 2300, character determination processing 2320, filter processing 2340, etc.). In such a circuit configuration, the data stored in the main memory (SDRAM) 2200 is read for a plurality of lines in the main scanning direction, stored in dedicated line buffers (2400a to 2400d), and subjected to individual image processing. The composition was taken.

As a prior art disclosing the configuration of the above-described conventional example, there is one disclosed in Patent Document 1, for example.
JP-A-7-170372

  However, in a circuit configuration in which dedicated line buffers 2400a to 2400d are provided for each processing unit, the maximum number of pixels in the main scanning direction that can be processed depends on the memory capacity of the dedicated line buffer provided in each processing unit. As a result, the processing throughput is limited.

  Further, in order to improve the processing capability, in the hardware configuration of the image processing circuit, an increase in the capacity of the line buffer increases the cost burden, and hinders cost reduction of the entire image processing apparatus.

  Further, since the signals output from the CCD 2010 and CIS 2110 as the image reading device are processed by dedicated interface circuits (2000, 2100) suitable for the respective output formats, the read image data is developed on the main memory 2200. Therefore, it depends on which device (for example, CCD or CIS) is used, and dedicated image data input processing has become indispensable. That is, the image processing circuit is customized depending on which image reading device is used, and this has been a factor that hinders generalization and cost reduction of the image processing circuit.

In view of the above problems, and an object thereof is to provide a compatible image processing apparatus or the like to various image reading devices.

  In order to achieve the above object, an image processing apparatus according to the present invention mainly includes the following configuration.

That is, the image processing apparatus, the first image reading device, image data of multiple several colors to be output to the serial image data of a plurality of colors in a line unit of one line in the main scanning direction using a single data channel The second image reading device that outputs in parallel in units of lines in which the main scanning direction is one line using a plurality of data channels corresponding to the number of colors, or the plurality of color image data using the plurality of data channels Interface means connected to one of the third image reading devices that serially output one line in a unit divided according to the number of channels ;
Generating address information for DMA transfer of the image data of the plurality of colors input via the interface means to the memory, DMA transfer of the image data of the plurality of colors to the memory based on the address information, DMA transfer means having a plurality of DMA transfer units corresponding to a plurality of data channels,
When the first image reading device is connected to the interface means and the image data of the plurality of colors is serially input to any one of the plurality of DMA transfer units in units of lines , The DMA transfer unit generates the address information so that the image data of the plurality of colors is stored in different areas for each color,
When the second image reading device is connected to the interface means, and the image data of the plurality of colors is input to each of the plurality of DMA transfer units in parallel in units of lines for each color, the plurality of DMA transfers Each of the units generates the address information so that the image data of the plurality of colors is stored in a different area for each color ,
When the third image reading device is connected to the interface means, and the image data of the plurality of colors is serially input to each of the plurality of DMA transfer units in units obtained by dividing the one line according to the number of channels. Each of the plurality of DMA transfer units generates the address information so that the image data of the plurality of colors is stored in different areas for each color and the image data can be read from the memory in units of lines. To do.

  According to the present invention, a first image reading device that serially outputs image data of a plurality of colors using a single data channel in units of lines with the main scanning direction as one line, the number of colors of image data of a plurality of colors A second image reading device that outputs a plurality of data channels in parallel using a plurality of data channels in parallel with the main scanning direction as one line, or a plurality of color image data using a plurality of data channels, one line per channel It is possible to support a third image reading device that outputs serially in units divided according to the image data, and even when any image reading device is connected, the image data of a plurality of colors is stored in different memory areas for each color. It is possible to perform DMA transfer and read image data from the memory in units of lines.

  Regardless of the output format of the image reading device, R, G, and B data are separated and image data is stored in the main memory. Therefore, it is not necessary to perform DMA transfer according to the output format of the image reading device to the subsequent image processing unit, and it is only necessary to perform DMA transfer according to the required image processing. Therefore, it is possible to provide an image processing apparatus corresponding to the output format of the image reading device with a very simple configuration / control.

  Alternatively, by setting a rectangular area corresponding to the image processing mode on the memory and switching the unit of the rectangular area, it is possible to realize resolution and high-definition processing corresponding to each image processing mode.

  Alternatively, according to the image processing mode, a rectangular area including a predetermined margin is set, and image processing is performed in units of the rectangular area, so that a predetermined image can be obtained without intervening individual line buffers in each image processing unit. It becomes possible to execute processing.

  FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus 200 according to an embodiment of the present invention. A scanner interface (hereinafter referred to as “scanner I / F”) unit 10 is connected to a CCD 17 and a CIS 18 via an analog front end (AFE) 15, and the read data without interposing dedicated dedicated circuits. Can be taken into the image processing apparatus 200. Data processing of the scanner I / F unit 10 will be described in detail later.

  Reference numeral 20 denotes a scanner image processing unit. The image data developed in the main memory 100 by the processing of the scanner I / F unit 10 is set in an image processing operation mode (color copy, monochrome copy, color scan, monochrome scan, etc.). It is a processing unit that executes corresponding image processing. Details of the scanner image processing unit 20 will be described later.

  The printer image processing unit 30 is a processing unit for outputting image data obtained as a result of image processing to a printer, and an image is connected to a laser beam printer (LBP) 45 connected through an LBP interface (I / F) 40. Execute processing to output the processing result.

  Reference numerals 50 and 60 denote JPEG and JBIG modules, which are processing units for executing image data compression / decompression processing conforming to a predetermined standard.

  Reference numeral 70 denotes a memory control unit, which is connected to the first BUS 80 of the image processing system and the second BUS 85 of the computer system, and is a processing unit (LDMAC_A to F (105a) for executing DMA control related to writing and reading of data with respect to the main memory (SDRAM) 100. To 105f)). Here, “DMA (Direct Memory Access)” refers to a process of moving data directly between the main storage device and the peripheral device.

  The above-described scanner I / F unit 10, scanner image processing unit 20, printer image processing unit 30, LBP I / F unit 40, JPEG processing unit 50, JBIG processing unit 60, and each processing unit Corresponding to (10-60), processing units (LDMAC_A to F (105a to 105f)) for executing DMA control of image data are connected.

  Each of the LDMAC_A to F (105a to 105f) generates predetermined address information for executing DMA control regarding data exchange between each image processing unit (10 to 60) and the main memory 100, and stores the information in this information. Based on this, the DMA is controlled. For example, the LDMAC_A (105a) stores address information (DMA) for transferring the image data read by the scanner I / F unit 10 to the main memory 100 according to the type of the image reading device, the CCD 17, and the CIS 18. Start address, offset information for switching the memory address, etc.) are generated for each DMA channel. Also, the LDMAC_B (105b) generates address information for reading the image data expanded on the main memory 100 according to the DMA channel.

  Similarly, for LDMAC_C to F (105c to f), predetermined address information can be generated, and DMA control related to data exchange with the main memory 100 can be executed based on the information. In other words, the LDMAC_C to F (105c to f) have channels corresponding to data writing and reading, generate address information corresponding to these channels, and control the DMA.

  Reference numeral 80 denotes a first BUS capable of transferring data between the processing units (10 to 60) of the image processing system. Reference numeral 85 denotes a CPU 180, a communication and user interface control unit 170, a mechatronics system control unit 125, and a ROM 95. Is the second BUS of the computer system to be connected. The CPU 180 can control the above-described LDMAC_A to F (105a to f) based on the control parameter and the control program stored in the ROM 95.

  The mechatronics system control unit 125 includes a motor control unit 110 and an interrupt timer control unit 120 that controls timing for controlling motor drive timing and image processing system processing.

  The LCD control unit 130 is a unit that controls display for displaying various settings, processing statuses, and the like of the image processing apparatus on the LCD 135.

  Reference numerals 140 and 150 denote USB interface units that enable connection with peripheral devices. FIG. 1 shows a state in which the BJ-printer 175 is connected.

  Reference numeral 160 denotes a media access control (MAC) unit that controls at what timing (access) data should be sent to a connected device.

  A CPU 180 controls the overall operation of the image processing apparatus 200.

<Configuration of Scanner I / F Unit 10>
The scanner I / F unit 10 can correspond to the CCD 17 and the CIS 18 as image reading devices, and inputs signals of both image reading devices. The image data input here is DMA-transferred by LDMAC_A (105a) and developed on the main memory 100.

  FIG. 2 is a block diagram illustrating a schematic configuration of the scanner I / F unit 10. For the CCD 17 / CIS 18, the timing controller 11a generates and outputs a reading device control signal corresponding to the reading speed. This device control signal is synchronized with a synchronization signal generated in the scanner I / F unit 10, whereby the reading timing in the main scanning direction and the reading process can be synchronized.

  The LED lighting control unit 11b is a unit that controls the lighting of the LED 19 serving as the light source of the CCD 17 / CIS 18, and is a synchronization signal (TG, SP, FIG. 5) for controlling the sequential lighting of LEDs corresponding to the R, G, and B color elements. 3 (a) (see FIG. 4), clock signal (CLK, see FIG. 4) and dimming control corresponding to the CCD 17 / CIS 18, start of lighting, and extinction control. This control timing is based on the synchronization signal received from the above-described timing control unit, and the lighting of the LED 19 synchronized with the driving of the image reading device is controlled.

  3A to 3D are diagrams illustrating an output signal from the CCD 17. The light emitted from the LED 19 illuminates the document surface, and the reflected light is guided to the CCD 17 for photoelectric conversion. For example, the original surface is sequentially scanned for each line in the main scanning direction while moving the reading position at a constant speed in the direction perpendicular to the line direction of the CCD 17 that is the main scanning direction (sub-scanning direction). Can be read. As shown in FIG. 3A, signals corresponding to R, G, and B elements for one line of the CCD 17 are output in parallel based on the synchronization signal (TG) output from the timing controller 11a (FIG. 3). (See (b), (c), (d)).

  On the other hand, FIG. 4 is a timing chart regarding the lighting control of the LED 19 with respect to the CIS 18, and based on the synchronization signal (SP) and the clock (CLK) generated by the LED lighting control unit 11b, the lighting of each R, G, B LED is performed. Start and turn-off timing are controlled. The period of the synchronization signal (SP) is indicated by Tstg, and the lighting of the LED is controlled by any one of these colors (R, G, B) or a combination thereof within this time. Tled indicates the lighting time of the LED in one cycle (Tstg) of the synchronization signal (SP).

  FIG. 5A shows the lighting of LEDs corresponding to R, G, and B ((a) to (d)) according to the timing chart of FIG. 4 described above, and the reflected light of the LED accumulated during the lighting time. It is a timing chart which shows the photoelectrically converted output (e). As is clear from (e) of FIG. 5A, the output of the signals corresponding to the R, G, and B colors is output as R data, G output, and B output, respectively, as serial data, and the CCD 17 described above. Is different from the output signal.

  FIG. 5B is a diagram showing the timing when the R, G, B LEDs 19 are sequentially lit within one cycle of the synchronization signal (SP) in relation to the control of the CIS 18, and R, G, B data Thus, the input of the image reading device in this case can be taken into the image processing apparatus 200 as monochrome image data.

  FIG. 5C is a diagram illustrating an output when the CIS 18 is provided with two channels in the main scanning direction. The output of channel 1 ((c) of FIG. 5C) is synchronized with the falling edge of the Nth CLK signal (see (b) of FIG. 5C), and an arbitrary dummy bit string (of (c) of FIG. 5C). In this case, 22 bits) are output, and then a signal corresponding to 3254 effective bits is output ((c) in FIG. 5C). On the other hand, the output of channel 2 ((d) in FIG. 5C) is synchronized with the falling edge of the Nth CLK signal from the valid bit 3255th bit (the bit following the last bit 3254 of the sensor output of channel 1). 2794 bits are output as valid bits.

  The data for one line in the main scanning direction can be divided and read by the sensor outputs of the two channels. Note that the configuration of the CIS is not limited to a maximum of 2 channels. For example, even if the configuration is a 3 channel, only the number of outputs of the number of effective bits changes, and the gist of the present invention is not limited.

  Returning to the block diagram of FIG. 2, the output signal of the image reading device (CCD 17 / CIS 18) is input to an AFE (analog front end) 15. As shown in FIG. 6, the processing of the AFE 15 performs gain adjustment (15a, 15d) and A / D conversion processing (15b, c, e) on the output signals of the CCD 17 and the CIS 18, and from each image reading device. The output analog signal is converted into a digital signal and input to the scanner I / F unit 10. The AFE 15 can convert parallel data output from the image reading device into serial data and output the serial data.

  The synchronization control unit 11c in FIG. 2 sets a predetermined threshold level for the AFE 15 according to the analog signal of each device (17, 18), and adjusts the output signal level according to the difference in the image reading device. Further, sampling control of the analog signal and generation and output of a synchronous clock for outputting the digital signal to the AFE 15 are received, and read image data by a predetermined digital signal is received from the AFE 15. This data is input to the output data control unit 11d via the synchronization control unit 11c. The output data control unit 11d buffers the image data received from the AFE 15 in accordance with the output mode of the scanner I / F unit 10 (11e , F, g).

  The output mode of the scanner I / F unit 10 can be switched between a single mode, a 2-channel (ch) mode, and a 3-channel (ch) mode, depending on the image reading device to be connected.

  The single mode is a mode selected when main scanning direction data is serially input from the AFE 15, and in this case, only one buffer is available.

  The 2ch mode is a mode selected when data input from the AFE 15 is input at the same timing as information for two channels of the image reading device. In this case, two buffers (for example, 11e, 11f) is set to an available state.

  The 3ch mode is a mode that is selected when image data received from the AFE 15 is input at the same timing as R, G, and B outputs. In this case, three buffers (11e, f, and g) are provided. Set to available state.

  When the color image data is read by the CIS 18 in the single mode, the data received from the AFE 15 is serially output as R, G, B data according to the lighting order of the LEDs as shown in FIG. 5A (e). The output data control unit 11d stores the data in one buffer (for example, the first buffer (11e)) according to this arrangement. The same applies when monochrome image data is read by the CIS 18, and the monochrome image data is stored in one buffer.

  When the color image data is read by the 2-channel CIS 18, the above-described 2ch mode is set. As shown in FIGS. 5C and 5D, the data received from the AFE 15 is data for each area divided into two in the main scanning direction. In order to store the data for each area, the output data control unit 11d stores the received data in two buffers (for example, the first buffer (11e) and the second buffer (11f)). This process is the same even when monochrome image data is read by the CIS2 channel.

  When the color image data is read by the CCD 17, the output data control unit 11d receives the data received from the AFE 15 in three buffers (first, second, and third buffers) for each of R, G, and B data in the above-described 3ch mode. (11e, f, g)) can be sorted and stored.

  Next, a description will be given of a process in which image data stored in a predetermined buffer (11e, f, g) is DMA-transferred to the main memory (SDRAM) 100 and stored by the process of the scanner I / F unit 10. The process of storing the image data by DMA transfer to the main memory 100 is controlled by the LDMAC_A (105a).

  FIG. 7 shows an example of a DMA between the LDMAC_A (105a) for DMA transfer of image data read by the image reading device (17, 18) to the main memory (SDRAM) 100, and the main memory 100 and the scanner image processing unit 20. It is a figure which shows the schematic structure of LDMAC_B (105b) which controls.

  A buffer controller 75 controls the LDMAC_A (105a) and the LDMAC_B (105b) in order to arbitrate data writing and reading when the main memory 100 is used as a ring buffer.

<Configuration of LDMAC_A (105a)>
Here, the LDMAC_A (105a) includes a data arbitration unit 71a, a first write data interface (I / F) unit 71b, and an I / O interface unit 71c.

  In order to store data in the main memory 100, the I / O interface unit 71c sets predetermined address information generated by the LDMAC_A in the first write data I / F unit 71b. Also, the image data is received from the scanner I / F unit 10 and stored in each buffer channel (hereinafter referred to as “channel”) (ch0 to ch2) in the LDMAC_A (105a).

  The first write data I / F unit 71b is connected to the third BUS 73 for writing data to the main memory 100, and the data stored in each channel (ch0 to ch2) according to the generated predetermined address information. Are transferred to the main memory 100 by DMA. The data arbitration unit 71a reads the data stored in each channel, and delivers the data of each channel in accordance with the writing process of the first write data I / F unit 71b.

  The first write data I / F unit 71b is connected to the buffer controller 75, and is controlled so that memory access does not compete with data read or write by the LDMAC_B (105b) described later. Even when the main memory 100 is used as a ring buffer by controlling access to the main memory 100, data is overwritten to the same memory address before the data stored in the main memory 100 is read. Troubles can be prevented and memory resources can be used effectively.

<(1) Storage of data for one channel>
FIGS. 8A and 8B are diagrams for describing processing in which the LDMAC_A 105 a writes data for one channel to the main memory (SDRAM) 100. Like the output example shown in FIG. 5A (e), R, G, B data for one line in the main scanning direction is serially output, and one buffer (11 in FIG. 2) of the scanner I / F unit 10 is output. When data is stored in (e)), the data is transferred to one corresponding channel (ch0, see FIG. 7) in LDMAC_A (105a). Here, in FIGS. 8A, 8B, 9A, 9B, and 10, the data of the channel (ch0) is transferred to the data arbitration unit 71a and the first write data I / F unit 71b. The configuration for performing DMA transfer and storing in the main memory 100 is denoted as “first LDMAC”, the configuration for processing channel (ch1) data is “second LDMAC”, and the channel (ch2) data is processed. The configuration for this is denoted as “third LDMAC”.

  FIG. 8A is a diagram illustrating a process of storing color image data of one channel separately into R, G, and B data. The first LDMAC writes R data for one line (R1 to R2) in the main scanning direction among the R, G, and B data in the line order to the R area (1000a) of the main memory 100, and is the next writing area G. The write address is switched to the start address (G1) of the area (1000b). Then, the first LDMAC writes the G data for one line (G1 to G2) in the main scanning direction among the R, G, and B data to the G area (1000b) of the main memory 100, and the next B area that is the next writing area The write address is switched to the start address (B1) of (1000c). The first LDMAC writes the B data for one line (B1 to B2) in the main scanning direction to the B area (1000c) of the main memory 100, and then addresses the first address (R2) of the second line in the R area (1000a). Switch to. Thereafter, the G data and B data are similarly written by shifting the data write address to the second line in the sub-scanning direction.

  In the DMA control in which the first LDMAC writes data, the address of the memory that is the storage destination of data corresponding to the R data, G data, and B data is given as offset information (A, B), and the storage area for each color data is switched. Thus, the R, G, and B data in the line order can be stored in the main memory 100 separately from the R data, the G data, and the B data.

  The start address for starting DMA transfer (R1 in the case of FIG. 8A), offset information (A, B), and the like are due to the generation of the LDMAC_A (105a) described above.

  FIG. 8B is a diagram illustrating monochrome image data writing processing by the CIS 18 obtained at the LED lighting timing shown in FIG. 5B. In the case of monochrome image data, since it is not necessary to separate the data for each of R, G, and B, monochrome image data of line order is obtained as data for one line (M1 to M2) in the main scanning direction of the main memory 100. Write, the write address is shifted in the sub-scanning direction of the same area (1000d), and data for the next second line (M3 to M4) is written. Thereafter, monochrome image data can be stored in the main memory area (1000d) by sequentially performing the same processing.

<(2) Data storage by CIS2 channel>
FIG. 9A is a diagram illustrating a process of storing color image data of two channels separated into R, G, and B data as shown in FIG. 5C. The memory area in the main scanning direction is divided corresponding to the two channels.

  Image data read by the two-channel CIS 18 (chip 0, chip 1) is stored in the two buffers (11e, 11f) of the scanner I / F unit 10, and the two buffers (11e, 11f) are controlled by the LDMAC_A 105a. Is transferred to the channels (ch0, ch1) in 105a.

  The first LDMAC stores the data (chip0_data) of the channel (ch0) in the areas indicated as the first R area (1100a), the first G area (1200a), and the first B area (1300a) in FIG.

  In FIG. 9A, the first LDMAC writes R data (RA1 to RA2) among the R, G, and B data input from chip0 to the first R area (1100a) of the main memory, and in the next writing area. The write address is switched to the start address (GA1) of a certain first G area (1200a) (offset information C). The first LDMAC writes G data (GA1 to GA2) among R, G, and B data to the first G area (1200a) of the main memory, and the first address (BA1) of the first B area (1300a) that is the next writing area. ) To switch the write address (offset information C). Then, the first LDMAC writes B data (BA1 to BA2) among the R, G, and B data to the B area (1300a) of the main memory, and after the processing is completed, the address is set in the sub-scanning direction of the R area (1100a). To the first address (RA3) of the second line (offset information D). Thereafter, the G data and B data are similarly written by shifting the data write address to the second line in the sub-scanning direction.

  The first LDMAC has a data storage area for each of the areas indicated as the first R area (1100a), the first G area (1200a), and the first B area (1300a) in FIG. The memory address can be arbitrarily set based on the offset information (C, D), and the data stored in the channel (ch0) is stored in the main memory 100 according to the setting.

  The second LDMAC stores the data (chip1_data) of the channel (ch1) in the areas indicated as the second R area (1100b), the second G area (1200b), and the second B area (1300b) in FIG. 9A.

  In FIG. 9A, the second LDMAC writes R data (RB1 to RB2) among the R, G, and B data input from chip1 to the second R area (1100b) of the main memory, and in the next writing area. The write address is switched to the start address (GB1) of a certain second G area (1200b) (offset information E). The second LDMAC writes G data (GB1 to GB2) among the R, G, and B data to the second G area (1200b) of the main memory 100, and the first address of the second B area (1300b) that is the next writing area ( The write address is switched to BB1) (offset information E). Then, the second LDMAC writes the B data (BB1 to BB2) among the R, G, and B data to the second B area (1300b) of the main memory 100, and after the processing is completed, the address is stored in the second R area (1100b). Switch to the first address (RB3) of the second line in the sub-scanning direction (offset information F). Thereafter, the G data and B data are similarly written by shifting the data write address to the second line in the sub-scanning direction.

  In the DMA control in which the first and second LDMACs write data, the address of the memory serving as the data storage destination corresponding to the R data, G data, and B data is given as offset information (C, D, E, F), and each color data By switching the storage area for each line, the R, G, and B data in the line order can be separated from the R data, the G data, and the B data and stored in the main memory 100.

  The start address for starting DMA transfer (RA1, RB1 in the case of FIG. 8A), offset information (C, D, E, F), etc. are due to the generation of the above-mentioned LDMAC_A (105a).

  FIG. 9B is a diagram for explaining monochrome image data writing processing by CIS of two channels obtained at the lighting timing of the LEDs shown in FIG. 5B. In the case of monochrome image data, unlike the case of the color image data described above, it is not necessary to separate the data for each of R, G, and B. Therefore, the monochrome image data of line order is 1 in the main scanning direction of the main memory 100. Write the data for the lines (MA1 to MA2, MB1 to MB2), shift the write address in the sub-scanning direction of the same area (1400a, 1400b), and then the next second line (MA3 to MA4, MB3 to MB4) Write the data. Thereafter, monochrome image data can be stored in the main memory area (1400a, 1400b) by sequentially performing the same processing.

<(3) Storage of 3 channel data>
FIG. 10 shows the case where the output data control unit 11d in the scanner I / F unit 10 processes the image data read by the CCD 17 as data of three channels (R data, G data, B data). FIG. 5 is a diagram for describing processing in which first to third LDMACs write data to a main memory 100.

  Data stored in the three buffers (11e, 11f, and 11g in FIG. 2) is transferred to the channels (ch0, ch2, and ch3) in the 105a under the control of the LDMAC_A (105a). The data transferred to ch0 is written to the main memory 100 by the first LDMAC, the data transferred to ch1 is written to the main memory 100 by the second LDMAC, and the data transferred to ch2 is Data is written to the main memory 100 by the third LDMAC. The first to third LDMACs write R into the areas corresponding to the R area (1500a), G area (1500b), and B area (1500c) of the main memory 100, thereby separating the R, G, and B data into the main memory. 100 can be stored.

  In this case, the start address (SA1, SA2, SA3 in the case of FIG. 10) for starting the DMA transfer is generated by the generation of the above-described LDMAC_A (105a).

  As described above, the image data read by the image reading device (CCD 17, CIS 18) is distributed to channels for controlling DMA transfer according to the output format, and address information and offset for controlling DMA with respect to the distributed data. By generating information, it is possible to cope with various image reading devices.

  In the present embodiment, R, G, and B data are separated and stored in the main memory 100 regardless of the output format of the image reading device (CCD 17, CIS 18). For this reason, it is not necessary to perform DMA transfer according to the output format of the image reading device (CCD 17, CIS 18) to the later-described image processing unit, and it is only necessary to perform DMA transfer according to the required image processing. Therefore, it is possible to provide an image processing apparatus corresponding to the output format of the image reading device (CCD 17, CIS 18) with a very simple configuration / control.

<Main memory area setting and DMA transfer>
In order to DMA transfer image data to the main memory 100, the LDMAC_A (105a) generates address information for the main memory 100, and controls DMA transfer according to the address information. FIG. 11A is a diagram illustrating a state where the main memory 100 is divided into predetermined rectangular areas (blocks), and FIG. 11B is a diagram illustrating a case where the main memory 100 is used as a ring buffer. In order to perform image processing in units of rectangular areas on the image data stored in the main memory 100, address information for defining the rectangular areas is set according to the image processing mode (copy mode or scanner mode). The In FIG. 11A, SA indicates a DMA start address, and an area in the main scanning direction (X-axis direction) is divided by a predetermined byte length (XA, XB). A region in the sub-scanning direction (Y-axis direction) is divided by a predetermined number of lines (YA, YB). When used as a ring buffer (FIG. 11B), the areas 101a and 101b shown with hatching are the same memory area.

  The DMA for the rectangular area (0, 0) starts from the start address SA, and when data for XA is transferred in the main scanning direction, it is offset data (OFF1A) as a transfer address shifted by one line in the sub-scanning direction. The indicated address is set. Similarly, when transfer in the main scanning direction and address shift by offset data (OFF1A) are controlled and DMA for the rectangular area (0, 0) is completed, the DMA shifts to DMA for the next rectangular area (1, 0).

  The DMA for the rectangular area (1, 0) jumps to the address indicated by the offset address (OFF2A). Hereinafter, similarly to the rectangular area (0, 0), transfer in the main scanning direction and offset data (OFF1A). When the address shift by is controlled and DMA for the rectangular area (1, 0) is completed, the process proceeds to the next rectangular area (2, 0). Similarly, when the DMA for the YA line is completed up to the area (n, 0), the next DMA is jumped to the address indicated by the offset data (OFF3), and the process proceeds to the process for the rectangular area (0, 1). . Similarly, the DMA for the areas (1, 1), (2, 1). For example, when the size of the rectangular area differs depending on the memory capacity (when defined by XB and YB), offset data (OFF1B, OFF2B) corresponding to the area size is further set to control the DMA.

  The rectangular area described above includes a pixel in the main scanning direction as an overlapping area between the rectangular areas due to the resolution in the main scanning direction according to the set image processing mode and the pixel area to be referred to. The number of lines in the sub-scanning direction is set, and assignment (division) of image data developed on the memory is controlled.

<Specific example>
12A to 12C are diagrams illustrating capacity required for the main memory for each image processing mode, and are set as follows according to each processing mode.

(A) Color copy mode • Effective pixels: 600 dpi in the main scanning direction
Character determination processing: top and bottom 11 lines, left 12 pixels, right 13 pixels Color judgment filtering processing: top and bottom 2 lines, left 2 pixels, right 2 pixels Scaling processing: bottom n lines, right m pixels (m and n are (Depending on magnification)
(B) In black and white copy mode • Effective pixels: 600 dpi in the main scanning direction
-Color judgment filtering processing: upper and lower 2 lines, left and right 2 pixels-Scaling processing: lower 1 line (c) In color scan mode mode-Effective pixels: 1200 dpi in the main scanning direction
-Scaling processing: Bottom one line

  Further, the setting of the glue amount affects not only memory resources but also transfer efficiency between the main memory 100 and the scanner image processing unit 20. The transfer efficiency is defined as the area ratio of the effective pixel area to the image area including the margin area, and as described above, in the copy mode, since the margin area is indispensable, the transfer efficiency is low. In the scanner mode, the transfer efficiency is high because there is no margin for excluding scaling processing.

  For example, in the case of the color copy mode of FIG. 12A, if a rectangular area including a margin area is 281 pixels × 46 lines, an effective area obtained by subtracting the maximum margin area (character determination processing) is 256 pixels × 24 lines, and the transfer efficiency is (256 pixels × 24 lines) / (281 pixels × 46 lines) ≈48%. On the other hand, in the scanner mode of FIG. 12C, if the scaling process is not performed, there is no margin and the transfer efficiency is 100%.

  Since the contents of the image processing differ between the scanner mode and the copy mode, the necessary memory area is appropriately set according to the processing contents. For example, as shown in FIG. 12A, since character determination processing and color determination filtering processing are necessary in the color copy mode, a margin amount for extracting an effective pixel region (in the figure, secured around the effective pixel). However, since it is necessary to secure a resolution of about 600 dpi as the number of effective pixels in the main scanning direction, the margin area is determined by a trade-off with the memory area.

  On the other hand, in the scanner mode, it is not necessary to secure the amount of margin except for the scaling process, but it is necessary to secure about 1200 dpi as the number of effective pixels in the main scanning direction. Therefore, when the memory allocation amount is approximately the same in the scanner mode and the copy mode, if the number of lines in the sub-scanning direction is, for example, 24 lines, the main memory allocation amount in the color copy mode and the scanner mode can be reduced. It can be about the same. Hereinafter, the flow of storage processing for each image processing mode will be described with reference to FIGS.

<Storage processing in copy mode>
FIG. 13 is a diagram for explaining the flow of data storage processing in the copy mode. First, in step S10, it is determined whether or not the copy mode is color. If it is color (S10-YES), the process proceeds to step S20, and address information for DMA transfer in the color copy mode is as follows. Set as follows.

(A) In case of writing including a margin: A valid pixel (for example, resolution 600 dpi in the main scanning direction) is secured from the top of the buffer, and a margin (upper and lower 11 lines, left 12 pixels, right 13 pixels) is also provided in the periphery. Is set (see FIG. 12A).

(B) When writing only valid pixels • Start address (SA)
= Start address of memory (BUFTOP)
+ Number of pixels in the main scanning direction of a one-page image including the margin (TOTALWIDTH) × 11 (sub scanning margin (top)) +12 (main scanning direction margin (left))
(TOTALWIDTH = number of effective main scan pixels for one page image (IMAGEWIDTH)
+ Left margin pixel number + Right margin pixel number)
-UA = Memory end address (BUFFBOTTOM) + 1
= Ring buffer loopback address ・ OFF1A = TOTALWIDTH-IMAGEWIDTH

  On the other hand, in the monochrome copy mode (step S30), address information for DMA transfer is set as follows.

(A) In case of writing including a margin: An effective pixel (for example, a resolution of 600 dpi in the main scanning direction) is secured from the top of the buffer, and a margin (two upper and lower lines, two left and right pixels) is set around it ( (Refer FIG.12 (b)).

(B) When writing only valid pixels • Start address (SA)
= Start address of memory (BUFTOP)
+ Number of pixels in the main scanning direction of a one-page image including the margin (TOTALWIDTH) × 2 (sub scanning margin (upper)) +2 (main scanning direction margin (left))
-UA = Memory end address (BUFFBOTTOM) + 1
・ OFF1A = TOTALWIDTH-IMAGEWIDTH

  When address information for DMA transfer is set in step S20 and step S30, the process proceeds to step S40, and transfer starts. Data stored in each channel in the LDMAC_A 105a is sequentially read and DMA-transferred according to predetermined address information (S50, 60). When the reading of the data stored in the channels (ch0 to ch2) is completed (S70), the DMA transfer is completed (S80).

<Storage process in scanner mode>
FIG. 14 is a diagram for explaining the flow of data storage processing in the scanner mode. First, in step S100, address information for DMA transfer in the scanner mode is set as follows.

(A) When writing including the margin of margin The effective pixels (for example, resolution of 1200 dpi in the main scanning direction) are secured from the top of the buffer, and further, the margin of lower one line is set in the sub-scanning direction (FIG. 12C )).

(B) When writing only effective pixels • Start address (SA) = start address of memory (BUFTOP)
-UA = Memory end address (BUFFBOTTOM) + 1
= Ring buffer return address • OFF1A = 0 (TOTALWIDTH = IMAGEWIDTH)

  When the address information is set in step S100, the process proceeds to step S110 to start DMA transfer. Data stored in each channel in the LDMAC_A 105a is sequentially read and DMA-transferred according to predetermined address information (S120, 130). When the reading of the data stored in the channels (ch0 to ch2) is completed (S140), the DMA transfer is completed (S150).

  As described above, the image data is developed in the main memory 100 according to the set processing mode by the processing of FIGS. 13 and 14. 13 and 14 are parameters that can be arbitrarily set, and the gist of the present invention is not limited by these conditions. For example, in the case of color transmission of a photograph or the like, the character determination process may be removed, and the amount of glue may be arbitrarily set according to the number of reference pixels for image processing necessary to perform only the filter process.

<Reading data>
The image data developed in the main memory 100 is loaded into the scanner image processing unit 20 as corresponding R, G, B data or monochrome image data for each predetermined rectangular area, and image processing is executed for each rectangular area. Is done. In order to perform image processing for each rectangular area, the CPU 180 stores in the main memory 100 shading (SHD) correction data for correcting variations in sensitivity of the light receiving elements of the image reading device (CCD 17 / CIS 18), variations in the amount of light of the LEDs 19, and the like. The rectangular area shading data and the rectangular area image data are DMA-transferred to the scanner image processing unit 20 by LDMAC_B (105b) described later.

  FIGS. 15A and 15B are diagrams for explaining reading of data when image data in a rectangular area is transferred to the block buffer RAM 210 (FIG. 16) of the scanner image processing unit 20. For the area (0, 0), the margin area AB1CD1 is set for the effective pixel area (abcd) (FIG. 15A), and image data is read out with A as the start address. Data is read up to the B1 address in the main scanning direction. When the reading of data in the main scanning direction is completed, the address of the next data to be read is moved to the A2 address in the figure shifted by one line in the sub-scanning direction, and the data is read up to the pixel at the B3 address in the main scanning direction. . In the same manner, data is read out, and data in the main scanning direction from the C address corresponding to the last line in the margin area is read in the main scanning direction, and the reading of data in the area (0, 0) is completed. .

  For the area (0, 1), the margin area B2ED2F is set for the effective pixel area (bedf) (FIG. 15B), and image data is read out using B2 as the start address. Data is read up to the main scanning direction E address. When the reading of the data in the main scanning direction is completed, the address of the next data to be read is moved to the B4 address in the figure shifted by one line in the sub-scanning direction, and the data is read up to the pixel at the B5 address in the main scanning direction. Then, the image data in the main scanning direction from the D2 address to the F address corresponding to the last line in the margin area is read, and the reading of the data in the second area is completed. Through the above processing, the data of the rectangular area including the margin area is read out. Thereafter, the same processing is performed for each rectangular area.

<Configuration of LDMAC_B (105b)>
Reading of data stored in the main memory 100 is controlled by the LDMAC_B (105b) in FIG. The read data I / F unit 72a is connected to the main memory 100 via the fourth BUS 74 for reading data, and the read data I / F unit 72a refers to the address information generated by the LDMAC_B (105b), and Predetermined image data can be read from 100.

  The read data is set to a plurality of predetermined channels (ch3 to ch6) by the data setting unit 72b. For example, image data for shading correction is channel 3 (ch3), frame sequential R data is channel 4 (ch4), frame sequential G data is channel 5 (ch5), and frame sequential B data is channel 6 (ch6). Each data is set.

  The data set for each channel (ch3 to ch6) is sequentially DMA-transferred via the I / P interface 72c under the control of the LDMAC_B (105b), and the block buffer RAM 210 of the scanner image processing unit 20 (FIG. 16). To be loaded.

  Further, channel 7 (ch7) in LDMAC_B (105b) stores dot sequential image data output from the scanner image processing unit 20 in order to store data subjected to predetermined image processing in the main memory 100. It is a channel to do. The scanner image processing unit 20 outputs address information (block end signal, line end signal) in accordance with the output of dot sequential image data, and based on this address information, the second write data I / F 72d is The image data stored in the channel 7 is stored in the main memory 100. The contents of this process will be described later in detail.

<Image processing>
FIG. 16 is a block diagram illustrating a schematic configuration of the scanner image processing unit 20, and processing corresponding to each image processing mode is executed on the data loaded in the block buffer RAM 210. FIGS. 19A to 19D are diagrams schematically showing the size of the rectangular area required for each image processing. The scanner image processing unit 20 executes processing by switching a rectangular pixel region to be referenced with respect to the rectangular region in accordance with the set image processing mode. Hereinafter, the contents of the image processing will be described with reference to FIG. 16, and the size of the rectangular area referred to during the processing will be described with reference to FIGS. 19 (a) to 19 (d).

  In FIG. 16, a shading correction block (SHD) 22 is a processing block for correcting variations in the light amount distribution of the light source (LED 19) in the main scanning direction, variations in light receiving elements of the image reading device, and dark output offset. The shading data stores correction data for one pixel in the order of bright R, bright G, bright B, dark R, dark G, and dark B on the main memory 100, and the number of pixels corresponding to the rectangular area ( XA pixels in the main scanning direction and YA pixels (see FIG. 19A) in the sub-scanning direction are input. The input frame sequential correction data is converted into dot sequential data by the input data processing unit 21 and stored in the block buffer RAM 210 of the scanner image processing unit 20. Then, when the shading data capturing of the rectangular area is completed, the process proceeds to image data transfer.

  The input data processing unit 21 is a processing unit that executes processing for reconstructing frame sequential data separated into R, G, and B into dot sequential data. One-pixel data is stored in the main memory 100 as frame-sequential data for each color of R, G, and B, and when these data are loaded into the block buffer RAM 210, the input data processing unit 21 One pixel data is taken out every time and reconstructed as R, G, B data of one pixel. Reconstruction processing is performed for each pixel, and frame sequential image data is converted to dot sequential data.

  FIG. 17 is a diagram schematically showing a target region for image processing and a reference region (ABCD) for performing filter processing for executing the processing, in which an effective pixel region (abcd) is illustrated. Thus, “Na” and “Nb” pixels are set as the margin amounts in the main scanning direction (X direction), and “Nc” and “Nd” pixels are set as the margin amounts in the sub scanning direction (Y direction). Has been.

  FIG. 18 is a diagram exemplifying a margin for each image processing mode (color copy mode, monochrome copy mode, scanner mode). Since scaling processing is required at the time of scaling, only m pixels and n lines are scaled. The reference area becomes larger than the time. In the color copy mode, the largest reference area is required in the image processing mode in order to determine black characters. In order to detect black characters, it is necessary to ensure the determination of halftone dots and black characters. Therefore, in order to determine the period of halftone dots, main scanning direction (24 + m) pixels, sub-scanning direction (21 + n) pixels (variable) Is the reference area. In the monochrome copy mode, the main scanning direction (4 + m) pixels and the sub-scanning direction (4 + n) pixels (during zooming) are used as reference areas in order to perform edge enhancement on the character portion. In the scanner mode, since a necessary image processing is performed by a scanner driver or application on the host computer, a reference area is not required at the same magnification, but at the time of magnification, m pixels and sub-pixels are arranged in the main scanning direction according to the magnification. Reference regions for n pixels are set in the scanning direction. Needless to say, the gist of the present invention is not limited to the amount of glue shown here, and can be arbitrarily set.

  In the processing block 23, the averaging processing unit (SUBS) is a processing block for performing sub-sampling (simple decimation) or averaging processing for reducing the reading resolution in the main scanning direction, and the input masking processing unit (INPMSK). This is a processing block for calculating color correction of inputted R, G, B data. The γ correction processing unit (LUT) is a processing block that gives predetermined gradation characteristics to input data.

  The character determination processing block 24 is a processing block for performing black character determination and line drawing outline pixel determination on input image data. In the black character discrimination process, as described above, it is necessary to refer to an area wider than the halftone dot period, so that the main scanning direction (24 + m) pixels and the sub scanning direction (21 + n) pixels (lines) (“m”, “n” "" Depends on the magnification of the scaling process.) It is desirable to refer to a corresponding margin area. Similar to the input of the shading correction block (SHD) 21, the input data of the character determination processing block 24 is data of main scanning direction XA pixels (effective pixels + replacement) × sub-scanning direction YA pixels (effective pixels + replacement) ( Reference is made to FIG.

  In the processing block 25, the MTF correction processing unit is a processing unit that performs filter processing in the main scanning direction for MTF difference correction and moire reduction at the time of reduction / magnification when the image reading device is changed. On the other hand, this is a block for multiplying and adding each coefficient for a predetermined pixel in the main scanning direction. In FIG. 19B, 2 pixels on the left hatched part (b1) and 3 pixels on the right hatched part (b2) are secured for the attention area G1, and the process for the area G1 is executed.

  The (RGB → (L, Ca, Cb)) conversion processing unit (CTRN) performs multiple values of R, G, and B colors in the filtering (lightness enhancement, saturation enhancement, color determination) performed in the subsequent filter processing block 26. Image data conversion processing is performed.

  The background density adjustment processing unit (ABC) automatically recognizes the background density of the document and corrects the background density value to the white side to execute binarized data suitable for facsimile communication or the like.

  The filter processing block 26 performs edge determination and saturation (Ca, Cb) of the lightness component (L) of the image as processing for performing color determination and filtering on the obtained data in the previous CTRN processing. Perform emphasis processing. Further, the coloring of the input image is determined and the result is output. Further, the emphasis amount parameter can be changed based on the character generated in the character determination processing block 24, the determination signal of the line drawing outline portion, and the like. The filtered data is converted from L, Ca, Cb to R, G, B data and output. This processing block functions as an edge enhancement filter of 5 pixels × 5 pixels when processing monochrome image data.

  In FIG. 19C, the above-described filtering process is performed on the attention area G2 with reference to the upper and lower two pixel (line) and left and right two pixel areas (hatched areas).

  The scaling process (LIP) block 27 is a processing block that performs linear interpolation scaling processing in the main scanning and sub-scanning directions. In FIG. 19D, the region G3 is a region obtained as a result of the linear interpolation scaling process, and from the image data (d: (X− (Na + Nb) pixel) × (Y− (Nc + Nd) pixel)), The hatched area is scaled in the main scanning direction and the sub-scanning direction according to a predetermined scaling factor (main scanning direction (+ m pixels), sub-scanning direction (+ n line)), and the area of the region G3 is determined. The

  In FIGS. 19B to 19D, “Na” and “Nb” in the figure indicate the number of pixels set as the amount of margin in the main scanning direction (X direction) as in FIG. ”And“ Nd ”indicate the number of pixels set as the amount of margin in the sub-scanning direction (Y direction).

  The image processing described above is performed on the image data in units of rectangular areas according to the set image processing mode (copy mode, scanner mode). By setting a rectangular area corresponding to the image processing mode on the memory and switching the unit of the rectangular area, it becomes possible to realize resolution and high-definition processing corresponding to each image processing mode. In addition, each rectangular area includes a margin required for image processing of each processing block. Therefore, in order to process the edge of the rectangular image data to be processed, the image data in the adjacent area is processed in rectangular units. There is no need to read out data, and a further reduction in work memory can be achieved as compared with a method in which an image is simply divided into rectangles and processed.

  FIG. 20 is a diagram for explaining the starting point in the DMA main scanning direction for DMA transfer of image data of the next rectangular data after the processing of one rectangular data is completed. When the DMA of the first rectangular area ABCD is completed and the transfer to the pixel of point D is completed, the starting point in the main scanning direction is a position (point S1 in the figure) that is returned by Na + Nb pixels in the main scanning direction. Thereafter, when the DMA of the rectangular data for one column is sequentially completed and the DMA at the point E corresponding to the final rectangular data of the first column is transferred, the sub-scan is performed to transfer the rectangular data of the next column. The starting point for shifting in the direction is the position returned by Nc + Nd pixels (S2 in the figure).

  FIG. 21 and FIG. 22 are flowcharts for explaining the DMA transfer processing for each image processing mode and the flow of image processing. The address information described with reference to FIGS. 21 and 22 uses specific numerical values as an example, but is not limited to these numerical values, and can be arbitrarily set.

<Processing in copy mode>
FIG. 21 is a flowchart for explaining the flow of data reading and image processing in the copy mode. First, in step S200, it is determined whether the mode is the color mode or the monochrome mode. If it is the color mode (S200-YES), the process proceeds to step S210, and if it is the monochrome mode (S200-NO), the process proceeds to step S220.

  In step S210, address information for reading in the color copy mode is set as follows. This address information is generated by LDMAC_B (105b) (the same applies to step S220), and based on this address information, LDMAC_B (105b) controls the DMA.

-Start address (SA) = Memory start address (BUFTOP)
-UA = Memory end address (BUFFBOTTOM) + 1
XA = rectangular effective main scanning pixel
+ Glue margin (Left margin pixel number (12 pixels), Right margin pixel number (13 pixels))
YA = rectangular effective sub-scanning pixel (line)
+ Margin (the number of upper margin pixels (11 pixels (line)), the number of lower margin pixels (11 pixels (line)))
・ OFF1A = TOTALWIDTH-XA
・ OFF2A =-(TOTALWIDTH x YA + margin (12 pixels on the left, 13 pixels on the right))
・ OFF3A =-(TOTALWIDTH × (paste (top 11 pixels, bottom 11 pixels)
+ Effective main scanning pixel + margin (left 12 pixels, right 13 pixels))
(TOTALWIDTH = number of effective main scan pixels for one page image (IMAGEWIDTH)
+ Left margin pixel number + Right margin pixel number)
XANUM = effective main scanning pixel / rectangular effective main scanning pixel

  In step S220, address information for reading in the monochrome copy mode is set as follows.

-Start address (SA) = Memory start address (BUFTOP)
-Memory end address (BUFFBOTTOM) + 1
XA = rectangular effective main scanning pixel + paste margin (number of left margin pixels (2 pixels), number of right margin pixels (2 pixels))
YA = rectangular effective sub-scanning pixel (line) + margin (upper margin pixel number (2 pixels (line)), lower margin pixel number (2 pixels (line)))
・ OFF1A = TOTALWIDTH-XA
・ OFF2A =-(TOTALWIDTH x YA + margin (2 pixels left, 2 pixels right))
・ OFF3A =-(TOTALWIDTH × (paste (top 2 pixels, bottom 2 pixels)
+ Effective main scanning pixel + margin (left 12 pixels, right 13 pixels))
(TOTALWIDTH = number of effective main scan pixels for one page image (IMAGEWIDTH)
+ Left margin pixel number + Right margin pixel number)
XANUM = effective main scanning pixel / rectangular effective main scanning pixel

  When the address information is set in the read data I / F unit 72a in steps S210 and S220, the process proceeds to step S230, and it is determined whether the LDMAC_B (105b) is in a state where data can be read. For example, if the buffer controller 75 is in a state in which buffer reading is prohibited, the process waits until the state is canceled (S230-NO). If buffer reading is possible (S230-YES), the process proceeds to step S240. Proceed to

  In step S240, the read data I / F unit 72a reads the data according to the set address information, and the data setting unit 72b sets the data for a predetermined channel (ch3 to ch6). Then, the LDMAC_B (105b) DMA-transfers the data set for each channel to the buffer RAM 210 of the scanner image processing unit 20. Here, the DMA transferred data is loaded into the buffer of the scanner image processing unit 20, and image processing corresponding to each image processing mode is executed. Since the contents of the individual image processing have been described above, detailed description thereof is omitted here.

  The loaded shading correction data and image data are converted from frame sequential data to dot sequential data by the above-described input data processing unit 21, and the following image processing is performed.

  In step S250, it is determined whether the copy mode is the color copy mode or the monochrome copy mode. If the copy mode is the color copy mode (S250-YES), the process proceeds to step S260 to execute the character determination process. In the monochrome copy mode (S250-NO), step S260 (character determination process) is skipped, the filter process of step S270 is executed, and the scaling process is executed in step S280.

  The above processing is executed for each piece of rectangular area data, and the dot sequential image data that has undergone image processing in step S290 is further DMA-transferred and stored in a predetermined memory area that stores the image processed data. This storage process will be described in detail later.

  In step S300, it is determined whether the image processing of the rectangular area and the data storage processing have been completed. If the processing has not been completed, the processing returns to step S250 again, and the same processing is executed. When the processing of the rectangular area is completed (S300-YES), the process proceeds to step S310, and it is determined whether the processing of the rectangular area constituting the entire page is completed (S310). If the processing for the entire page has not been completed (S310-NO), the process returns to step S230, the subsequent image data is read from the main memory 100, and the image processing (steps after S230) is performed on that data.

  On the other hand, if the page processing is completed (S310-YES), the process proceeds to step S320, and the DMA transfer (S320) to the scanner image processing unit 20 and the data writing process to the buffer of the scanner image processing unit 20 are ended. (S330), the image processing in the scanner image processing unit 20 is ended (S340).

  With the above processing, the image processing for the data read in the copy mode is completed.

<Processing in scanner mode>
FIG. 22 is a flowchart for explaining the flow of data reading and image processing in the scanner mode. First, in step S400, address information for reading data from the main memory 100 is set as follows. The address information is generated by the LDMAC_B (105b), and the LDMAC_B (105b) controls the DMA based on the address information.

-Start address (SA) = Memory start address (BUFTOP)
-UA = Memory end address (BUFFBOTTOM) + 1
XA = rectangular effective main scanning pixel YA = rectangular effective sub-scanning pixel (line)
+ Glue margin (number of pixels in the bottom glue (1 pixel (line))
・ OFF1A = TOTALWIDTH-XA
・ OFF2A =-(TOTALWIDTH × YA)
・ OFF3A =-(TOTALWIDTH x (paste margin (number of subplot margin pixels (1 pixel))
+ Effective main scanning pixel)
(TOTALWIDTH = number of effective main scan pixels for one page image (IMAGEWIDTH)
+ Left margin pixel number + Right margin pixel number)
XANUM = effective main scanning pixel / rectangular effective main scanning pixel

  When the address information is set in the read data I / F unit 72a in step S400, the process proceeds to step S410, and it is determined whether the LDMAC_B (105b) is in a state where data can be read. For example, if the buffer controller 75 is in a state where reading of data is prohibited, the process waits until the state is canceled (S230-NO). If buffer reading is possible (S230-YES), the process is stepped. Proceed to S420.

  In step S420, the read data I / F unit 72a reads the data according to the set address information, and the data setting unit 72b sets the data for a predetermined channel (ch3 to ch6). Then, the LDMAC_B (105b) DMA-transfers the data set for each channel to the buffer of the scanner image processing unit 20. Here, the DMA transferred data is loaded into the buffer of the scanner image processing unit, and image processing corresponding to each image processing mode is executed. Since the details of the image processing have been described above, detailed description thereof will be omitted.

  The loaded image data is converted from frame-sequential data to dot-sequential data by the input data processing unit 21 described above, and scaling processing is executed in step S430.

  In step S440, the image-processed dot-sequential image data is further DMA-transferred and stored in a predetermined memory area for storing the image-processed data. This storage process will be described in detail later.

  In step S450, it is determined whether or not the image processing of the rectangular area and the data storage processing have been completed. If the processing has not been completed, the processing returns to step S430 and the same processing is executed. When the processing of the rectangular area is completed (S450-YES), the process proceeds to step S460, and it is determined whether the processing of the entire page is completed (S460). If the processing for the entire page has not been completed (S460-NO), the processing returns to step S410, the subsequent image data is read from the main memory 100, and the image processing is executed on that data.

  On the other hand, when the page processing is completed (S460-YES), the process proceeds to step S470, and the DMA transfer (S470) to the scanner image processing unit 20 and the data writing process to the buffer of the scanner image processing unit 20 are terminated. (S480), the image processing in the scanner image processing unit 20 is terminated (S490).

  With the above processing, the image processing for the image data read in the scanner mode is completed.

  According to the image processing mode, a rectangular area including a predetermined amount of margin is set, and image processing is performed in units of the rectangular area, thereby performing predetermined image processing without intervening individual line buffers of each image processing unit. It becomes possible to execute.

<Storage of image processed data>
FIG. 23 is a diagram for explaining processing for transferring the scaling-processed rectangular data from the scaling processing block (LIP) 27 to the main memory 100. For example, when the rectangular data of 256 pixels × 256 pixels is reduced to 70%, 256 pixels × 0.7 = 179.2 pixels, and it is necessary to create rectangular data of 179.2 pixels × 179.2 pixels in numerical calculation. is there. However, since pixel data reflecting numerical values below the decimal point cannot be generated, the overall probability is reduced by controlling the appearance probability of 180 pixels and 179 pixels to 2: 8 in the main scanning direction and the sub-scanning direction. 179.2 pixels corresponding to a magnification of 70% are generated. In FIG. 23, the size of the rectangular area is different from the area B11 (XA1 = 180 pixels) and B12 (XA2 = 179 pixels) in the main scanning direction, and B11 (YA1 = 180 pixels) and B21 (YA2 = 179 pixels). And the sizes of the rectangular areas are different in the sub-scanning direction. Appearance probabilities of rectangular areas having different sizes are controlled according to the result of the scaling process, and predetermined scaled image data can be obtained. Then, in order to return the image-processed data to the main memory 100, a signal for controlling the DMA is notified from the scaling processing block (LIP) 27 to the LDMAC_B (105b) (FIG. 24).

  Next, processing in step S290 in FIG. 21 and step S440 in FIG. 22 will be described. FIG. 25 is a timing chart showing the relationship between data and signals sent from the scaling processing block (LIP) 27 to the LDMAC_B (105b) in order to DMA transfer image-processed data to the main memory 100.

  When the image processed data is stored in the main memory 100, the LDMAC_B (105b) starts DMA transfer with the rectangular main scanning length and sub-scanning length unknown. When the final data (XA1, XA2) of the main scanning width in one rectangle is transferred from the scaling processing block 27, a line end signal is output, and the main scanning length of the rectangle is changed by the line end signal. To LDMAC_B (105b).

  A block end signal is output to the LDMAC_B (105b) at the time of final data transfer within one rectangle from the scaling processing block 27, and thereby the sub-scanning length can be recognized. When all the data in the sub-scanning direction YA1 is processed, the DMA transfer is shifted to the areas B21 and B22 (see FIG. 23), and similarly the data XA in the main scanning direction is sent out. The DMA is controlled by a line end signal and a block end signal. Thereby, the rectangular area of the DMA can be dynamically switched according to the calculation result of the scaling processing block 27.

  The above-described line end signal, block end signal, and dot sequential image data are input to the interface unit 72c of the LDMAC_B (105b), and among these, the image data is stored in the channel (ch) 7. The line end signal and the block end signal are used as address information when the data stored in the channel (ch) 7 is expanded on the main memory 100, and the second write data I / F unit 72d receives these addresses. Based on the information, the data of ch7 is read and stored in the main memory 100.

  FIG. 26 is a diagram for explaining a state in which data is expanded in the main memory 100 in accordance with the line end signal and the block end signal. In the figure, SA indicates a DMA transfer start address, and dot sequential RGB data is stored from this address in the main scanning direction. Based on the line end signal, the DMA transfer address is switched by offset information (OFF1A), and data is similarly stored in the main scanning direction from the address shifted by one pixel (line) in the sub-scanning direction. Then, based on the block end signal of the rectangular area (0, 0), the process proceeds to data storage for the next rectangular area (1, 0). The DMA transfer address is switched by the offset information (OFF2A). In this case, OFF2A is switched as an address shifted by one pixel in the main scanning direction with respect to the region (0, 0) and jumped to the first line in the sub-scanning direction.

  Hereinafter, similarly, the area (2, 0),... (N−1), (n, 0) and data are stored, and when storage of n blocks is completed, the offset information (OFF3). To switch the DMA transfer address. In this case, OFF3 is switched as an address that is shifted by one pixel (line) in the sub-scanning direction with respect to the pixel in the last line of the region (0, 0) and jumped to the first pixel in the main scanning direction.

  As described above, the image-processed data is DMA-transferred to a predetermined area of the main memory 100 by dynamically switching the offset information (OFF1A, OFF2A, OFF3) by the line end signal and the block end signal. Can be stored.

<Other embodiments>
In the above embodiment, the present invention has been described with a composite image processing apparatus having various image input / output functions. However, the present invention is not limited to this, and a single-function scanner device, printer device, or other The present invention can also be applied to an option card for expansion connection to the apparatus. Further, the unit configuration of the apparatus related to the present invention is not limited, and for example, the apparatus or system related to the present invention may be configured to be achieved by a plurality of apparatuses connected via a network. .

  An object of the present invention is to read and execute a program code stored in a storage medium by a computer (or CPU or MPU) of a system or apparatus that stores a program code of software that realizes the functions of the above-described embodiments. Is also achieved. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  As a storage medium for supplying the program code, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, nonvolatile memory card, ROM, or the like is used. be able to.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code. A case where part or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing is also included.

  Further, after the program code read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion board is based on the instruction of the program code. Also included is a case where the CPU or the like provided in the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

1 is a block diagram showing a schematic configuration of an image processing apparatus 200 according to an embodiment of the present invention. 2 is a block diagram showing a schematic configuration of a scanner I / F unit 10. FIG. It is a figure which illustrates the output signal by CCD17. It is a timing chart regarding the lighting control of LED19 with respect to CIS18. 5 is a timing chart showing the relationship between LED lighting corresponding to R, G, and B, ((a) to (d)), and output (e) according to the timing chart of FIG. 4. It is a figure which shows the timing in case each LED19 of R, G, B lights up sequentially within 1 period of a synchronizing signal (SP) in connection with control of CIS18. It is a figure which illustrates the output in case CIS18 is provided with 2 channels in the main scanning direction. It is a block diagram explaining the process of AFE15. It is a figure which shows schematic structure of LDMAC_A for DMA-transferring the image data read with the image reading device to main memory, and LDMAC_B which controls DMA between a main memory and a scanner image process part. FIG. 10 is a diagram for describing processing in which the LDMAC_A 105a writes data for one channel to the main memory 100. FIG. 10 is a diagram for describing processing in which the LDMAC_A 105a writes data for two channels to the main memory 100. FIG. 10 is a diagram for describing processing in which the LDMAC_A 105a writes data for three channels to the main memory 100. It is a figure which shows the state which divided | segmented the main memory 100 into the predetermined | prescribed rectangular area | region (block). It is a figure which illustrates the capacity | capacitance required for a main memory according to image processing mode. It is a figure explaining the flow of the storage process of the data at the time of copy mode. It is a figure explaining the flow of the storage process of the data at the time of scanner mode. FIG. 5 is a diagram for explaining reading of data when image data in a rectangular area is transferred to the block buffer RAM of the scanner image processing unit 20. FIG. 2 is a block diagram illustrating a schematic configuration of a scanner image processing unit 20. It is a figure which shows roughly the reference area | region for performing the filter process etc. for performing the object process of image processing, and the process. It is a figure which illustrates the transfer margin according to image processing mode (color copy mode, monochrome copy mode, scanner mode). It is a figure which shows typically the size of the rectangular area which each image processing requires. It is a figure explaining the starting point of the DMA main scanning direction for the DMA transfer of the image data of the following rectangular data after the process of one rectangular data is complete | finished. It is a figure explaining the reading of the data at the time of copy mode, and the flow of image processing. It is a figure explaining the reading of the data in a scanner mode, and the flow of image processing. FIG. 5 is a diagram for describing processing for transferring rectangular data subjected to scaling processing from a scaling processing block (LIP) 27 to a main memory 100. It is a figure which shows the connection of scaling process block (LIP) 27 and LDMAC_B (105b). 7 is a timing chart showing the relationship between data and signals sent from the scaling processing block (LIP) 27 to the LDMAC_B (105b) in order to DMA transfer image-processed data to the main memory 100. It is a figure explaining the state which expand | deployed the data to the main memory 100 according to the line end signal and the block end signal. It is a block diagram which shows the structure of the scanner image processing circuit in the conventional image processing apparatus.

Claims (9)

Multiple corresponding first image reading device for outputting a main scanning direction on the serial line by line to 1 line by using a plurality of colors single data channel image data of the image data of the multiple number of colors in the color number The second image reading device that outputs the data in parallel in line units with the main scanning direction as one line using a plurality of data channels, or the image data of a plurality of colors using a plurality of data channels, the one line corresponding to the number of channels Interface means connected to one of the third image reading devices that output serially in divided units ;
Generating address information for DMA transfer of the image data of the plurality of colors input via the interface means to the memory, DMA transfer of the image data of the plurality of colors to the memory based on the address information, DMA transfer means having a plurality of DMA transfer units corresponding to a plurality of data channels,
When the first image reading device is connected to the interface means and the image data of the plurality of colors is serially input to any one of the plurality of DMA transfer units in units of lines , The DMA transfer unit generates the address information so that the image data of the plurality of colors is stored in different areas for each color,
When the second image reading device is connected to the interface means, and the image data of the plurality of colors is input to each of the plurality of DMA transfer units in parallel in units of lines for each color, the plurality of DMA transfers Each of the units generates the address information so that the image data of the plurality of colors is stored in a different area for each color ,
When the third image reading device is connected to the interface means, and the image data of the plurality of colors is serially input to each of the plurality of DMA transfer units in units obtained by dividing the one line according to the number of channels. Each of the plurality of DMA transfer units generates the address information so that the image data of the plurality of colors is stored in different areas for each color and the image data can be read from the memory in units of lines. An image processing apparatus.   A second transfer unit configured to generate read address information for reading out the image data of a plurality of colors stored in the memory for each color and to read the image data of the plurality of colors for each color based on the read address information; The image processing apparatus according to claim 1.   3. The image processing apparatus according to claim 2, wherein the second transfer unit reads image data of a plurality of colors stored in the memory in units of rectangular areas divided in a main scanning direction and a sub-scanning direction. . Image processing means for executing image processing on the image data of the rectangular area unit;
The image processing apparatus according to claim 3, wherein the second transfer unit transfers the image data in units of the rectangular area from the memory to the image processing unit.   5. The image according to claim 4, wherein the second transfer unit transfers, from the image processing unit, the image data of the rectangular area unit, on which the image processing has been performed by the image processing unit, to the memory. Processing equipment. The first image reading device can output monochromatic image data serially using a single data channel;
2. The DMA transfer unit generates the address information according to whether the first image reading device outputs a plurality of colors of image data or a single color of image data. 6. The image processing apparatus according to any one of 5 above. The first image reading device, an image processing apparatus according to any one of claims 1 to 6, characterized in that a CIS. The second image reading device, an image processing apparatus according to any one of claims 1 to 6, characterized in that a CCD. The first image reading device and the second image reading device, an image data according to a plurality of colors, to any one of claims 1 to 8, characterized in that the output for each line constituting the image data The image processing apparatus described.

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