JP3869760B2 - Matched filter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a matched filter used in synchronization establishment processing of a spread spectrum communication system.
[0002]
[Prior art]
In recent years, spread spectrum communication, particularly CDMA (Code Division Multiple Access), which has high frequency utilization efficiency and enables high-speed and high-quality data communication, has become mainstream in mobile communication systems. A feature required for a mobile communication terminal device of a mobile communication system is small size and light weight, and one of the achievements is a reduction in circuit scale. Even in a base station apparatus of a mobile communication system, in order to increase the number of users that can be handled, a large number of large-scale receiving circuits are built in, and it is therefore a problem to reduce the circuit scale of the apparatus.
[0003]
An effective item for reducing the size of both the mobile communication terminal device and the base station device is to reduce the size of the matched filter used in the synchronization unit. The matched filter is used in the receiving unit and outputs data (delay profile) indicating how much the received data received from the user is delayed from the reference timing of the apparatus. The apparatus performs RAKE reception based on the delay profile data output from the matched filter.
[0004]
In general, a transmission baseband signal processing unit of a CDMA mobile communication system performs processing with a minimum unit of chip rate data obtained by spreading data to be transmitted with a spreading code. On the other hand, in the matched filter used in the reception baseband processing unit, the A / D (Analog / Digital) converter provided in the previous stage is doubled in order to double the timing accuracy of the delay profile in one chip section. Sampled data is generated and input to a matched filter for computation.
[0005]
In the conventional matched filter, in order to make the accuracy of oversampling variable as a system, a matched filter for calculating a correlation result from received data that has been oversampled by 1 time is provided in parallel for the corresponding number of oversamples. The correlation output is selected and output by the selection circuit.
[0006]
FIG. 10 is a block diagram showing a configuration of a conventional matched filter.
The matched filter 1001 shown in this figure corresponds to oversampling of 1 ×, 2 ×, and 4 ×. When the calculation accuracy (= number of oversamples) of the matched filter required by a device (for example, a CDMA receiver) is required up to four times the chip rate, the configuration corresponds to four times oversampling.
[0007]
The matched filter 1001 selects the contents to be output by the matched filter 1001 from the correlation calculation results of the correlation calculation units 1002, 1003, 1004, and 1005 and the correlation calculation units 1002, 1003, 1004, and 1005 corresponding to the sampling phases, respectively. The selection unit 1006 and the memory unit 1020 are provided. The correlation calculation units 1002, 1003, 1004, and 1005 include clock generation units 1007, 1008, 1009, and 1010. Clock generators 1007, 1008, 1009, and 1010 output clocks Ca, Cb, Cc, and Cd at timings corresponding to four types of phases A to D of received input data Di.
[0008]
[4 times oversampling operation]
FIG. 11 is a timing chart when the matched filter 1001 performs a 4-times oversampling operation.
[0009]
In this figure, received input data Di is data that has been oversampled four times from phase A to phase D in one chip interval. The A-system correlation signal is output from the symbol integration unit 1011 of the correlation calculation unit 1002. The B-system correlation signal is output from the symbol integration unit 1014 of the correlation calculation unit 1003.
[0010]
Further, the C-system correlation signal is output from the symbol integration unit 1012 of the correlation calculation unit 1004. The D-system correlation signal is output from the symbol integration unit 1013 of the correlation calculation unit 1005. The correlation calculation unit 1002 operates with the A-system clock Ca, and the correlation calculation unit 1003 operates with the B-system clock Cb. Further, the correlation calculation unit 1004 operates with the C-system clock Cc, and the correlation calculation unit 1005 operates with the D-system clock Cd. The selection signal SS is output from the selection signal generator 1015. From the selection unit 1006, a correlation output result of 4 times oversample is obtained. In this case, the correlation output result is accumulated in the memory unit 1020 to obtain the correlation output So.
[0011]
[Double oversampling operation]
FIG. 12 is a timing chart when the matched filter 1001 performs a double oversampling operation.
[0012]
In this figure, received input data Di is data that has been oversampled four times from phase A to D in one chip interval. In this case, the received input data Di may be data oversampled twice. Clocks are output from the clock generators 1007 and 1009 at timings corresponding to the two types of phases A and C of the received input data Di.
[0013]
The B-system clock Cb corresponding to the other two types of phase B and the D-system clock Cd corresponding to the phase D are fixed at the low level in order to reduce power consumption because the correlation calculation units 1003 and 1005 are not used. The The correlation calculation unit 1002 operates with the A-system clock Ca, and the correlation calculation unit 1004 operates with the C-system clock Cc. The A-system correlation signal is output from the symbol integration unit 1011 of the correlation calculation unit 1002, and the C-system correlation signal is output from the symbol integration unit 1012 of the correlation calculation unit 1004. The selection signal generator 1015 outputs a selection signal SS, and the selection unit 1006 obtains a 2-fold oversampled correlation output result. In this case, the correlation output result is accumulated in the memory unit 1020 to obtain the correlation output So.
[0014]
[1x oversample operation]
FIG. 13 is a timing chart when the matched filter 1001 performs a one-time oversampling operation.
[0015]
In this figure, received input data Di is data that has been oversampled four times from phase A to phase D in one chip interval. In this case, the received input data Di may be data that has been oversampled by a factor of 1. A clock is output from the clock generation unit 1007 at a timing corresponding to one type of phase A of the received input data Di. For the B-system clock Cb, C-system clock Cc, and D-system clock Cd corresponding to the other three types of phases B, C, and D, the correlation calculation units 1003, 1004, and 1005 are not used, so that power consumption can be reduced. It is fixed at the Low level.
[0016]
The correlation calculation unit 1002 operates with the A-system clock Ca, and an A-system correlation signal is output from the symbol integration circuit 1011 of the correlation calculation unit 1002. The selection signal SS is output from the selection signal generation unit 1015, and a correlation output result of 1-time oversample is obtained from the selection unit 1006. In this case, the correlation output result is accumulated in the memory unit 1020 to obtain the correlation output So.
[0017]
[Problems to be solved by the invention]
However, in the conventional matched filter, when the number of oversamples is made variable, it is necessary to provide four matched filters of 1 × oversample. For this reason, the size of the matched filter becomes large, and it is difficult to reduce the size and weight of an applied device (for example, a CDMA receiving device), and it is difficult to reduce the cost.
[0018]
In other words, when adopting a configuration in which the number of oversamples from 1 × oversample to 4 × oversample is variable, 4 matched filters with 1 oversample configuration with 1 symbol length taps are provided for each output. It is necessary to adopt a configuration for switching and outputting at a predetermined timing.
[0019]
However, it is not necessary to operate two matched filters when a correlated output of 2 times oversampling is required, and operates 3 matched filters when a correlated output of 1 times oversample is required. There is no need to let them. That is, when the conventional matched filter configuration supports a variable number of oversamples, a redundant circuit configuration exists depending on the operation. Therefore, the scale of the matched filter becomes large, which also affects the increase in the scale of the applied device.
[0020]
SUMMARY An advantage of some aspects of the invention is that it provides a matched filter capable of simplifying a circuit configuration while changing the number of oversamples.
[0021]
[Means for Solving the Problems]
The matched filter according to the first aspect of the present invention includes a plurality of sets of shift registers each including four data registers, and shifts and holds input data oversampled four times by one symbol length. A data shift means for outputting the output of the data register located at the last stage of the shift register for despreading operation; a clock signal supply means for supplying a clock signal synchronized with a 4-times oversampling phase to the data shift means; A data shift switching means for performing data update and holding control in the data shift means for each oversampling of double, double, and quadruple and switching the data shift path is adopted.
[0022]
According to this configuration, since the data shift register for 4 times oversampling is provided and the data shift path for performing different shift operations for each of 1, 2, 4 times oversampling is switched, the code register, despreading operation unit The circuit configuration of the symbol integration unit is only required for 1-time oversampling, and it becomes unnecessary to provide four matched filters with a 1-oversampling configuration as in the prior art, so that the circuit scale can be reduced. Accordingly, the size and weight can be reduced, and the cost can be reduced by the reduction in size and weight.
[0023]
The matched filter according to a second aspect of the present invention includes a plurality of sets of shift registers each including four data registers, and shifts and holds input data oversampled four times by one symbol length. Data shift means for outputting the output of the data register located at the last stage of the shift register for despreading operation, and data for switching the data shift path in the data shift means for every 1 ×, 2 ×, 4 × oversample numbers A shift switching means and a clock control means for supplying the data shift means with a clock signal synchronized with an oversampling phase corresponding to each oversample of 1 ×, 2 ×, and 4 × are adopted. .
[0024]
According to this configuration, since the data shift register for 4 times oversampling is provided and the data shift path for performing different shift operations for each of 1, 2, 4 times oversampling is switched, the code register, despreading operation unit The circuit configuration of the symbol integration unit is only required for 1-time oversampling, and it becomes unnecessary to provide four matched filters with a 1-oversampling configuration as in the prior art, so that the circuit scale can be reduced. Accordingly, the size and weight can be reduced, and the cost can be reduced by the reduction in size and weight.
[0025]
Incidentally, in the matched filter according to the first aspect of the present invention, the data shift switching means performs data update and holding control and path switching. In the matched filter of the second aspect of the present invention, path switching is performed by the data shift switching means. Then, data update and holding control are performed by the clock control means.
[0026]
A CDMA receiver according to a third aspect of the present invention comprises the matched filter according to the first or second aspect of the present invention, and is configured to perform synchronization acquisition or synchronization tracking based on a correlation detection result of the matched filter. take.
[0027]
According to this configuration, since the matched filter of the invention according to claim 1 or 2 is provided, it is possible to provide a CDMA receiver that can be reduced in size, cost and power consumption.
[0028]
A base station apparatus according to a fourth aspect of the present invention comprises the matched filter according to the first or second aspect of the present invention, wherein synchronization is acquired with respect to a spread spectrum modulation signal by the matched filter, and the acquired synchronization timing The control is performed based on the above.
[0029]
According to this configuration, since the matched filter of the invention according to claim 1 or 2 is provided, it is possible to provide a base station apparatus that can be reduced in size, cost, and power consumption.
[0030]
According to a fifth aspect of the present invention, there is provided a mobile communication terminal apparatus comprising the matched filter according to the first or second aspect, wherein the matched filter acquires synchronization for a spread spectrum modulation signal, and the acquired synchronization timing is obtained. The structure which controls based on this is taken.
[0031]
According to this configuration, since the matched filter of the invention according to claim 1 or 2 is provided, it is possible to provide a mobile communication terminal apparatus that can be reduced in size, cost, and power consumption.
[0032]
A mobile communication system according to a sixth aspect of the invention employs a configuration comprising the base station apparatus according to the fourth aspect and the mobile communication terminal apparatus according to the fifth aspect.
[0033]
According to this configuration, it is possible to provide a mobile communication system including a base station apparatus and a mobile communication terminal apparatus that can be reduced in size, cost, and power consumption.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
The essence of the present invention is that the input data oversampled four times is shifted and held by one symbol length, and the output of the data register located at the last stage of each set of shift registers is output for despreading operation. A clock signal synchronized with the 4-times oversampling phase is always supplied to the shift means, and data update and hold control in the data shift means is performed for each 1-, 2-, 4-times oversample.
[0035]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0036]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a matched filter according to Embodiment 1 of the present invention.
[0037]
In FIG. 1, a matched filter 101 includes a data shift register 102 and an oversample shift control unit 103 that generates a selection signal (1 ×, 2 ×, 4 × oversample switching signal) necessary for the data shift register 102; The clock generator 104 that generates a clock and supplies the clock to the data shift register 102, the code register 105 that takes in the diffusion code necessary for one-symbol correlation calculation and performs serial / parallel conversion, and is stored in the data shift register 102 A despreading operation unit 106 that performs a despreading operation from the spread data stored in the code register 105, a symbol integration unit 107 that calculates a correlation result after the despreading operation, and a memory unit that accumulates a correlation output result 108.
[0038]
The data shift register 102 shifts and holds the received input data Di that has been oversampled four times by one symbol length, and a total of 256 shift registers including data registers 110, 111, 112, and 113 for four taps. In addition, selection circuits 114, 115, 116, and 117 are provided for each shift register. The output of the data register (for example, the data register 113 in the first set) located at the last stage of the 4-tap shift register is input to the despreading operation unit 106. This is because the output of the data register located at the end of each of the other 255 sets of shift registers is input to the despreading operation unit 106.
[0039]
The selection circuit 114 selects one of the received input data Di and the output of the data register 110 of the first tap from the data input side, based on the selection signal SEL41 from the oversample shift control unit 103. In response to a selection signal SEL421 from the oversample shift control unit 103, the selection circuit 115 selects one of the output of the data register 110, the received input data Di, and the output of the data register 111 located at the second tap from the data input side. Select.
[0040]
The selection circuit 116 selects one of the output of the data register 111 and the output of the data register 112 located at the third tap from the data input side by the selection signal SEL41 from the oversample shift control unit 103. In response to the selection signal SEL4210 from the oversample shift control unit 103, the selection circuit 117 outputs the data register 112, the data register 111, the received input data Di, and the data register located at the fourth tap from the data input side. One of the 113 outputs is selected.
[0041]
The data register 110 holds the data selected by the selection circuit 114. The data register 111 holds the data selected by the selection circuit 115. The data register 112 holds the data selected by the selection circuit 116. The data register 113 holds the data selected by the selection circuit 117. The despreading operation unit 106 performs a despreading operation on the data held in the data register 113 and the first tap data from the input side of the code register 105, and outputs the result to the symbol integration circuit 107. The code register 105 inputs a spreading code necessary for one-symbol correlation calculation, serial / parallel converts it, and outputs it.
[0042]
Next, the operation of the matched filter 101 configured as described above will be described with reference to the timing charts shown in FIGS.
[0043]
[4 times oversampling operation]
FIG. 2 is a timing chart showing the operation of the matched filter 101 when 4 times oversampling is set.
[0044]
From the clock generation unit 104, the clock signal CLK synchronized with the quadruple oversampling phase is input to the data shift register 102. Received input data Di is input with four phases of sampling phases A to D as one chip period. In this 4 times oversampling operation, all of the data registers 110 to 113 are used. From the oversample shift control unit 103, control signals SEL41, SEL421, and SEL4210 used in the data shift register 102 are output.
[0045]
The control signals SEL41, SEL421, and SEL4210 signals are all fixed to “4” when the 4-fold oversampling is set. As a result, the data registers 110, 111, 112, and 113 of the data shift register 102 are connected to the shift register, and their outputs tap0, tap1, tap2, and tap3 are synchronized with the clock signal CLK as shown in FIG. The received input data Di is shifted. That is, the received input data data Di is shifted in the order of tap0 → tap1 → tap2 → tap3 →. As a result, the correlation output So is as shown in the figure.
[0046]
[Double oversampling operation]
Next, FIG. 3 is a timing chart showing the operation when the matched filter 101 is set to double oversampling.
[0047]
A clock signal CLK synchronized with the quadruple oversampling phase is supplied from the clock generation unit 104 to the data shift register 102. The received input data Di is input with four phases of sampling phases A to D as one chip period. In this double oversampling operation, the data registers 110 and 112 are not used, and only the data registers 111 and 113 are used.
[0048]
Control signals SEL41 and SEL4210 used in the data shift register 102 are output from the oversample shift control unit 103. The control signal SEL421 when setting the double oversampling specifies whether the data register 111 holds or updates data. Control signal SEL4210 designates whether data register 113 holds or updates data.
[0049]
By generating the control signal SEL421, the control signal SEL421, and the control signal SEL4210 as shown in FIG. 3, the selection circuit 115 switches the input selection to 2, 1, 2, 1,. In addition, the selection circuit 117 switches the input selection to 2, 0, 2, 0. Therefore, the output tap1 of the data register 111 and the output tap3 of the data register 113 are shifted from the data Di of the received input data in the order of tap1, tap1, tap3, tap3,... As shown in FIG. As a result, the correlation output So is as shown in the figure.
[0050]
[1x oversample operation]
FIG. 4 is a timing chart showing the operation when the matched filter 101 is set to 1 × oversampling.
[0051]
A clock signal CLK synchronized with the quadruple oversampling phase is supplied from the clock generation unit 104 to the data shift register 102. The received input data Di is input with four phases of sampling phases A to D as one chip period. A control signal SEL 4210 used in the data shift register 102 is output from the oversample shift control unit 103.
[0052]
The control signal SEL4210 at the time of setting the 1 × oversample designates whether the data register 113 holds or updates data. By generating the control signal SEL4210 as shown in FIG. 4, the selection circuit 117 switches the input selection to 1, 0, 0, 0, 1, 0, 0, 0. Therefore, as shown in FIG. 4, the output tap3 of the data register 113 is shifted from the data Di of the received input data in the order of tap3 → tap3 → tap3 → tap3 →. As a result, the correlation output So is as shown in the figure.
[0053]
As described above, according to the matched filter 101 of the present embodiment, the input data that is oversampled four times is shifted and held by one symbol length, and the data register located at the last stage of each set of shift registers. Is always supplied to the data shift register 102 that outputs the output of the signal for despreading operation in synchronization with the 4-times oversampling phase, and in the data shift register 102 for each oversample of 1 time, 2 times, 4 times Performs data update and retention control.
[0054]
Therefore, as compared with the conventional matched filter 1001, the code register, the despreading operation unit, and the symbol integration unit can be reduced to about ¼, and the correlation output selection unit can be deleted. This makes it possible to reduce the size and weight and reduce the cost.
[0055]
Note that the matched filter 101 of the present embodiment shows an example in which the number of oversamples is variable by 1 to 4 times, and the case where the number of oversamples is variable by using the same concept. But it is possible.
[0056]
(Embodiment 2)
FIG. 5 is a block diagram showing the configuration of the matched filter according to Embodiment 2 of the present invention.
[0057]
In FIG. 5, a matched filter 501 of this embodiment includes a data shift register 502, an oversample shift control unit 503 that generates and outputs a selection control signal necessary for the data shift register 502, and a clock for generating data. A clock generator 504 to be supplied to the shift register 502, a code register 505 for taking in a spread code necessary for one-symbol correlation calculation and serial / parallel conversion, and data stored in the data shift register 502 and stored in the code register 505 A despreading operation unit 506 that performs a despreading operation from the spread code, a symbol integration unit 507 that calculates a correlation result after the despreading operation, and a memory unit 508 that stores a correlation output result.
[0058]
The data shift register 502 shifts and holds the received input data Di that has been oversampled four times by one symbol length, and totals shift registers including data registers 510, 511, 512, and 513 for four taps. In addition to 256 sets, selection circuits 514 and 515 are provided for each shift register. The output of the data register (for example, the data register 513 in the first set) located at the last stage of the 4-tap shift register is input to the despreading operation unit 506. This is because the output of the data register located at the end of each of the other 255 sets of shift registers is input to the despreading operation unit 506.
[0059]
The data register 510 is located at the first tap from the data input side, and holds the received input data Di by the clock CLK4 from the clock generation unit 504. The data register 511 is located at the second tap from the data input side, and holds the output of the selection circuit 514 by the clock CLK 42 from the clock generation unit 504. The data register 512 is located at the third tap from the data input side, and holds the output of the data register 511 by the clock CLK4 from the clock generation unit 504. The data register 513 is located at the fourth tap from the data input side, and holds the output of the selection circuit 515 by the clock CLK 421 from the clock generation unit 504.
[0060]
The selection circuit 514 selects one of the output of the data register 510 and the received input data Di in accordance with the selection signal SEL42 from the oversample shift control unit 503. The selection circuit 515 selects one of the output of the data register 511, the output of the data register 512, and the reception input data Di in accordance with the selection signal SEL421 from the oversample shift control unit 503. The code register 505 performs serial / parallel conversion on a spreading code necessary for one symbol correlation calculation. The despreading operation unit 506 performs despreading operation on the contents of the first tap from the output of the data register 513 and the data input side of the code register 505, and outputs the result to the symbol integration unit 507.
[0061]
Next, the operation of the matched filter 501 will be described with reference to the timing charts shown in FIGS.
[0062]
[4 times oversampling operation]
FIG. 6 is a timing chart showing the operation of the matched filter 501 when setting 4 times oversampling.
[0063]
Clock signals CLK 421, CLK 42, and CLK 4 synchronized with the 4-times oversampling phase are input from the clock generator 504 to the data shift register 502. The received input data Di is input with four phases of sampling phase A to phase D as one chip period. In the 4 × oversample operation, all of the data registers 510 to 512 are used.
[0064]
From the oversample shift control unit 503, control signals SEL42 and SEL421 used in the data shift register 502 are output. The control signals SEL42 and SEL421 are all fixed to “4” when the 4-times oversampling is set. As a result, the data registers 510, 511, 512, and 513 of the data shift register 502 are connected to the shift register, and their outputs tap0, tap1, tap2, and tap3 are received input data in synchronization with the clock as shown in FIG. Shift Di. As a result, the correlation output So is as shown in the figure.
[0065]
[Double oversampling operation]
FIG. 7 is a timing chart showing the operation of the matched filter 501 when setting the double oversampling.
[0066]
Clock signals CLK 421 and CLK 42 synchronized with the double oversampling phase are supplied from the clock generator 504 to the data shift register 502. The received input data Di is input with four phases of sampling phase A to phase D as one chip period. In the double oversampling operation, the data register 511 and the data register 513 are used.
[0067]
The oversample shift control unit 503 outputs control signals SEL42 and SEL421 used in the data shift register 502. The control signal SEL42 at the time of double oversampling selects data to be input to the data register 511. A control signal SEL 421 selects data to be input to the data register 513. By fixing the control signals SEL421 and SEL42 to “2” as shown in FIG. 7, the output tap1 of the data register 511 and the output tap3 of the data register 513 are as shown in FIG. As a result, the correlation output So is as shown in the figure.
[0068]
[1x oversample operation]
FIG. 8 is a timing chart showing the operation of the matched filter 501 when the 1 × oversampling is set.
[0069]
A clock signal CLK 421 synchronized with the 1 × oversampling phase is supplied from the clock generator 504 to the data shift register 502. The received input data Di is input with four phases of sampling phase A to phase D as one chip period. The oversample shift control unit 503 outputs control signals SEL42 and SEL421 used in the data shift register 502. The control signal SEL 421 at the time of 1-time oversampling selects data to be input to the data register 513.
[0070]
By inputting the control signal SEL421 as shown in FIG. 8, the output tap3 of the data register 13 becomes as shown in FIG. As a result, the correlation output So is as shown in the figure. As a point here, the matched filter 501 of the present embodiment can reduce the selection circuit in the data register front stage in the data shift register 502 as compared with the matched filter 101 of the first embodiment described above. Therefore, the circuit scale and power consumption can be further reduced. In addition, there is an advantage that ON / OFF control of clock supply to the data register in the data shift register 502 is easy.
[0071]
Note that the matched filter 501 shown in FIG. 5 shows an example in which the number of oversamples can be varied by 1 to 4 times, and even if the number of oversamples is variable by using the same concept. It is possible.
[0072]
As described above, according to the matched filter 501 of this embodiment, the input data that has been oversampled four times is shifted and held by one symbol length, and the data register located at the last stage of each set of shift registers. Is supplied to the data shift register 502 that outputs the output for despreading operation for each oversample of 1 ×, 2 ×, and 4 ×, and a clock signal synchronized with the oversampling phase corresponding to each oversample is supplied. The data shift path in the data shift register 502 is switched every 2 times or 4 times the number of oversamples.
[0073]
Therefore, although the function of the clock generation unit 504 is complicated, the number of selection circuits 514 and 515 of the data shift register 502 can be reduced as compared with the matched filter 101 of the first embodiment, and the clock supply to the data shift register is also reduced. Therefore, the circuit scale and power consumption can be further reduced.
[0074]
(Embodiment 3)
FIG. 13 is a block diagram showing the main configuration of the CDMA receiving apparatus according to Embodiment 3 of the present invention.
[0075]
The CDMA receiver shown in the figure includes a receiving antenna 901, a high-frequency signal processing unit 902 that performs predetermined filtering and amplification, an A / D converter 903, a demodulator 904, a decoder 905, and a decoded signal as audio. And a matched filter 101. The matched filter 101 is that of the first embodiment described above, but of course the matched filter 501 of the second embodiment may be used. The spread spectrum received signal is subjected to correlation calculation by the matched filter 101 and a correlation result is output.
[0076]
Since the matched filter 101 performs an oversampling operation variably corresponding to 1 to 4 times with a circuit scale smaller than that of the conventional matched filter 1001, the CDMA receiver according to the present embodiment uses a matched filter. The increase in circuit scale can be suppressed, and the price, size and power consumption of the apparatus can be reduced. In the case of a communication terminal device, the device size can be further reduced, and in the base station device, the power consumption of the entire system mounted in a highly integrated channel can be reduced.
[0077]
【The invention's effect】
As described above, according to the present invention, when the number of oversamples to be calculated is varied from 1 to 4 times, the circuit scale of a necessary code register, despreading operation circuit unit, and symbol integration block is about 1 Therefore, it is possible to reduce the size and weight of a device to be applied (for example, a CDMA receiving device, a communication terminal device, a base station device, etc.) and reduce the cost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a matched filter according to Embodiment 1 of the present invention.
FIG. 2 is a timing chart at the time of setting a 4-fold oversample of the matched filter according to the first embodiment of the present invention;
FIG. 3 is a timing chart when setting a double oversampling of the matched filter according to the first embodiment of the present invention.
FIG. 4 is a timing chart at the time of setting a 1 × oversample of the matched filter according to the first embodiment of the present invention;
FIG. 5 is a block diagram showing a configuration of a matched filter according to Embodiment 2 of the present invention.
FIG. 6 is a timing chart when a 4-fold oversampling of the matched filter according to the second embodiment of the present invention is set.
FIG. 7 is a timing chart when setting a double oversampling of the matched filter according to the second embodiment of the present invention.
FIG. 8 is a timing chart when the oversampling of the matched filter according to the second embodiment of the present invention is set.
FIG. 9 is a block diagram showing a main configuration of a CDMA receiving apparatus according to Embodiment 3 of the present invention.
FIG. 10 is a block diagram showing the configuration of a conventional matched filter
FIG. 11 is a timing chart when setting 4 times oversampling of a conventional matched filter.
FIG. 12 is a timing chart when setting twice oversampling of a conventional matched filter.
FIG. 13 is a timing chart when setting a 1 × oversample of a conventional matched filter.
[Explanation of symbols]
101, 501 matched filter
102, 502 Data shift register
103, 503 Oversample shift control unit
104, 504 Clock generator
105, 505 Code register
106, 506 Despreading operation unit
107,507 Symbol integration unit
108,508 Memory part
110, 111, 112, 113 Data register
114, 115, 116, 117 selection circuit
901 Receive antenna
902 High frequency signal processor
903 A / D converter
904 demodulator
905 Decoder
906 Codec section

Claims (6)

Provide multiple sets of shift registers consisting of 4 data registers, shift and hold 4 times oversampled input data by 1 symbol length, and output the data register located at the last stage of each set of shift registers By means of data shift means for outputting the signal for despreading operation, clock signal supply means for supplying a clock signal synchronized with the quadruple oversampling phase to the data shift means, and setting of the oversample number which is the calculation accuracy of the matched filter Data shift switching means for performing data update and holding control in the data shift means and switching the data shift path for each timing synchronized with a sampling frequency at a speed that is determined to be 1 time, 2 times or 4 times faster than the chip rate , Matchtow characterized by comprising Filter. Provide multiple sets of shift registers consisting of 4 data registers, shift and hold 4 times oversampled input data by 1 symbol length, and output the data register located at the last stage of each set of shift registers For each timing synchronized with a sampling frequency at a speed that is 1 time, 2 times, or 4 times faster than the chip rate, determined by the data shift means for outputting the signal for despreading operation and the oversample number setting that is the calculation accuracy of the matched filter The data shift switching means for switching the data shift path in the data shift means, and the sampling frequency at a speed that is 1 time, 2 times or 4 times faster than the chip rate, which is determined by the oversample number setting which is the calculation accuracy of the matched filter. a clock signal synchronized timing Matched filter, characterized by comprising: a clock control unit supplies the serial data shift means.   A CDMA receiving apparatus comprising the matched filter according to claim 1 or 2, wherein synchronization acquisition or synchronization tracking is performed based on a correlation detection result of the matched filter.   A base station apparatus, wherein synchronization is acquired for a spread spectrum modulation signal using the matched filter according to claim 1 and control is performed based on the acquired synchronization timing.   A mobile communication terminal apparatus that acquires synchronization for a spread spectrum modulation signal using the matched filter according to claim 1 and performs control based on the acquired synchronization timing.   A mobile communication system comprising the base station apparatus according to claim 4 and the mobile communication terminal apparatus according to claim 5.

Images