JP3864679B2 - Recording apparatus and recording method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a recording apparatus and a recording method, and more particularly to a recording apparatus and a recording method for generating a strategy and recording a digital information signal on a rewritable optical disc.
[0002]
[Prior art]
Conventionally, in the field of rewritable optical discs such as DVD-RW, further increase in information recording density has been promoted. The mark edge recording employed in the field of the rewritable optical disc can improve the recording density as compared with the mark position recording, but the occurrence of data errors due to the distortion of the mark shape increases as compared with the mark position recording. There is a write strategy technique as a technique for suppressing the distortion of the mark shape. This is a technology that divides the recording waveform of the laser beam into a plurality of short pulses and irradiates the optical disk with the writing laser beam, so as to eliminate the distortion of the recording mark by suppressing heat accumulation at the rear end of the recording mark. It is a thing.
[0003]
For example, the write strategy technology used for DVD-RW uses a plurality of laser pulses having three power levels. The three power levels are, in order from the highest level, peak power (write power), medium power (erase power), and bias power (read power). When the optical disk is irradiated with the laser beam having the above peak power, the recording film of the optical disk is melted. Thereafter, when it is rapidly cooled, the optical disk is in an amorphous state (amorphous state), and the light reflectance is lowered. This is used as a recording mark. For example, the peak power requires an optical output of about 11 mW.
[0004]
When the optical disk is irradiated with medium power laser light, the recording film of the optical disk is brought into a crystalline state. The optical disk portion that was in the amorphous state before the laser light irradiation is in the crystalline state, and the optical disk portion that was originally in the crystalline state remains in the crystalline state as it is. Thereby, the recording mark can be erased. The optical output of the semiconductor laser required for erasing the recording mark is required to be about 5 mW, for example. The laser beam with the bias power is used for reading the information signal recorded on the optical disc.
[0005]
As an example, FIG. 11 shows a basic specification of a write strategy in DVD-RW. FIG. 4A shows recording data after NRZI (Non Return to Zero Inverted) conversion, and FIG. 4B shows a write pulse input to the laser light source. This write pulse includes a top pulse I having a width Ttop synchronized with the rising edge of recording data (information signal) after NRZI conversion shown in FIG. 11A, a multi-pulse II in a period of “1” of the subsequent recording data, It consists of a cooling pulse III having a width Tcl during the period “0” of the recording data. The multi-pulse II is a pulse train in which the peak power level of the width Tmp and the bias power level of the width (T-Tmp) are alternately repeated. The multi-pulse is used to suppress heat accumulation during recording. It is. Here, T is a 1-bit bit period of the recording data.
[0006]
Here, the falling edge of the top pulse I is set so as to be a position delayed by 2T from the rising edge of the recording data after NRZI conversion, and the multipulse II starts from the position delayed by 2T, and after the NRZI conversion. Is set to end at the multi-value falling edge position of the recording data. The cooling pulse III is set to start from the falling edge of the recording data after NRZI conversion. Various values can be set for the widths Ttop, Tmp, and Tcl. However, even if the linear velocity fluctuates due to uneven rotation of the disk, that is, even if the bit period T fluctuates, T Since it is desirable to set the position at a constant ratio, it is basically expressed as a ratio to T, and Ttop = 0.50T, Tmp = 0.40T, Tcl = 0.60T. Is the recommended value.
[0007]
[Problems to be solved by the invention]
However, it is possible to control the widths Ttop, Tmp, and Tcl to positions represented by a certain ratio with respect to the bit period T of the recording data by using a clock with a higher frequency synchronized with T. It is difficult to use such a high clock in both the device performance and the cost in a consumer optical disc apparatus that is rigorously required to reduce the price. Therefore, in practice, the above-described write pulse is generated by using a plurality of fixed delay lines or using an output from a tap close to a target position from another stage delay block carved in fine steps.
[0008]
However, since it is directly affected by temperature characteristics and variations, even if calibration is performed to measure how many steps the length of T corresponds to, the time accuracy of the order of several nanoseconds or 1 nsec or less should be maintained. It is difficult.
[0009]
Further, it is expected that double-speed recording (2X, 10X, 20X, etc.) having the merit of high speed will be expected in the future. However, there is a method of switching the delay amount according to the speed using the above-described multistage delay block, but it is still difficult to maintain time accuracy on the order of several nanoseconds or 1 nsec or less.
[0010]
In the future, CAV recording and ZCAV recording, which have the merit that the spindle motor can be miniaturized by keeping the rotational speed of the disk constant, are expected in the field of optical disks, but the linear velocity depends on the disk radial position. Since it changes, it is desirable to follow the write pulse. In this case as well, it is conceivable that the delay amount is switched according to the disk radial position using the above-described multistage delay block, but it is still difficult to maintain time accuracy on the order of several nanoseconds or 1 nsec or less. is there.
[0011]
The present invention has been made in view of the above points, and can record information signals by generating write pulses by adaptively following disk rotation unevenness and changes in linear velocity without using a high-frequency clock. An object is to provide an apparatus and a recording method.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the recording apparatus of the present invention generates a write pulse corresponding to the write strategy by the strategy generation circuit based on the first clock synchronized with the recording data and the recording data. In a recording apparatus that drives a light source and records recording data on an optical recording medium based on a laser beam emitted from a writing light source, a strategy generation circuit adds a error signal to a first clock and outputs a second signal. Error signal adding means for generating a second clock, clock generating means for generating a third clock by shaping the waveform of the second clock by a comparator operation, and extracting a low frequency component of the third clock as an error signal And an error signal extracting means for supplying the error signal adding means to maintain the duty of the second clock at 50%. It is.
[0013]
In the present invention, the duty of the internal clock of the strategy generation circuit can be maintained at 50% by the loop composed of the error signal addition means, the clock generation means, and the error signal extraction means.
[0014]
In order to achieve the above object, the recording apparatus of the present invention generates a write pulse corresponding to the write strategy by the strategy generation circuit based on the first clock synchronized with the recording data and the recording data. In a recording apparatus that drives a light source for writing and records recording data on an optical recording medium based on laser light emitted from the light source for writing, the strategy generation circuit adds an error signal to the first clock. Error signal adding means for generating the second clock, the second clock and the recording data are received as inputs, the rising or falling timing of the clock corresponding to the first clock, and the second clock A clock that maintains the relationship between the falling edge or rising edge timing of the clock at a fixed ratio with respect to the period of the first clock. An error that generates a control pulse and generates a write pulse corresponding to the recording data and the duty control pulse, and an error that extracts the low frequency component of the duty control pulse as an error signal and supplies it to the error signal adding means And a signal extraction means.
[0015]
In the present invention, the duty of the internal clock of the strategy generation circuit can be maintained at an arbitrary value by a loop composed of the error signal addition means, the pulse generation means, and the error signal extraction means.
[0016]
In order to achieve the above object, according to the present invention, the pulse generating means corresponds to the second clock by using the rising or falling edge of the clock corresponding to the first clock as the trailing edge or the leading edge. The first means for generating m pulses having the leading or trailing edge of the falling or rising edge of the clock, and when the duty ratio of m pulses is m: n (where m + n = 1), m When the natural number p times the difference of n becomes the natural number q, the logical value “1” of the m pulse is forced to the logical value “0” or “1” at a rate of q times in the p period of the second clock. And a second means for generating a duty control pulse.
[0017]
In order to achieve the above object, according to the present invention, instead of the error signal adding means, variable delay means for variably controlling the delay time for the first clock according to the level of the error signal is provided. It may be.
[0018]
In order to achieve the above object, the method of the present invention generates a write pulse corresponding to the write strategy based on the recording data synchronized with the first clock and the first clock, and is driven by this write pulse. In a recording method for recording recording data on an optical recording medium based on a laser beam to be generated, a first step of generating a second clock by adding a first error signal to a first clock; A second step of generating a fourth clock by shaping the waveform of the second clock by a comparator operation and generating a third clock and adding a second error signal to the first clock or the second clock And the rise or fall timing of the clock corresponding to the second clock and the fall or rise timing of the clock corresponding to the fourth clock. And a third step of generating a duty control pulse that maintains a constant ratio with respect to the period of the first or second clock, and a low frequency component of the third clock as the first error signal. A fourth step for extracting the low frequency component of the duty control pulse as a second error signal, and a sixth step for generating a write pulse corresponding to the recording data and the duty control pulse. It is characterized by including.
[0019]
In the present invention, a write pulse can be generated without using a clock having a repetition frequency equal to or higher than the repetition frequency of the first to fourth clocks.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Next, each embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of a recording apparatus according to the present invention. In the figure, an information signal extracted by source encoding such as compression encoding by a source encoder 11 is temporarily stored in a recording track buffer 12 and then supplied to a channel encoder 13, where it is supplied from a clock generation circuit 14. In synchronization with the clock, code modulation such as EFM plus and NRZI conversion for mark edge recording are performed to obtain recording data.
[0021]
The recording data extracted from the channel encoder 13 causes the strategy generation circuit 15 to generate a write pulse corresponding to the recording data in synchronization with the clock from the clock generation circuit 14. The above-described clock is locked to pre-pit information or the like on the disc as necessary using a phase locked loop (PLL) circuit. This light pulse is converted into a laser drive signal by the laser drive circuit 16 and supplied to the optical pickup 17 to drive the laser light source in the optical pickup 17, and thereby the laser light whose light intensity is modulated in accordance with the recording data. Recording is performed by irradiating and irradiating a rewritable optical disk such as a DVD-RW (not shown). At this time, in order to optimally control the laser power of the laser light, the APC (Auto Power Control) circuit 18 processes the laser drive signal and feeds it back to the laser drive circuit 16 as necessary. .
[0022]
Although the above block configuration itself is conventionally known, the present invention is characterized by the configuration of the strategy generation circuit 15. In other words, the present invention is a recording apparatus having a strategy generation circuit 15 having a novel configuration.
[0023]
FIG. 2 shows a circuit system diagram of the first embodiment of the strategy generation circuit which is the main part of the recording apparatus according to the present invention. The recording data after NRZI conversion extracted from the channel encoder 13 of FIG. 1 is input to the digital signal processing means 21 of FIG. On the other hand, the clock output from the clock generation circuit 14 in FIG. 1 is supplied as the first clock CLK1 to the first error signal adding means 22 and the second error signal adding means 23 in FIG.
[0024]
The digital signal processing means 21 further receives two clocks (second clock CLK2 and fourth clock CLK4) described later as inputs, and receives two pulses PP and MP corresponding to the recording data after the NRZI conversion. And a third clock CLK3 and a duty control pulse are generated and output. The above-mentioned pulses PP and MP are converted into a target write pulse by being subtracted in an analog manner by a subtractor comprising an operational amplifier 27 and resistors R1 to R4.
[0025]
An object of the present invention is to generate the above-described pulses PP and MP as pulses of appropriate timing. For this purpose, it is only necessary to generate a plurality of clocks present at appropriate timing and duty (ratio) in the digital signal processing means 21. Here, in order to realize the basic strategy of DVD-RW, two clocks (second clock CLK2 and fourth clock CLK4) are generated and input to the digital signal processing means 21 in two loops.
[0026]
First, generation of the first clock, that is, the second clock CLK2 will be described. The second clock CLK 2 is output from the first error signal adding means 22. The first error signal adding means 22 has, for example, a circuit configuration as shown in FIG. 3, and the high frequency component is removed from the first clock CLK1 by an integrating circuit unit including resistors R11 and R12 and a capacitor C1. Thereafter, the first error signal ERR1 extracted by the first error signal extraction means 25 in FIG. 2 to be described later is added through the mixing resistor R13 in FIG. 3, and the added signal is output as the second clock CLK2. .
[0027]
The second clock CLK2 is supplied to the digital signal processing means 21 of FIG. 2, and is converted into a square-wave third clock CLK3 through an internal buffer 24 having a threshold level near the center level of the second clock CLK2. After that, it is output to the outside of the digital signal processing means 21 and supplied to the first error signal extraction means 25.
[0028]
The first error signal extraction means 25 is configured as shown in FIG. 5, for example, and after integrating the third clock CLK3 by an integration circuit comprising a resistor R13 and a capacitor C3, the buffer and polarity inversion circuit 31 temporarily The polarity is inverted and the polarity inversion signal of the low frequency component of the third clock CLK3 is output as the first error signal ERR1. The first error signal ERR1 is supplied to the first error signal adding means 22 shown in FIG. 2 and added to the first clock CLK1 to be the second clock CLK2.
[0029]
Here, the second clock CLK2 supplied to the digital signal processing means 21 is used as an internal clock whose waveform is shaped at a certain threshold level by the comparator operation of the input unit. Even if the clock CLK1 is a rectangular wave with an accurate duty of 50%, the duty of the internal clock is not necessarily 50%. However, there should be a condition in which the duty of the internal clock becomes 50% by slightly grading the second clock CLK2 (making it close to a sine wave) and controlling it to an appropriate DC level. Further, at that time, the duty of the output third clock CLK3 should also be 50%. Therefore, the first clock CLK1 is obtained by integrating it and inverting the polarity as the first error signal ERR1. By adding to, a negative feedback operation is performed, and the internal clock can stably maintain a duty of 50% regardless of the clock cycle.
[0030]
Next, generation of another clock (fourth clock CLK4) will be described. The fourth clock CLK4 is output from the second error signal adding means 23. The second error signal adding means 23 has a circuit configuration as shown in FIG. 4, for example, and the high-frequency component is removed from the first clock CLK1 by an integrating circuit unit composed of resistors R21 and R22 and a capacitor C2. Thereafter, the second error signal ERR2 extracted by the second error signal extraction means 26 shown in FIG. 2, which will be described later, is added via the mixing resistor R23 shown in FIG. 4, and the added signal is output as the fourth clock CLK4. .
[0031]
The fourth clock CLK4 is supplied to the digital signal processing means 21, and is output as a duty control pulse by calculation as described later. The duty control pulse is supplied to the second error signal extraction unit 26, and the low frequency component is output as the second error signal ERR2 by the integration operation. That is, the second error signal extracting means 26 is configured as shown in FIG. 6, for example, and after integrating the duty control pulse by an integrating circuit composed of a resistor R41 and a capacitor C4, the second error signal extracting means 26 temporarily holds it in the buffer 32, The low frequency component of the duty control pulse is output as the second error signal ERR2. This second error signal ERR2 is supplied to the above-described second error signal adding means 23 of FIG. 2 and added to the first clock CLK1 to become the fourth clock CLK4.
[0032]
Here, the fourth clock CLK4 supplied to the digital signal processing means 21 is used as an internal clock whose waveform is shaped at a certain threshold level by the comparator operation of the input unit. Even if the first clock CLK1 is an accurate rectangular wave with a duty of 60%, the duty of the internal clock is not always 60%.
[0033]
However, there should be a condition that the duty of the internal clock becomes 60% by slightly grading the fourth clock CLK4 (making it close to a sine wave) and controlling it to an appropriate DC level. Although a method for generating the duty control pulse will be described later, a negative feedback operation is performed by adding an integrated signal to the second clock as the second error signal ERR2, and the internal clock is stable regardless of the clock cycle. Thus, the edge can be kept at a certain ratio with respect to the second clock CLK2. As a result, a pulse having an arbitrary duty described later can be obtained, and a stable write pulse can be generated.
[0034]
Next, generation of duty control pulses by the digital signal processing means 21 will be described with reference to the timing chart of FIG. Here, in order to create a basic strategy of DVD-RW, a duty control pulse generation method for obtaining a pulse with a duty ratio of 0.6T: 0.4T will be described.
[0035]
7A shows a second waveform obtained by shaping the waveform of the second clock CLK2 input to the digital signal processing means 21 at a certain threshold level by the comparator operation of the input section of the digital signal processing means 21. FIG. An internal clock corresponding to this clock, and the duty is accurately controlled to 50% by the loop described above. FIG. 7B shows a fourth waveform obtained by shaping the waveform of the fourth clock CLK4 input to the digital signal processing means 21 at a certain threshold level by the comparator operation of the input section of the digital signal processing means 21. This is an internal clock corresponding to the other clock.
[0036]
The digital signal processing means 21 generates a waveform pulse shown in FIG. 7C by a logical operation calculation using the internal clocks corresponding to the second clock and the fourth clock as inputs. Here, as shown in FIGS. 7A to 7C, the pulse is a waveform that rises at the falling edge of the internal clock in FIG. 7B and falls at the rising edge of the internal clock in FIG. is there. In the correct position, the duty of the pulse should be 0.6T for the L level period and 0.4T for the H level period as shown in FIG. 7C.
[0037]
Next, the digital signal processing means 21 performs a modulo 6 count operation on the internal clock corresponding to the second clock shown in FIG. 7A to obtain a count value as shown in FIG. Thus, the H level of the polarity inversion pulse of the pulse within the period when the count value is “0” is forcibly set to the L level. As described above, the duty control pulse shown in FIG. 7E is forcibly setting the H level during the period of 0.6T to the L level at a ratio of one period among the six periods of the pulse whose polarity is inverted. is there.
[0038]
The duty control pulse is extracted from the digital signal processing means 21 and integrated by the second error signal extraction means 26 in FIG. 2 as described above, and the low frequency component is output as the second error signal ERR2. When the DC component for each period T is calculated by setting the H level of the duty control pulse to +1 and the L level to -1, the result is as shown in FIG. 7 (F), and the DC component becomes 0 after integration. I understand. That is, as shown in FIG. 7C, when the pulse has an L level period of 0.6T (or 0.4T) and an H level period of 0.4T (or 0.6T) (that is, 0). .6T: 0.4T), the second error signal ERR2 is zero.
[0039]
Even if the DC component of the fourth clock CLK4 is deviated and the waveform of the clock shown in FIG. 7B is changed, and as a result, the duty ratio of the pulse deviates from 0.6T: 0.4T, Since the DC component of the duty control pulse changes in the direction opposite to the duty shift direction of the pulse, a negative feedback loop results, and the duty control pulse is stabilized as shown in FIG.
[0040]
When the duty ratio of the pulse is set to 0.7T: 0.3T, the internal clock corresponding to the second clock is modulo 5 counted, and the pulse H level is set to twice every five times. If the duty of mpulse is to be set to mT: nT (m> n, where m + n = 1), the natural number p times (mn) becomes the natural number q. The H level of the pulse may be forced to the L level at a rate of q times during the period of pT. If the polarity etc. are taken into consideration, a state of m <n can be created.
[0041]
Next, the operation of generating the pulses PP and MP for generating the write pulse by the digital signal processing means 21 will be described with reference to the timing chart of FIG. FIG. 8A shows a second waveform obtained by shaping the waveform of the second clock CLK2 input to the digital signal processing means 21 at a certain threshold level by the comparator operation of the input section of the digital signal processing means 21. An internal clock corresponding to this clock, and the duty is accurately controlled to 50% by the loop described above. FIG. 7B shows recording data after NRZI conversion input to the digital signal processing means 21 from the channel encoder 13 of FIG.
[0042]
The digital signal processing means 21 delays the above-mentioned input recording data in synchronization with the internal clock corresponding to the second clock (FIG. 8A) by a latch operation as much as necessary, and forms an input recording by assembling a logic circuit. A multi-pulse that rises at the falling edge of the top pulse gate pulse (FIG. 8 (C)) and the top pulse gate pulse rises when it is delayed by 1T from the rising edge of the data, and falls at the falling edge of the recording data. A pulse gate pulse (FIG. 8D) and a cooling pulse gate pulse having a width T rising at the falling edge of the multi-pulse gate pulse (FIG. 8E) are generated.
[0043]
Then, the digital signal processing means 21 uses the pulse shown in FIG. 8 (F) generated by the method described with reference to FIG. 7 and already maintained at an appropriate duty ratio, and the above three types of gate pulses. A first pulse PP shown in FIG. 8G and a second pulse MP shown in FIG. 8H are generated.
[0044]
That is, the H pulse period of the top pulse gate pulse shown in FIG. 8C rises in synchronization with the fall of the internal clock in FIG. 8A, and the top pulse gate pulse in FIG. A pulse composed of a pulse having a width of 0.5 T that falls in synchronization with the falling edge and a pulse that is output as a gate during the H level period of the multi-pulse gate pulse shown in FIG. To do. In addition, during the H level period of the multi-pulse gate pulse shown in FIG. 8 (D), the gate output pulse having the polarity reversed in the pulse of FIG. 8 (F) and the cooling pulse gate pulse H shown in FIG. 8 (E). During the level period, a pulse composed of the internal clock shown in FIG.
[0045]
The first pulse PP is extracted from the digital signal processing means 21 and supplied to the non-inverting input terminal of the operational amplifier 27 through a resistance voltage dividing circuit composed of resistors R1 and R2 shown in FIG. The second pulse MP is extracted from the digital signal processing means and supplied to the inverting input terminal 27 of the operational amplifier 27 through the resistor R3 shown in FIG. The operational amplifier 27 having the feedback resistor R4 operates as a subtracter, performs an analog subtraction operation of (PP-MP), generates a pulse shown in FIG. 8 (I), and outputs this as a write pulse.
[0046]
As described above, according to the present embodiment, the repetition frequency of the clocks CLK1 to CLK4 used is a low frequency of about 27 MHz, for example, and a write pulse can be generated without using a high frequency clock of 50 MHz or more. it can. The write pulse shown in FIG. 8I generated according to the present embodiment changes the first clock CLK1 following the change in the linear velocity of the optical disk at the time of recording. Since the clocks CLK2 and CLK4 operate so that the error signals ERR1 and ERR2 are minimized by the negative feedback operation of the two loops, the two pulses PP and MP generated by the digital signal processing means 21 fluctuate, Even if the absolute length of T changes due to a change in linear velocity, a light pulse that follows the length can be generated.
[0047]
Next, another embodiment of the present invention will be described. FIG. 9 is a circuit diagram of a second embodiment of the strategy generation circuit which is the main part of the recording apparatus according to the present invention. In the figure, the same components as those in FIG. The second embodiment shown in FIG. 9 is characterized in that a variable delay means 35 is provided instead of the second error signal adding means 23 in FIG.
[0048]
The variable delay means 35 is a block whose delay time can be varied according to the voltage. For example, as shown in FIG. 10, the variable delay means 35 supplies the second error signal to the anode of the varicap 37 to vary its capacitance value. Thus, the integration time constant of the integration circuit composed of the resistor 36 and the varicap 37 is changed, and the rising slope of the first clock CLK1 input to one end of the resistor 36 is varied and output as the fourth clock CLK4. . The fourth clock CLK4 of the analog waveform is subjected to a comparison process at a certain threshold level at the input portion of the digital signal processing means 21 at the subsequent stage, whereby the fourth clock CLK4 is shaped into a square wave and its rising edge Is delayed according to the capacitance value of the varicap 37.
[0049]
The present invention is not limited to the above embodiment, and the second clock CLK2 is input to the second error signal adding means 23 and the variable delay means 35 in place of the first clock CLK1. In addition, when the duty control pulse is generated, the first clock CLK1 can be used together with the fourth clock CLK4 instead of the second clock CLK2.
[0050]
【The invention's effect】
As described above, according to the present invention, the duty control pulse can be stably obtained without using a clock having a repetition frequency equal to or higher than the repetition frequency of the first to fourth clocks. Based on this, a write pulse can be generated stably. Further, according to the present invention, since the first clock is generated in phase synchronization with the reproduction information of the pre-pits recorded in advance on the optical recording medium, recording is performed due to fluctuations in linear velocity due to rotation irregularities of the optical recording medium Even if the absolute recording length of the data bit period T varies, the write pulse can be generated following the variation, and an appropriate bit pattern can be recorded without being affected by variations in linear velocity. .
[0051]
As described above, according to the present invention, at the time of double speed recording having the advantage of high-speed recording, recording can be performed without using a high-frequency clock, and CAV recording, ZCAV recording having the advantage of downsizing the spindle motor, etc. Then, even if the linear velocity changes according to the radial position of the disk-shaped optical recording medium, it is possible to generate a light pulse that adaptively follows the change in linear velocity without using a high-frequency clock, This makes it possible to always record a good information signal.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a circuit system diagram of a first embodiment of a strategy generation circuit which is a main part of the device of the present invention;
FIG. 3 is a circuit diagram of an example of first error signal adding means in FIG. 2;
4 is a circuit diagram of an example of second error signal adding means in FIG. 2. FIG.
FIG. 5 is a circuit diagram of an example of first error signal extraction means in FIG. 2;
6 is a circuit diagram of an example of second error signal extraction means in FIG. 2. FIG.
7 is a timing chart for explaining a method of generating a duty control pulse by the digital signal processing means in FIG. 2. FIG.
8 is a timing chart for explaining a method of generating pulses PP and MP by the digital signal processing means in FIG. 2 and a write pulse in FIG.
FIG. 9 is a circuit diagram of a second embodiment of a strategy generation circuit that is a main part of the device of the present invention;
10 is a circuit diagram of an example of a variable delay means in FIG. 9. FIG.
FIG. 11 is a diagram showing a relationship between recording data transfer and pulses of an optical disc of the DVD-RW standard.
[Explanation of symbols]
11 Source encoder
12 Recording track buffer
13 channel encoder
14 Clock generation circuit
15 Strategy generation circuit
16 Laser drive circuit
17 Optical pickup
21 Digital signal processing means
22 First error signal adding means
23 Second error signal adding means
25 First error signal extraction means
26 Second error signal extraction means
27 Operational amplifier
35 Variable delay means

Claims (6)

A laser emitted from the write light source by generating a write pulse corresponding to the write strategy by the strategy generation circuit based on the first clock synchronized with the record data and the record data, driving the write light source In a recording apparatus for recording the recording data on an optical recording medium based on light,
The strategy generation circuit includes:
Error signal adding means for adding an error signal to the first clock to generate a second clock;
Clock generating means for generating a third clock by shaping the waveform of the second clock by a comparator operation;
Error signal extracting means for extracting the low frequency component of the third clock as the error signal and supplying it to the error signal adding means to maintain the duty of the second clock at 50%. A recording device. A laser emitted from the write light source by generating a write pulse corresponding to the write strategy by the strategy generation circuit based on the first clock synchronized with the record data and the record data, driving the write light source In a recording apparatus for recording the recording data on an optical recording medium based on light,
The strategy generation circuit includes:
Error signal adding means for adding an error signal to the first clock to generate a second clock;
The second clock and the recording data are received as inputs, the rising or falling timing of the clock corresponding to the first clock, and the falling or rising timing of the clock corresponding to the second clock, Generating a duty control pulse having a constant ratio with respect to the period of the first clock, and a pulse generating means for generating the write pulse corresponding to the recording data and the duty control pulse; ,
A recording apparatus comprising: an error signal extracting unit that extracts a low frequency component of the duty control pulse as the error signal and supplies the extracted error signal to the error signal adding unit. The pulse generation means uses a rising or falling edge of a clock corresponding to the first clock as a trailing edge or a leading edge, and a falling or rising edge of a clock corresponding to the second clock as a leading edge or a leading edge. When the first means for generating the m pulse as the trailing edge and the duty ratio of the m pulse is m: n (where m + n = 1), the natural number p times the difference between m and n becomes the natural number q. When the second clock is generated, the logic value “1” of the m pulse is forcibly set to the logic value “0” or “1” at a rate of q times in the p period of the second clock. 3. A recording apparatus according to claim 2, further comprising: means. 4. A variable delay means for variably controlling a delay time with respect to the first clock according to a level of the error signal, instead of the error signal adding means. A recording apparatus according to claim 1. 4. The recording apparatus according to claim 1, wherein the first clock is generated in phase with a reproduction signal of prepit information recorded in advance on the optical recording medium. A write pulse corresponding to a write strategy is generated based on recording data synchronized with a first clock and the first clock, and the recording is performed on an optical recording medium based on a laser beam driven by the write pulse. In a recording method for recording data,
A first step of adding a first error signal to the first clock to generate a second clock;
A waveform of the second clock is shaped by a comparator operation to generate a third clock, and a second error signal is added to the first clock or the second clock to generate a fourth clock. A second step;
The relationship between the rise or fall timing of the clock corresponding to the second clock and the fall or rise timing of the clock corresponding to the fourth clock is expressed by the period of the first or second clock. A third step of generating a duty control pulse held at a constant ratio with respect to,
A fourth step of extracting a low frequency component of the third clock as the first error signal;
A fifth step of extracting a low frequency component of the duty control pulse as the second error signal;
And a sixth step of generating the write pulse corresponding to the duty control pulse.

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