JP3864031B2

JP3864031B2 - Semiconductor integrated circuit for LCD panel drive

Info

Publication number: JP3864031B2
Application number: JP2000105317A
Authority: JP
Inventors: 誠司山縣; 政利國分; 真也鵜戸
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 2000-04-06
Filing date: 2000-04-06
Publication date: 2006-12-27
Anticipated expiration: 2020-04-06
Also published as: JP2001290123A

Description

【０００１】
【発明の属する技術分野】
本発明は、液晶パネル駆動用半導体集積回路に関し、特に、デジタル画像データを基にアナログ階調電圧を液晶パネルに出力する液晶パネル駆動用半導体集積回路に関する。
【０００２】
【従来の技術】
図１２は、従来技術による液晶表示装置の構成図である。液晶表示装置は、ＴＦＴ液晶パネルＰＮＬ及び液晶パネル駆動用半導体集積回路４０を有する。半導体集積回路４０は、データラッチ部ＬＴ、セレクタ部ＳＥＬ、オペアンプ部ＯＰ、出力切替部ＳＷを有する。データラッチ部ＬＴには、２×ｍ個のデータラッチＬＴ１〜ＬＴ４が水平方向に配列されている。セレクタ部ＳＥＬには、２×ｍ個のセレクタＳＥＬ１〜ＳＥＬ４が水平方向に配列されている。オペアンプ部ＯＰには、２×ｍ個のオペアンプＯＰ１〜ＯＰ４が水平方向に配列されている。出力切替部ＳＷには、ｍ個の出力切替部ＳＷ１，ＳＷ２が水平方向に配列されている。
【０００３】
半導体集積回路４０は、例えば３８４出力の場合、数値ｍが１９２になる。なお、図１２では、図の簡略化のために、水平方向の数を減らして示している。
【０００４】
データラッチ部ＬＴには、直上に配置されるデータラッチ線が配線コンタクト部１（●印で示す）で接続され、負極性データラッチＬＴ１，ＬＴ３と正極性データラッチＬＴ２，ＬＴ４とが交互に水平方向に２×ｍ個配列されている。負極性データラッチＬＴ１，ＬＴ３は、所定階調の負極性のアナログ階調電圧を発生させるためのｎビット（６４階調の場合は６ビット）のデジタル画像データを外部から入力して保持する。正極性データラッチＬＴ２，ＬＴ４は、所定階調の正極性のアナログ階調電圧を発生させるためのｎビットのデジタル画像データを外部から入力して保持する。
【０００５】
セレクタ部ＳＥＬには、負極性セレクタＳＥＬ１，ＳＥＬ３と正極性セレクタＳＥＬ２，ＳＥＬ４とが交互に水平方向に２×ｍ個配列されている。負極性セレクタＳＥＬ１，ＳＥＬ３はＮチャネルＭＯＳトランジスタにより構成され、正極性セレクタＳＥＬ２，ＳＥＬ４はＰチャネルＭＯＳトランジスタにより構成される。セレクタＳＥＬ１〜ＳＥＬ４の直上には、例えば６４階調の場合、６４×２本の正極性及び負極性階調電圧線ＬＮが配置される。負極性セレクタＳＥＬ１，ＳＥＬ３には６４本の負極性階調電圧線ＬＮが配線コンタクト部１で接続され、正極性セレクタＳＥＬ１，ＳＥＬ３には６４本の正極性階調電圧線ＬＮが配線コンタクト部１で接続されている。
【０００６】
負極性セレクタＳＥＬ１，ＳＥＬ３は、負極性階調電圧線ＬＮ上に発生させられる例えば６Ｖから０Ｖまでの負極性のアナログ階調電圧を基に、データラッチＬＴ１，ＬＴ３が保持するデジタル画像データに応じて所定の階調の負極性アナログ階調電圧を選択する。正極性セレクタＳＥＬ２，ＳＥＬ４は、正極性階調電圧線ＬＮ上に発生させられる例えば６Ｖから１２Ｖまでの正極性のアナログ階調電圧を基に、データラッチＬＴ２，ＬＴ４が保持するデジタル画像データに応じて所定の階調の正極性アナログ階調電圧を選択する。
【０００７】
オペアンプ部ＯＰには、負極性オペアンプＯＰ１，ＯＰ３と正極性オペアンプＯＰ２，ＯＰ４とが交互に水平方向に２×ｍ個配列されている。負極性オペアンプＯＰ１，ＯＰ３は、負極性セレクタＳＥＬ１，ＳＥＬ３により選択された負極性アナログ階調電圧を増幅して出力する。正極性オペアンプＯＰ２，ＯＰ４は、正極性セレクタＳＥＬ２，ＳＥＬ４により選択された正極性アナログ階調電圧を増幅して出力する。
【０００８】
出力切替部ＳＷには、出力切替部ＳＷ１，ＳＷ２が水平方向にｍ個配列されている。出力切替部ＳＷ１は、負極性オペアンプＯＰ１から出力される負極性アナログ階調電圧及び正極性オペアンプＯＰ２から出力される正極性アナログ階調電圧の信号経路をストレート又はクロスに切り替えて液晶パネルＰＮＬに出力する。出力切替部ＳＷ２は、負極性オペアンプＯＰ３から出力される負極性アナログ階調電圧及び正極性オペアンプＯＰ４から出力される正極性アナログ階調電圧の信号経路をストレート又はクロスに切り替えて液晶パネルＰＮＬに出力する。液晶パネルＰＮＬは、赤色と緑色と青色の３色からなる各画素を各色について所定の階調電圧で液晶表示を行う。
【０００９】
【発明が解決しようとする課題】
半導体集積回路４０は、データラッチ部ＬＴ、セレクタ部ＳＥＬ及びオペアンプ部ＯＰの縦方向に並ぶ列が水平方向に２×ｍ組（例えば３８４組）繰り返し並ぶため、水平方向の長さ２４が長い長方形の半導体集積回路４０が形成される。例えば、水平方向の長さ２４が約１５ｍｍであり、垂直方向の長さが約２ｍｍである。この半導体集積回路４０は、面積が比較的大きいので、より小さい面積の半導体集積回路４０の開発が望まれている。特に、半導体集積回路４０の水平方向の長さを短くすることが望まれている。
【００１０】
また、負極性セレクタＳＥＬ１，ＳＥＬ３の直上では、負極性階調電圧線ＬＮは配線コンタクト部１において負極性セレクタＳＥＬ１，ＳＥＬ３と接続されているが、正極性階調電圧線ＬＮは負極性セレクタＳＥＬ１，ＳＥＬ３と接続されておらず、その領域（図上の斜線領域）が未使用領域２として無駄になってしまう。同様に、正極性セレクタＳＥＬ２，ＳＥＬ４にも、無駄な未使用領域２が生じてしまう。
【００１１】
また、ＮチャネルＭＯＳトランジスタで構成される負極性セレクタＳＥＬ１，ＳＥＬ３とＰチャネルＭＯＳトランジスタで構成される正極性セレクタＳＥＬ２，ＳＥＬ４とが交互に配置されるため、異なるチャネルタイプのセレクタ間の距離２３をある程度以上は広げなければならず、半導体集積回路４０の水平方向の長さ２４を必要以上に長くせざるを得ない。
【００１２】
本発明の目的は、液晶パネル駆動用半導体集積回路を小さい面積で構成できるようにすることである。
【００１３】
【課題を解決するための手段】
本発明の液晶パネル駆動用半導体集積回路は、外部から入力されるｎビットのデジタル画像データを保持するデータラッチと、各階調の正極性のアナログ階調電圧を正極性階調電圧線上に発生させる正極性階調電圧発生部と、各階調の負極性のアナログ階調電圧を負極性階調電圧線上に発生させる負極性階調電圧発生部と、直上に前記負極性階調電圧線が配置されずに前記正極性階調電圧線が配置され、前記データラッチが保持したｎビットのデジタル画像データに応じて、前記正極性階調電圧発生部により発生させられる各階調の正極性のアナログ階調電圧を選択する正極性セレクタと、直上に前記正極性階調電圧線が配置されずに前記負極性階調電圧線が配置され、前記データラッチが保持したｎビットのデジタル画像データに応じて、前記負極性階調電圧発生部により発生させられる各階調の負極性のアナログ階調電圧を選択する負極性セレクタと、前記正極性セレクタ及び前記負極性セレクタにより選択された正極性アナログ階調電圧及び負極性アナログ階調電圧を増幅して出力するオペアンプと、前記オペアンプにより出力される正極性アナログ階調電圧及び負極性アナログ階調電圧の信号経路をストレート又はクロスに切り替えて液晶パネルに出力する出力切替部とを備え、前記データラッチは、正極性のアナログ階調電圧を発生させるためのデジタル画像データを保持する正極性データラッチと、負極性のアナログ階調電圧を発生させるためのデジタル画像データを保持する負極性データラッチとを含み、前記正極性セレクタは、前記正極性データラッチが保持したデジタル画像データに応じて前記正極性のアナログ階調電圧を選択し、前記負極性セレクタは、前記負極性データラッチが保持したデジタル画像データに応じて前記負極性のアナログ階調電圧を選択し、前記オペアンプは、前記正極性セレクタにより選択された正極性アナログ階調電圧を増幅して出力する正極性オペアンプと、前記負極性セレクタにより選択された負極性アナログ階調電圧を増幅して出力する負極性オペアンプとを含み、前記正極性データラッチ及び前記正極性セレクタを一組として前記正極性階調電圧線に対して水平方向に複数並べ、前記負極性データラッチ及び前記負極性セレクタを一組として前記負極性階調電圧線に対して水平方向に複数並べて配置したことを特徴とする。
【００１４】
本発明は上記技術手段より成るので、セレクタの直上に配置されている階調電圧線が同一極性のものだけで済み、セレクタの未使用領域をなくすことが可能となる。また、異なるタイプのセレクタを交互に配置しなくても済むので、同タイプのトランジスタをまとめて配置することが可能となり、素子間隔を短くすることが可能となる。
【００１５】
【発明の実施の形態】
以下、本発明の一実施形態を図面に基づいて説明する。
（第１の実施形態）
図１は、第１の実施形態による液晶表示装置の構成例を示す図である。液晶表示装置は、ＴＦＴ液晶パネルＰＮＬ及び液晶パネル駆動用半導体集積回路３０を有する。半導体集積回路３０は、負極性セレクタ部（Ｎチャネルセレクタ部）ＮＳＥＬ、データラッチ部ＬＴ、正極性セレクタ部（Ｐチャネルセレクタ部）ＰＳＥＬ、オペアンプ部ＯＰ、出力切替部ＳＷを有する。本実施形態では、図１２のセレクタ部ＳＥＬが、負極性セレクタ部ＮＳＥＬと正極性セレクタ部ＰＳＥＬとに分割されている。また、ＴＦＴ液晶パネルＰＮＬは、図１２に示したものと同様のものである。
【００１６】
データラッチ部ＬＴには、直上に配置されるデータラッチ線が配線コンタクト部１（●印で示す）で接続される。データラッチ部ＬＴは、上段に負極性データラッチＬＴ１，ＬＴ３が水平方向にｍ個配列され、その下段に隣接して正極性データラッチＬＴ２，ＬＴ４が水平方向にｍ個配列されている。負極性データラッチＬＴ１，ＬＴ３は、所定階調の負極性のアナログ階調電圧を発生させるためのｎビット（６４階調の場合は６ビット）のデジタル画像データを外部から入力して保持する。正極性データラッチＬＴ２，ＬＴ４は、所定階調の正極性のアナログ階調電圧を発生させるためのｎビットのデジタル画像データを外部から入力して保持する。
【００１７】
負極性セレクタ部ＮＳＥＬは、ＮチャネルＭＯＳトランジスタ（転送ゲート）により構成され、負極性セレクタＳＥＬ１，ＳＥＬ３が水平方向にｍ個配列されている。負極性セレクタＳＥＬ１，ＳＥＬ３の直上には、ｍ／３本（例えば６４本）の負極性階調電圧線ＮＬＮが水平方向に延びるように垂直方向に並んで配置されており、負極性セレクタＳＥＬ１，ＳＥＬ３にはｍ／３本の負極性階調電圧線ＮＬＮが配線コンタクト部１で接続されている。
【００１８】
負極性セレクタＳＥＬ１，ＳＥＬ３は、負極性階調電圧線ＮＬＮ上に発生させられる例えば６Ｖから０Ｖまでの負極性のアナログ階調電圧を基に、負極性データラッチＬＴ１，ＬＴ３から信号線３を介して与えられるデジタル画像データに応じて所定の階調を示す負極性アナログ階調電圧を選択し、信号線４を介してオペアンプ部ＯＰに供給する。
【００１９】
図２は、負極性セレクタ（Ｎチャネルセレクタ）ＳＥＬ１及びそれに接続される階調電圧発生部５の回路図である。階調電圧発生部５の端子Ｖ₊には例えば６Ｖが印加され、端子Ｖ_-には例えば０Ｖが印加される。端子Ｖ₊と端子Ｖ_-の間には、ラダー抵抗６が接続される。ラダー抵抗６を抵抗分割するように、ラダー抵抗６にはｍ／３本（例えば６４本）の負極性階調電圧線ＮＬＮが接続され、例えば６Ｖから０Ｖまでの間で６４階調分の負極性のアナログ階調電圧が発生させられる。
【００２０】
６４階調（６ビット）の場合には、各負極性階調電圧線ＮＬＮには６個のＮチャネルＭＯＳトランジスタ（転送ゲート）Ｔｒが直列に接続される。ＮチャネルＭＯＳトランジスタＴｒは、６行６４列の２次元行列として配置され、各トランジスタＴｒのゲートには、負極性データラッチＬＴ１（図１）からの信号線３が接続される。信号線３に供給されるデジタル画像データに応じて、６４本の負極性階調電圧線ＮＬＮのうちのいずれか一本が選択されて、信号線４を介して所定階調のアナログ階調電圧が負極性オペアンプＯＰ１（図１）に出力される。負極性セレクタＳＥＬ３の構成は、上記の負極性セレクタＳＥＬ１の構成と同様である。
【００２１】
図１に戻り、正極性セレクタ部ＰＳＥＬは、ＰチャネルＭＯＳトランジスタ（転送ゲート）により構成され、正極性セレクタＳＥＬ２，ＳＥＬ４が水平方向にｍ個配列されている。正極性セレクタＳＥＬ２，ＳＥＬ４の直上には、ｍ／３本（例えば６４本）の正極性階調電圧線ＰＬＮが水平方向に延びるように垂直方向に並んで配置されており、正極性セレクタＳＥＬ２，ＳＥＬ４にはｍ／３本の正極性階調電圧線ＰＬＮが配線コンタクト部１で接続されている。
【００２２】
正極性セレクタＳＥＬ２，ＳＥＬ４は、正極性階調電圧線ＰＬＮ上に発生させられる例えば６Ｖから１２Ｖまでの正極性のアナログ階調電圧を基に、正極性データラッチＬＴ２，ＬＴ４が保持するデジタル画像データに応じて所定の階調を示す正極性アナログ階調電圧を選択する。正極性セレクタＳＥＬ２，ＳＥＬ４及びそれに接続される階調電圧発生部は、図２に示したものと同様であるが、トランジスタＴｒがＮチャネルではなくＰチャネルにより構成され、端子Ｖ_-には６Ｖが印加され、端子Ｖ₊には１２Ｖが印加される点が異なる。この場合、階調電圧生成部５は、６Ｖから１２Ｖまでの正極性階調電圧を発生させる。
【００２３】
オペアンプ部ＯＰには、上段に正極性（ハイレベル側）のオペアンプＯＰ２，ＯＰ４が水平方向にｍ個配列され、その下に隣接して負極性（ローレベル側）のオペアンプＯＰ１，ＯＰ３が水平方向にｍ個配列されている。負極性オペアンプＯＰ１，ＯＰ３は、負極性セレクタＳＥＬ１，ＳＥＬ３により選択された負極性アナログ階調電圧を増幅して出力する。正極性オペアンプＯＰ２，ＯＰ４は、正極性セレクタＳＥＬ２，ＳＥＬ４により選択された正極性アナログ階調電圧を増幅して出力する。
【００２４】
出力切替部ＳＷには、出力切替部ＳＷ１，ＳＷ２が水平方向にｍ個配列されている。出力切替部ＳＷ１は、負極性オペアンプＯＰ１から出力される負極性アナログ階調電圧及び正極性オペアンプＯＰ２から出力される正極性アナログ階調電圧の信号経路をストレート又はクロスに切り替えて液晶パネルＰＮＬに出力する。出力切替部ＳＷ２は、負極性オペアンプＯＰ３から出力される負極性アナログ階調電圧及び正極性オペアンプＯＰ４から出力される正極性アナログ階調電圧の信号経路をストレート又はクロスに切り替えて液晶パネルＰＮＬに出力する。液晶パネルＰＮＬは、赤色と緑色と青色の３色からなる各画素を各色について所定の階調電圧で液晶表示を行う。
【００２５】
本実施形態では、正極性セレクタＳＥＬ２，ＳＥＬ４及び正極性データラッチＬＴ２，ＬＴ４を正極性の組とし、負極性セレクタＳＥＬ１，ＳＥＬ３及び負極性データラッチＬＴ１，ＬＴ３を負極性の組として、正極性データラッチＬＴ２，ＬＴ４と負極性データラッチＬＴ１，ＬＴ３とが正極性階調電圧線ＰＬＮ及び負極性階調電圧線ＮＬＮに対して垂直方向に隣接するように、正極性の組及び負極性の組を同一直線上に配置する。そして、この垂直方向に一直線上に配置した構成を一組として、正極性階調電圧線ＰＬＮ及び負極性階調電圧線ＮＬＮに対して水平方向に複数組並べて配置する。
【００２６】
これにより、半導体集積回路３０は、負極性セレクタ部ＮＳＥＬ、データラッチ部ＬＴ、正極性セレクタ部ＰＳＥＬ及びオペアンプ部ＯＰの縦方向に並ぶ列が水平方向にｍ組（例えば１９２組）繰り返し並ぶ。図１２に示す半導体集積回路４０は水平方向に２×ｍ組（例えば３８４組）が並ぶが、本実施形態の半導体集積回路３０は水平方向にｍ組（例えば１９２組）が並ぶので、図１２に示すものよりも水平方向の長さ２２が約１／２になる。すなわち、本実施形態の水平方向の長さ２２は、図１２の水平方向の長さ２４の約１／２になり、半導体集積回路３０の面積を小さくすることができる。なお、半導体集積回路３０の垂直方向の長さは、図１２のものに比べてほとんど変わらない。
【００２７】
また、図１２の半導体集積回路４０では、セレクタ部ＳＥＬの直上に配置された階調電圧線ＬＮがセレクタ部ＳＥＬに接続されていない未使用領域（図上の斜線領域）２が生じていたが、本実施形態の半導体集積回路３０ではそのような未使用領域がなくなり、負極性セレクタ部ＮＳＥＬ及び正極性セレクタ部ＰＳＥＬの配線を効率的にレイアウトすることができ、全体として、半導体集積回路３０の面積を小さくすることができる。
【００２８】
また、図１２の半導体集積回路４０では、異なるチャネルタイプのセレクタＳＥＬ間の距離２３をある程度以上は広げなければならなかったが、本実施形態では負極性セレクタＳＥＬ１及びＳＥＬ３は同じＮチャネルタイプのトランジスタを用いているため、セレクタＳＥＬ１及びＳＥＬ３の間の距離２１を短くすることができる。同様に、正極性セレクタＳＥＬ２及びＳＥＬ４も同じＰチャネルタイプのトランジスタを用いているため、セレクタＳＥＬ２及びＳＥＬ４の間の距離を短くすることができるので、半導体集積回路３０の面積をより小さくすることができる。
【００２９】
（第２の実施形態）
図３は、第２の実施形態による液晶表示装置の構成例を示す図である。液晶表示装置は、ＴＦＴ液晶パネルＰＮＬ及び液晶パネル駆動用半導体集積回路３０を有する。本実施形態は、第１の実施形態（図１）と比べて、負極性セレクタ部ＮＳＥＬとデータラッチ部ＬＴの上段との上下位置を逆にするとともに、正極性セレクタ部ＰＳＥＬとデータラッチ部ＬＴの下段との上下位置とを逆にしたものである。
【００３０】
本実施形態の半導体集積回路３０は、負極性データラッチ部ＮＬＴ、負極性セレクタ部ＮＳＥＬ、正極性セレクタ部ＰＳＥＬ、正極性データラッチ部ＰＬＴ、オペアンプ部ＯＰ、出力切替部ＳＷがこの順に垂直方向に並んでいる。負極性データラッチ部ＮＬＴには負極性データラッチＬＴ１，ＬＴ３が水平方向にｍ個配列され、正極性データラッチ部ＰＬＴには正極性データラッチＬＴ２，ＬＴ４が水平方向にｍ個配列されている。
【００３１】
本実施形態では、正極性セレクタＰＳＥＬ及び正極性データラッチＰＬＴを正極性の組とし、負極性セレクタＮＳＥＬ及び負極性データラッチＮＬＴを負極性の組として、正極性セレクタＰＳＥＬと負極性セレクタＮＳＥＬとが階調電圧線ＮＬＮ，ＰＬＮに対して垂直方向に隣接するように、正極性の組及び負極性の組を一直線上に配置する。そして、この垂直方向に一直線上に配置した構成を一組として、正極性階調電圧線ＰＬＮ及び負極性階調電圧線ＮＬＮに対して水平方向に複数組並べる。この構成は、第１の実施形態（図１）に対して配置のみが異なり、第１の実施形態と等価な動作及び効果を奏する。
【００３２】
（第３の実施形態）
図４は、第３の実施形態による液晶表示装置の構成例を示す図である。液晶表示装置は、ＴＦＴ液晶パネルＰＮＬ及び液晶パネル駆動用半導体集積回路３０を有する。本実施形態は、第２の実施形態（図３）と比べて、正極性セレクタ部ＰＳＥＬと正極性データラッチ部ＰＬＴとの上下位置を逆にしたものである。
【００３３】
本実施形態の半導体集積回路３０は、負極性データラッチ部ＮＬＴ、負極性セレクタ部ＮＳＥＬ、正極性データラッチ部ＰＬＴ、正極性セレクタ部ＰＳＥＬ、オペアンプ部ＯＰ、出力切替部ＳＷがこの順に垂直方向に並んでいる。
【００３４】
本実施形態では、正極性セレクタＰＳＥＬ及び正極性データラッチＰＬＴを正極性の組とし、負極性セレクタＮＳＥＬ及び負極性データラッチＮＬＴを負極性の組として、正極性及び負極性の異なる組のセレクタＳＥＬ１，ＳＥＬ３とデータラッチＬＴ２，ＬＴ４とが垂直方向に隣接するように、正極性の組及び負極性の組を一直線上に配置する。そして、この垂直方向に一直線上に配置した構成を一組として、正極性階調電圧線ＰＬＮ及び負極性階調電圧線ＮＬＮに対して水平方向に複数組並べて配置する。この構成は、第１の実施形態（図１）に対して配置のみが異なり、第１の実施形態と等価な動作及び効果を奏する。
【００３５】
（第４の実施形態）
図５は、第４の実施形態による液晶表示装置の構成例を示す図である。液晶表示装置は、ＴＦＴ液晶パネルＰＮＬ及び液晶パネル駆動用半導体集積回路３０を有する。本実施形態は、第２の実施形態（図３）に対して、負極性セレクタ部ＮＳＥＬを第１の負極性セレクタ部ＮＳＥＬａと第２の負極性セレクタ部ＮＳＥＬｂに分割し、正極性セレクタ部ＰＳＥＬを第１の正極性セレクタ部ＰＳＥＬａと第２の正極性セレクタ部ＰＳＥＬｂに分割した点が異なる。上記のセレクタの分割は、例えば、階調値の順番で半分に分けて分割する。
【００３６】
本実施形態の半導体集積回路３０は、第１の負極性セレクタ部ＮＳＥＬａ、負極性データラッチ部ＮＬＴ、第２の負極性セレクタ部ＮＳＥＬｂ、第１の正極性セレクタ部ＰＳＥＬａ、正極性データラッチ部ＰＬＴ、第２の正極性セレクタ部ＰＳＥＬｂ、オペアンプ部ＯＰ、出力切替部ＳＷがこの順に垂直方向に並んでいる。第１の負極性セレクタ部ＮＳＥＬａと第２の負極性セレクタ部ＮＳＥＬｂとは、間に負極性データラッチ部ＮＬＴを挟むように垂直方向に配列される。第１の正極性セレクタ部ＰＳＥＬａと第２の正極性セレクタ部ＰＳＥＬｂとは、間に正極性データラッチ部ＰＬＴを挟むように垂直方向に配列される。
【００３７】
本実施形態では、正極性データラッチＰＬＴを第１及び第２の正極性セレクタ部ＰＳＥＬａ，ＰＳＥＬｂの間に挟んだものを正極性の組とし、負極性データラッチＮＬＴを第１及び第２の負極性セレクタ部ＮＳＥＬａ，ＮＳＥＬｂの間に挟んだものを負極性の組とし、正極性の組と負極性の組とを垂直方向の同一線上に配列する。そして、この垂直方向に同一線上に配置したものを一組として、正極性階調電圧線ＰＬＮ及び負極性階調電圧線ＮＬＮに対して水平方向に複数組並べて配置する。この際、第２の負極性セレクタ部ＮＳＥＬｂと第１の正極性セレクタ部ＰＳＥＬａとが垂直方向に隣接するように正極性の組と負極性の組とが配列される。この構成は、第１の実施形態（図１）に対して配置のみが異なり、第１の実施形態と等価な動作及び効果を奏する。
【００３８】
（第５の実施形態）
図６は、第５の実施形態による液晶表示装置の構成例を示す図である。液晶表示装置は、ＴＦＴ液晶パネルＰＮＬ及び液晶パネル駆動用半導体集積回路３０を有する。本実施形態は、第１の実施形態（図１）に対して、データラッチ部ＬＴの上段部を第１の負極性データラッチ部ＮＬＴａと第２の負極性データラッチ部ＮＬＴｂに分割するとともに、データラッチ部ＬＴの下段部を第１の正極性データラッチ部ＰＬＴａと第２の正極性データラッチ部ＰＬＴｂに分割した点が異なる。上記のデータラッチの分割は、例えば、デジタル画像データ（ｎビット信号）の順番で半分に分けて分割する。なお、データラッチＮＬＴａ，ＮＬＴｂ，ＰＬＴａ，ＰＬＴｂは、上記の分割によりそれぞれ面積が半分になる。
【００３９】
本実施形態の半導体集積回路３０は、第１の負極性データラッチ部ＮＬＴａ、負極性セレクタ部ＮＳＥＬ、第２の負極性データラッチ部ＮＬＴｂ、第１の正極性データラッチ部ＰＬＴａ、正極性セレクタ部ＰＳＥＬ、第２の正極性データラッチ部ＰＬＴｂ、オペアンプ部ＯＰ、出力切替部ＳＷがこの順に垂直方向に並んでいる。第１の負極性データラッチ部ＮＬＴａと第２の負極性データラッチ部ＮＬＴｂとは、間に負極性セレクタ部ＮＳＥＬを挟むように垂直方向に配列される。第１の正極性データラッチ部ＰＬＴａと第２の正極性データラッチ部ＰＬＴｂとは、間に正極性セレクタ部ＰＳＥＬを挟むように垂直方向に配列される。
【００４０】
本実施の形態では、正極性セレクタＰＳＥＬを第１及び第２の正極性データラッチ部ＰＬＴａ，ＰＬＴｂの間に挟んだものを正極性の組とし、負極性セレクタＮＳＥＬを第１及び第２の負極性データラッチ部ＮＬＴａ，ＮＬＴｂの間に挟んだものを負極性の組とし、正極性の組と負極性の組とを垂直方向の同一直線上に配列する。そして、この垂直方向に同一直線上に配置したものを一組として、正極性階調電圧線ＰＬＮ及び負極性階調電圧線ＮＬＮに対して水平方向に複数組並べて配置する。その際、第２の負極性データラッチ部ＮＬＴｂと第１の正極性データラッチ部ＰＬＴａとが垂直方向に隣接するように正極性の組と負極性の組とを配列したものを一組とする。この構成は、第１の実施形態（図１）に対して配置のみが異なり、第１の実施形態と等価な動作及び効果を奏する。
【００４１】
（第６の実施形態）
図７は、第６の実施形態による液晶表示装置の構成例を示す図である。液晶表示装置は、ＴＦＴ液晶パネルＰＮＬ及び液晶パネル駆動用半導体集積回路３０を有する。第１の実施形態（図１）では負極性データラッチＬＴ１，ＬＴ３と正極性データラッチＬＴ２，ＬＴ４とをそれぞれ垂直方向に隣接させたが、本実施形態では、負極性データラッチＬＴ１，ＬＴ３と正極性データラッチＬＴ２，ＬＴ４とをそれぞれ水平方向に隣接させる。
【００４２】
本実施形態の半導体集積回路３０は、負極性セレクタ部ＮＳＥＬ、データラッチ部ＬＴ、正極性セレクタ部ＰＳＥＬ、オペアンプ部ＯＰ、出力切替部ＳＷがこの順に垂直方向に並んでいる。このうち、データラッチ部ＬＴでは、負極性データラッチＬＴ１，ＬＴ３と正極性データラッチＬＴ２，ＬＴ４とがそれぞれ交互に水平方向に配列されている。
【００４３】
本実施形態では、負極性データラッチＬＴ１，ＬＴ３と正極性データラッチＬＴ２，ＬＴ４とを、正極性階調電圧線ＰＬＮ及び負極性階調電圧線ＮＬＮに対して水平方向に隣接させて配置する。この構成は、第１の実施形態（図１）に対して配置のみが異なり、第１の実施形態と等価な動作及び効果を奏する。
【００４４】
（第７の実施形態）
図８は、第７の実施形態による液晶表示装置の構成例を示す図である。液晶表示装置は、ＴＦＴ液晶パネルＰＮＬ及び液晶パネル駆動用半導体集積回路３０を有する。第５の実施形態（図６）では第２の負極性データラッチＬＴ１ｂ，ＬＴ３ｂと第１の正極性データラッチＬＴ２ａ，ＬＴ４ａとをそれぞれ垂直方向に隣接させたが、本実施形態では、第２の負極性データラッチＬＴ１ｂ，ＬＴ３ｂと第１の正極性データラッチＬＴ２ａ，ＬＴ４ａとをそれぞれ水平方向に隣接させる。
【００４５】
本実施形態の半導体集積回路３０は、第１の負極性データラッチ部ＮＬＴ、負極性セレクタ部ＮＳＥＬ、第２の負極性及び第１の正極性データラッチ部ＮＰＬＴ、正極性セレクタ部ＰＳＥＬ、第２の正極性データラッチ部ＰＬＴ、オペアンプ部ＯＰ、出力切替部ＳＷがこの順に垂直方向に並んでいる。このうち、第２の負極性及び第１の正極性データラッチ部ＮＰＬＴでは、第２の負極性データラッチＬＴ１ｂ，ＬＴ３ｂと第１の正極性データラッチＬＴ２ａ，ＬＴ４ａとがそれぞれ交互に水平方向に配列される。
【００４６】
本実施形態では、第２の負極性データラッチＮＬＴ１ｂ，ＮＬＴ３ｂと第１の正極性データラッチＰＬＴ１ａ，ＰＬＴ３ａとを、正極性階調電圧線ＰＬＮ及び負極性階調電圧線ＮＬＮに対して水平方向に隣接させて配置する。この構成は、第１の実施形態（図１）に対して配置のみが異なり、第１の実施形態と等価な動作及び効果を奏する。
【００４７】
（第８の実施形態）
図９は、第８の実施形態による液晶表示装置の構成例を示す図である。液晶表示装置は、ＴＦＴ液晶パネルＰＮＬ及び液晶パネル駆動用半導体集積回路３０を有する。半導体集積回路３０は、データラッチ部及びセレクタ部１１、オペアンプ部ＯＰ及び出力切替部ＳＷを有する。データラッチ部及びセレクタ部１１は、第１〜第７の実施形態で示したデータラッチ部及びセレクタ部のいずれかの組み合わせであってもよい。
【００４８】
オペアンプ部ＯＰは、負極性オペアンプＯＰ１，ＯＰ３と正極性オペアンプＯＰ２，ＯＰ４とを有する。負極性オペアンプＯＰ１，ＯＰ３を上段に配置し、その下に隣接して正極性オペアンプＯＰ２，ＯＰ４を配置している。
【００４９】
第１〜第８の実施形態では、負極性オペアンプＯＰ１，ＯＰ３と正極性オペアンプＯＰ２，ＯＰ４とを、正極性階調電圧線ＰＬＮ及び負極性階調電圧線ＮＬＮに対して垂直方向に隣接させて配置する。この構成は、第１の実施形態と等価な動作及び効果を奏する。
【００５０】
（第９の実施形態）
図１０は、第９の実施形態による液晶表示装置の構成例を示す図である。液晶表示装置は、ＴＦＴ液晶パネルＰＮＬ及び液晶パネル駆動用半導体集積回路３０を有する。第８の実施形態（図９）では負極性オペアンプＯＰ１，ＯＰ３と正極性オペアンプＯＰ２，ＯＰ４とを垂直方向に隣接させて配置したが、本実施形態では、負極性オペアンプＯＰ１，ＯＰ３と正極性オペアンプＯＰ２，ＯＰ４とをそれぞれ水平方向に交互に隣接させて配置する。
【００５１】
本実施形態では、正極性オペアンプＯＰ２，ＯＰ４と負極性オペアンプＯＰ１，ＯＰ３とを、正極性階調電圧線ＰＬＮ及び負極性階調電圧線ＮＬＮに対して水平方向に隣接させて配置する。この構成は、第１の実施形態と等価な動作及び効果を奏する。
【００５２】
（第１０の実施形態）
図１１（Ａ）は、上記の第１〜第９の実施形態の液晶パネル駆動用半導体集積回路（液晶ドライバ）３０の配置例を示す平面図である。半導体集積回路３０は、データラッチ部及びセレクタ部を有する領域３０ａと、オペアンプ部及び出力切替部を有する領域３０ｂとを有する。
【００５３】
本実施形態では、正極性及び負極性データラッチ並びに正極性及び負極性セレクタの領域３０ａを、正極性及び負極性オペアンプ並びに出力切替部の領域３０ｂの片側のみに隣接するように配置する。
【００５４】
図１１（Ｂ）は、第１０の実施形態による液晶パネル駆動用半導体集積回路（液晶ドライバ）３０の配置例を示す平面図である。本実施形態は、第１０の実施形態（図１１）のデータラッチ部及びセレクタ部の領域３０ａを、第１のデータラッチ部及びセレクタ部の領域３１ａと第２のデータラッチ部及びセレクタ部の領域３１ｂとに分割する。オペアンプ部及び出力切替部の領域３０ｂを間に挟んで、第１のデータラッチ部及びセレクタ部の領域３１ａと第２のデータラッチ部及びセレクタ部の領域３１ｂとを領域３０ｂの両側に隣接して配置する。
【００５５】
本実施形態では、正極性及び負極性データラッチ並びに正極性及び負極性セレクタの領域３１ａ，３１ｂを、正極性及び負極性オペアンプ並びに出力切替部の領域３０ｂの両側に隣接するように配置する。この構成は、第１の実施形態と等価な動作及び効果を奏する。
【００５６】
また、本実施形態では、オペアンプ部及び出力切替部の領域３０ｂが半導体集積回路３０の中央部に配置され、出力切替部ＳＷの出力端子を有する領域３０ｂにボンディングパッドを設けることができるので、フリップチップを形成しやすい。すなわち、通常のデュアルライン型ＩＣ等を形成する場合にはボンディングパッドを半導体集積回路３０の端に設けることが好ましいが、フリップチップを形成する場合には半導体集積回路３０の中央部にボンディングパッドを設け、リードフレームを使わずに、ＴＡＢ等により直接配線することにより、パッケージサイズを小さくすることができる。
【００５７】
以上詳しく説明したように、第１〜第１０の実施形態では、正極性の組と負極性の組とを水平方向に並列に配列するので、半導体集積回路３０の水平方向の長さは、図１２の半導体集積回路４０の水平方向の長さの１／２になり、半導体集積回路３０の面積を小さくすることができる。
【００５８】
また、図１２の半導体集積回路４０では、未使用領域（図上の斜線領域）２が生じていたが、本実施形態の半導体集積回路３０ではそのような未使用領域がなくなり、負極性セレクタ部ＮＳＥＬ及び正極性セレクタ部ＰＳＥＬの配線を効率的にレイアウトすることができ、全体として、半導体集積回路３０の面積を小さくすることができる。
【００５９】
また、図１２の半導体集積回路４０では、異なるチャネルタイプのセレクタＳＥＬ間の距離をある程度以上は広げなければならなかったが、本実施形態の半導体集積回路３０では水平方向に隣接するセレクタは同じチャネルタイプのトランジスタを用いているため、水平方向に隣接するセレクタ間の距離を短くすることができ、半導体集積回路３０の面積をより小さくすることができる。
【００６０】
なお、上記実施例は、何れも本発明を実施するにあたっての具体化のほんの一例を示したものに過ぎず、これらによって本発明の技術的範囲が限定的に解釈されてはならないものである。すなわち、本発明はその精神、またはその主要な特徴から逸脱することなく、様々な形で実施することができる。
【００６１】
本発明の様々な形態をまとめると、以下のようになる。
（付記１）外部から入力されるｎビットのデジタル画像データを保持するデータラッチと、各階調のアナログ階調電圧が生じる階調電圧線が直上に配置され、前記データラッチが保持したｎビットのデジタル画像データに応じていずれかのアナログ階調電圧を選択するセレクタとに関して、
同一極性の階調電圧線のみが直上に配置されたセレクタを組とし、正極性の組と負極性の組とを前記階調電圧線に対して垂直方向に並べて配置したことを特徴とする液晶パネル駆動用半導体集積回路。
（付記２）外部から入力されるｎビットのデジタル画像データを保持するデータラッチと、
各階調の正極性のアナログ階調電圧を正極性階調電圧線上に発生させる正極性階調電圧発生部と、
各階調の負極性のアナログ階調電圧を負極性階調電圧線上に発生させる負極性階調電圧発生部と、
直上に前記負極性階調電圧線が配置されずに前記正極性階調電圧線が配置され、前記データラッチが保持したｎビットのデジタル画像データに応じて、前記正極性階調電圧発生部により発生させられる各階調の正極性のアナログ階調電圧を選択する正極性セレクタと、
直上に前記正極性階調電圧線が配置されずに前記負極性階調電圧線が配置され、前記データラッチが保持したｎビットのデジタル画像データに応じて、前記負極性階調電圧発生部により発生させられる各階調の負極性のアナログ階調電圧を選択する負極性セレクタと、
前記正極性セレクタ及び前記負極性セレクタにより選択された正極性アナログ階調電圧及び負極性アナログ階調電圧を増幅して出力するオペアンプと、
前記オペアンプにより出力される正極性アナログ階調電圧及び負極性アナログ階調電圧の信号経路をストレート又はクロスに切り替えて液晶パネルに出力する出力切替部とを備えたことを特徴とする液晶パネル駆動用半導体集積回路。
【００６２】
（付記３）前記データラッチは、正極性のアナログ階調電圧を発生させるためのデジタル画像データを保持する正極性データラッチと、負極性のアナログ階調電圧を発生させるためのデジタル画像データを保持する負極性データラッチとを含み、
前記正極性セレクタは、前記正極性データラッチが保持したデジタル画像データに応じて前記正極性のアナログ階調電圧を選択し、
前記負極性セレクタは、前記負極性データラッチが保持したデジタル画像データに応じて前記負極性のアナログ階調電圧を選択し、
前記オペアンプは、前記正極性セレクタにより選択された正極性アナログ階調電圧を増幅して出力する正極性オペアンプと、前記負極性セレクタにより選択された負極性アナログ階調電圧を増幅して出力する負極性オペアンプとを含むことを特徴とする付記２記載の液晶パネル駆動用半導体集積回路。
（付記４）前記正極性セレクタはＰチャネルの転送ゲートにより構成され、前記負極性セレクタはＮチャネルの転送ゲートにより構成されていることを特徴とする付記２記載の液晶パネル駆動用半導体集積回路。
【００６３】
（付記５）前記正極性データラッチ及び前記正極性セレクタを一組として前記正極性階調電圧線に対して水平方向に複数並べ、前記負極性データラッチ及び前記負極性セレクタを一組として前記負極性階調電圧線に対して水平方向に複数並べて配置したことを特徴とする付記３記載の液晶パネル駆動用半導体集積回路。
（付記６）前記正極性セレクタ及び前記正極性データラッチを正極性の組とし、前記負極性セレクタ及び前記負極性データラッチを負極性の組として、前記正極性データラッチと前記負極性データラッチとが隣接するように前記正極性の組及び前記負極性の組を配置してこれを一組とし、前記正極性階調電圧線及び前記負極性階調電圧線に対して水平方向に複数組並べて配置したことを特徴とする付記３記載の液晶パネル駆動用半導体集積回路。
【００６４】
（付記７）前記正極性データラッチと前記負極性データラッチとを、前記正極性階調電圧線及び前記負極性階調電圧線に対して垂直方向に隣接させて配置したことを特徴とする付記６記載の液晶パネル駆動用半導体集積回路。
（付記８）前記正極性データラッチと前記負極性データラッチとを、前記正極性階調電圧線及び前記負極性階調電圧線に対して水平方向に隣接させて配置したことを特徴とする付記６記載の液晶パネル駆動用半導体集積回路。
【００６５】
（付記９）前記正極性セレクタ及び前記正極性データラッチを正極性の組とし、前記負極性セレクタ及び前記負極性データラッチを負極性の組として、前記正極性セレクタと前記負極性セレクタとが隣接するように前記正極性の組及び前記負極性の組を配置してこれを一組とし、前記正極性階調電圧線及び前記負極性階調電圧線に対して水平方向に複数組並べて配置したことを特徴とする付記３記載の液晶パネル駆動用半導体集積回路。
（付記１０）前記正極性セレクタ及び前記正極性データラッチを正極性の組とし、前記負極性セレクタ及び前記負極性データラッチを負極性の組として、前記正極性及び負極性の異なる組のセレクタとデータラッチとが隣接するように前記正極性の組及び前記負極性の組を配置してこれを一組とし、前記正極性階調電圧線及び前記負極性階調電圧線に対して水平方向に複数組並べて配置したことを特徴とする付記３記載の液晶パネル駆動用半導体集積回路。
【００６６】
（付記１１）前記正極性セレクタは第１の正極性セレクタ部と第２の正極性セレクタ部とを有し、前記負極性セレクタは第１の負極性セレクタ部と第２の負極性セレクタ部とを有し、
前記正極性データラッチを前記第１及び第２の正極性セレクタ部の間に挟んだものを正極性の組とし、前記負極性データラッチを前記第１及び第２の負極性セレクタ部の間に挟んだものを負極性の組とし、前記正極性の組と前記負極性の組とを配置してこれを一組とし、前記正極性階調電圧線及び前記負極性階調電圧線に対して水平方向に複数組並べて配置したことを特徴とする付記３記載の液晶パネル駆動用半導体集積回路。
（付記１２）前記第２の正極性セレクタ部と前記第１の負極性セレクタ部とが隣接するように前記正極性の組と前記負極性の組とを配置してこれを一組とし、前記正極性階調電圧線及び前記負極性階調電圧線に対して水平方向に複数組並べて配置したことを特徴とする付記１１記載の液晶パネル駆動用半導体集積回路。
【００６７】
（付記１３）前記正極性データラッチは第１の正極性データラッチ部と第２の正極性データラッチ部とを有し、前記負極性データラッチは第１の負極性データラッチ部と第２の負極性データラッチ部とを有し、
前記正極性セレクタを前記第１及び第２の正極性データラッチ部の間に挟んだものを正極性の組とし、前記負極性セレクタを前記第１及び第２の負極性データラッチ部の間に挟んだものを負極性の組とし、前記正極性の組と前記負極性の組とを配置してこれを一組とし、前記正極性階調電圧線及び前記負極性階調電圧線に対して水平方向に複数組並べて配置したことを特徴とする付記３記載の液晶パネル駆動用半導体集積回路。
（付記１４）前記第２の正極性データラッチ部と前記第１の負極性データラッチ部とが隣接するように前記正極性の組と前記負極性の組とを配置してこれを一組とし、前記正極性階調電圧線及び前記負極性階調電圧線に対して水平方向に複数組並べて配置したことを特徴とする付記１３記載の液晶パネル駆動用半導体集積回路。
【００６８】
（付記１５）前記第２の正極性データラッチ部と前記第１の負極性データラッチ部とを、前記正極性階調電圧線及び前記負極性階調電圧線に対して垂直方向に隣接させて配置したことを特徴とする付記１３記載の液晶パネル駆動用半導体集積回路。
（付記１６）前記第２の正極性データラッチ部と前記第１の負極性データラッチ部とを、前記正極性階調電圧線及び前記負極性階調電圧線に対して水平方向に隣接させて配置したことを特徴とする付記１３記載の液晶パネル駆動用半導体集積回路。
【００６９】
（付記１７）前記正極性オペアンプと前記負極性オペアンプとを、前記正極性階調電圧線及び前記負極性階調電圧線に対して垂直方向に隣接させて配置したことを特徴とする付記３記載の液晶パネル駆動用半導体集積回路。
（付記１８）前記正極性オペアンプと前記負極性オペアンプとを、前記正極性階調電圧線及び前記負極性階調電圧線に対して水平方向に隣接させて配置したことを特徴とする付記３記載の液晶パネル駆動用半導体集積回路。
【００７０】
（付記１９）前記正極性及び負極性データラッチ並びに前記正極性及び負極性セレクタの領域を、前記正極性及び負極性オペアンプ並びに出力切替部の領域の片側のみに隣接するように配置したことを特徴とする付記３記載の液晶パネル駆動用半導体集積回路。
（付記２０）前記正極性及び負極性データラッチ並びに前記正極性及び負極性セレクタの領域を、前記正極性及び負極性オペアンプ並びに出力切替部の領域の両側に隣接するように配置したことを特徴とする付記３記載の液晶パネル駆動用半導体集積回路。
【００７１】
【発明の効果】
以上説明したように本発明によれば、階調電圧線に対して水平方向の長さを大幅に短くすることができ、全体として液晶パネル駆動用半導体集積回路の面積を小さくすることができる。
【図面の簡単な説明】
【図１】第１の実施形態による液晶表示装置の構成例を示す図である。
【図２】階調電圧発生部及びセレクタの構成例を示す回路図である。
【図３】第２の実施形態による液晶表示装置の構成例を示す図である。
【図４】第３の実施形態による液晶表示装置の構成例を示す図である。
【図５】第４の実施形態による液晶表示装置の構成例を示す図である。
【図６】第５の実施形態による液晶表示装置の構成例を示す図である。
【図７】第６の実施形態による液晶表示装置の構成例を示す図である。
【図８】第７の実施形態による液晶表示装置の構成例を示す図である。
【図９】第８の実施形態による液晶表示装置の構成例を示す図である。
【図１０】第９の実施形態による液晶表示装置の構成例を示す図である。
【図１１】第１０の実施形態による液晶パネル駆動用半導体集積回路の構成例を示す平面図である。
【図１２】従来技術による液晶表示装置の構成例を示す図である。
【符号の説明】
１配線コンタクト部
２未使用領域
５階調電圧発生部
６ラダー抵抗
１１データラッチ部及びセレクタ部
３０，４０液晶パネル駆動用半導体集積回路
Ｔｒトランジスタ
ＳＥＬセレクタ部
ＮＳＥＬ負極性セレクタ部
ＰＳＥＬ正極性セレクタ部
ＬＮ階調電圧線
ＮＬＮ負極性階調電圧線
ＰＬＮ正極性階調電圧線
ＬＴデータラッチ部
ＮＬＴ負極性データラッチ部
ＰＬＴ正極性データラッチ部
ＯＰオペアンプ部
ＳＷ出力切替部
ＰＮＬＴＦＴ液晶パネル[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit for driving a liquid crystal panel, and more particularly to a semiconductor integrated circuit for driving a liquid crystal panel that outputs an analog gradation voltage to a liquid crystal panel based on digital image data.
[0002]
[Prior art]
FIG. 12 is a configuration diagram of a conventional liquid crystal display device. The liquid crystal display device includes a TFT liquid crystal panel PNL and a liquid crystal panel driving semiconductor integrated circuit 40. The semiconductor integrated circuit 40 includes a data latch unit LT, a selector unit SEL, an operational amplifier unit OP, and an output switching unit SW. In the data latch part LT, 2 × m data latches LT1 to LT4 are arranged in the horizontal direction. In the selector unit SEL, 2 × m selectors SEL1 to SEL4 are arranged in the horizontal direction. In the operational amplifier section OP, 2 × m operational amplifiers OP1 to OP4 are arranged in the horizontal direction. In the output switching unit SW, m output switching units SW1 and SW2 are arranged in the horizontal direction.
[0003]
For example, in the case of 384 outputs, the semiconductor integrated circuit 40 has a numerical value m of 192. In FIG. 12, the number in the horizontal direction is reduced to simplify the drawing.
[0004]
The data latch line LT is connected to the data latch part LT at the wiring contact part 1 (indicated by a black circle), and the negative data latches LT1 and LT3 and the positive data latches LT2 and LT4 are alternately horizontal. 2 × m are arranged in the direction. The negative data latches LT1 and LT3 input and hold n-bit (6 bits in the case of 64 gradations) digital image data for generating a negative analog gradation voltage of a predetermined gradation from the outside. The positive data latches LT2 and LT4 receive and hold n-bit digital image data for generating a positive analog gradation voltage of a predetermined gradation from the outside.
[0005]
In the selector unit SEL, 2 × m negative selectors SEL1 and SEL3 and positive selectors SEL2 and SEL4 are alternately arranged in the horizontal direction. Negative polarity selectors SEL1, SEL3 are constituted by N channel MOS transistors, and positive polarity selectors SEL2, SEL4 are constituted by P channel MOS transistors. For example, in the case of 64 gradations, 64 × 2 positive and negative gradation voltage lines LN are arranged immediately above the selectors SEL1 to SEL4. The negative polarity selectors SEL1 and SEL3 are connected to 64 negative polarity gradation voltage lines LN at the wiring contact portion 1, and the positive polarity selectors SEL1 and SEL3 are connected to 64 positive polarity gradation voltage lines LN at the wiring contact portion 1. Connected with.
[0006]
The negative selectors SEL1 and SEL3 correspond to the digital image data held by the data latches LT1 and LT3 based on the negative analog gradation voltage generated on the negative gradation voltage line LN, for example, from 6V to 0V. To select a negative analog gradation voltage having a predetermined gradation. The positive selectors SEL2 and SEL4 correspond to the digital image data held by the data latches LT2 and LT4 based on the positive analog gradation voltage from 6 V to 12 V, for example, generated on the positive gradation voltage line LN. The positive polarity analog gradation voltage of a predetermined gradation is selected.
[0007]
In the operational amplifier OP, 2 × m negative operational amplifiers OP1 and OP3 and positive operational amplifiers OP2 and OP4 are alternately arranged in the horizontal direction. The negative operational amplifiers OP1 and OP3 amplify and output the negative analog gradation voltage selected by the negative selectors SEL1 and SEL3. The positive operational amplifiers OP2 and OP4 amplify and output the positive analog gradation voltage selected by the positive selectors SEL2 and SEL4.
[0008]
In the output switching unit SW, m output switching units SW1 and SW2 are arranged in the horizontal direction. The output switching unit SW1 switches the signal path of the negative polarity analog gradation voltage output from the negative polarity operational amplifier OP1 and the positive polarity analog gradation voltage output from the positive polarity operational amplifier OP2 to straight or cross and outputs it to the liquid crystal panel PNL. To do. The output switching unit SW2 switches the signal path of the negative analog gradation voltage output from the negative operational amplifier OP3 and the positive analog gradation voltage output from the positive operational amplifier OP4 to straight or cross and outputs it to the liquid crystal panel PNL. To do. The liquid crystal panel PNL performs liquid crystal display on each pixel composed of three colors of red, green, and blue with a predetermined gradation voltage for each color.
[0009]
[Problems to be solved by the invention]
In the semiconductor integrated circuit 40, since the columns of the data latch unit LT, the selector unit SEL, and the operational amplifier unit OP arranged in the vertical direction are repeatedly arranged in 2 × m sets (for example, 384 sets) in the horizontal direction, the rectangle 24 has a long horizontal length 24. The semiconductor integrated circuit 40 is formed. For example, the horizontal length 24 is about 15 mm and the vertical length is about 2 mm. Since the semiconductor integrated circuit 40 has a relatively large area, development of the semiconductor integrated circuit 40 having a smaller area is desired. In particular, it is desired to shorten the length of the semiconductor integrated circuit 40 in the horizontal direction.
[0010]
Further, immediately above the negative polarity selectors SEL1, SEL3, the negative polarity gradation voltage line LN is connected to the negative polarity selectors SEL1, SEL3 in the wiring contact portion 1, but the positive polarity gradation voltage line LN is connected to the negative polarity selector SEL1. , SEL3 are not connected, and the area (shaded area in the figure) is wasted as the unused area 2. Similarly, a wasteful unused area 2 is also generated in the positive selectors SEL2 and SEL4.
[0011]
Since the negative selectors SEL1 and SEL3 composed of N-channel MOS transistors and the positive selectors SEL2 and SEL4 composed of P-channel MOS transistors are alternately arranged, the distance 23 between the selectors of different channel types can be set as follows. The horizontal length 24 of the semiconductor integrated circuit 40 must be increased more than necessary.
[0012]
An object of the present invention is to enable a liquid crystal panel driving semiconductor integrated circuit to be configured with a small area.
[0013]
[Means for Solving the Problems]
The semiconductor integrated circuit for driving a liquid crystal panel of the present invention comprises:A data latch that holds n-bit digital image data input from the outside, a positive gradation voltage generator that generates a positive analog gradation voltage of each gradation on the positive gradation voltage line, A negative gradation voltage generating unit for generating a negative analog gradation voltage on the negative gradation voltage line; and the positive gradation voltage line is disposed without the negative gradation voltage line being disposed immediately above. A positive polarity selector that selects a positive analog gradation voltage of each gradation generated by the positive gradation voltage generator in accordance with n-bit digital image data held by the data latch; The negative gradation voltage line is arranged without the positive gradation voltage line, and is generated by the negative gradation voltage generator according to the n-bit digital image data held by the data latch. A negative selector that selects a negative analog gradation voltage of each gradation, and a positive analog gradation voltage and a negative analog gradation voltage selected by the positive selector and the negative selector are amplified and output. An operational amplifier, and an output switching unit that switches a signal path of the positive analog gradation voltage and the negative analog gradation voltage output by the operational amplifier to straight or cross and outputs the signal path to the liquid crystal panel. A positive polarity data latch for holding digital image data for generating a negative analog gradation voltage, and a negative polarity data latch for holding digital image data for generating a negative polarity analog gradation voltage, The positive selector selects the positive polarity according to the digital image data held by the positive data latch. The negative polarity selector selects the negative polarity analog gradation voltage according to the digital image data held by the negative polarity data latch, and the operational amplifier is selected by the positive polarity selector. A positive polarity operational amplifier that amplifies and outputs the positive polarity analog grayscale voltage, and a negative polarity operational amplifier that amplifies and outputs the negative polarity analog grayscale voltage selected by the negative polarity selector. A plurality of latches and positive polarity selectors are arranged horizontally in the horizontal direction with respect to the positive polarity gradation voltage line, and the negative polarity data latch and negative polarity selector are set as a set to the negative polarity gradation voltage line. It is characterized by being arranged in a row in the horizontal direction.
[0014]
Since the present invention comprises the above technical means, it is only necessary that the gradation voltage lines arranged immediately above the selector have the same polarity, and it is possible to eliminate the unused area of the selector. In addition, since different types of selectors do not have to be alternately arranged, it is possible to arrange the same type of transistors together, and to shorten the element spacing.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of the liquid crystal display device according to the first embodiment. The liquid crystal display device includes a TFT liquid crystal panel PNL and a liquid crystal panel driving semiconductor integrated circuit 30. The semiconductor integrated circuit 30 includes a negative selector unit (N channel selector unit) NSEL, a data latch unit LT, a positive selector unit (P channel selector unit) PSEL, an operational amplifier unit OP, and an output switching unit SW. In the present embodiment, the selector unit SEL of FIG. 12 is divided into a negative polarity selector unit NSEL and a positive polarity selector unit PSEL. The TFT liquid crystal panel PNL is the same as that shown in FIG.
[0016]
A data latch line arranged immediately above the data latch part LT is connected by a wiring contact part 1 (indicated by a black circle). In the data latch unit LT, m negative polarity data latches LT1 and LT3 are arranged in the horizontal direction in the upper stage, and m positive polarity data latches LT2 and LT4 are arranged in the horizontal direction adjacent to the lower stage. The negative data latches LT1 and LT3 input and hold n-bit (6 bits in the case of 64 gradations) digital image data for generating a negative analog gradation voltage of a predetermined gradation from the outside. The positive data latches LT2 and LT4 receive and hold n-bit digital image data for generating a positive analog gradation voltage of a predetermined gradation from the outside.
[0017]
The negative selector NSEL is composed of an N-channel MOS transistor (transfer gate), and m negative selectors SEL1, SEL3 are arranged in the horizontal direction. Immediately above the negative selectors SEL1, SEL3, m / 3 (for example, 64) negative polarity gradation voltage lines NLN are arranged side by side in the vertical direction so as to extend in the horizontal direction. M / 3 negative gradation voltage lines NLN are connected to the SEL 3 by wiring contact portions 1.
[0018]
The negative selectors SEL1 and SEL3 are connected to the negative polarity data latches LT1 and LT3 via the signal line 3 based on the negative polarity analog gradation voltage generated on the negative polarity gradation voltage line NLN, for example, from 6V to 0V. The negative analog gradation voltage indicating a predetermined gradation is selected according to the supplied digital image data, and is supplied to the operational amplifier unit OP via the signal line 4.
[0019]
FIG. 2 is a circuit diagram of the negative polarity selector (N channel selector) SEL1 and the gradation voltage generator 5 connected thereto. Terminal V of the gradation voltage generator 5₊For example, 6V is applied to the terminal V_-For example, 0V is applied. Terminal V₊And terminal V_-Between these, a ladder resistor 6 is connected. In order to divide the ladder resistor 6, m / 3 (for example, 64) negative polarity gradation voltage lines NLN are connected to the ladder resistor 6, and for example, negative electrodes for 64 gradations between 6V and 0V. An analog gradation voltage is generated.
[0020]
In the case of 64 gradations (6 bits), six N-channel MOS transistors (transfer gates) Tr are connected in series to each negative gradation voltage line NLN. The N-channel MOS transistor Tr is arranged as a two-dimensional matrix of 6 rows and 64 columns, and the signal line 3 from the negative data latch LT1 (FIG. 1) is connected to the gate of each transistor Tr. According to the digital image data supplied to the signal line 3, any one of the 64 negative gradation voltage lines NLN is selected and an analog gradation voltage having a predetermined gradation is supplied via the signal line 4. Is output to the negative operational amplifier OP1 (FIG. 1). The configuration of the negative selector SEL3 is the same as the configuration of the negative selector SEL1.
[0021]
Returning to FIG. 1, the positive polarity selector unit PSEL is composed of a P-channel MOS transistor (transfer gate), and m positive polarity selectors SEL2 and SEL4 are arranged in the horizontal direction. Immediately above the positive polarity selectors SEL2 and SEL4, m / 3 (for example, 64) positive polarity gradation voltage lines PLN are arranged in the vertical direction so as to extend in the horizontal direction. M / 3 positive gradation voltage lines PLN are connected to the SEL 4 by wiring contact portions 1.
[0022]
The positive selectors SEL2 and SEL4 are digital image data held by the positive data latches LT2 and LT4 based on a positive analog gradation voltage of, for example, 6V to 12V generated on the positive gradation voltage line PLN. A positive polarity analog gradation voltage showing a predetermined gradation is selected according to the above. The positive polarity selectors SEL2 and SEL4 and the gradation voltage generator connected to them are the same as those shown in FIG. 2, but the transistor Tr is constituted by the P channel instead of the N channel, and the terminal V_-6V is applied to the terminal V₊Is different in that 12V is applied. In this case, the gradation voltage generator 5 generates a positive gradation voltage from 6V to 12V.
[0023]
In the operational amplifier unit OP, m positive operational amplifiers OP2 and OP4 are arranged in the horizontal direction in the upper stage, and negative operational amplifiers OP1 and OP3 having negative polarity (low level side) are arranged in the horizontal direction below. M are arranged. The negative operational amplifiers OP1 and OP3 amplify and output the negative analog gradation voltage selected by the negative selectors SEL1 and SEL3. The positive operational amplifiers OP2 and OP4 amplify and output the positive analog gradation voltage selected by the positive selectors SEL2 and SEL4.
[0024]
In the output switching unit SW, m output switching units SW1 and SW2 are arranged in the horizontal direction. The output switching unit SW1 switches the signal path of the negative polarity analog gradation voltage output from the negative polarity operational amplifier OP1 and the positive polarity analog gradation voltage output from the positive polarity operational amplifier OP2 to straight or cross and outputs it to the liquid crystal panel PNL. To do. The output switching unit SW2 switches the signal path of the negative analog gradation voltage output from the negative operational amplifier OP3 and the positive analog gradation voltage output from the positive operational amplifier OP4 to straight or cross and outputs it to the liquid crystal panel PNL. To do. The liquid crystal panel PNL performs liquid crystal display on each pixel composed of three colors of red, green, and blue with a predetermined gradation voltage for each color.
[0025]
In this embodiment, the positive polarity selectors SEL2 and SEL4 and the positive polarity data latches LT2 and LT4 are set as a positive polarity group, and the negative polarity selectors SEL1 and SEL3 and the negative polarity data latches LT1 and LT3 are set as a negative polarity set. The positive polarity group and the negative polarity group are arranged such that the latches LT2 and LT4 and the negative polarity data latches LT1 and LT3 are adjacent to the positive polarity gradation voltage line PLN and the negative polarity gradation voltage line NLN in the vertical direction. Arrange on the same straight line. Then, a plurality of sets arranged in a straight line in the vertical direction are arranged in a horizontal direction with respect to the positive gradation voltage line PLN and the negative gradation voltage line NLN.
[0026]
Thereby, in the semiconductor integrated circuit 30, m rows (for example, 192 sets) of columns arranged in the vertical direction of the negative polarity selector unit NSEL, the data latch unit LT, the positive polarity selector unit PSEL, and the operational amplifier unit OP are repeatedly arranged in the horizontal direction. The semiconductor integrated circuit 40 shown in FIG. 12 has 2 × m sets (for example, 384 sets) arranged in the horizontal direction, but the semiconductor integrated circuit 30 of the present embodiment has m sets (for example, 192 sets) arranged in the horizontal direction. The length 22 in the horizontal direction is about ½ that shown in FIG. That is, the horizontal length 22 of the present embodiment is about ½ of the horizontal length 24 of FIG. 12, and the area of the semiconductor integrated circuit 30 can be reduced. Note that the length of the semiconductor integrated circuit 30 in the vertical direction is almost the same as that of FIG.
[0027]
Further, in the semiconductor integrated circuit 40 of FIG. 12, there is an unused region (shaded region in the drawing) 2 in which the gradation voltage line LN arranged immediately above the selector unit SEL is not connected to the selector unit SEL. In the semiconductor integrated circuit 30 of the present embodiment, such unused areas are eliminated, and the wiring of the negative polarity selector unit NSEL and the positive polarity selector unit PSEL can be efficiently laid out. The area can be reduced.
[0028]
In the semiconductor integrated circuit 40 of FIG. 12, the distance 23 between the different channel type selectors SEL has to be increased to some extent, but in this embodiment, the negative polarity selectors SEL1 and SEL3 are the same N channel type transistors. Therefore, the distance 21 between the selectors SEL1 and SEL3 can be shortened. Similarly, since the positive polarity selectors SEL2 and SEL4 also use the same P-channel type transistor, the distance between the selectors SEL2 and SEL4 can be shortened, so that the area of the semiconductor integrated circuit 30 can be further reduced. it can.
[0029]
(Second Embodiment)
FIG. 3 is a diagram illustrating a configuration example of the liquid crystal display device according to the second embodiment. The liquid crystal display device includes a TFT liquid crystal panel PNL and a liquid crystal panel driving semiconductor integrated circuit 30. Compared with the first embodiment (FIG. 1), the present embodiment reverses the vertical positions of the negative selector unit NSEL and the upper stage of the data latch unit LT, and the positive selector unit PSEL and the data latch unit LT. The up and down position with respect to the lower stage is reversed.
[0030]
In the semiconductor integrated circuit 30 of the present embodiment, the negative polarity data latch unit NLT, the negative polarity selector unit NSEL, the positive polarity selector unit PSEL, the positive polarity data latch unit PLT, the operational amplifier unit OP, and the output switching unit SW are arranged in this order in the vertical direction. Are lined up. In the negative polarity data latch unit NLT, m negative polarity data latches LT1 and LT3 are arranged in the horizontal direction, and in the positive polarity data latch portion PLT, m positive polarity data latches LT2 and LT4 are arranged in the horizontal direction.
[0031]
In the present embodiment, the positive polarity selector PSEL and the positive polarity data latch PLT are a positive polarity group, the negative polarity selector NSEL and the negative polarity data latch NLT are a negative polarity group, and the positive polarity selector PSEL and the negative polarity selector NSEL are The positive polarity group and the negative polarity group are arranged on a straight line so as to be adjacent to the gradation voltage lines NLN and PLN in the vertical direction. Then, a plurality of sets are arranged in the horizontal direction with respect to the positive polarity gradation voltage line PLN and the negative polarity gradation voltage line NLN as a set of configurations arranged on a straight line in the vertical direction. This configuration differs from the first embodiment (FIG. 1) only in arrangement, and provides operations and effects equivalent to those of the first embodiment.
[0032]
(Third embodiment)
FIG. 4 is a diagram illustrating a configuration example of the liquid crystal display device according to the third embodiment. The liquid crystal display device includes a TFT liquid crystal panel PNL and a liquid crystal panel driving semiconductor integrated circuit 30. In the present embodiment, the vertical positions of the positive polarity selector unit PSEL and the positive polarity data latch unit PLT are reversed as compared with the second embodiment (FIG. 3).
[0033]
In the semiconductor integrated circuit 30 of this embodiment, the negative polarity data latch unit NLT, the negative polarity selector unit NSEL, the positive polarity data latch unit PLT, the positive polarity selector unit PSEL, the operational amplifier unit OP, and the output switching unit SW are arranged in this order in the vertical direction. Are lined up.
[0034]
In the present embodiment, the positive selector PSEL and the positive data latch PLT are set to a positive polarity, the negative selector NSEL and the negative data latch NLT are set to a negative polarity, and the selectors SEL1 having different positive polarity and negative polarity are used. , SEL3 and the data latches LT2 and LT4 are arranged in a straight line so that the positive polarity group and the negative polarity group are adjacent to each other in the vertical direction. Then, a plurality of sets arranged in a straight line in the vertical direction are arranged in a horizontal direction with respect to the positive gradation voltage line PLN and the negative gradation voltage line NLN. This configuration differs from the first embodiment (FIG. 1) only in arrangement, and provides operations and effects equivalent to those of the first embodiment.
[0035]
(Fourth embodiment)
FIG. 5 is a diagram illustrating a configuration example of the liquid crystal display device according to the fourth embodiment. The liquid crystal display device includes a TFT liquid crystal panel PNL and a liquid crystal panel driving semiconductor integrated circuit 30. In this embodiment, the negative polarity selector unit NSEL is divided into a first negative polarity selector unit NSELa and a second negative polarity selector unit NSELb, and the positive polarity selector unit PSEL is compared with the second embodiment (FIG. 3). Is different from the first positive selector section PSELa and the second positive selector section PSELb. For example, the selector is divided in half in the order of gradation values.
[0036]
The semiconductor integrated circuit 30 of the present embodiment includes a first negative selector unit NSELa, a negative data latch unit NLT, a second negative selector unit NSELb, a first positive selector unit PSELa, and a positive data latch unit PLT. The second positive selector PSELb, the operational amplifier OP, and the output switching unit SW are arranged in this order in the vertical direction. The first negative selector section NSELa and the second negative selector section NSELb are arranged in the vertical direction so as to sandwich the negative data latch section NLT therebetween. The first positive polarity selector unit PSELa and the second positive polarity selector unit PSELb are arranged in the vertical direction so as to sandwich the positive polarity data latch unit PLT therebetween.
[0037]
In the present embodiment, the positive data latch PLT sandwiched between the first and second positive selectors PSELa and PSELb is used as a positive set, and the negative data latch NLT is used as the first and second negative electrodes. The pair sandwiched between the polarity selectors NSELa and NSELb is set as a negative polarity group, and the positive polarity group and the negative polarity group are arranged on the same vertical line. A plurality of sets arranged on the same line in the vertical direction are arranged in a horizontal direction with respect to the positive polarity gradation voltage line PLN and the negative polarity gradation voltage line NLN. At this time, the positive polarity group and the negative polarity group are arranged so that the second negative polarity selector unit NSELb and the first positive polarity selector unit PSELa are adjacent to each other in the vertical direction. This configuration differs from the first embodiment (FIG. 1) only in arrangement, and provides operations and effects equivalent to those of the first embodiment.
[0038]
(Fifth embodiment)
FIG. 6 is a diagram illustrating a configuration example of the liquid crystal display device according to the fifth embodiment. The liquid crystal display device includes a TFT liquid crystal panel PNL and a liquid crystal panel driving semiconductor integrated circuit 30. The present embodiment divides the upper part of the data latch unit LT into the first negative data latch unit NLTa and the second negative data latch unit NLTb, as compared to the first embodiment (FIG. 1). The difference is that the lower part of the data latch part LT is divided into a first positive data latch part PLTa and a second positive data latch part PLTb. For example, the data latch is divided in half in the order of digital image data (n-bit signal). The data latches NLTa, NLTb, PLTa, and PLTb are each halved in area by the above division.
[0039]
The semiconductor integrated circuit 30 according to this embodiment includes a first negative data latch unit NLTa, a negative selector unit NSEL, a second negative data latch unit NLTb, a first positive data latch unit PLTa, and a positive selector unit. The PSEL, the second positive data latch unit PLTb, the operational amplifier unit OP, and the output switching unit SW are arranged in this order in the vertical direction. The first negative data latch unit NLTa and the second negative data latch unit NLTb are arranged in the vertical direction with the negative selector unit NSEL interposed therebetween. The first positive data latch unit PLTa and the second positive data latch unit PLTb are arranged in the vertical direction so as to sandwich the positive selector unit PSEL therebetween.
[0040]
In the present embodiment, a positive polarity selector PSEL sandwiched between the first and second positive polarity data latch portions PLTa and PLTb is used as a positive polarity set, and the negative polarity selector NSEL is set as the first and second negative polarity selectors. The negative data sets are sandwiched between the positive data latch portions NLTa and NLTb, and the positive and negative sets are arranged on the same straight line in the vertical direction. A plurality of sets arranged on the same straight line in the vertical direction are arranged in a horizontal direction with respect to the positive gradation voltage line PLN and the negative gradation voltage line NLN. At that time, a set in which the positive polarity group and the negative polarity group are arranged so that the second negative polarity data latch unit NLTb and the first positive polarity data latch unit PLTa are adjacent in the vertical direction is set as one set. . This configuration differs from the first embodiment (FIG. 1) only in arrangement, and provides operations and effects equivalent to those of the first embodiment.
[0041]
(Sixth embodiment)
FIG. 7 is a diagram illustrating a configuration example of the liquid crystal display device according to the sixth embodiment. The liquid crystal display device includes a TFT liquid crystal panel PNL and a liquid crystal panel driving semiconductor integrated circuit 30. In the first embodiment (FIG. 1), the negative polarity data latches LT1 and LT3 and the positive polarity data latches LT2 and LT4 are adjacent to each other in the vertical direction, but in this embodiment, the negative polarity data latches LT1 and LT3 and the positive polarity data latches LT2 and LT4 are adjacent to each other. The sex data latches LT2 and LT4 are adjacent to each other in the horizontal direction.
[0042]
In the semiconductor integrated circuit 30 of this embodiment, the negative selector unit NSEL, the data latch unit LT, the positive selector unit PSEL, the operational amplifier unit OP, and the output switching unit SW are arranged in this order in the vertical direction. Among these, in the data latch unit LT, the negative polarity data latches LT1 and LT3 and the positive polarity data latches LT2 and LT4 are alternately arranged in the horizontal direction.
[0043]
In the present embodiment, the negative polarity data latches LT1 and LT3 and the positive polarity data latches LT2 and LT4 are arranged adjacent to the positive polarity gradation voltage line PLN and the negative polarity gradation voltage line NLN in the horizontal direction. This configuration differs from the first embodiment (FIG. 1) only in arrangement, and provides operations and effects equivalent to those of the first embodiment.
[0044]
(Seventh embodiment)
FIG. 8 is a diagram illustrating a configuration example of the liquid crystal display device according to the seventh embodiment. The liquid crystal display device includes a TFT liquid crystal panel PNL and a liquid crystal panel driving semiconductor integrated circuit 30. In the fifth embodiment (FIG. 6), the second negative data latches LT1b and LT3b and the first positive data latches LT2a and LT4a are adjacent to each other in the vertical direction. Negative polarity data latches LT1b and LT3b and first positive polarity data latches LT2a and LT4a are adjacent to each other in the horizontal direction.
[0045]
The semiconductor integrated circuit 30 of the present embodiment includes a first negative data latch unit NLT, a negative selector unit NSEL, a second negative and first positive data latch unit NPLT, a positive selector unit PSEL, a second The positive polarity data latch unit PLT, the operational amplifier unit OP, and the output switching unit SW are arranged in the vertical direction in this order. Among these, in the second negative polarity and first positive polarity data latch unit NPLT, the second negative polarity data latches LT1b and LT3b and the first positive polarity data latches LT2a and LT4a are alternately arranged in the horizontal direction. Is done.
[0046]
In the present embodiment, the second negative data latches NLT1b and NLT3b and the first positive data latches PLT1a and PLT3a are arranged in a horizontal direction with respect to the positive polarity gradation voltage line PLN and the negative polarity gradation voltage line NNLN. Place them next to each other. This configuration differs from the first embodiment (FIG. 1) only in arrangement, and provides operations and effects equivalent to those of the first embodiment.
[0047]
(Eighth embodiment)
FIG. 9 is a diagram illustrating a configuration example of the liquid crystal display device according to the eighth embodiment. The liquid crystal display device includes a TFT liquid crystal panel PNL and a liquid crystal panel driving semiconductor integrated circuit 30. The semiconductor integrated circuit 30 includes a data latch unit and selector unit 11, an operational amplifier unit OP, and an output switching unit SW. The data latch unit and selector unit 11 may be any combination of the data latch unit and selector unit shown in the first to seventh embodiments.
[0048]
The operational amplifier OP includes negative operational amplifiers OP1 and OP3 and positive operational amplifiers OP2 and OP4. Negative operational amplifiers OP1 and OP3 are arranged in the upper stage, and positive operational amplifiers OP2 and OP4 are arranged adjacent to the lower ones.
[0049]
In the first to eighth embodiments, the negative-polarity operational amplifiers OP1 and OP3 and the positive-polarity operational amplifiers OP2 and OP4 are vertically adjacent to the positive-polarity gradation voltage line PLN and the negative-polarity gradation voltage line NLN. Deploy. This configuration has operations and effects equivalent to those of the first embodiment.
[0050]
(Ninth embodiment)
FIG. 10 is a diagram illustrating a configuration example of the liquid crystal display device according to the ninth embodiment. The liquid crystal display device includes a TFT liquid crystal panel PNL and a liquid crystal panel driving semiconductor integrated circuit 30. In the eighth embodiment (FIG. 9), the negative-polarity operational amplifiers OP1 and OP3 and the positive-polarity operational amplifiers OP2 and OP4 are arranged adjacent to each other in the vertical direction, but in this embodiment, the negative-polarity operational amplifiers OP1 and OP3 and the positive-polarity operational amplifier. OP2 and OP4 are alternately arranged adjacent to each other in the horizontal direction.
[0051]
In this embodiment, the positive operational amplifiers OP2 and OP4 and the negative operational amplifiers OP1 and OP3 are arranged adjacent to the positive gradation voltage line PLN and the negative gradation voltage line NLN in the horizontal direction. This configuration has operations and effects equivalent to those of the first embodiment.
[0052]
(Tenth embodiment)
FIG. 11A is a plan view showing an arrangement example of the liquid crystal panel driving semiconductor integrated circuit (liquid crystal driver) 30 of the first to ninth embodiments. The semiconductor integrated circuit 30 includes a region 30a having a data latch unit and a selector unit, and a region 30b having an operational amplifier unit and an output switching unit.
[0053]
In the present embodiment, the positive and negative polarity data latches and the positive and negative polarity selector regions 30a are arranged adjacent to only one side of the positive and negative polarity operational amplifiers and the output switching unit region 30b.
[0054]
FIG. 11B is a plan view showing an arrangement example of the liquid crystal panel driving semiconductor integrated circuit (liquid crystal driver) 30 according to the tenth embodiment. In the present embodiment, the data latch unit and selector unit region 30a of the tenth embodiment (FIG. 11) is replaced with the first data latch unit and selector unit region 31a and the second data latch unit and selector unit region. It is divided into 31b. The first data latch unit / selector unit region 31a and the second data latch unit / selector unit region 31b are adjacent to both sides of the region 30b with the operational amplifier unit and output switching unit region 30b interposed therebetween. Deploy.
[0055]
In the present embodiment, the positive and negative polarity data latches and the positive and negative polarity selector regions 31a and 31b are arranged adjacent to both sides of the positive and negative polarity operational amplifiers and the output switching unit region 30b. This configuration has operations and effects equivalent to those of the first embodiment.
[0056]
In this embodiment, the operational amplifier section and the output switching section area 30b are arranged in the center of the semiconductor integrated circuit 30, and a bonding pad can be provided in the area 30b having the output terminal of the output switching section SW. Easy to form chips. That is, when forming a normal dual line type IC or the like, it is preferable to provide a bonding pad at the end of the semiconductor integrated circuit 30, but when forming a flip chip, a bonding pad is provided at the center of the semiconductor integrated circuit 30. The package size can be reduced by providing the wiring directly by TAB or the like without using the lead frame.
[0057]
As described above in detail, in the first to tenth embodiments, since the positive polarity group and the negative polarity group are arranged in parallel in the horizontal direction, the horizontal length of the semiconductor integrated circuit 30 is Thus, the length of the twelve semiconductor integrated circuits 40 in the horizontal direction can be reduced, and the area of the semiconductor integrated circuit 30 can be reduced.
[0058]
Further, in the semiconductor integrated circuit 40 of FIG. 12, an unused area (shaded area in the figure) 2 is generated, but in the semiconductor integrated circuit 30 of this embodiment, such an unused area disappears, and the negative selector section The wiring of the NSEL and the positive polarity selector unit PSEL can be efficiently laid out, and the area of the semiconductor integrated circuit 30 can be reduced as a whole.
[0059]
In the semiconductor integrated circuit 40 of FIG. 12, the distance between the selectors SEL of different channel types has to be increased to some extent. However, in the semiconductor integrated circuit 30 of the present embodiment, the selectors adjacent in the horizontal direction have the same channel. Since a transistor of the type is used, the distance between selectors adjacent in the horizontal direction can be shortened, and the area of the semiconductor integrated circuit 30 can be further reduced.
[0060]
The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. In other words, the present invention can be implemented in various forms without departing from the spirit or main features thereof.
[0061]
The various aspects of the present invention are summarized as follows.
(Supplementary Note 1) A data latch for holding n-bit digital image data inputted from the outside and a gradation voltage line for generating an analog gradation voltage of each gradation are arranged immediately above, and the n-bit data held by the data latch Regarding a selector that selects any analog gradation voltage according to digital image data,
A liquid crystal comprising a selector in which only gradation voltage lines of the same polarity are arranged directly above, and a positive polarity group and a negative polarity group are arranged in a direction perpendicular to the gradation voltage line. Panel drive semiconductor integrated circuit.
(Appendix 2) A data latch for holding n-bit digital image data input from the outside;
A positive gradation voltage generating section for generating a positive analog gradation voltage for each gradation on a positive gradation voltage line;
A negative polarity gradation voltage generating section for generating a negative polarity analog gradation voltage for each gradation on a negative polarity gradation voltage line;
According to the n-bit digital image data held by the data latch, the positive gray scale voltage line is arranged without the negative gray scale voltage line being arranged directly above the negative gray scale voltage line. A positive polarity selector for selecting a positive polarity analog gradation voltage of each gradation to be generated;
In accordance with the n-bit digital image data held by the data latch, the negative gradation voltage line is arranged by the negative gradation voltage line without the positive gradation voltage line. A negative polarity selector for selecting a negative analog gradation voltage of each gradation to be generated;
An operational amplifier that amplifies and outputs the positive analog gradation voltage and the negative analog gradation voltage selected by the positive polarity selector and the negative polarity selector;
A liquid crystal panel drive comprising: an output switching unit that switches a signal path of a positive analog gradation voltage and a negative analog gradation voltage output by the operational amplifier to straight or cross and outputs the signal path to the liquid crystal panel Semiconductor integrated circuit.
[0062]
(Supplementary Note 3) The data latch holds a positive polarity data latch for holding digital image data for generating a positive polarity analog gradation voltage, and holds a digital image data for generating a negative polarity analog gradation voltage. Negative polarity data latch
The positive selector selects the positive analog gradation voltage according to the digital image data held by the positive data latch,
The negative selector selects the negative analog gradation voltage according to digital image data held by the negative data latch,
The operational amplifier includes a positive operational amplifier that amplifies and outputs the positive analog gradation voltage selected by the positive selector, and a negative output that amplifies and outputs the negative analog gradation voltage selected by the negative selector. The semiconductor integrated circuit for driving a liquid crystal panel according to appendix 2, characterized by comprising a functional operational amplifier.
(Supplementary note 4) The liquid crystal panel driving semiconductor integrated circuit according to supplementary note 2, wherein the positive polarity selector is constituted by a P-channel transfer gate, and the negative polarity selector is constituted by an N-channel transfer gate.
[0063]
(Supplementary Note 5) A plurality of the positive polarity data latch and the positive polarity selector are arranged in a horizontal direction with respect to the positive polarity gradation voltage line, and the negative polarity data latch and the negative polarity selector are set as a set and the negative polarity. 4. The semiconductor integrated circuit for driving a liquid crystal panel according to appendix 3, wherein a plurality of the grayscale voltage lines are arranged side by side in the horizontal direction.
(Supplementary Note 6) The positive polarity data latch and the negative polarity data latch are defined as the positive polarity selector and the positive polarity data latch as a positive polarity set, and the negative polarity selector and the negative polarity data latch as a negative polarity set. The positive polarity group and the negative polarity group are arranged so as to be adjacent to each other, and a plurality of sets are arranged in a horizontal direction with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. 4. A semiconductor integrated circuit for driving a liquid crystal panel according to appendix 3, wherein the semiconductor integrated circuit is arranged.
[0064]
(Supplementary note 7) The positive polarity data latch and the negative polarity data latch are arranged adjacent to each other in the vertical direction with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. 7. A semiconductor integrated circuit for driving a liquid crystal panel according to 6.
(Supplementary note 8) The positive polarity data latch and the negative polarity data latch are arranged adjacent to each other in the horizontal direction with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. 7. A semiconductor integrated circuit for driving a liquid crystal panel according to 6.
[0065]
(Supplementary Note 9) The positive selector and the negative selector are adjacent to each other with the positive selector and the positive data latch as a positive pair, and the negative selector and the negative data latch as a negative pair. As described above, the positive polarity group and the negative polarity group are arranged to form one set, and a plurality of sets are arranged in a horizontal direction with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. 4. A semiconductor integrated circuit for driving a liquid crystal panel according to appendix 3, wherein:
(Supplementary Note 10) The positive polarity selector and the positive polarity data latch are set as a positive polarity set, the negative polarity selector and the negative polarity data latch are set as a negative polarity set, and the selectors of different sets of positive polarity and negative polarity The positive polarity group and the negative polarity group are arranged so as to be adjacent to the data latch, and are set as one set, and are arranged in a horizontal direction with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. The semiconductor integrated circuit for driving a liquid crystal panel according to appendix 3, wherein a plurality of sets are arranged side by side.
[0066]
(Supplementary Note 11) The positive polarity selector includes a first positive polarity selector portion and a second positive polarity selector portion, and the negative polarity selector includes a first negative polarity selector portion and a second negative polarity selector portion. Have
The positive data latch is sandwiched between the first and second positive selector sections to form a positive pair, and the negative data latch is interposed between the first and second negative selector sections. The sandwiched one is a negative polarity group, the positive polarity group and the negative polarity group are arranged, and this is set as one set, with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. 4. The semiconductor integrated circuit for driving a liquid crystal panel according to appendix 3, wherein a plurality of sets are arranged in the horizontal direction.
(Supplementary Note 12) The positive polarity group and the negative polarity group are arranged so that the second positive polarity selector portion and the first negative polarity selector portion are adjacent to each other, 12. The semiconductor integrated circuit for driving a liquid crystal panel according to appendix 11, wherein a plurality of sets are arranged in a horizontal direction with respect to the positive gradation voltage line and the negative gradation voltage line.
[0067]
(Supplementary Note 13) The positive polarity data latch includes a first positive polarity data latch portion and a second positive polarity data latch portion, and the negative polarity data latch includes a first negative polarity data latch portion and a second negative polarity data latch portion. Negative polarity data latch part,
A structure in which the positive selector is sandwiched between the first and second positive data latch sections is a positive pair, and the negative selector is interposed between the first and second negative data latch sections. The sandwiched one is a negative polarity group, the positive polarity group and the negative polarity group are arranged, and this is set as one set, with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. 4. The semiconductor integrated circuit for driving a liquid crystal panel according to appendix 3, wherein a plurality of sets are arranged in the horizontal direction.
(Supplementary Note 14) The positive polarity group and the negative polarity group are arranged so that the second positive polarity data latch portion and the first negative polarity data latch portion are adjacent to each other. 14. The semiconductor integrated circuit for driving a liquid crystal panel according to appendix 13, wherein a plurality of sets are arranged in a horizontal direction with respect to the positive gradation voltage line and the negative gradation voltage line.
[0068]
(Supplementary Note 15) The second positive polarity data latch unit and the first negative polarity data latch unit are adjacent to each other in the vertical direction with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. 14. A semiconductor integrated circuit for driving a liquid crystal panel according to appendix 13, wherein the semiconductor integrated circuit is arranged.
(Supplementary Note 16) The second positive polarity data latch unit and the first negative polarity data latch unit are horizontally adjacent to the positive polarity gradation voltage line and the negative polarity gradation voltage line. 14. A semiconductor integrated circuit for driving a liquid crystal panel according to appendix 13, wherein the semiconductor integrated circuit is arranged.
[0069]
(Supplementary note 17) The supplementary note 3, wherein the positive operational amplifier and the negative operational amplifier are arranged adjacent to each other in the vertical direction with respect to the positive gradation voltage line and the negative gradation voltage line. Liquid crystal panel drive semiconductor integrated circuit.
(Supplementary note 18) The supplementary note 3, wherein the positive polarity operational amplifier and the negative polarity operational amplifier are disposed adjacent to each other in the horizontal direction with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. Liquid crystal panel drive semiconductor integrated circuit.
[0070]
(Supplementary Note 19) The positive and negative polarity data latches and the positive and negative polarity selector regions are arranged so as to be adjacent to only one side of the positive and negative polarity operational amplifier and output switching unit regions. The semiconductor integrated circuit for driving a liquid crystal panel according to appendix 3.
(Supplementary Note 20) The positive and negative polarity data latches and the positive and negative polarity selector regions are arranged adjacent to both sides of the positive and negative polarity operational amplifier and output switching unit regions. The semiconductor integrated circuit for driving a liquid crystal panel according to appendix 3.
[0071]
【The invention's effect】
As described above, according to the present invention, the length in the horizontal direction with respect to the gradation voltage line can be greatly shortened, and the area of the semiconductor integrated circuit for driving the liquid crystal panel can be reduced as a whole.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of a liquid crystal display device according to a first embodiment.
FIG. 2 is a circuit diagram illustrating a configuration example of a gradation voltage generation unit and a selector.
FIG. 3 is a diagram illustrating a configuration example of a liquid crystal display device according to a second embodiment.
FIG. 4 is a diagram illustrating a configuration example of a liquid crystal display device according to a third embodiment.
FIG. 5 is a diagram illustrating a configuration example of a liquid crystal display device according to a fourth embodiment.
FIG. 6 is a diagram illustrating a configuration example of a liquid crystal display device according to a fifth embodiment.
FIG. 7 is a diagram illustrating a configuration example of a liquid crystal display device according to a sixth embodiment.
FIG. 8 is a diagram illustrating a configuration example of a liquid crystal display device according to a seventh embodiment.
FIG. 9 is a diagram illustrating a configuration example of a liquid crystal display device according to an eighth embodiment.
FIG. 10 is a diagram illustrating a configuration example of a liquid crystal display device according to a ninth embodiment.
FIG. 11 is a plan view illustrating a configuration example of a semiconductor integrated circuit for driving a liquid crystal panel according to a tenth embodiment.
FIG. 12 is a diagram illustrating a configuration example of a conventional liquid crystal display device.
[Explanation of symbols]
1 Wiring contact part
2 Unused area
5 gradation voltage generator
6 Ladder resistance
11 Data latch and selector
30, 40 Liquid crystal panel driving semiconductor integrated circuit
Tr transistor
SEL selector section
NSEL Negative selector
PSEL Positive selector
LN gradation voltage line
NLN Negative gradation voltage line
PLN Positive gradation voltage line
LT Data latch part
NLT Negative data latch
PLT Positive data latch
OP Operational Amplifier
SW output switching part
PNL TFT LCD panel

Claims

A data latch for holding n-bit digital image data input from the outside;
  A positive gradation voltage generating section for generating a positive analog gradation voltage for each gradation on a positive gradation voltage line;
  A negative polarity gradation voltage generating section for generating a negative polarity analog gradation voltage for each gradation on a negative polarity gradation voltage line;
  According to the n-bit digital image data held by the data latch, the positive gray scale voltage line is arranged without the negative gray scale voltage line being arranged directly above the negative gray scale voltage line. A positive polarity selector for selecting a positive polarity analog gradation voltage of each gradation to be generated;
  In accordance with the n-bit digital image data held by the data latch, the negative gradation voltage line is arranged by the negative gradation voltage line without the positive gradation voltage line. A negative polarity selector for selecting a negative analog gradation voltage of each gradation to be generated;
  An operational amplifier that amplifies and outputs the positive analog gradation voltage and the negative analog gradation voltage selected by the positive polarity selector and the negative polarity selector;
  An output switching unit for switching the signal path of the positive polarity analog gradation voltage and the negative polarity analog gradation voltage output by the operational amplifier to straight or cross and outputting to the liquid crystal panel;
  The data latch includes a positive data latch that holds digital image data for generating a positive analog gradation voltage, and a negative data that holds digital image data for generating a negative analog gradation voltage. Including a latch,
  The positive selector selects the positive analog gradation voltage according to the digital image data held by the positive data latch,
  The negative selector selects the negative analog gradation voltage according to digital image data held by the negative data latch,
  The operational amplifier includes a positive operational amplifier that amplifies and outputs the positive analog gradation voltage selected by the positive selector, and a negative output that amplifies and outputs the negative analog gradation voltage selected by the negative selector. Including operational op amps,
  A plurality of the positive polarity data latches and the positive polarity selector are arranged in a horizontal direction with respect to the positive polarity gradation voltage line, and the negative polarity data latch and the negative polarity selector are set as a set to form the negative polarity gradation voltage. A semiconductor integrated circuit for driving a liquid crystal panel, wherein a plurality of the semiconductor integrated circuits are arranged in a horizontal direction with respect to a line.

A data latch for holding n-bit digital image data input from the outside;
  A positive gradation voltage generating section for generating a positive analog gradation voltage for each gradation on a positive gradation voltage line;
  A negative polarity gradation voltage generating section for generating a negative polarity analog gradation voltage for each gradation on a negative polarity gradation voltage line;
  According to the n-bit digital image data held by the data latch, the positive gray scale voltage line is arranged without the negative gray scale voltage line being arranged directly above the negative gray scale voltage line. A positive polarity selector for selecting a positive polarity analog gradation voltage of each gradation to be generated;
  In accordance with the n-bit digital image data held by the data latch, the negative gradation voltage line is arranged by the negative gradation voltage line without the positive gradation voltage line. A negative polarity selector for selecting a negative analog gradation voltage of each gradation to be generated;
  An operational amplifier that amplifies and outputs the positive analog gradation voltage and the negative analog gradation voltage selected by the positive polarity selector and the negative polarity selector;
  An output switching unit for switching the signal path of the positive polarity analog gradation voltage and the negative polarity analog gradation voltage output by the operational amplifier to straight or cross and outputting to the liquid crystal panel;
  The data latch includes a positive data latch that holds digital image data for generating a positive analog gradation voltage, and a negative data that holds digital image data for generating a negative analog gradation voltage. Including a latch,
  The positive selector selects the positive analog gradation voltage according to the digital image data held by the positive data latch,
  The negative selector selects the negative analog gradation voltage according to digital image data held by the negative data latch,
  The operational amplifier includes a positive operational amplifier that amplifies and outputs the positive analog gradation voltage selected by the positive selector, and a negative output that amplifies and outputs the negative analog gradation voltage selected by the negative selector. Including operational op amps,
  The positive polarity data latch and the negative polarity data latch are adjacent to each other with the positive polarity selector and the positive polarity data latch as a positive polarity group and the negative polarity selector and the negative polarity data latch as a negative polarity group. The positive polarity set and the negative polarity set are arranged in a single set, and a plurality of sets are arranged in a horizontal direction with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. A semiconductor integrated circuit for driving a liquid crystal panel.

A data latch for holding n-bit digital image data input from the outside;
  A positive gradation voltage generating section for generating a positive analog gradation voltage for each gradation on a positive gradation voltage line;
  A negative polarity gradation voltage generating section for generating a negative polarity analog gradation voltage for each gradation on a negative polarity gradation voltage line;
  According to the n-bit digital image data held by the data latch, the positive gray scale voltage line is arranged without the negative gray scale voltage line being arranged directly above the negative gray scale voltage line. A positive polarity selector for selecting a positive polarity analog gradation voltage of each gradation to be generated;
  In accordance with the n-bit digital image data held by the data latch, the negative gradation voltage line is arranged by the negative gradation voltage line without the positive gradation voltage line. A negative polarity selector for selecting a negative analog gradation voltage of each gradation to be generated;
  An operational amplifier that amplifies and outputs the positive analog gradation voltage and the negative analog gradation voltage selected by the positive polarity selector and the negative polarity selector;
  An output switching unit for switching the signal path of the positive polarity analog gradation voltage and the negative polarity analog gradation voltage output by the operational amplifier to straight or cross and outputting to the liquid crystal panel;
  The data latch includes a positive data latch that holds digital image data for generating a positive analog gradation voltage, and a negative data that holds digital image data for generating a negative analog gradation voltage. Including a latch,
  The positive selector selects the positive analog gradation voltage according to the digital image data held by the positive data latch,
  The negative selector selects the negative analog gradation voltage according to digital image data held by the negative data latch,
  The operational amplifier includes a positive operational amplifier that amplifies and outputs the positive analog gradation voltage selected by the positive selector, and a negative output that amplifies and outputs the negative analog gradation voltage selected by the negative selector. Including operational op amps,
  The positive polarity selector and the positive polarity data latch are set as a positive polarity set, and the negative polarity selector and the negative polarity data latch are set as a negative polarity set so that the positive polarity selector and the negative polarity selector are adjacent to each other. The positive polarity group and the negative polarity group are arranged as a set. A liquid crystal panel driving semiconductor integrated circuit, wherein a plurality of sets are arranged in a horizontal direction with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line.

A data latch for holding n-bit digital image data input from the outside;
  A positive gradation voltage generating section for generating a positive analog gradation voltage for each gradation on a positive gradation voltage line;
  A negative polarity gradation voltage generating section for generating a negative polarity analog gradation voltage for each gradation on a negative polarity gradation voltage line;
  According to the n-bit digital image data held by the data latch, the positive gray scale voltage line is arranged without the negative gray scale voltage line being arranged directly above the negative gray scale voltage line. A positive polarity selector for selecting a positive polarity analog gradation voltage of each gradation to be generated;
  In accordance with the n-bit digital image data held by the data latch, the negative gradation voltage line is arranged by the negative gradation voltage line without the positive gradation voltage line. A negative polarity selector for selecting a negative analog gradation voltage of each gradation to be generated;
  An operational amplifier that amplifies and outputs the positive analog gradation voltage and the negative analog gradation voltage selected by the positive polarity selector and the negative polarity selector;
  An output switching unit for switching the signal path of the positive polarity analog gradation voltage and the negative polarity analog gradation voltage output by the operational amplifier to straight or cross and outputting to the liquid crystal panel;
  The data latch includes a positive data latch that holds digital image data for generating a positive analog gradation voltage, and a negative data that holds digital image data for generating a negative analog gradation voltage. Including a latch,
  The positive selector selects the positive analog gradation voltage according to the digital image data held by the positive data latch,
  The negative selector selects the negative analog gradation voltage according to digital image data held by the negative data latch,
  The operational amplifier includes a positive operational amplifier that amplifies and outputs the positive analog gradation voltage selected by the positive selector, and a negative output that amplifies and outputs the negative analog gradation voltage selected by the negative selector. Including operational op amps,
  The positive polarity selector and the positive polarity data latch are set as a positive polarity set, the negative polarity selector and the negative polarity data latch are set as a negative polarity set, and the selectors and data latches of the positive polarity and the negative polarity are different. The positive polarity group and the negative polarity group are arranged so as to be adjacent to each other, and a plurality of sets are arranged in a horizontal direction with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. A semiconductor integrated circuit for driving a liquid crystal panel.

A data latch for holding n-bit digital image data input from the outside;
  A positive gradation voltage generating section for generating a positive analog gradation voltage for each gradation on a positive gradation voltage line;
  A negative polarity gradation voltage generating section for generating a negative polarity analog gradation voltage for each gradation on a negative polarity gradation voltage line;
  According to the n-bit digital image data held by the data latch, the positive gray scale voltage line is arranged without the negative gray scale voltage line being arranged directly above the negative gray scale voltage line. A positive polarity selector for selecting a positive polarity analog gradation voltage of each gradation to be generated;
  In accordance with the n-bit digital image data held by the data latch, the negative gradation voltage line is arranged by the negative gradation voltage line without the positive gradation voltage line. A negative polarity selector for selecting a negative analog gradation voltage of each gradation to be generated;
  An operational amplifier that amplifies and outputs the positive analog gradation voltage and the negative analog gradation voltage selected by the positive polarity selector and the negative polarity selector;
  An output switching unit for switching the signal path of the positive polarity analog gradation voltage and the negative polarity analog gradation voltage output by the operational amplifier to straight or cross and outputting to the liquid crystal panel;
  The data latch includes a positive data latch that holds digital image data for generating a positive analog gradation voltage, and a negative data that holds digital image data for generating a negative analog gradation voltage. Including a latch,
  The positive selector selects the positive analog gradation voltage according to the digital image data held by the positive data latch,
  The negative selector selects the negative analog gradation voltage according to digital image data held by the negative data latch,
  The operational amplifier includes a positive operational amplifier that amplifies and outputs the positive analog gradation voltage selected by the positive selector, and a negative output that amplifies and outputs the negative analog gradation voltage selected by the negative selector. Including operational op amps,
  The positive polarity selector has a first positive polarity selector portion and a second positive polarity selector portion, and the negative polarity selector has a first negative polarity selector portion and a second negative polarity selector portion,
  The positive data latch is sandwiched between the first and second positive selector sections to form a positive pair, and the negative data latch is interposed between the first and second negative selector sections. The sandwiched one is a negative polarity group, the positive polarity group and the negative polarity group are arranged, and this is set as one set, with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. A semiconductor integrated circuit for driving a liquid crystal panel, wherein a plurality of sets are arranged in a horizontal direction.

A data latch for holding n-bit digital image data input from the outside;
  A positive gradation voltage generating section for generating a positive analog gradation voltage for each gradation on a positive gradation voltage line;
  A negative polarity gradation voltage generating section for generating a negative polarity analog gradation voltage for each gradation on a negative polarity gradation voltage line;
  According to the n-bit digital image data held by the data latch, the positive gray scale voltage line is arranged without the negative gray scale voltage line being arranged directly above the negative gray scale voltage line. A positive polarity selector for selecting a positive polarity analog gradation voltage of each gradation to be generated;
  In accordance with the n-bit digital image data held by the data latch, the negative gradation voltage line is arranged by the negative gradation voltage line without the positive gradation voltage line. A negative polarity selector for selecting a negative analog gradation voltage of each gradation to be generated;
  An operational amplifier that amplifies and outputs the positive analog gradation voltage and the negative analog gradation voltage selected by the positive polarity selector and the negative polarity selector;
  An output switching unit for switching the signal path of the positive polarity analog gradation voltage and the negative polarity analog gradation voltage output by the operational amplifier to straight or cross and outputting to the liquid crystal panel;
  The data latch includes a positive data latch that holds digital image data for generating a positive analog gradation voltage, and a negative data that holds digital image data for generating a negative analog gradation voltage. Including a latch,
  The positive selector selects the positive analog gradation voltage according to the digital image data held by the positive data latch,
  The negative selector selects the negative analog gradation voltage according to digital image data held by the negative data latch,
  The operational amplifier includes a positive operational amplifier that amplifies and outputs a positive analog gradation voltage selected by the positive selector, and a negative analog selected by the negative selector. A negative-polarity operational amplifier that amplifies the grayscale voltage and outputs it,
  The positive polarity data latch includes a first positive polarity data latch portion and a second positive polarity data latch portion, and the negative polarity data latch includes a first negative polarity data latch portion and a second negative polarity data latch. And
  A structure in which the positive selector is sandwiched between the first and second positive data latch sections is a positive pair, and the negative selector is interposed between the first and second negative data latch sections. The sandwiched one is a negative polarity group, the positive polarity group and the negative polarity group are arranged, and this is set as one set, with respect to the positive polarity gradation voltage line and the negative polarity gradation voltage line. A semiconductor integrated circuit for driving a liquid crystal panel, wherein a plurality of sets are arranged in a horizontal direction.