JP3862240B2 - Signal deskew system for synchronous logic - Google Patents

Description

Background of the Invention
Field of Invention
The present invention relates to a system for deskewing a signal transmitted between a digital system signal source and a remote operating module and / or for compensating the time axis of the signal.
Explanation of related technology
In a synchronous digital logic circuit formed by a set of interconnected operation modules, one of the signals distributed to each module is a clock signal for controlling the operation timing between the modules. For example, a computer may include several circuit boards that are mounted in a chassis and interconnected by a backplane wiring to a motherboard that includes a central controller and a clock signal source. Typically, one of the conductors in the backplane wiring transmits a clock signal to each circuit board. In some types of synchronization systems, it is desirable to synchronize the reference signal in relative time so that the amount of delay in the reference signal path does not introduce timing latencies (signal skew) in the system.
Signal skew can also be a problem in electronic devices with distributed components that must operate in sync with each other. For example, integrated circuit (IC) testersHost unitAnd the relevantHost unitAnd a plurality of operation modules connected to each other. Each operating module provides an interface to a separate pin of the IC under test. At various times, the operating module transmits a test signal to the IC pin and captures output data generated by the IC at that pin.Host unitOne of the functions is to coordinate each operation of the motion module. In order to synchronize the arrival times of signals to the device under test (DUT), it is necessary to remove signal skew (distortion) between the modules. For example, to signal the start of the testHost unitSends a “start” signal to each motion module.Host unitAlso sends a clock signal to each operating module to synchronize the operation of the operating module under test and to synchronize communication between the host and the operating module during the test. When clock signals and other control and data signals travel different distances to reach the operating module, they arrive at different modules at different times. If such control and clock signal skew is sufficiently large relative to the tester operating frequency, timing mismatch between module operations may occur, and the module to device under test (DUT) can be synchronized. It may adversely affect the incoming signal.
US Pat. No. 5,369,640, granted to Watson et al. On November 29, 1994, provides a separate transmission line from the clock signal source to each operating module and adjusts the transmission line Thus, a system is disclosed for reducing the skew of the clock signal sent to remotely control each operating module so that all lines are the same length. However, this “star bus” solution to the problem of signal skew requires a very large number of transmission lines to be routed from the signal source, which is somewhat practical in systems with a large number of operating modules. Not right.
Another method for removing signal skew is disclosed in US Pat. No. 4,447,870, issued May 8, 1984 to Tague et al. Here, an adjustable delay circuit is provided for each operating module to further delay the clock signal after the clock signal arrives at each operating module. The delay circuit of each operation module is adjusted such that the sum of the delay amount of the clock signal transmission line and the delay amount provided by the adjustable delay circuit is equal to the standard delay amount. This method can provide a clock signal to the operating module from a single transmission line connected to all the operating modules as in the backplane. However, this method requires time-consuming and difficult work of manually calibrating the delay circuit of each operation module. Also, the clock delay circuit must be readjusted when the motion module is moved to a new position along the transmission line.
Summary of invention
The deskew system (time base correction system) according to the present invention is responsive to a global reference signal generated by a single signal source.Digital systemEach of the distribution modules provides a local clock signal. A global signal is supplied from a supply source to each module via two independent transmission lines having the same length and different signal propagation speeds. Since the phase difference between the two global signals arriving at each module via the two transmission lines is proportional to the length of the transmission line, it is proportional to the inherent clock signal delay amount of one of the transmission lines. The deskew circuit of each module generates a local clock signal in the module by further delaying after the global signal arrives on the first of the two transmission lines. The deskew circuit detects the phase difference between corresponding global reference signals arriving at the module on the two transmission lines to determine the inherent delay amount of the first transmission line. Next, the deskew circuit adjusts the local clock delay amount so that the sum of the inherent transmission line delay amount and the local clock delay amount becomes equal to the standard delay amount. With the same standard delay amount in all modules, local clock signals generated in all modules are in phase with each other.
Accordingly, it is an object of the present invention to provide a system for strictly synchronizing the operation of separate modules of a synchronous logic circuit system.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However, by reading the remaining portions of the specification with reference to the accompanying drawings, in which the same reference characters represent the same parts, the structure and method of implementation of the present invention, together with further effects and objects thereof, will be described. Those skilled in the art will best understand.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating module synchronization logic using a signal deskew system according to the present invention.
FIG. 2 is a block diagram showing the deskew circuit of FIG. 1 in more detail.
FIG. 3 is a block diagram showing the delay control circuit of FIG. 2 in more detail.
FIG. 4 is a block diagram illustrating a prior art circuit suitable for using the phase detection circuit of FIG.
FIG. 5 is a block diagram showing a conventional delay circuit.
FIG. 6 is a block diagram showing another embodiment of the delay control circuit of FIG.
FIG. 7 is a block diagram showing a conventional delay circuit.
FIG. 8 is a block diagram showing another embodiment of the deskew circuit of FIG.
FIG. 9 is a block diagram illustrating clock signal delay in the deskew system of FIG.
FIG. 10 is a cross-sectional view of a circuit board that provides transmission lines that vary the propagation speed of signals.
DESCRIPTION OF PREFERRED EMBODIMENTS
Referring to FIG. 1, the present inventionHost unit12 between the host logic circuit 10 in the 12 and the N distributed local logic circuits 14 (1) -14 (N) in the operation module 16 (1) -16 (N) of the synchronous logic system. Relates to a system for deskewing a received signal. The operation module 16 is located at various distances from the host logic circuit 10. The host logic circuit 10 and the local logic circuit 14 are application dependent. For example, in the logic system, the host logic circuit 10 is a conventional microprocessor and the local logic circuit.14Can be a computer such as a memory or peripheral I / O controller or other device that communicates with a computer processor synchronously. System 10 may be, for example, a distributed architecture integrated circuit tester in which each local logic circuit 14 provides an interface to a separate pin of the integrated circuit device under test. At various times during the test, the motion module transmits a test signal to terminals 25 (1) -25 (N) of the device under test or captures output data generated by the IC at the pins.Host unitProvides control signals and instructions to the motion module.
In a typical synchronous logic system, a global clock signal is sent simultaneously to each local logic circuit to synchronize operation. Since the local logic circuits are spatially distributed, pulses of the clock signal generated from the common clock signal source cannot reach the local logic circuit at the same time. This is particularly true when the local logic circuit captures the global clock signal by tapping the common transmission line at different locations. The difference in delay (skew) between the time that the clock signal pulse leaves the clock source and the time that the pulse arrives at various local logic circuits affects the ability to operate synchronously. The present invention compensates for clock signal skew and is in phase with each other in each local logic circuit 14.Local clockProvide a signal. The signal distribution system also compensates for skew in control and communication signals transmitted between the host logic circuit 10 and the local logic circuit 14 due to signal path length differences.
Accordingly, the deskew system of the present invention includes a set of N deskew circuits 18 (1) -18 (N), each deskew circuit beingEach correspondingOperation module 16 (1) -16 (N)Built in. The deskew system also includes a control signal bus 20 for transmitting communication and / or control signals between the host logic circuit 10 and each deskew circuit 18. Bus 20Same as CLKA transmission path [28 (A)]Use a transmission path with propagation speed. The I th deskew circuit 18 (I) provides an interface between the corresponding I th local logic circuit 14 (I) and the control signal bus 20. Here, “I” is a number from 1 to N. The output signal generated by the host logic circuit 10 passes to each deskew circuit 18 (I) via the bus 20, and the local logic circuit corresponding as the input signal 22 via the delay circuit DELAY (I) which can be adjusted here. 14 (I).
The signal distribution system of the present invention also includes a clock supply source 26 and a pair of transmission lines 28A and 28B connected to each other by the clock supply source 26, each interconnecting the clock supply source 26 to the deskew circuit 18. The clock source 26 simultaneously generates a periodic global clock signal CLKG on each of the transmission lines 28A and 28B. Transmission lines 28A and 28B supply global clock signals to deskew circuit 18 as separate clock signals CLKA and CLKB, respectively. Each deskew circuit 18 taps transmission lines 28A and 28B at equal distances along transmission lines 28A and 28B. The CLKA and CLKB signals arrive at an arbitrary (I-th) deskew circuit 18 (I) and then arrive at the deskew circuit 18 (I + 1). However, when moving between the clock source 26 and the I-th deskew circuit 18 (I), the CLKA signal has substantially the same distance on the transmission line 28A as the CLKB signal travels along the transmission line 28B. Move along.
According to the present invention, transmission lines 28A and 28BsoHave different signal propagation speeds. More specifically, the propagation speed of the CLKA signal on the transmission line 28A is M times faster than the propagation speed of the CLKB signal on the transmission line 28B (where M is a number greater than 1). In other words, the pulse of the CLKA signal arrives at the I-th deskew circuit 18 (I) before the corresponding pulse of the CLKB signal, although it travels the same distance. The delay time between the arrival of the CLKA signal and the CLKB signal at the corresponding pulse deskew circuit 18 (I) is determined by the clock supply source.26And the length of the transmission lines 28A and 28B between the deskew circuit 18 (I). That is, the phase difference between CLKA and CLKB is a measure of the length of the transmission line from the clock source 26 to the point along the transmission lines 28A and 28B where the deskew circuit 18 (I) detects CLKA and CLKB. is there.
Bus 20 includes one or more transmission lines having the same propagation speed as transmission line 28A. The distance between the host logic circuit 10 and the deskew circuit 18 (I) along the bus 20 is substantially the same as the distance along the transmission line 28A between the clock source 26 and the deskew circuit 18 (I). . If signal pulses depart simultaneously from the host logic circuit 10 on the bus 20 and the clock source 26 on the transmission line 28, they travel the same distance and have the same propagation speed, so that they are simultaneously sent to the deskew circuit 18 (I). arrive.
Each deskew circuit 18 (I) extracts the local clock signal CLK (I) from the CLKA and CLKB signals and supplies the local clock signal CLK (I) as an input to the corresponding local logic circuit 14 (I). The deskew circuit 18certainlyLocal clock signals CLK (1) -CLK (N) are all substantially in phase with each otherMake. The local logic circuit 14 (1) -14 (N) uses this as a timing signal to generate a local input signal.22 (1) -22 (N)Synchronize operations including receiving
Each deskew circuit 18 (I) generates its local clock signal CLK (I) by delaying the input CLKA signal by an adjustable delay time DELAY (I). The closer the deskew circuit 18 (I) is to the clock supply source 26, the longer the deskew circuit 18 (I) delays the CLKA signal to generate the local clock signal CLK (I) output. More specifically, each deskew circuit 18 (I) delays CLKA by an amount of time sufficient to bring all local clock signals CLKL (1) -CLKL (N) into phase with one another.
Each deskew circuit 18 (I) first determines the amount of time to delay the CLKA signal by measuring the period between the arrival of both corresponding pulses of the CLKA and CLKB signals. Since this measured period is proportional to the length of the transmission line 28A (or transmission line 28B) from the clock supply source 26 to the deskew circuit 18 (I), the CLKA signal from the clock supply source 26 to each deskew circuit 18 (I). Is also proportional to the time D (I) required to move. The delay time DELAY (I) is adjusted so that the sum of time D (I) and DELAY (I) is equal to a certain total delay amount TD:
SKEW (I) = TD
= D (I) + DELAY (I)
= Constant
Here, SKEW (I) is the skew of the local clock signal CLK (I) with respect to the global clock signal at the clock supply source 26.
Each deskew circuit 18 (I) also supplies a local input signal 22 (I) from the transmission line of the bus 20 to the local logic circuit 14 (I) via the same delay circuit DELAY (I). That is, the signal starting from the host logic circuit 10 simultaneously arrives at all the local logic circuits 14 (I) as the local input signal 22 (I).
Referring to FIG. 2, according to the preferred embodiment of the present invention, the deskew circuit 18 (I) of FIG. 1 adjustably delays the CLKA signal by a delay time DELAY (I) to adjust the local clock signal CLK ( A delay circuit 32 for generating I). The delay control circuit 34 measures the phase difference and generates an output signal CS that appropriately adjusts the delay time DELAY (I) of the delay circuit 32. The CS signal is also applied as a delay control signal to a delay circuit 36 that is structurally the same as the delay circuit 32, and provides the same delay time DELAY (I) in response to the CS signal. Delay circuit 36 delays the signal arriving on the bus 20 line and provides local input signal 22 (I) to local logic circuit 14 (I) of FIG. For simplicity, only one delay circuit 36 is shown in FIG. The same delay circuit controlled by the CS signal can be provided as needed to link each line of the bus 20 to the input and / or output of the local logic circuit.
FIG. 3 shows one embodiment of the delay control circuit 34. Delay control circuit 34 includes a phase detection circuit 40 that receives the CLKA and CLKB signals and generates an output signal VPH having a voltage proportional to the phase difference between CLKA and CLKB. The A / D converter 42 converts the VPH signal into a digital value ADDR having a similar magnitude. The digital value ADDR addresses the addressable memory 44 storing control data (DATA) at each address and supplies the D / A converter 46 with the currently addressed DATA. The DAC 46 generates a CS signal having a magnitude proportional to the magnitude of DATA. The data stored at each address of the memory 44 is adjusted so that the CS signal has a magnitude that provides an appropriate amount of delay to the delay circuit 32 for any phase difference between the CLKA and CLKB signals. . Such stored DATA values are monitored using an oscilloscope or other phase detector to monitor the phase relationship between the global clock signal CLKG and the local clock signal CLK (I), and the local clock signal CLK It can be determined by repeatedly adjusting DATA until (I) and the global clock signal CLKG have the desired phase relationship for each value of the digital value ADDR.
FIG.3A known prior art phase detection circuit suitable for use as the first phase detection circuit 40 is shown. The D-type flip-flop 50 sets the output signal 52 to a high value when the CLKA signal precedes the CLKB signal, and sets the output signal 52 to a low value when the CLKA signal lags behind the CLKB signal. Low pass filter 54 filters signal 52 and provides an input to amplifier 58. Amplifier 58 generates a VPH signal output in response to input signal 56. The magnitude of VPH is proportional to the phase difference between the CLKA and CLKB signals.
FIG. 5 shows a known delay circuit suitable for use as the delay circuit 32 of FIG. The delay circuit 32 includes a set of inverter circuits 60 connected in series, where the CLKA signal is supplied to the input of the first inverter circuit in series, and the local clock signal CLK (I) is the last inverter circuit in series. Occurs in the output. CS signal is an inverterPowerSupply power. When the magnitude of the CS signal increases, the signal propagation rate of each inverter circuit 60 also increases, and thereby the delay amount of the delay circuit 32 decreases.
6 and 7 show another embodiment of the delay control circuit 34 and the delay circuit 32. FIG. Figure6Referring to FIG. 2, the delay control circuit 343The same phase detection circuit 62, A / D converter 64, and memory 66 as the phase detection circuit 40, A / D converter 42, and memory 44. However, in this embodiment, the CS signal supplied to the delay circuit 32 is3In the same way that the memory 44 generates the output DATA signal.Memory 66Is a digital data signal generated by Referring to FIG. 7, another delay circuit 32 includes a set of inverter circuits 68 connected in series, and the CLKA signal is provided as an input to a first inverter circuit in series. Multiplexer controlled by digital CS output of memory 66 of FIG.70Selects one output of inverter 66 to be the output local clock signal CLK (I).Memory 66The value of the conversion data stored in3In order to confirm the value of the conversion data to be stored in the memory 44, the value was experimentally set by the method described earlier in this specification. The embodiment of delay circuit 32 illustrated in FIG. 7 is well known to those skilled in the art.
FIG. 8 shows another embodiment of the deskew circuit 30 (I) of FIG.71Indicates. Deskew circuit71Includes a pair of delay circuits 72A and 72B. The delay circuit 72A delays the CLKA signal to generate a first local clock LA (the clock LA is used as the output local clock signal CLK (I)). Delay circuit 72B delays CLKB signal to generate a second local clock signal LB. The LA and LB signals are supplied as inputs to a phase detection circuit 76 (similar to phase detection circuit 40 of FIG. 4), which has an output signal having a voltage proportional to the phase difference between LA and LB.VPHIs generated. The differential amplifier 78 isVPHCompare the signal to the constant voltage reference signal VREF,VPHAnd an output signal VPLL having a magnitude proportional to the difference between VREF and VREF. The VPLL signal is commonly supplied as a control input to both the delay circuit 72A and the delay circuit 72B.
Delay circuits 72A and 72B vary in a similar manner. As the VPLL increases, the amount of delay provided by both delay circuits 72A and 72B decreases. However, for any size of VPLL, the delay time provided by delay circuit 72B is M times longer than the delay time provided by delay circuit 72A. As described earlier in this specification, the signal propagation speed of transmission line 28A in FIG. 1 is M times greater than the signal propagation speed of transmission line 28B. That is, the signal delay time provided by the transmission line 28B between the clock supply source and the deskew circuit is M times longer than the delay amount of the transmission line 28A. If the delay circuits 72A and 72B are similar to the delay circuit 32 of FIG. 5, the delay ratio M between the two delay circuits can be set, for example, by using a different number of inverter stages for the two delay circuits. . In addition, when the inverter stage is implemented by, for example, a CMOS transistor, the delay ratio M is determined by a method well known to those skilled in the art.Inverter 60Fine adjustment can be made by changing the channel width of the CMOS transistor forming the.
FIG. 9 shows the signal delay of the circuit of FIG. The local module taps the transmission lines 28A and 28B at a variable distance L from the clock source 26 to obtain the CLKA and CLKB signals. The inherent signal delay amount D (L) in the transmission line 26A between the tap and the clock supply source 26 is linearly proportional to L. Since the signal propagation speed in the transmission line 28A is M times larger than that in the transmission line 28B, the specific signal delay amount M * D (L) in the transmission line 28B is equal to the specific signal delay amount D (L in the transmission line 28 (A). ) M times longer (where the symbol “*” represents multiplication). The amount of delay provided by delay circuit 72A is also a function of L and is represented as D '(L) in FIG. Since the delay amount provided by the delay circuit 72B of FIG. 7 is M times larger than the delay amount provided by the delay circuit 72A for an arbitrary size VPLL, the delay amount of the delay circuit 72B is M * D ′ (L). is there.
As can be seen from the verification of FIG. 9, the local clock LA is a periodic global clock signal at the output of the clock supply source 20 by the sum of the delay amounts D (L) and D ′ (L) of the transmission line 28A and the delay circuit 72A. Delayed from CLKG. That is, the phase of the local clock LA is relative to the periodic global clock signal CLKG.
PHASE (LA) = [D (L)] + [D ′ (L)] (1)
It becomes.
Similarly, the phase of the local clock LB with respect to the periodic global clock signal CLKG is
PHASE (LB) = [M * D (L) + M * D ′ (L)] (2)
It becomes.
Figure8The phase difference between LA and LB detected by the phase detection circuit 76 of
PHASE (B: A) = PHASE (LB) −PHASE (LA)
PHASE (B: A) = [M * D (L) + M * D ′ (L)] − [D (L) + D ′ (L)]
PHASE (B: A) = (M−1) * [D (L) + D ′ (L)] (3)
It becomes.
From Equation (1) and Equation (3)
PHASE (LA) = D (L) + D ′ (L)
= PHASE (B: A) / (M-1) (4)
It becomes.
The feedback control VPLL provided by the phase detection circuit 76 and the differential amplifier 78 calculates the phase difference PHASE (B: A) between the local clocks LB and LA to the voltage of the reference signal VREF supplied to the differential amplifier 78. Is held at a constant value determined by. The feedback loop requires that the VPH voltage is equal to the VREF voltage. Since the VPH voltage is proportional to the phase PHASE (B: A), PHASE (B: A) is fixed at some value required to make the VPH voltage equal to the VREF voltage.
Since PHASE (B: A) and M are constants independent of L, PHASE (LA) from Equation (4), that is, the period global clock signal of the local clock LA at the output of the clock source 26 It can be seen that the phase with respect to CLKG is also independent of L. This is because when the VREF signal of the same magnitude is supplied to the differential amplifier 78 inside all the deskew circuits, the local clock signal LA generated by all the deskew circuits in the system is This indicates that the output has the same phase with respect to the periodic global clock signal CLKG. Since the LA signal is used as the local clock signal CLK (I) output to the local logic circuit, all the local clock signals CLK (1) -CLK (N) in FIG. The operations of the logic circuits 14 (1) -14 (N) are strictly synchronized.
The magnitude of VREF in FIG. 8 should be selected so that the constant phase difference PHASE (B: A) between the local clock signals LA and LB is equal to (M−1) * D (LMAX). LMAX is the clock source rather than the most distant local module transmission line tap26The distance along the transmission lines 248 and 248 from the point to the farther point. D (LMAX) is therefore the clock source26And the total delay amount of the inherent signal on the transmission line 28A between these points. The value of VREF ensures that the obtained delay amount DELAY (1) -DELAY (N) is positive and within the capability range of the internal delay circuit in the deskew circuit 18 (1) -18 (N). Should be selected.
From equation (4), it can also be understood that the value of M, which is the ratio of the signal propagation speeds of the two transmission lines, should be greater than one. One way to do this when the transmission line is mounted on a backplane circuit board is to use a microstrip conductor for one transmission line and a stripline conductor for the other transmission line. is there. The microstrip conductor is formed on top of the substrate, and the stripline conductor is sandwiched between the layers of the circuit board. For example, in the fiber glass substrate G-10 having a relative dielectric constant of 5.0, the propagation speed of the microstrip conductor is 565 pS / ft (picosecond / ft), while the propagation speed of the stripline conductor is 442 pS / ft. That is, the speed ratio M is 1.28. The difference in signal delay between the two conductors is 68 pS / inch in transmission line length.
By using circuit board layers with different dielectric constants, M can be increased to improve deskew resolution. In FIG. 10, the microstrip conductors 90 and 91 that provide the transmission line 28A and the bus 20 line are formed on the upper FR4 dielectric layer 92 (relative dielectric constant = 4.8) above the ground plane conductor 94. A cross-sectional view of a multilayer circuit board 89 is shown. A stripline conductor 95 providing the transmission line 28B is sandwiched between two duroid dielectric layers 96 and 97 (dielectric constant = 10) and a second ground plane 98 is at the bottom of the circuit board. With this structure, a propagation velocity ratio M = 1.82 is obtained. The difference in signal delay between the two conductors is 120 ps per inch of transmission line length.
Thus, a signal deskew system for a distributed synchronous logic circuit has been described. While the foregoing description has described preferred embodiments of the invention, those skilled in the art can make many modifications to the preferred embodiments in a broad aspect without departing from the invention. Accordingly, the following claims are intended to protect all such modifications that fall within the true scope and spirit of the present invention.

Claims (19)

A method for generating local clock signals separately in each of a plurality of modules of a distributed synchronous logic system in response to a global clock signal generated by a clock signal source, wherein the local clock signals are mutually connected Are substantially in phase,
Transmitting the global clock signal from the clock signal supply source to each module via the first and second transmission lines, wherein the first and second transmission lines are the clock signal supply source and each module. Having substantially the same length but substantially different signal propagation velocities between,
Detecting the length of the first and second transmission lines between the clock signal supply source and each module;
When arriving at each module on one of the first and second transmission lines, the global clock signal is reduced by a delay time that is a function of the detected transmission line length between the module and the clock signal source. And causing each module to generate a separate local clock signal by delaying. The method of claim 1, wherein the delay time is inversely proportional to the detected transmission line length. The global clock when the step of detecting the lengths of the first and second transmission lines between the clock signal supply source and each module arrives at each module via the first transmission line The method according to claim 1 , wherein the phase of the signal is compared with the phase of the global clock signal as it arrives at each module via the second transmission line. Detecting the lengths of the first and second transmission lines and delaying the global clock signal;
The phase of the global clock signal when arriving at each module via the first transmission line is compared with the phase of the global clock signal when arriving at the module via the second transmission line. Generating a first signal having a magnitude representative of a length;
Generating a second signal in response to the first signal so that the magnitude of the second signal is a predetermined function of the magnitude of the first signal;
Passing the global clock signal through a delay circuit and generating the local clock signal after the global clock signal has arrived at the module via one of the first and second transmission lines; A sub-step of delaying the global clock signal by the delay time so that the delay time is controlled according to the magnitude of the second signal provided as a control input to the delay circuit; 2. The method of claim 1 comprising : Generating the second signal comprises:
A sub-process for storing data values at separate addresses in addressable memory; and
Sub-addressing the addressable memory according to the magnitude of the first signal so that the addressable memory reads one of the stored data values;
5. The method of claim 4, further comprising a sub-step of generating a magnitude of the second signal according to the read data value. A method for generating a separate local clock signal in each of a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, comprising:
Transmitting the global clock signal from the clock signal supply source to each module via each of the first and second transmission lines;
Generating a first local clock signal at the module by delaying the global clock signal by a first delay time adjustable upon arrival at each module via the first transmission line;
Generating a second local clock signal in the module by delaying the global clock signal by a second delay time adjustable upon arrival at each module via the second transmission line;
Adjusting the first and second delay times in each module to provide a predetermined phase relationship between the first and second local clock signals generated in each module;
The first and second transmission lines are substantially equal in length between the clock signal supply source and each module, but the global clock signal propagation speed of the first transmission line is the same as that of the second transmission line. A method characterized in that it is M times the global clock signal propagation speed (M is a number other than 1). The method of claim 6 , wherein the ratio of the second delay time to the first delay time is substantially equal to M for each module. An apparatus for generating separate local clock signals for a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, wherein the local clock signals are substantially each other. In phase,
A first transmission line for transmitting the global clock signal from the clock signal supply source to each module;
A second transmission line for transmitting the global clock signal from the clock signal supply source to each module;
A length of the first and second transmission lines is detected between the clock signal supply source and the module related thereto, and is associated with one of the first and second transmission lines. Deskew means for delaying the global clock signal by a delay time that is a function of the detected transmission line length when arriving at the module;
The apparatus wherein the first and second transmission lines have substantially the same length but a substantially different global clock signal propagation speed between the clock signal source and each module. 9. The apparatus of claim 8, wherein the delay time is inversely proportional to the detected transmission line length. The phase of the global clock signal when the deskew means arrives at the attached module via the first transmission line and the global clock when it arrives at the attached module via the second transmission line 9. Apparatus according to claim 8 , characterized in that it comprises means for comparing the phase of the signal. The deskew means comprises:
A phase of the global clock signal when arriving at the attached module via the first transmission line and a phase of the global clock signal when arriving at the attached module via the second transmission line; Means for generating a first signal of a magnitude representative of said length;
Means for generating a second signal in response to the first signal such that the magnitude of the second signal is a predetermined function of the magnitude of the first signal;
Generating the local clock signal by delaying the global clock signal by the delay time after the global clock signal arrives at the module via one of the first and second transmission lines; 9. The delay means according to claim 8, wherein the delay time is controlled according to the magnitude of the second signal supplied as an input to the delay means. apparatus. The means for generating the second signal comprises:
Addressable memory for storing data values at separate addresses;
Means for addressing the addressable memory in accordance with the magnitude of the first signal such that the addressable memory reads the addressed one of the stored data values;
12. A device according to claim 11, comprising means for generating a magnitude of the second signal in accordance with the read data value. An apparatus for generating a separate local clock signal in each of a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, wherein the local clock signals are substantially mutually connected In phase,
A first transmission line for transmitting the global clock signal from the clock signal supply source to each module;
Associated with each module is a first for the associated module by delaying the global clock signal by a first delay time adjustable when arriving at each module via the first transmission line. First delay means for generating a local clock signal;
Associated with each module is a second local clock signal at the module by delaying the global clock signal by a second delay time that is adjustable when arriving at each module via the second transmission line. A second delay means for generating
Accompanying each module is adjusting the first and second delay times of the first and second delay means associated with the module to adjust the first and second local clocks of the associated module. Comprising means for providing a predetermined phase relationship between the signals,
The global clock signal propagation speed of the first transmission line is M times the global clock signal propagation speed of the second transmission line (M is a number that varies substantially from 1). . 14. The ratio of claim 13 wherein the ratio of the second delay time of the second delay means to the first delay time of the first delay means is substantially equal to M. apparatus. In a synchronous logic system comprising a host unit and a plurality of logic modules remote from the host unit, wherein the host unit includes a clock signal source for generating a global clock signal, a separate local clock for each module A method for generating a signal and for transmitting a data signal between the host unit and each module, comprising:
Transmitting the global clock signal from the clock signal supply source to each module via a transmission line;
Detecting the length of the transmission line between the clock signal supply source and each module;
The global clock signal is delayed in the module by delaying the global clock signal by a delay time that is a function of the detected transmission line length between the clock signal source and the module when arriving at each module via the transmission line. A process of generating a clock signal;
Transmitting a data signal via a data line between each of the host unit and the module;
Delaying the data signal in each of the modules by the delay time that is a function of the detected transmission line length between the clock signal source and the module. Generating a separate local clock signal in response to a global clock signal generated by a clock signal source within a host unit of the synchronous logic system in a plurality of modules of the synchronous logic system; A device for transmitting a data signal between the module and the module,
A first transmission line for transmitting the global clock signal from the clock signal supply source to each module;
A second transmission line for transmitting the global clock signal from the clock signal supply source to each module and the first and second transmission lines;
A data line for transmitting the data signal between each of the host unit and the module;
Attached to each module to detect a phase difference between the global clock signals arriving at the attached module on the first and second transmission lines;
By delaying the global clock signal arriving at one of the first and second transmission lines by the associated module by a delay time that is a function of the detected phase difference, a local clock is produced by the associated module. An apparatus comprising: a deskew means for generating a signal; and transmitting the data signal between the data line and the associated module with a delay amount equal to the delay time. The first and second transmission lines and the data line have substantially the same length between the clock signal supply source and each module, but the global clock signal propagation speed of the first transmission line is the second. M times the global clock signal propagation speed of the transmission line (M is a number other than 1), and the data signal propagation speed of the data line is substantially equal to the speed of the first transmission line. The apparatus according to claim 16 . Generating a separate local clock signal in each of a plurality of modules of the synchronous logic system in response to a global clock signal generated by a clock signal source, and data between the host unit and each of said modules An apparatus for transmitting a signal,
A first transmission line for transmitting the global clock signal from the clock signal supply source to each module;
A second transmission line for transmitting the global clock signal from the clock signal supply source to each module;
First for each attached module by delaying said global clock signal by a first delay time adjustable upon arrival at each module via said first transmission line. First delay means for generating a local clock signal of:
A second local for each module is attached to each module by delaying the global clock signal by a second delay time that is adjustable upon arrival at each module via the second transmission line. Second delay means for generating a clock signal;
A third delay means attached to each module for delaying the data signal by the adjustable first delay time between the data line and the attached module;
Associated with each module is a means for adjusting the first and second delay times and providing a predetermined phase relationship between the first and second local clock signals of the associated module. Consisting of
The global clock signal propagation speed of the first transmission line is M times the global clock signal propagation speed of the second transmission line (M is a number that substantially changes to 1 or more ), and An apparatus characterized in that a signal propagation speed is substantially equal to a propagation speed of the first transmission line, and a ratio of the second delay time to the first delay time in each module is substantially equal to M. . An apparatus for generating an output signal representing the magnitude of signal skew in a first transmission line,
A pulse generator circuit for generating electrical pulses;
A phase detection circuit;
A first transmission line for transmitting the pulse from the pulse generator circuit to the phase detection circuit;
A second transmission line for separately transmitting the pulses from the pulse generator circuit to the phase detection circuit;
The first and second transmission lines have the same length but different signal propagation speeds between the pulse generator circuit and the phase detection circuit;
The phase detection circuit generates an output signal representative of a phase difference between the arrival times of the pulses on the first and second transmission lines;
The apparatus wherein the phase difference is proportional to the magnitude of signal skew on the first transmission line between the pulse generator circuit and the phase detection circuit.

Images