JP3856559B2 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Description

【００４１】
図８は図７の実施例でセルアレイを構成した場合において、書込時における非選択ビットの電子放出及び電子注入を矢印で表す図であり、（Ａ）は選択ビットと同じワードライン上（同じ制御ゲート電極４上）の非選択ビットの様子、（Ｂ）は選択ビットと同じビットライン上（同じ選択ゲート電極６上）の非選択ビットの様子を表す。
【００４２】
図８（Ａ）において、制御ゲート電極４に正電位が与えられているため、絶縁膜１３と絶縁膜１２を介して制御ゲート電極４と選択ゲート電極６と基板１がカップリングし、浮遊ゲート電極５から制御ゲート電極４へトンネル電流が流れることが懸念される（図中矢印）。これについては、図５の実施例では表１に示す電気的手段の範囲でそれほど問題にはならないことがわかっているが、図６の参考例の構造では制御ゲート電極４と選択ゲート電極６と基板１のカップリングが低いため懸念されるところである。そこで、絶縁膜１３を酸化膜、窒化膜及び酸化膜の３層膜からなるＯＮＯ積層膜で構成し、電流が流れにくくすることが好ましい。
【００４３】
図８（Ｂ）において、選択ゲート電極６に負電位が与えられているため、選択ビット、非選択ビットを問わず少なからず選択ゲート電極６から基板１にトンネル電流が流れる（図中矢印イ）。これについて、表１に示す電気的手段の範囲では書込時にはほとんど問題にはならないことがわかっているが、長期的に見るとストレスリークなどの信頼性が若干懸念されるところである。また、選択ゲート電極６から浮遊ゲート電極５への過剰書込（図中矢印ロ）については、ほとんど問題にならないことがわかっている。また、浮遊ゲート電極５からウェル基板１への電子放出（ディスターブ：図中矢印ハ）も若干懸念されているところである。
【００４４】
図９は、Ｐ型シリコン基板１にジャンクション位置が数ミクロン程度の深いdeep-Ｎウェル１nを形成し、さらにその中にＰウェル１ｐを形成し、その上部にＮ型のメモリ素子（拡散層がＮ型）を形成した実施例を表す図である。この構造によれば、メモリ素子を配置しているウェル１ｐが基板１と電気的に分離されているため、これを浮遊電位にすることによって上記問題を解決することができる。
【００４５】
半導体記憶装置の場合、チャージポンプ回路やメモリ駆動用回路（例えばＣＭＯＳ回路）を同じ基板内に内蔵しなければならないので、少なくともＰウェル及びＮウェルが必要となる。加えて図９の実施例ではdeep-Ｎウェルが必要であるため、３つのウェルを作る必要がある。これはトリプルウェルと呼ばれる難度の高い技術であり、またコスト的にも若干不利なところもある。従って、この技術を採用するか否かは適宜その用途によって定めればよい。
【００４６】
図９の実施例において、浮遊ゲート電極５と制御ゲート電極４間の絶縁膜１３（容量Ｃa，平均膜厚Ｔa）と、浮遊ゲート電極５と選択ゲート電極６間の絶縁膜１４（容量Ｃb，平均膜厚Ｔｂ）との間に、
ＣbＴb ＜ ＣaＴa
なる関係が満たされていることが好ましい。
【００４７】
すなわち、絶縁膜１４を介して、浮遊ゲート電極５−選択ゲート電極６間のポリ−ポリ間トンネル書込を行うためには、少なくとも絶縁膜１３より絶縁膜１４の方に高電界を印加しなければならない。従って、書込時に絶縁膜１３，１４にセルフバイアスされる電圧をそれぞれＶａ，Ｖｂとすれば、
Ｖａ／Ｔａ＜Ｖｂ／Ｔｂ
なる条件が必要である。図９の実施例の装置の場合、メモリを構成しているウエル領域１ｐがシリコン基板１と電気的に分離されているため、トンネル消去時にウエル１ｐ、ソース２及びドレイン３の電位を浮遊電位にしておけば良く特別な設定がいらない。従って、浮遊ゲート電極５に電子がチャージされていない簡単な場合を考えると、大まかに下式が成立する。
Ｃａ・Ｖａ＝Ｃｂ・Ｖｂ
よって、下式を得る。
Ｃｂ・Ｔｂ＜Ｃａ・Ｔａ
【００４８】
実際には、上記の関係が顕著である（Ｃｂ・Ｔｂ≪Ｃａ・Ｔａ）ほど、書込動作は容易であり、選択ゲート電極６−制御ゲート電極４間の印加電圧をより低電圧化できる。また、書込時に電位差を正電圧、負電圧の２つに分配することができる点を考慮すれば、結果的に昇圧回路をより低電圧化でき回路負担を低減できる。
【００４９】
また、図９の実施例において、制御ゲート電極４−浮遊ゲート電極５間の酸化膜１３（面積Ｓa）と、浮遊ゲート電極５−選択ゲート電極６間の酸化膜１４（面積Ｓｂ）との間に、
Ｓb＜Ｓa
なる関係が満たされていることが好ましい。ここで、面積Ｓa、Ｓbとはシリコン酸化膜の平均膜厚換算での容量面積を示す。
【００５０】
すなわち、浮遊ゲート電極５−選択ゲート電極６間の酸化膜１４でポリポリ間トンネルが起こるためには、少なくとも酸化膜１３より酸化膜１４に高電界を印加されねばならないので、Ｃｂ・Ｔｂ＜Ｃａ・Ｔａ の関係がある。そして、どちらの絶縁膜も
Ｓｂ＜Ｓａ
実際には、上記の関係が顕著である（Ｓｂ≪Ｓａ）ほど、書込動作は容易であり、選択ゲート電極６−制御ゲート電極４間の印加電圧をより低電圧化できる。
【００５１】
図１０は図９の実施例における、メモリ消去動作時の各部の電位を表したものであり、（Ａ）は浮遊ゲート電極５からドレイン３へのトンネル電子放出を概略的に表す断面図、（Ｂ）は浮遊ゲート電極５からウェル１ｐへのトンネル電子放出を概略的に表す。図１０（Ａ）において、制御ゲート電極４に負電位、ドレイン３に正電位を与える。その結果、浮遊ゲート電極５からドレイン３にトンネル電子放出が起こる。このとき、ソース２及び選択ゲート電極６は浮遊電位にしておけばよい。このような電気的手段の場合、制御ゲート電極４とドレイン３間に印加された電位差は、制御ゲート電極４−浮遊ゲート電極５間の絶縁膜１３の容量と、浮遊ゲート電極５−基板ウェル１ｐ間の絶縁膜１２のゲート電極オーバラップ部分（浮遊ゲート電極５とドレイン３のオーバーラップ部分）の容量との間で分配される。従って、容量の小さい浮遊ゲート電極５−ドレイン３間にその電位差の大部分がかかる（カップリング比が高い）ことになる。この実施例ではトリプルウェルを示しているが、この場合は基板ウェル１ｐが浮遊電位状態でなくても良好に動作するので、通常のウェルであっても問題はない。以下にこの実施例に基づいた電気的手段の参考値を示す。
【００５２】
【表２】

【００５３】
図１０（Ｂ）において、制御ゲート電極４に負電位、ウェル１ｐに正電位を与える。その結果、浮遊ゲート電極４からウェル１ｐにトンネル電子放出が起こる。このとき、ソース２及び選択ゲート電極６は浮遊電位にしておけばよい。このような電気的手段の場合、制御ゲート電極４とウェル１ｐ間に印加された電位差は、制御ゲート電極４−浮遊ゲート電極５間の絶縁膜１３の容量と、浮遊ゲート電極４−ウェル１ｐ間の絶縁膜１２の容量との間で分配される。この場合、ドレイン３へのトンネル消去に比べカップリング比は小さくなる。しかし、この実施例の構造では絶縁膜１３の容量を非常に大きくとれるので、この方式が可能となる。但し、この場合は基板とは分離されたウェルが必要となる。以下に実施例に基づいた電気的手段の参考値を示す。
【００５４】
【表３】

【００５５】
図１１は図９の実施例における、メモリアクセス（読出）動作時の各部の電位を表したものである。読出方式はソース２とドレイン３を事実上反対にして行う。これは読出ディスターブの低減を図るためである。また図１１の実施例ではトリプルウェルを示しているが、この場合は基板ウェルが浮遊状態でなくても良好に動作するため、通常のウェルであっても問題はない。以下に実施例に基づいた電気的手段の参考値を示す。
【００５６】
【表４】

【００５７】
本発明の半導体記憶装置は、メモリ素子のソース及びドレインをチャネル幅方向に拡散層配線で連結(コンタクトレス化されたビットライン)し、またこれと同方向に選択ゲート電極（ソース／ドレインと同様にビットラインとして作用する）が連結し、またこれと直交する方向(チャネル長方向)に制御ゲート電極を連結(ワードライン)して、半導体メモリ素子をアレイ配置し、ビットラインとワードラインとによりマトリックス選択が可能となっている。
【００５８】
図１２及び図１３に本発明の装置のそれぞれの実施例の概略図を示す。それぞれ（Ａ）は平面図、（Ｂ）は（Ａ）のＳ−Ｓ’線位置での断面図、（Ｃ）は（Ａ）のＣ−Ｃ’線位置での断面図である。図１２、図１３共に図５の実施例をアレイ化した場合を例に取っているが、例えば図６の例をアレイ化してもよいし、これに限られるものではない。
【００５９】
この装置では、図１２又は図１３に示すように、ライン状の制御ゲート電極４がワードラインを構成し、ソース２及び／又はドレイン３がこれに対し直交する方向に配されるビットラインを構成し、ライン状の選択ゲート電極６がビットラインと同方向に配されている。選択ゲート電極６方向に並ぶメモリ素子は素子分離膜１５により分離されている。このような配置にすることにより、メモリアレイ内のあるメモリ素子の選択（アクセス）は制御ゲート電極４（ワードライン）と拡散層２及び３（ビットライン）のマトリックス選択により可能となる。このとき選択ゲート電極６は擬似的なビットラインとして作用し、アクセス前に予め所望の正電位（表４のバイアス条件参照）に設定しておくことでメモリアクセスの時間を短縮させる効果も持っている。
【００６０】
ここで、図１２は一般にVirtual-Ground-Array(仮想グランドアレイ)方式に属するものであり、ソースライン２とドレインライン３が交互に配置され、ワードライン(制御ゲート電極ライン４)方向に隣り合うメモリ素子同士において、一方の素子のソース２と他方の素子のドレイン３が共通となっている。従って、選択される素子によって、動作上のソースとドレインが決定される。即ち、通常メモリアクセス時にグランド電位にされるソース(本装置ではリードディスターブ抑制のため図中符号３のドレインがソースとして使われる)が、選択されるメモリの位置によって交代するものである。このようなアレイ配置では図１３のそれと比して、全てのセルが同方向を向いているのでそれに関するデバイス特性のバラツキが無いという利点が有る。また、選択ゲート電極６のライン／スペースが一定であり、段差の低い部分(選択ゲート電極トランジスタの上部)に制御ゲート電極４のポリシリコン膜を埋め込むことができ、トータル段差低減、プロセスの容易化に有利という点がある。
【００６１】
消去動作においては、全ての拡散層(ソース２及びドレイン３)を所望の共通正電位にしておけばワードライン(制御ゲート電極ライン４)上の素子群を一括消去できる。
書込動作においては、１つのビットライン(選択ゲート電極ライン６)上の素子群において、書込(電子注入)が必要なビットの制御ゲート電極４を所望の共通正電位にしておけば１つのビットライン上の素子群を一括書込できる。或いは、１つのワードライン(制御ゲート電極ライン４)上の素子群において、書込(電子注入)が必要なビットの選択ゲート電極６を所望の共通負電位にしておけば１つのワードライン上の素子群を一括書込できる。このような一括書込が可能になるのは、ゲート電極間でのポリ−ポリ間トンネル電流書込方式であるが故であり、本発明の重要な特徴の一つである。
【００６２】
また、図１２のような本発明の素子構造・アレイ配置及び電気的手段によると、上記に説明したマトリックス選択、一括消去、一括書込の全てを同時に実現できることがわかる。
また、このセルアレイの場合、アクセスする選択ビットによって、チャネル幅方向(図中（Ａ）縦方向)に延びるソースライン２とドレインライン３が順次切り替わる。ソースとドレインのどちらか一方(一般的にはソース)はグランド電位で使用されるのが普通であり、この配列では選択ビットによってグランド電位に当たるラインが切り替わるため仮想グランド型と言われる。
【００６３】
図１３はコンタクトレスＮＯＲ型に属すが、ソースライン２とドレインライン３が交互に配置され、ソースもドレインもワードライン(制御ゲート電極ライン４)方向に隣り合うメモリ素子間で共通となっている。従って、図１２の場合のように選択される素子によって、動作上のソース２とドレイン３が入れ替わることはなく、拡散層ラインは選択ビットによって切り替わらず固定されていて、電気的手段の設定も容易であるという利点がある。これも図１２の場合と同様に、各素子のソース及びドレインがチャネル幅方向に拡散層配線（コンタクトレス化されたビットライン）で連結され、ビットラインと同方向に選択ゲート電極６（これもビットラインとして作用する）が連結され、さらにビットラインと直交する方向（メモリ素子のチャネル長方向）に制御ゲート電極４（ワードライン）が連結されている。このような配置にすれば、書込時、消去時又はアクセス（読出）時に、ビットラインとワードラインとにより、各メモリ素子のマトリックス選択が可能となる。
【００６４】
消去動作においては、ドレイン３を全て共通の正電位にしておけば、選択したワードライン(制御ゲート電極ライン４)上の素子群を一括消去できる。ここで、図１３の実施例では、図１２の実施例と異なり、拡散層ラインは選択ビットによって切り替わらず固定される。
書込動作においては、１つのビットライン(選択ゲート電極ライン６)上の素子群において、書込(電子注入)が必要なビットの制御ゲート電極４を所望の共通正電位にしておけば１つのビットライン上の素子群を一括書込できる。或いは、１つのワードライン(制御ゲート電極ライン４)上の素子群において、書込(電子注入)が必要なビットの選択ゲート電極６を所望の共通負電位にしておけば１つのワードライン上の素子群を一括書込できる。
【００６５】
図１２及び図１３のメモリアレイは、フラッシュメモリの分類上はＮＯＲ型に属する。一般にＮＯＲ型のアレイはＥＴＯＸ型やＳＳＴ型に代表されるように、ドレインコンタクト（ビットラインのコンタクト）が必要であり、高速アクセスが可能であるが集積度向上に不利と言われてきた。これに対し、本発明ではＳunＤisk型やＢＭＩ型と同様に拡散層配線を採用することでこれを回避し、高集積化に極めて有利な構造をしている。拡散層配線はコンタクト及びメタルによる配線に比べて抵抗が高いので高速アクセスに不利となる場合があるが、ある周期毎(例えば３２ビット周期毎)にコンタクトを設け、メタル配線で裏打ちすることによりこれを回避できる。
【００６６】
図１４は図５のメモリ素子を製造するプロセスを示す工程断面図である。
（Ａ）写真製版技術、イオン注入技術、拡散技術等の公知技術を用いて、シリコン基板上にウェル１や素子分離用のフィールド酸化膜を形成したあと、基板(ウェル)１表面にゲート酸化膜１１を形成する。次に選択ゲート電極６用のポリシリコン層及び絶縁層１６を形成し、これをライン状(選択ゲート電極ライン)に加工する。
【００６７】
（Ｂ）写真製版工程、不純物イオン注入工程により、フォトレジスト２０をマスクとしてソース２，ドレイン３用の不純物導入を行う。
（Ｃ）不要な酸化膜の除去を行ったあと、酸化工程によりソース・ドレイン用の不純物拡散層上の絶縁酸化膜１７とトンネル酸化膜１２と酸化膜１４を同時に形成する。ここでの酸化工程は不要酸化膜(プリゲート酸化膜等)の除去を含め複数回であっても良く、また、メモリ周辺のトランジスタ形成等を考慮すると、この工程の間に写真製版工程が必要な場合もある。従って、酸化膜１２，１４，１７の膜厚バランスは、そのトータルのプロセスの設計に盛り込んで整合されるものである。ちなみに、シリコン基板上の酸化膜１２より、ポリシリコン酸化膜１４の方が厚く形成され、さらに拡散層上の酸化膜１７はシリコン基板上の酸化膜より数倍厚く形成されるのが普通である。この実施例ではこれをうまくプロセスを利用している。また、この酸化工程は拡散層のドライブ・活性化を兼ねている。
【００６８】
（Ｄ）浮遊ゲート電極５用のポリシリコン層を形成し、これを写真製版技術及びドライエッチング技術によって、チャネル幅方向（図中紙面に垂直な方向）に平行な帯状に加工する。次に酸化膜、窒化膜、酸化膜の３層膜からなるＯＮＯ積層膜１３を形成する。ここでの酸化膜は酸化又は高温ＣＶＤ技術によって形成する。窒化膜は例えばＣＶＤ膜である。
【００６９】
（Ｅ）制御ゲート電極４用のポリシリコン膜を形成し、これを写真製版技術及びドライエッチング技術によってチャネル長方向(図中横方向)に加工するに加工する。この際、工程（Ｄ）で帯状に加工した浮遊ゲート電極５用ポリシリコン膜及びＯＮＯ積層膜１３を同一マスク下で方形状に加工して所望の形状を得て、それぞれのメモリ素子領域で分離して形成する。
制御ゲート電極４用ポリシリコン層上に予め低抵抗化用のシリサイド層やその保護層を形成しておくことが好ましい。
【００７０】
絶縁膜１４はトンネル膜として使用するので、実施例では酸化膜を用いている。この膜厚は１５〜４０ｎｍ程度でよい。また、絶縁膜１３は消去時、書込時、読出時においてカップリング用の重要な絶縁膜であり、容量が大きく(容量膜厚が小さく)、電流が流れない(電荷リークが少ない)ことが必要であるので、ＯＮＯ積層膜が極めて適している。実施例では、例えば、４〜８ｎｍ(トップ酸化膜)／４〜１６ｎｍ(窒化膜)／４〜８ｎｍ（ボトム酸化膜）程度の膜厚を用いている。
【００７１】
図１５は図４のメモリ素子を製造するプロセスを示す工程断面図である。
（Ａ）図１４の工程（Ａ）と同様にして、ウェル１、フィールド酸化膜、ゲート酸化膜１１、選択ゲート電極６及び絶縁層１６を形成する。
【００７２】
（Ｂ）不要な酸化膜の除去を行ったあと、酸化工程によりトンネル酸化膜１２，１４を同時に形成する。ここでの酸化工程は図１４の工程（Ｂ）と同様に、不要酸化膜の除去を含め複数回であっても良く、また、メモリ周辺のトランジスタ形成などを考慮するとこの間に写真製版工程を行なう場合もある。したがって、酸化膜１２，１４の膜厚バランスはそのトータルのプロセスの設計に盛り込んで整合されるものである。ここでも酸化膜１４は酸化膜１２より厚く形成される。次に、浮遊ゲート電極５用のポリシリコン層を形成し、その上にＯＮＯ積層膜１３用のボトム酸化膜及び窒化膜からなる積層膜１３ａを形成する。この酸化膜は酸化又は高温ＣＶＤ技術によって形成する。窒化膜はＣＶＤ膜である。次に、写真製版技術及びドライエッチング技術により、浮遊ゲート電極５用のポリシリコン層及び積層膜１３ａをチャネル幅方向(紙面垂直方向)に帯状に加工する。次に、同一マスクを用いて、拡散層用の不純物イオン注入を行う。
【００７３】
（Ｃ）ＯＮＯ膜１３用のトップ酸化膜、浮遊ゲート電極５側面の酸化膜１３ｂ、選択ゲート電極６側面の酸化膜１４ｂ及び拡散層上の酸化膜１７を、１回のＣＶＤ酸化膜形成工程と１回の酸化処理工程により同時に形成する。例えば、まず、ＣＶＤ膜の１種である高温酸化膜を５ｎｍ程度形成した後、１回の酸化処理を施すと、トップ酸化膜が５ｎｍ程度、浮遊ゲート電極側面の酸化膜１３ｂが１５ｎｍ程度、選択ゲート電極側面の酸化膜１４ｂが１５ｎｍ程度、拡散層上の酸化膜１７が２０ｎｍ程度の膜厚で形成されることがわかっている。また、この酸化膜形成工程は拡散層のドライブ・活性化を兼用している。
【００７４】
（Ｄ）制御ゲート電極４用のポリシリコン膜を形成し、これを写真製版技術及びドライエッチング技術によってチャネル長方向に加工する(図中横方向)に加工する。この際、工程（Ｂ）で帯状に加工した浮遊ゲート電極５用ポリシリコン膜を同一マスク下で方形状に加工して所望の形状を得て、それぞれのメモリ素子領域で分離して形成する。
図１４及び図１５に示した実施例のプロセスは一例であり、本発明のプロセスはこれに限るものではない。
【００７５】
【発明の効果】
本発明のメモリ素子は選択ゲート電極を持つため、過剰消去の問題がなく、低電圧化や多値化が容易であり、ポリシリコン−ポリシリコン間トンネル書込のため、ＣＨＥ方式やＳＳＩ方式に比べ遥かに電流容量が小さいので消費電力が小さくて済み、チャージポンプの昇圧が容易となり単一電源化が容易に図れる。さらに、チャージポンプのキャパシタ面積の低減が図れることから、高集積化に寄与し、集積度の向上が図れる。
書込と消去とでは別々のトンネル膜を用いるので、装置仕様の設計・製造が容易であり、さらに、トンネル酸化膜の高い信頼性及び耐久性を得ることができる。
浮遊ゲート電極と制御ゲート電極間の絶縁膜の容量面積が大きく、書込時又は消去時のカップリング比が大きいので、低電圧化が容易である。また、カップリング比を若干許容すると、浮遊ゲート電極と制御ゲート電極間の絶縁膜の信頼性向上を図ることができる。さらに、カップリング比を若干許容すると、書込時或いは消去時に用いるトンネル膜の膜厚を相対的に大きくでき、信頼性向上を図ることができる。
【００７６】
本発明のメモリ素子をアレイ状に配置する際に、ドレイン拡散とソース拡散のうち少なくともソース拡散、好ましくはドレイン拡散も連続して配列された複数のメモリ素子で共通に使用されるように連続した拡散層として形成し、選択ゲート電極をソース拡散と平行な方向のライン状に形成し、かつ、制御ゲート電極を制御ゲート電極と直交する方向のライン状に形成する。そして、ソース拡散及びドレイン拡散を、それらを挟んで隣り合うメモリ素子により共有化されるように配置してコンタクトレス構造にするか、又はソース拡散とドレイン拡散を交互に配置してコンタクトレス構造で仮想グランド型アレイ方式とすることにより、集積度の向上、大容量化に寄与することができる。
同一のワードライン上のメモリ素子群を一括消去することができるので、複数のワードライン上の素子群をブロック化すると、一括高速消去を行なうことができる。さらに、同一ワードライン上の素子群、又は同一ビットライン上の素子群を一括消去できるので、プログラミング時間を事実上短縮でき、高速書込を実現することができる。このように、本発明は一括高速消去及び高速書込が同時に可能であり、さらに、消去時、書込時又は読出時のいずれの場合においても、１素子のマトリックス選択が可能であるため、種々の仕様のメモリチップに対応でき、多品種生産にも容易に対応できる。
【図面の簡単な説明】
【図１】 従来のＥＴＯＸ型メモリ素子アレイを示す図であり、（Ｃ）は平面図で、（Ａ）は（Ｃ）におけるＡ−Ａ’線位置での断面図、（Ｂ）は（Ｃ）におけるＢ−Ｂ’線位置での断面図である。
【図２】 従来のＳｕｎＤｉｓｋ型メモリ素子アレイを示す図であり、（Ｃ）は平面図、（Ａ）は（Ｃ）におけるＡ−Ａ’線位置での断面図、（Ｂ）は（Ｃ）におけるＢ−Ｂ’線位置での断面図である。
【図３】 従来のＳＳＴ型メモリ素子アレイを示す図であり、（Ｃ）は平面図、（Ａ）は（Ｃ）におけるＡ−Ａ’線位置での断面図、（Ｂ）は（Ｃ）におけるＢ−Ｂ’線位置での断面図である。
【図４】 従来のＢＭＩ型メモリ素子アレイを示す図であり、（Ｃ）は平面図、（Ａ）は（Ｃ）におけるＡ−Ａ’線位置での断面図、（Ｂ）は（Ｃ）におけるＢ−Ｂ’線位置での断面図である。
【図５】 一実施例の１つのメモリ素子を示す断面図である。
【図６】 比較例の１つのメモリ素子を示す断面図である。
【図７】 さらに他の実施例の１つのメモリ素子を、メモリ書込動作時の各部の電位とともに示す断面図である。
【図８】 図５の実施例の書込時における非選択ビットのディスターブを矢印で表す断面図であり、（Ａ）は選択ビットと同じワードライン上の非選択ビットの様子、（Ｂ）は選択ビットと同じビットライン上の非選択ビットの様子を表す。
【図９】 さらに他の実施例の１つのメモリ素子をメモリ書込動作時の各部の電位とともに示す断面図である。
【図１０】 図９の実施例における、メモリ消去動作時の各部の電位を表したものであり、（Ａ）は浮遊ゲート電極５からドレイン３へのトンネル電子放出様式を表す断面図、（Ｂ）は浮遊ゲート電極５からウェル１ｐへのトンネル電子放出様式を表す断面図である。
【図１１】 図９の実施例における、メモリアクセス（読出）動作時の各部の電位を表す断面図である。
【図１２】 図５のメモリ素子をアレイ化した一実施例を表す図であり、（Ａ）は平面図、（Ｂ）は（Ａ）のＳ−Ｓ’線位置での断面図、（Ｃ）は（Ａ）のＣ−Ｃ’線位置での断面図である。
【図１３】 図５のメモリ素子をアレイ化した他の実施例を表す図であり、（Ａ）は平面図、（Ｂ）は（Ａ）のＳ−Ｓ’線位置での断面図、（Ｃ）は（Ａ）のＣ−Ｃ’線位置での断面図である。
【図１４】 図５のメモリ素子を製造するプロセスを示す工程断面図である。
【図１５】 図６のメモリ素子を製造するプロセスを示す工程断面図である。
【符号の説明】
１ 半導体基板又はウェル
２ ソース
３ ドレイン
４ 制御ゲート電極
５ 浮遊ゲート電極
６ 選択ゲート電極
１１ ゲート酸化膜
１２，１４ トンネル酸化膜
１３ ＯＮＯ膜
１６，１７ 絶縁膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device that has a floating gate and is electrically rewritable and erasable, and relates to a memory device called an EEPROM or a flash EEPROM (also called a flash memory). The EEPROM and the flash memory are suitable for use in, for example, an electronic notebook, a telephone, a voice recognition / storage device, a storage device of a signal processing circuit in a computer, a storage device of a portable device, and the like.
[0002]
[Prior art]
Among nonvolatile semiconductor memory devices that can be electrically rewritten and erased, flash memory has attracted attention in recent years, and development for mass production has been actively conducted throughout the industry. Conventional EEPROM is generally based on single-bit erasing, whereas flash memory is predicated on erasing in units of blocks, and is difficult to use. However, by adopting single-bit single element or block erasing, etc. It is attracting attention as a next-generation memory that can be expected to have a degree of integration comparable to or higher than DRAM, and its market size is immeasurable.
[0003]
Various structures and systems have been proposed by various companies so far for flash memories, but floating gate type nonvolatile memory elements are generally used. In a floating gate type nonvolatile memory element, a threshold voltage that holds a charge in a floating gate electrode surrounded by an insulator and forms a channel between a source and a drain when a bias is applied to the control gate electrode, This is common in that data is stored by utilizing the change in the amount of electric charge in the floating gate electrode. However, writing and erasing methods differ depending on each method.
[0004]
The most commonly known one is the so-called ETOX type (also called NOR type) shown in FIG. (C) is a top view of the memory element array, (A) is a sectional view taken along the line AA ′ in (C), and (B) is a sectional view taken along the line BB ′ in (C). FIG. In the ETOX type, a floating gate electrode 105 is formed on a channel formation region between the source 102 and the drain 103 formed on the semiconductor substrate 101 via a gate insulating film, and further on the control gate via an insulating film. An electrode 106 is formed. Reference numeral 115 denotes a field oxide film that separates adjacent memory elements.
[0005]
Data writing is performed by injecting hot electrons generated on the drain side of the channel when a current is passed through the channel into the floating gate electrode 105. Data is erased by extracting electrons to the source 102 by a current (FN current) that flows through the gate insulating film when a high electric field is applied between the floating gate electrode 105 and the source 102. Yes. Reading is performed by identifying whether or not electrons move from the source 102 to the drain 103 through the channel when the control gate electrode 106 is biased. In FIG. 1 and other drawings as well, arrows in the drawing indicate W for writing, E for erasing, and R for electron movement during reading.
[0006]
The feature of this memory element is that the structure is simple. However, since the writing is performed by hot electrons generated on the drain side of the channel, the ratio of the current injected into the floating gate electrode to the channel current is low. In other words, there is a problem in that the writing efficiency is low and it is difficult to make a single power source, and there is a problem that over-erasing occurs due to the structure without the selection transistor, which is extremely in terms of process and circuit. Advanced ones are required.
[0007]
FIG. 1C shows a state in which the memory elements are arranged in an array as cells. Each memory cell is separated by a field oxide film 115, and the source 102 is a diffusion layer (in the channel width direction). Are connected by a source line) to be at a common potential. The control gate electrode 106 extends in a line in parallel with the source line 102 and is common to the cells in this direction, thereby forming a word line. The drain 103 is connected to a line-shaped metal electrode (referred to as a bit line) 124 orthogonal to the word line via a contact hole 121. The selection of a specific cell among the cells arranged in an array is performed by selecting the word line 106 and the bit line 124 in a matrix. As described above, since the ETOX type cell requires a contact hole in the drain, an area is required in this portion, and the area per memory element becomes large for a simple cell structure. is there.
[0008]
As a method for partially solving these drawbacks, a structure and method of the SunDisk type (see US Pat. No. 5070032 and US Pat. No. 5,198,380), a structure and method of the SST type (US Pat. No. 5,029,130, US Pat. No. 5,045,488, U.S. Pat. No. 5,067,108), BMI type structure / method (see U.S. Pat. No. 5,280,446), and the like. Common to these three is that a floating gate electrode is formed adjacent to the drain and separated from each other by a distance from the source, and the substrate surface between the floating gate electrode and the source is selected. As a channel, a gate insulating film is formed on the select channel, and a select gate electrode (also referred to as a select gate electrode) is arranged from the upper part of the floating gate electrode to the select channel. It has a structure that is extremely advantageous for low voltage and multi-value. These are different from each other only in the cell structure, the array arrangement, and the erasing / writing method. Each is briefly described below.
[0009]
The SunDisk type is shown in FIG. (C) is a top view of the memory element array, (A) is a sectional view taken along the line AA ′ in (C), and (B) is a sectional view taken along the line BB ′ in (C). FIG. The control gate electrode 204 covers the floating gate electrode 205 and also serves as a selection gate electrode, and extends in the channel length direction (direction from the source 202 toward the drain 203) to form a word line. Sources 202 and drains 203 are alternately arranged, and both extend in a direction perpendicular to the word line 204 to form a bit line. This memory array system employs a so-called virtual ground array system in which the source and drain are changed depending on the cell position selected in the matrix.
[0010]
Further, an erase gate electrode 207 arranged in a line so as to be sandwiched between the word lines 204 is provided. The floating gate electrode 205, the control gate electrode 204, and the erase gate electrode 207 are formed of different polysilicon layers, and have a three-layer polysilicon structure.
[0011]
Writing is the most common CHE injection method (hot electron injection from the drain side), and erasing is a poly-poly (polysilicon-polysilicon) FN tunnel emission from the floating gate electrode 205 to the erase gate electrode 207. The method is adopted. Reading is performed with the source and drain reversed. This is because it is advantageous in suppressing read disturb (a phenomenon in which hot electrons are injected into the floating gate electrode during reading).
[0012]
The feature of the SunDisk type is that it has a select gate electrode, is a virtual ground type array system, and simultaneously realizes poly-poly FN erasure. As an advantage of this method,
1) Since the selection gate electrode is provided, there is no problem of over-erasing, and low voltage and multi-value are easy.
2) Since it is a virtual ground type array system, miniaturization and capacity increase are easy. Disadvantages include the fact that the normal CHE writing method is used, so that the injection efficiency is poor and it is difficult to achieve a single power source.
[0013]
The SST type is shown in FIG. (C) is a top view of the memory element array, (A) is a sectional view taken along the line AA ′ in (C), and (B) is a sectional view taken along the line BB ′ in (C). FIG. The control gate electrode 306 rides on the floating gate electrode 305 via the interlayer insulating film and extends on the select channel, so that it also serves as the select gate electrode, and the channel width direction (direction perpendicular to the direction from the source 302 to the drain 303) It extends to the word line. The source 302 extends in a direction parallel to the word line 306, and the drain 303 is connected to a line-shaped metal electrode (bit line) 324 orthogonal to the word line 306 through a contact hole 321.
[0014]
Writing employs an SSI (Source Side Injection) method with high injection efficiency, and erasing employs a poly-poly FN tunnel emission method from the floating gate electrode to the control gate electrode. Here again, the source and the drain are used in the opposite direction for reading in order to be advantageous for read disturb.
As a feature, it has a select gate electrode, SSI writing method is possible, two-layer polysilicon process (no polysilicon layer dedicated for erasure), and simultaneously realizing poly-poly FN erasure It is.
[0015]
As an advantage of this method,
1) Since it has a select gate electrode, there is no problem of over-erasing, and it is easy to reduce voltage and multi-value.
2) Since the SSI writing method is possible, the injection efficiency is high, and it is advantageous for a single power supply.
3) It has a two-layer polysilicon structure and is easy to process.
Etc.
[0016]
As a disadvantage,
1) This method uses a capacitive coupling (coupling) between the floating gate electrode and the drain, and since the drain is largely overlapped with the floating gate electrode, there is an increase in the size of the portion.
2) The memory channel length (channel length under the floating gate electrode) and the select channel length are not self-aligned,
3) It is disadvantageous for reducing the cell size and increasing the capacity from various aspects such as an array of NOR type structure that requires a drain contact like the ETOX type.
[0017]
The BMI type is shown in FIG. (C) is a top view of the memory element array, (A) is a sectional view taken along the line AA ′ in (C), and (B) is a sectional view taken along the line BB ′ in (C). FIG. The control gate electrode 406 covers the floating gate electrode 405, extends in the channel width direction (a direction orthogonal to the direction from the source 402 to the drain 403) to become a pseudo bit line, and the selection gate electrode 404 covers the channel region. The word line extends in the channel length direction (the direction from the source to the drain), and the source 402 and the drain 403 extend in a direction orthogonal to the word line 404 to become a bit line.
The SSI method with high injection efficiency is used for writing, and the FN erasing method from the floating gate electrode to the drain side is used for erasing. Here again, the source and the drain are used in the opposite direction for reading in order to be advantageous for read disturb.
[0018]
The feature is that it has a select gate electrode, is capable of the SSI writing method, and simultaneously adopts the contactless method using the diffusion layer wiring. The advantage of this method is
1) Since the selection gate electrode is provided, there is no problem of over-erasing, and low voltage and multi-value are easy.
2) Since the SSI writing method is possible, the injection efficiency is high and it is advantageous for the single power supply.
3) Since it is a contactless method using diffusion layer wiring as in the virtual ground type array method, it can be easily miniaturized and increased in capacity as much as the SST virtual ground type array method.
Disadvantages include a three-layer polysilicon structure that has a high gap and is relatively difficult to manufacture.
[0019]
In the above four structures and methods, the SST type and the BMI type use the SSI writing method, and the writing efficiency is relatively higher than the ETOX type or SunDisk type CHE method. However, from the viewpoint of low power consumption and a single power supply, a writing method using a poly-poly FN current having a writing efficiency of 100% is considered to be most effective in the future.
[0020]
[Problems to be solved by the invention]
An object of the present invention is to provide a non-volatile semiconductor memory device that eliminates the drawbacks of some of the structures and systems described in the above prior art and is easy to achieve low voltage, single power supply, and high integration. Specifically, it is a split gate type that is easy to reduce voltage and multi-value, is a writing method using poly-poly FN current that is easy to reduce power consumption and single power supply, and is an erasing method using FN current. Another object of the present invention is to provide a nonvolatile semiconductor memory device having a structure and electrical means that can simultaneously realize a contactless array system that can be easily integrated.
[0021]
[Means for Solving the Problems]
None of the conventional split gate type nonvolatile semiconductor memory devices satisfy the above-described writing method and erasing method at the same time. In addition, no contactless NOR type memory array has been realized while satisfying the aforementioned write / erase scheme. According to the present invention, it is possible to provide a nonvolatile semiconductor memory device that satisfies all of these requirements and is easy to achieve low voltage, single power supply, and high integration.
[0022]
The present invention relates to a split gate type nonvolatile semiconductor memory device that is advantageous for lowering voltage and multi-valued, and has a low power consumption and poly-to-poly tunnel current writing and drain or It has a structure and electrical means satisfying the tunnel current erasure to the well substrate. Further, the present invention has a structure or electrical means for realizing contactless memory array formation (contactless NOR type or virtual ground type) advantageous for high integration while satisfying such functions.
[0023]
Nonvolatile semiconductor according to the present invention Memory In the device, a drain and a source are formed in a semiconductor substrate or well, an insulating film is provided on the substrate or on the well, and a selection gate electrode (split gate) common to a plurality of memory elements with a distance from the drain adjacent to the source. The source diffusion layer portion is provided on an oxide film formed thicker than the gate insulating film, and the selection gate electrode is covered with the upper surface and side surfaces of the selection gate electrode through the insulating film. On the substrate or well between the electrode and the drain diffusion layer, a floating gate electrode is provided adjacent to the drain diffusion layer and separated for each memory element via a gate insulating film. A control gate electrode straddling the floating gate electrode and the selection gate electrode is provided between the floating gate electrode and the floating gate electrode via an insulating film. An electrically erasable nonvolatile semiconductor memory element that performs tunnel current writing between gate electrodes, and an insulating film between the control gate electrode and the floating gate electrode and an insulating film between the floating gate electrode and the selection gate electrode are These three gate electrodes are electrically capacitively coupled, the capacitance between the floating gate electrode and the control gate electrode is Ca, and the average film thickness of the insulating film between them is Ta, and between the floating gate electrode and the selection gate electrode When the capacitance is Cb and the average film thickness of the insulating film therebetween is Tb,
Cb ・ Tb <Ca ・ Ta
Satisfies the relationship.
The well may be electrically separated from the semiconductor substrate.
[0024]
The effects achieved by the present invention are as follows.
1) A split gate electrode type memory device has no problem of over-erasing, and it is extremely easy to reduce the voltage and multi-value.
2) The poly-poly tunnel writing method is a method in which electrons are directly injected, which is very advantageous for a single power source with low power consumption. In addition, for example, since the supply current to the memory can be reduced, such as reduction of the charge pump circuit, the burden on the peripheral booster circuit can be reduced, and it can be said that it is advantageous for lowering the voltage. Since the control of the poly-poly tunnel current is easy to operate, the reliability such as retention resistance and oxide film reliability is high. In recent years, the tunnel oxide film formed on the substrate has been concerned about reliability as the thickness of the tunnel oxide film is reduced. Again, its reliability has been highly evaluated.
3) Contactless bit lines contribute directly to memory size reduction and are extremely advantageous for high integration.
[0025]
FIG. 5 shows a nonvolatile semiconductor memory device as a specific example of the present invention. A source 2 and a drain 3 are formed on a well substrate 1 formed on a semiconductor substrate, and the source 2 and the drain 3 are covered with a thick oxide film 17. A selection gate electrode 6 common to a plurality of memory elements is provided on the well substrate 1 via a gate insulating film 11 and extending in the channel width direction (perpendicular to the plane of the drawing) with a distance from the source 2 adjacent to the source 2. A part of the drain 3 overlaps the well substrate 1 between the selection gate electrode 6 and the drain 3 via the gate insulating film 12, and the upper surface and side surfaces of the selection gate electrode 6 also pass through the insulating film 16 or 14. A floating gate electrode 5 formed separately for each memory element is provided, and an insulating film 13 is provided between the floating gate electrode 5 and an oxide film 17 is provided on the source 2 and the drain 3 via an oxide film 17. A control gate electrode 4 extending in the longitudinal direction and common to a plurality of memory elements is provided. The floating gate electrode 5 is electrically coupled to the control gate electrode 4, the selection gate electrode 6 and the substrate well substrate 1.
[0026]
The poly-poly tunnel current writing, which is one of the features of the present invention, works more effectively under a certain range of film thickness or film thickness ratio between the three gate electrodes. It is supposed to be. More specifically, a structure and electrical means are employed so that electrons can be injected from the selection gate electrode 6 to the floating gate electrode 5.
Similarly, the tunneling current emission to the drain 3 is also caused by a specific insulating film 13 between the control gate electrode 4 and the floating gate electrode 5 and an insulating film 12 between the well substrate 1 and the floating gate electrode 5. It works more effectively under a range of film thickness or film thickness ratio.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
When the memory elements of the present invention are arranged in an array, at least the source of the drain and the source is formed as a continuous diffusion layer so as to be used in common by a plurality of memory elements arranged in succession. Preferably, the gate electrode is formed in a line shape in a direction parallel to the source, and the control gate electrode is formed in a line shape in a direction orthogonal to the selection gate electrode to constitute a word line.
[0028]
Furthermore, the drain is also formed as a continuous diffusion layer in parallel with the source so as to be used in common by a plurality of memory elements arranged in series, and the bit line is connected by the diffusion layer wiring of the source or drain. A contactless structure is preferable. By using a contactless structure, the element can be miniaturized, the degree of integration is improved, and the capacity is increased.
[0029]
It is preferable that the source, the drain, and the floating gate electrode are arranged so that the source and the drain are shared by the memory elements adjacent to each other. This also contributes to an increase in the degree of integration and an increase in capacity.
It is also preferable that the source and the drain are alternately arranged. In that case, it can be used as a memory element array of a virtual ground type array system, which also contributes to an improvement in the degree of integration and an increase in capacity.
[0030]
In the semiconductor memory device of the present invention, at the time of memory writing, a negative potential is applied to the selection gate electrode and a positive potential is applied to the control gate electrode, and tunnel electrons are injected from the selection gate electrode to the floating gate electrode. At that time, the memory elements sharing the selection gate electrode (bit line) or the control gate electrode (word line) can be collectively written.
[0031]
Further, when erasing the memory, it is preferable to apply a negative potential to the control gate electrode and a positive potential to the drain. As a result, tunnel electrons are emitted from the floating gate electrode to the drain. At this time, the memory elements sharing the word line can be erased collectively.
[0032]
Furthermore, it is preferable that a well electrically isolated from the semiconductor substrate is formed in the memory element region, and a negative potential is applied to the control gate electrode and a positive potential is applied to the well during memory erasing. As a result, tunnel electrons are emitted from the floating gate electrode to the well. At this time, the memory elements sharing the word line can be erased collectively.
[0033]
【Example】
FIG. 5 is a cross-sectional view of one memory device representing one embodiment.
On the channel region between the source 2 and the drain 3 formed on the P-type silicon substrate 1, via the gate oxide film 11, adjacent to the source 2 and away from the drain 3, the channel width direction (source 2 to drain) A line-shaped selection gate electrode 6 extending in a direction perpendicular to the direction toward 3 (direction perpendicular to the paper surface) is formed, and a selection channel is formed under the selection gate electrode 6. The well region (gate electrode channel region) between the select gate electrode 6 and the drain 3 is insulated via the oxide film 12, partially overlaps the drain, and insulated from the upper part of the select gate electrode 6 via the insulating film 16. In addition, the side wall of the selection gate electrode 6 is insulated through the insulating film 14, the source 2 and the drain 3 are insulated through the oxide film 17 thicker than the gate oxide film 11, and the selection gate electrode 6 from the gate electrode channel region is insulated. A floating gate electrode 5 is formed so as to be separated from each other and disposed across the top. The floating gate electrode 5 is insulated via an insulating film 13, the source 2 and the drain 3 are insulated via an insulating oxide film 17, and extend across the floating gate electrode 5 and the selection gate electrode 6 in the channel length direction (source 2 A control gate electrode 4 extending in the direction from the first to the third drain 3 and common to a plurality of memory elements is formed.
[0034]
The memory element of the present invention is characterized by having a selection gate electrode 6 that avoids the problem of over-erasing, a control gate electrode 4 that mainly controls the floating gate electrode 5 (programming control), The insulating film 13 between the control gate electrode 4 and the floating gate electrode 5, the insulating film 14 between the floating gate electrode 5 and the selection gate electrode 6, and the insulating film 12 between the floating gate electrode 5 and the well substrate 1 A structure in which the gate electrode and the well substrate 1 are electrically coupled with each other and a structure of an insulating film thickness, and a structure in which tunnel writing between poly-poly and tunnel erasure to the drain or the substrate are possible. It is. In addition, in order for the above three gate electrodes to obtain a desired electrical coupling, the control gate electrode 4 and the selection gate electrode 6 are completely insulated from each other, and the configuration and treatment are such that the electrical coupling is hardly performed. It has been taken. Also, when writing and erasing, Applied In order to efficiently distribute the potential difference to the tunnel film and obtain sufficient coupling, the capacity of the insulating film 13 is the capacity of the insulating film 14 or the gate electrode overlap portion of the insulating film 12 (the floating gate electrode 5 and the drain 3 The structure / arrangement is such that it is sufficiently larger than the capacity of the overlapping part.
[0035]
In the device of the present invention, a poly-poly insulating film (usually an oxide film) 14 between the floating gate electrode 5 and the select gate electrode 6 is used as a tunnel film. By using the corner portion of the select gate electrode 6, the electric field can be concentrated on the corner portion and efficient electron tunneling can be performed. From another viewpoint, since the electron tunneling is facilitated by using the corner portions in this way, the film thickness of the poly-poly insulating film can be relatively increased.
[0036]
By having the above structure, tunnel electrons can be injected from the selection gate electrode 6 to the floating gate electrode 5 by setting appropriate potentials to the source 2, drain 3, control gate electrode 4, and selection gate electrode 6. Become. This tunnel electron injection (writing) uses an electron tunnel phenomenon between polysilicon electrodes, and therefore is generally called a poly-poly tunnel.
[0037]
FIG. Comparative example FIG. Compared with the embodiment of FIG. 5, the floating gate electrode 5 straddles the selection gate electrode 6 in the embodiment of FIG. Comparative example In this structure, the floating gate electrode 5 rides on a part of the selection gate electrode 6. As a result, FIG. Comparative example Then, the capacity of the insulating film 13 is small Become .
[0038]
The arrangement of each electrode Example It is not limited to. For example, FIG. If the floating gate electrode 5 is formed adjacent to the corner (shoulder portion) of the select gate electrode 6, the same effect as in the embodiment can be obtained.
[0039]
FIG. FIG. In this embodiment, tunnel electrons are injected from the selection gate electrode 6 to the floating gate electrode 5, that is, the potential of each part during the memory write operation is shown. In the embodiment shown in FIG. 7, an element isolation film 15 for separating and forming the well 1 in each memory element is formed. In order to cause a tunnel phenomenon from the selection gate electrode 6 to the floating gate electrode 5, a negative potential is applied to the selection gate electrode 6 and a positive potential is applied to the control gate electrode 4. The source 2 and the drain 3 may be set to a floating potential (denoted as F in the drawing), while the potential of the well 1 is necessarily equal to the ground potential because the substrate potential is the ground. less than FIG. The reference value of the electric means based on the Example of this is shown.
[0040]
[Table 1]

[0041]
FIG. 8 is a diagram showing the electron emission and electron injection of unselected bits at the time of writing in the case where the cell array is configured in the embodiment of FIG. 7, and (A) is on the same word line (same as the selected bit). (B) shows the state of the non-selected bit on the same bit line (on the same selection gate electrode 6) as the selected bit.
[0042]
In FIG. 8A, since a positive potential is applied to the control gate electrode 4, the control gate electrode 4, the selection gate electrode 6 and the substrate 1 are coupled through the insulating film 13 and the insulating film 12, and the floating gate Tunnel current from electrode 5 to control gate electrode 4 Flowing There are concerns (arrows in the figure). This has been found not to be a significant problem in the range of electrical means shown in Table 1 in the embodiment of FIG. Reference example In this structure, the coupling between the control gate electrode 4, the selection gate electrode 6 and the substrate 1 is low, which is a concern. Therefore, it is preferable that the insulating film 13 is formed of an ONO laminated film including a three-layer film of an oxide film, a nitride film, and an oxide film so that current does not easily flow.
[0043]
In FIG. 8B, since a negative potential is applied to the selection gate electrode 6, a tunnel current flows from the selection gate electrode 6 to the substrate 1 at least regardless of whether the bit is selected or not (arrow a in the figure). . Regarding this, in the range of electrical means shown in Table 1, at the time of writing Almost Although it is known that it does not become a problem, reliability such as stress leak is a little concerned in the long term. Further, it has been found that overwriting (arrow B in the figure) from the selection gate electrode 6 to the floating gate electrode 5 hardly poses a problem. Also, there is some concern about electron emission from the floating gate electrode 5 to the well substrate 1 (disturb: arrow c in the figure).
[0044]
In FIG. 9, a deep deep-N well 1n having a junction position of several microns is formed on a P-type silicon substrate 1, and a P-well 1p is further formed therein, and an N-type memory element (a diffusion layer is formed on the upper portion). It is a figure showing the Example which formed N type). According to this structure, since the well 1p in which the memory element is arranged is electrically separated from the substrate 1, the above problem can be solved by setting this to a floating potential.
[0045]
In the case of a semiconductor memory device, since a charge pump circuit and a memory driving circuit (for example, a CMOS circuit) must be built in the same substrate, at least a P well and an N well are required. In addition, since the embodiment of FIG. 9 requires a deep-N well, three wells must be formed. This is a difficult technique called triple well, and there are some disadvantages in terms of cost. Therefore, whether or not to adopt this technique may be determined as appropriate depending on the application.
[0046]
In the embodiment of FIG. 9, the insulating film 13 (capacitance Ca, average film thickness Ta) between the floating gate electrode 5 and the control gate electrode 4 and the insulating film 14 (capacitance Cb, Average film thickness Tb)
CbTb <CaTa
It is preferable that the following relationship is satisfied.
[0047]
That is, in order to perform poly-poly tunnel writing between the floating gate electrode 5 and the selection gate electrode 6 via the insulating film 14, a high electric field is applied to at least the insulating film 14 from the insulating film 13. Applied Must. Therefore, if the voltages self-biased to the insulating films 13 and 14 at the time of writing are Va and Vb, respectively,
Va / Ta <Vb / Tb
The following conditions are necessary. In the device of the embodiment of FIG. 9, since the well region 1p constituting the memory is electrically isolated from the silicon substrate 1, the potentials of the well 1p, the source 2 and the drain 3 are set to the floating potential at the time of tunnel erasing. All you need is a special setting. Therefore, considering the simple case where the floating gate electrode 5 is not charged with electrons, the following equation is roughly established.
Ca · Va = Cb · Vb
Therefore, the following formula is obtained.
Cb ・ Tb <Ca ・ Ta
[0048]
Actually, as the above relationship is more conspicuous (Cb · Tb << Ca · Ta), the write operation is easier, and between the select gate electrode 6 and the control gate electrode 4 is easier. Applied The voltage can be further lowered. Considering the fact that the potential difference can be distributed to the positive voltage and the negative voltage at the time of writing, as a result, the voltage of the booster circuit can be further lowered and the circuit burden can be reduced.
[0049]
Further, in the embodiment of FIG. 9, between the oxide film 13 (area Sa) between the control gate electrode 4 and the floating gate electrode 5 and the oxide film 14 (area Sb) between the floating gate electrode 5 and the selection gate electrode 6. In addition,
Sb <Sa
It is preferable that the following relationship is satisfied. Here, the areas Sa and Sb indicate capacity areas in terms of average film thickness of the silicon oxide film.
[0050]
That is, in order for a polypoly tunnel to occur in the oxide film 14 between the floating gate electrode 5 and the selection gate electrode 6, at least a higher electric field is applied to the oxide film 14 than the oxide film 13. Applied Therefore, there is a relationship of Cb · Tb <Ca · Ta. And both insulating films
Sb <Sa
Actually, the more the above relation is significant (Sb << Sa), the easier the writing operation is, and the selection gate electrode 6 to the control gate electrode 4 are connected. Applied The voltage can be further lowered.
[0051]
FIG. 10 shows the potential of each part during the memory erasing operation in the embodiment of FIG. 9, and FIG. 10A is a cross-sectional view schematically showing tunnel electron emission from the floating gate electrode 5 to the drain 3. B) schematically represents tunneling electron emission from the floating gate electrode 5 to the well 1p. In FIG. 10A, a negative potential is applied to the control gate electrode 4 and a positive potential is applied to the drain 3. As a result, tunnel electron emission occurs from the floating gate electrode 5 to the drain 3. At this time, the source 2 and the selection gate electrode 6 may be set to a floating potential. In the case of such an electrical means, between the control gate electrode 4 and the drain 3 Applied The potential difference is caused by the capacitance of the insulating film 13 between the control gate electrode 4 and the floating gate electrode 5 and the gate electrode overlapping portion of the insulating film 12 between the floating gate electrode 5 and the substrate well 1p (the floating gate electrode 5 and the drain 3 Of the overlap portion). Therefore, most of the potential difference is applied between the floating gate electrode 5 and the drain 3 having a small capacitance (the coupling ratio is high). In this embodiment, a triple well is shown. In this case, since the substrate well 1p operates well even if it is not in a floating potential state, there is no problem even if it is a normal well. Reference values for electrical means based on this embodiment are shown below.
[0052]
[Table 2]

[0053]
In FIG. 10B, a negative potential is applied to the control gate electrode 4 and a positive potential is applied to the well 1p. As a result, tunnel electron emission occurs from the floating gate electrode 4 to the well 1p. At this time, the source 2 and the selection gate electrode 6 may be set to a floating potential. In the case of such an electrical means, between the control gate electrode 4 and the well 1p. Applied The potential difference thus distributed is distributed between the capacitance of the insulating film 13 between the control gate electrode 4 and the floating gate electrode 5 and the capacitance of the insulating film 12 between the floating gate electrode 4 and the well 1p. In this case, the coupling ratio is smaller than tunnel erasing to the drain 3. However, since the capacity of the insulating film 13 can be very large in the structure of this embodiment, this method is possible. In this case, however, a well separated from the substrate is required. Reference values for electrical means based on the examples are shown below.
[0054]
[Table 3]

[0055]
FIG. 11 shows the potential of each part during the memory access (reading) operation in the embodiment of FIG. The reading method is performed with the source 2 and the drain 3 being practically opposite. This is to reduce read disturb. Further, although the triple well is shown in the embodiment of FIG. 11, in this case, since the substrate well operates well even if it is not in a floating state, there is no problem even if it is a normal well. Reference values for electrical means based on the examples are shown below.
[0056]
[Table 4]

[0057]
In the semiconductor memory device of the present invention, the source and drain of the memory element are connected by a diffusion layer wiring in the channel width direction (a bit line made contactless), and the selection gate electrode (similar to the source / drain) is connected in the same direction. (Acting as a bit line) is connected, and the control gate electrode is connected (word line) in a direction (channel length direction) orthogonal to this, and a semiconductor memory element is arranged in an array, and the bit line and the word line Matrix selection is possible.
[0058]
12 and 13 show schematic views of respective embodiments of the apparatus of the present invention. (A) is a plan view, (B) is a cross-sectional view taken along the line SS ′ of (A), and (C) is a cross-sectional view taken along the line CC ′ of (A). 12 and 13 exemplify the case where the embodiment of FIG. 5 is arrayed, for example, the example of FIG. 6 may be arrayed and is not limited thereto.
[0059]
In this device, as shown in FIG. 12 or FIG. 13, the line-shaped control gate electrode 4 constitutes a word line, and the source 2 and / or the drain 3 constitute a bit line arranged in a direction orthogonal thereto. The line-shaped selection gate electrodes 6 are arranged in the same direction as the bit lines. The memory elements arranged in the direction of the select gate electrode 6 are separated by the element isolation film 15. With this arrangement, selection (access) of a certain memory element in the memory array can be performed by matrix selection of the control gate electrode 4 (word line) and the diffusion layers 2 and 3 (bit line). At this time, the selection gate electrode 6 acts as a pseudo bit line, and is set in advance to a desired positive potential (see bias conditions in Table 4) before access. memory It also has the effect of shortening the access time.
[0060]
Here, FIG. 12 generally belongs to the Virtual-Ground-Array (virtual ground array) system, and the source lines 2 and the drain lines 3 are alternately arranged and are adjacent to each other in the word line (control gate electrode line 4) direction. In the memory elements, the source 2 of one element and the drain 3 of the other element are common. Therefore, the source and drain in operation are determined by the selected element. That is, the source that is set to the ground potential at the time of normal memory access (in the present apparatus, the drain of reference numeral 3 in the figure is used as a source for suppressing read disturb) is changed depending on the position of the selected memory. Such an array arrangement has an advantage that there is no variation in device characteristics related to it because all the cells face the same direction as that in FIG. Further, the line / space of the select gate electrode 6 is constant, and the polysilicon film of the control gate electrode 4 can be embedded in a low step portion (above the select gate electrode transistor), thereby reducing the total step and facilitating the process. Is advantageous.
[0061]
In the erasing operation, if all the diffusion layers (source 2 and drain 3) are set to a desired common positive potential, the element group on the word line (control gate electrode line 4) can be erased collectively.
In the write operation, in the element group on one bit line (selection gate electrode line 6), if the control gate electrode 4 of a bit that needs to be written (electron injection) is set to a desired common positive potential, one element is provided. The element group on the bit line can be collectively written. Alternatively, in a group of elements on one word line (control gate electrode line 4), if the selection gate electrode 6 of a bit that requires writing (electron injection) is set to a desired common negative potential, The element group can be collectively written. Such batch writing is possible because of the poly-poly tunnel current writing method between the gate electrodes, which is an important feature of the present invention.
[0062]
In addition, according to the element structure / array arrangement and electrical means of the present invention as shown in FIG. 12, it can be understood that all of the matrix selection, batch erase, and batch write described above can be realized simultaneously.
In the case of this cell array, the source line 2 and drain line 3 extending in the channel width direction (vertical direction (A) in the figure) are sequentially switched depending on the selected bit to be accessed. Either the source or the drain (generally the source) is usually used at the ground potential, and in this arrangement, the line corresponding to the ground potential is switched by the selected bit, so that it is called a virtual ground type.
[0063]
Although FIG. 13 belongs to the contactless NOR type, the source lines 2 and the drain lines 3 are alternately arranged, and both the source and the drain are shared between adjacent memory elements in the word line (control gate electrode line 4) direction. . Therefore, the source 2 and the drain 3 are not interchanged by the element selected as in the case of FIG. 12, the diffusion layer line is fixed without being switched by the selection bit, and the setting of the electric means is easy. There is an advantage of being. Similarly to the case of FIG. 12, the source and drain of each element are connected by a diffusion layer wiring (contactless bit line) in the channel width direction, and the select gate electrode 6 (also in the same direction as the bit line). The control gate electrode 4 (word line) is connected in a direction perpendicular to the bit line (channel length direction of the memory element). With such an arrangement, it is possible to select a matrix of each memory element by bit lines and word lines at the time of writing, erasing or accessing (reading).
[0064]
In the erasing operation, if all the drains 3 are set to a common positive potential, the element group on the selected word line (control gate electrode line 4) can be erased collectively. Here, in the embodiment of FIG. 13, unlike the embodiment of FIG. 12, the diffusion layer line is fixed without being switched by the selection bit.
In the write operation, in the element group on one bit line (selection gate electrode line 6), if the control gate electrode 4 of a bit that needs to be written (electron injection) is set to a desired common positive potential, one element is provided. The element group on the bit line can be collectively written. Alternatively, in a group of elements on one word line (control gate electrode line 4), if the selection gate electrode 6 of a bit that requires writing (electron injection) is set to a desired common negative potential, The element group can be collectively written.
[0065]
The memory arrays of FIGS. 12 and 13 belong to the NOR type in terms of flash memory classification. In general, NOR type arrays require drain contacts (bit line contacts) as represented by ETOX type and SST type, and high speed access is possible, but it has been said to be disadvantageous in improving the degree of integration. On the other hand, the present invention avoids this by adopting diffusion layer wiring as in the SunDisk type and BMI type, and has a structure extremely advantageous for high integration. Diffusion layer wiring has a higher resistance than contacts and metal wiring, which may be disadvantageous for high-speed access. Can be avoided.
[0066]
FIG. 14 is a process sectional view showing a process for manufacturing the memory element of FIG.
(A) Using well-known techniques such as photoengraving technology, ion implantation technology, and diffusion technology, a well oxide and a field oxide film for element isolation are formed on a silicon substrate, and then a gate oxide film on the surface of the substrate (well) 1 11 is formed. Next, a polysilicon layer and an insulating layer 16 for the selection gate electrode 6 are formed and processed into a line shape (selection gate electrode line).
[0067]
(B) Impurities for the source 2 and drain 3 are introduced by using the photoresist 20 as a mask in the photolithography process and the impurity ion implantation process.
(C) After the unnecessary oxide film is removed, the insulating oxide film 17, the tunnel oxide film 12 and the oxide film 14 on the source / drain impurity diffusion layers are simultaneously formed by an oxidation process. The oxidation step here may be performed a plurality of times including the removal of unnecessary oxide films (such as pre-gate oxide films), and in consideration of the formation of transistors around the memory, a photoengraving step is necessary during this step. In some cases. Therefore, the film thickness balance of the oxide films 12, 14, and 17 is incorporated and matched in the design of the total process. Incidentally, it is common that the polysilicon oxide film 14 is formed thicker than the oxide film 12 on the silicon substrate, and the oxide film 17 on the diffusion layer is formed several times thicker than the oxide film on the silicon substrate. . This embodiment makes good use of this process. This oxidation process also serves as drive / activation of the diffusion layer.
[0068]
(D) A polysilicon layer for the floating gate electrode 5 is formed and processed into a strip shape parallel to the channel width direction (direction perpendicular to the paper surface in the figure) by photolithography and dry etching techniques. Next, an ONO multilayer film 13 composed of an oxide film, a nitride film, and an oxide film is formed. The oxide film here is formed by oxidation or high temperature CVD technology. The nitride film is, for example, a CVD film.
[0069]
(E) A polysilicon film for the control gate electrode 4 is formed and processed into a channel length direction (lateral direction in the figure) by a photoengraving technique and a dry etching technique. At this time, the polysilicon film for the floating gate electrode 5 and the ONO laminated film 13 processed into a band shape in the step (D) are processed into a rectangular shape under the same mask to obtain a desired shape, and separated in each memory element region. To form.
It is preferable to previously form a silicide layer for reducing resistance and its protective layer on the polysilicon layer for the control gate electrode 4.
[0070]
Since the insulating film 14 is used as a tunnel film, an oxide film is used in the embodiment. This film thickness may be about 15 to 40 nm. The insulating film 13 is an important insulating film for coupling at the time of erasing, writing, and reading, and has a large capacity (capacitance film thickness is small) and current does not flow (charge leakage is small). Since it is necessary, an ONO laminated film is very suitable. In the embodiment, for example, a film thickness of about 4 to 8 nm (top oxide film) / 4 to 16 nm (nitride film) / 4 to 8 nm (bottom oxide film) is used.
[0071]
FIG. 15 is a process sectional view showing a process for manufacturing the memory element of FIG.
(A) A well 1, a field oxide film, a gate oxide film 11, a select gate electrode 6 and an insulating layer 16 are formed in the same manner as in the step (A) of FIG.
[0072]
(B) After removing unnecessary oxide films, tunnel oxide films 12 and 14 are simultaneously formed by an oxidation process. The oxidation step here may be performed a plurality of times including the removal of the unnecessary oxide film as in the step (B) of FIG. 14, and the photoengraving step is performed during this period in consideration of the formation of transistors around the memory. In some cases. Therefore, the film thickness balance of the oxide films 12 and 14 is incorporated and matched in the design of the total process. Again, the oxide film 14 is formed thicker than the oxide film 12. Next, a polysilicon layer for the floating gate electrode 5 is formed, and a laminated film 13a made of a bottom oxide film and a nitride film for the ONO laminated film 13 is formed thereon. This oxide film is formed by oxidation or high temperature CVD technology. The nitride film is a CVD film. Next, the polysilicon layer and the laminated film 13a for the floating gate electrode 5 are processed into a band shape in the channel width direction (the direction perpendicular to the paper surface) by photolithography and dry etching techniques. Next, impurity ions are implanted for the diffusion layer using the same mask.
[0073]
(C) The top oxide film for the ONO film 13, the oxide film 13b on the side surface of the floating gate electrode 5, the oxide film 14b on the side surface of the selection gate electrode 6, and the oxide film 17 on the diffusion layer are formed in one CVD oxide film formation step. It forms simultaneously by one oxidation process. For example, when a high-temperature oxide film, which is a kind of CVD film, is first formed to about 5 nm and then subjected to one oxidation treatment, the top oxide film is about 5 nm and the oxide film 13b on the side surface of the floating gate electrode is about 15 nm. It has been found that the oxide film 14b on the side surface of the gate electrode is formed with a thickness of about 15 nm and the oxide film 17 on the diffusion layer is formed with a thickness of about 20 nm. Further, this oxide film forming step also serves to drive and activate the diffusion layer.
[0074]
(D) A polysilicon film for the control gate electrode 4 is formed and processed in the channel length direction (lateral direction in the figure) by the photoengraving technique and the dry etching technique. At this time, the polysilicon film for the floating gate electrode 5 processed into a strip shape in the step (B) is processed into a rectangular shape under the same mask to obtain a desired shape, and formed separately in each memory element region.
The process of the embodiment shown in FIGS. 14 and 15 is an example, and the process of the present invention is not limited to this.
[0075]
【The invention's effect】
Since the memory device of the present invention has a select gate electrode, there is no problem of over-erasing, and it is easy to reduce the voltage and multi-value. Compared with the far smaller current capacity, the power consumption can be reduced, the charge pump can be boosted easily and a single power source can be easily achieved. Further, since the capacitor area of the charge pump can be reduced, it contributes to high integration and can improve the integration degree.
Since separate tunnel films are used for writing and erasing, the device specifications can be easily designed and manufactured, and the high reliability and durability of the tunnel oxide film can be obtained.
Since the capacitance area of the insulating film between the floating gate electrode and the control gate electrode is large and the coupling ratio at the time of writing or erasing is large, the voltage can be easily reduced. If the coupling ratio is slightly allowed, the reliability of the insulating film between the floating gate electrode and the control gate electrode can be improved. Furthermore, if the coupling ratio is slightly allowed, the thickness of the tunnel film used at the time of writing or erasing can be relatively increased, and the reliability can be improved.
[0076]
When arranging the memory elements of the present invention in an array, at least the source diffusion, preferably the drain diffusion, of the drain diffusion and the source diffusion are continuously used so as to be commonly used by a plurality of memory elements arranged in succession. It is formed as a diffusion layer, the selection gate electrode is formed in a line shape in a direction parallel to the source diffusion, and the control gate electrode is formed in a line shape in a direction orthogonal to the control gate electrode. Then, the source diffusion and the drain diffusion are arranged so as to be shared by adjacent memory elements across the contact diffusion structure to form a contactless structure, or the source diffusion and the drain diffusion are arranged alternately to form a contactless structure. By adopting the virtual ground type array system, it is possible to contribute to improvement in integration degree and increase in capacity.
Since the memory element groups on the same word line can be erased at once, if the element groups on a plurality of word lines are made into blocks, batch high speed erasure can be performed. Furthermore, since the element group on the same word line or the element group on the same bit line can be erased at once, the programming time can be substantially reduced and high-speed writing can be realized. As described above, the present invention enables simultaneous high-speed erasure and high-speed writing. Further, since any element can be selected at the time of erasing, writing or reading, a matrix of one element can be selected. It can be used for memory chips with the above specifications and can easily handle multi-product production.
[Brief description of the drawings]
1A and 1B are diagrams showing a conventional ETOX memory element array, in which FIG. 1C is a plan view, FIG. 1A is a cross-sectional view taken along line AA ′ in FIG. 1C, and FIG. It is sectional drawing in the BB 'line position in FIG.
2A and 2B are diagrams showing a conventional SunDisk type memory element array, in which FIG. 2C is a plan view, FIG. 2A is a cross-sectional view taken along the line AA ′ in FIG. 2C, and FIG. It is sectional drawing in the BB 'line position in FIG.
3A and 3B are diagrams showing a conventional SST type memory element array, in which FIG. 3C is a plan view, FIG. 3A is a cross-sectional view taken along the line AA ′ in FIG. 3C, and FIG. It is sectional drawing in the BB 'line position in FIG.
4A and 4B are diagrams showing a conventional BMI memory element array, in which FIG. 4C is a plan view, FIG. 4A is a cross-sectional view taken along the line AA ′ in FIG. 4C, and FIG. It is sectional drawing in the BB 'line position in FIG.
FIG. 5 is a cross-sectional view showing one memory element according to one embodiment.
[Fig. 6] Comparative example It is sectional drawing which shows one memory element.
FIG. 7 is a cross-sectional view showing one memory element of still another embodiment together with potentials of respective parts during a memory write operation.
8 is a cross-sectional view showing the disturbance of unselected bits at the time of writing in the embodiment of FIG. 5 by arrows, (A) shows the state of unselected bits on the same word line as the selected bit, The state of the non-selected bit on the same bit line as the selected bit is represented.
FIG. 9 is a cross-sectional view showing one memory element of still another embodiment together with potentials of respective parts at the time of memory write operation.
FIG. 10 shows the potential of each part during the memory erasing operation in the embodiment of FIG. 9, where (A) is a cross-sectional view showing a tunnel electron emission mode from the floating gate electrode 5 to the drain 3; ) Is a cross-sectional view showing a tunnel electron emission mode from the floating gate electrode 5 to the well 1p.
11 is a cross-sectional view showing the potential of each part during a memory access (read) operation in the embodiment of FIG.
12A and 12B are diagrams illustrating an embodiment in which the memory elements in FIG. 5 are arrayed, in which FIG. 12A is a plan view, FIG. 12B is a cross-sectional view taken along line SS ′ in FIG. ) Is a cross-sectional view taken along the line CC ′ in FIG.
13A and 13B are diagrams illustrating another embodiment in which the memory elements of FIG. 5 are arrayed, where FIG. 13A is a plan view, FIG. 13B is a cross-sectional view taken along the line SS ′ in FIG. (C) is sectional drawing in the CC 'line position of (A).
14 is a process cross-sectional view showing a process for manufacturing the memory element of FIG. 5; FIG.
15 is a process sectional view showing a process for manufacturing the memory element of FIG. 6; FIG.
[Explanation of symbols]
1 Semiconductor substrate or well
2 source
3 Drain
4 Control gate electrode
5 Floating gate electrode
6 Select gate electrode
11 Gate oxide film
12, 14 Tunnel oxide film
13 ONO film
16, 17 Insulating film

Claims (14)

A drain diffusion layer and a source diffusion layer are formed in a semiconductor substrate or well, and an insulating film is formed on the substrate or the well, adjacent to the source diffusion layer and common to a plurality of memory elements at a distance from the drain diffusion layer. The selection gate electrode is provided on the oxide film formed thicker than the gate insulating film on the source diffusion layer portion, and the upper surface and the side surface of the selection gate electrode are covered via the insulating film, On the substrate or well between the selection gate electrode and the drain diffusion layer, a floating gate electrode is provided adjacent to the drain diffusion layer and separated for each memory element via a gate insulating film, A control gate electrode straddling the floating gate electrode and the selection gate electrode is provided between the selection gate electrode and the floating gate electrode via an insulating film, respectively. Cage, comprising an electrically erasable non-volatile semiconductor memory device which performs a tunneling current writing between the selection gate electrode and the floating gate electrode,
These three gate electrodes are the insulating film between the control gate electrode and the floating gate electrode, the insulating film between the floating gate electrode and the selection gate electrode, and the insulating film between the floating gate electrode and the substrate or well. Electrically capacitively coupled,
The capacitance between the floating gate electrode and the control gate electrode is Ca, the average film thickness of the insulating film therebetween is Ta, the capacitance between the floating gate electrode and the selection gate electrode is Cb, and the average film thickness of the insulating film therebetween is Tb. When
Cb ・ Tb <Ca ・ Ta
A non-volatile semiconductor memory device characterized by satisfying the following relationship: A drain diffusion layer and a source diffusion layer are formed in a well that is electrically isolated from the semiconductor substrate, and an insulating film is provided on the well, and a plurality of the diffusion layers adjacent to the source diffusion layer are spaced apart from each other by a distance. A selection gate electrode common to the memory elements is provided, and the source diffusion layer portion is provided on an oxide film formed thicker than the gate insulating film on the source diffusion layer portion, and an upper surface and side surfaces of the selection gate electrode are interposed via an insulating film. A floating gate electrode is provided on the well between the selection gate electrode and the drain diffusion layer, with a gate insulating film interposed between the selection gate electrode and the drain diffusion layer, and is separated for each memory element adjacent to the drain diffusion layer. A control gate electrode straddling the floating gate electrode and the selection gate electrode is provided between the selection gate electrode and between the floating gate electrode via an insulating film. Cage, comprising an electrically erasable non-volatile semiconductor memory device which performs a tunneling current writing between the selection gate electrode and the floating gate electrode,
These three gate electrodes are the insulating film between the control gate electrode and the floating gate electrode, the insulating film between the floating gate electrode and the selection gate electrode, and the insulating film between the floating gate electrode and the substrate or well. Electrically capacitively coupled,
The capacitance between the floating gate electrode and the control gate electrode is Ca, the average film thickness of the insulating film therebetween is Ta, the capacitance between the floating gate electrode and the selection gate electrode is Cb, and the average film thickness of the insulating film therebetween is Tb. When
Cb ・ Tb <Ca ・ Ta
A non-volatile semiconductor memory device characterized by satisfying the following relationship:   When the area Sa of the insulating film between the floating gate electrode and the control gate electrode of the nonvolatile semiconductor memory element and the area Sb of the insulating film between the floating gate electrode and the selection gate electrode are satisfied, the relationship of Sb <Sa is satisfied. The nonvolatile semiconductor memory device according to claim 1. 4. The nonvolatile semiconductor memory device according to claim 1, wherein conditions are set so that memory erasure is performed by tunnel electron emission from the floating gate electrode to the drain diffusion layer region. 5. The nonvolatile semiconductor memory device according to claim 2, wherein conditions are set so that memory erasure is performed by tunnel electron emission from the floating gate electrode to the well.   6. In memory writing, a negative potential is applied to the selection gate electrode and a positive potential is applied to the control gate electrode, whereby electrons between polysilicon and polysilicon are injected from the selection gate electrode to the floating gate electrode. The nonvolatile semiconductor memory device according to any one of the above.   5. The nonvolatile memory according to claim 1, wherein, when erasing the memory, tunnel electrons are emitted from the floating gate electrode to the drain diffusion layer by applying a negative potential to the control gate electrode and a positive potential to the drain diffusion layer. Semiconductor memory device.   6. The nonvolatile semiconductor memory device according to claim 5, wherein when erasing the memory, tunnel electrons are emitted from the floating gate electrode to the well by applying a negative potential to the control gate electrode and a positive potential to the well.   The drain diffusion layer and the source diffusion layer are formed as a continuous diffusion layer so as to be commonly used in a series of a plurality of memory devices, and a bit line is formed together with a selection gate electrode formed in a line shape in a direction parallel to these diffusion layers. And the control gate electrode is formed in a line shape in a direction perpendicular to the bit line to form a word line, and the bit line and the memory cell are written at any time of memory writing, memory erasing and memory reading. The nonvolatile semiconductor memory device according to claim 1, wherein a matrix selection of each memory element is possible by the word line. The nonvolatile semiconductor memory device according to claim 9, wherein an applied voltage of each electrode is set so that at least memory element groups on the same word line are erased collectively. The nonvolatile semiconductor memory device according to claim 9 or 10, wherein an applied voltage of each electrode is set so that memory element groups on the same bit line are simultaneously written. The nonvolatile semiconductor memory device according to claim 9, wherein conditions are set so that memory element groups on the same word line are written simultaneously.   The insulating film between the selection gate electrode and the floating gate electrode is formed of an oxide film, and the insulating film between the floating gate electrode and the control gate electrode is formed of an ONO laminated film composed of an oxide film, a nitride film, and an oxide film. The nonvolatile semiconductor memory device according to claim 1. The following steps:
(A) A selection gate electrode polysilicon film is formed on a gate oxide film on a substrate, an insulating film is further formed thereon, and the selection gate electrode polysilicon film and the insulating film are formed by photolithography and etching techniques. Forming a select gate electrode by patterning;
(B) a step of introducing impurities for a source and a drain by a photolithography process and an impurity ion implantation process;
(C) a step of simultaneously forming an insulating oxide film on the source impurity diffusion layer, an insulating oxide film on the drain impurity diffusion layer, a tunnel oxide film, and an oxide film on the side surface of the select gate electrode by an oxidation step;
(D) A floating gate electrode polysilicon film is formed in a region including part of the impurity diffusion layer for the source, the upper and side surfaces of the selection gate electrode, and the tunnel oxide film, Forming a floating gate electrode by patterning with photoengraving technology and etching technology so that the silicon film remains;
(E) forming an ONO stacked film composed of an oxide film, a nitride film, and an oxide film on the entire surface of the substrate, and further forming a control gate electrode polysilicon film thereon; (F) A control gate electrode is formed by patterning a polysilicon film for a control gate electrode in a direction perpendicular to the diffusion layer by photolithography and etching techniques, and then an ONO stacked film and floating layer are formed by photolithography and etching techniques using the same mask. A step of forming a floating gate electrode by patterning a polysilicon film for a gate electrode in the order of (A) to (F), and the capacitance between the floating gate electrode and the control gate electrode being Ca, and the insulating film therebetween When the average film thickness is Ta, the capacitance between the floating gate electrode and the selection gate electrode is Cb, and the average film thickness of the insulating film therebetween is Tb,
Cb ・ Tb <Ca ・ Ta
A method for manufacturing a nonvolatile semiconductor memory device, characterized in that a corresponding process condition is set so as to satisfy the following relationship.

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