JP3849757B2 - Oscillator circuit, electronic equipment and clock - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an oscillation circuit, an electronic circuit using the same, a semiconductor device using the same, an electronic apparatus, and a timepiece.
[0002]
[Background Art and Problems to be Solved by the Invention]
Conventionally, an oscillation circuit using a crystal resonator has been widely used in portable wristwatches, portable telephones, computer terminals, and the like. In such portable electronic devices, it is necessary to save power consumption and extend the life of the battery.
[0003]
From the viewpoint of saving power consumption, the inventor has analyzed the power consumption of an electronic circuit used in a portable electronic device, particularly a wristwatch. According to this analysis, it was confirmed that the power consumption of the crystal oscillation circuit was tightened to a larger percentage in the electronic circuit configured on the semiconductor substrate than in the other circuit portions. That is, it has been found that reducing power consumption in an oscillation circuit of an electronic circuit used in a portable electronic device is effective in extending the life of the battery used.
[0004]
In such a crystal oscillation circuit, when the voltage Vreg is applied to the signal inverting amplifier, the output of the signal inverting amplifier is phase-inverted 180 degrees and fed back to the gate. As a result, the pair of transistors constituting the signal inverting amplifier are alternately turned on and off, the oscillation output of the crystal oscillation circuit gradually increases, and finally the crystal resonator oscillates stably.
[0005]
However, after the stable oscillation, since the oscillation can be continued by supplementing the loss of inertia energy of the crystal resonator, less energy is required than at the time of startup.
[0006]
In addition, the energy required for stable oscillation may be different even in circuits of the same standard, depending on variations in the capability of the signal inverting amplifier during mass production.
[0007]
Regardless of this, the conventional crystal oscillation circuit is configured to always drive the pair of transistors alternately on and off at a constant voltage, both at startup and after stable oscillation. For this reason, this has been a major factor in increasing the power consumption of the entire circuit.
[0008]
An object of the present invention is to provide a crystal oscillation circuit that can oscillate stably with low power consumption, an electronic circuit using the crystal oscillation circuit, a semiconductor device, an electronic apparatus, and a timepiece using the crystal circuit.
[0009]
[Means for Solving the Problems]
(1)To achieve the purpose,BookThe oscillation circuit of the invention is
A signal inverting amplifier;
in frontPower control means for controlling the power supply voltage of the signal inverting amplifier according to the oscillation output;
IncludingSee
The power control means includes
A power supply circuit that outputs a plurality of power supply voltages having different voltages;
A determination control means for determining whether stable oscillation is continued based on the oscillation output, and determining an optimum voltage of the power supply voltage supplied to the signal inverting amplifier required for continuing the stable oscillation;
Switching means for switching and controlling a power supply voltage applied from the power supply circuit to the signal inverting amplifier based on the determination result;
Oscillation output correction means for correcting frequency fluctuations of oscillation output during the power supply voltage control;
It is characterized by including.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
In order to achieve the object, the oscillation circuit of the first embodiment includes:
A signal inverting amplifier;
Power control means for controlling the power supply voltage of the signal inverting amplifier according to the oscillation output;
It is characterized by including.
[0011]
Thereby, the power consumption of the circuit at the time of stable oscillation can be reduced.
[0012]
The oscillation circuit of the second embodiment is
In the first embodiment,
The power control means includes
A power supply circuit that outputs a plurality of power supply voltages having different voltages;
Determination control means for determining an optimum voltage of a power supply voltage supplied to the signal inverting amplifier based on an oscillation output;
Switching means for switching and controlling a power supply voltage applied from the power supply circuit to the signal inverting amplifier based on the determination result;
It is characterized by including.
[0013]
According to the present embodiment, the optimum value of the power supply voltage supplied to the signal inverting amplifier is determined based on the oscillation output of the oscillation circuit. Based on the determination result, the power supply voltage applied from the power supply circuit to the signal inverting amplifier is switched and controlled.
[0014]
As a result, even if the oscillation output of the oscillation circuit fluctuates for some reason, or when there is a variation in the capacity of the signal inverting amplifier, the optimum power supply voltage is always supplied to the signal inverting amplifier and stable oscillation continues. It is possible to reduce power consumption.
[0015]
The oscillation circuit of the third embodiment is
In the second embodiment,
The power control means includes
A logic level is set to each different value, and includes a plurality of inverters that compare the voltage of the oscillation output with the logic level and output a pulse signal,
The determination control means includes
The optimum voltage is determined based on the value of the pulse signal output from each inverter, and is configured to output a power supply voltage selection command.
The switching means is
The power supply voltage applied from the power supply circuit to the signal inverting amplifier is switched and controlled based on the selection command.
[0016]
According to the present embodiment, the oscillation output voltage of the oscillation circuit is compared with the logic levels of different voltages by the plurality of inverters, and a pulse signal is output.
[0017]
Therefore, the selection command output circuit can determine the optimum power supply voltage corresponding to the oscillation output based on the value of the pulse signal output from each of these inverters, and thereby the power supply voltage applied from the power supply circuit to the signal inverting amplifier. Can be controlled to the optimum value.
[0018]
Here, the third embodiment is preferably configured as in the fourth embodiment.
[0019]
That is, the oscillation circuit of the fourth embodiment is
In the third embodiment,
The power control circuit includes:
And a power supply switching element which is provided on a power supply line to the signal inverting amplifier and is on / off controlled based on an output of any one of the plurality of inverters.
[0020]
As described above, the power supply switching element provided in the power supply line to the signal inverting amplifier is turned on / off based on the output of any one of the plurality of inverters, thereby further reducing power consumption. In this case, the oscillation of the oscillation circuit is based on the output pulse of the inverter used for on / off control of the switching element for power supply and the output pulse of another inverter set to a different logic level. A state can be judged appropriately.
[0021]
That is, when the power supply switching element is intermittently controlled by controlling on / off of the power supply switching element to reduce power consumption, the off period of the power supply switching element is lengthened. If the supply power is reduced too much, the oscillation state becomes unstable, and if the ON period is too long, too much supply power is not preferable from the viewpoint of reducing power consumption.
[0022]
According to the present embodiment, in such an intermittent drive type crystal oscillation circuit, the output is set to a logic level different from the output of the inverter that outputs the pulse signal for on / off control of the switching element for power supply. By comparing with the output of another inverter, it is possible to monitor the oscillation state and perform feedback control so as to always supply power with an appropriate voltage.
[0023]
This makes it possible to achieve more stable oscillation and lower power consumption.
[0024]
The oscillation circuit of the fifth embodiment is
In any of the first to fourth embodiments,
It further includes oscillation output correcting means for correcting frequency fluctuation of the oscillation output during the power supply voltage control.
[0025]
In a crystal oscillation circuit configured on a semiconductor substrate, the main part of the circuit formed integrally with the semiconductor substrate is connected to a crystal resonator provided separately from the semiconductor substrate via an input / output terminal. Many. For this reason, an electrostatic protection circuit is provided on the input / output terminal side of the main circuit portion in order to protect the main circuit portion from a surge voltage entering from the outside through the input / output terminal.
[0026]
However, as described above, when the power supply voltage applied to the signal inverting amplifier is switched to reduce power consumption, the output impedance of the signal inverting amplifier changes and the parasitic capacitance value of the electrostatic protection circuit varies. As a result, there arises a problem that the oscillation frequency f of the oscillation circuit is slightly changed.
[0027]
As described above, when the oscillation frequency of the oscillation circuit fluctuates, in an electronic circuit that uses the oscillation output of the oscillation circuit as a reference clock for a watch, for example, an electronic circuit for a wristwatch, an accurate clock operation itself is impaired. The problem arises.
[0028]
The present embodiment employs a configuration in which the oscillation output correcting means is used to correct the frequency fluctuation of the oscillation output when controlling the power supply voltage applied to the signal inverting amplifier.
[0029]
As a result, it is possible to obtain an oscillation circuit capable of continuing stable oscillation, reducing power consumption during stable oscillation, and generating an accurate reference clock.
[0030]
Here, it is preferable that the oscillation output correction circuit is configured as in the sixth embodiment.
[0031]
That is, the oscillation circuit of the sixth embodiment is
In the fifth embodiment,
The oscillation output correction means includes
A frequency dividing means for counting the oscillation frequency;
Frequency division control means for performing frequency division control of the frequency division means based on the value of the power supply voltage applied to the signal inverting amplifier from the power supply circuit;
The frequency variation of the oscillation output generated with the variation of the power supply voltage is corrected.
[0032]
According to the present embodiment, the oscillation output of the oscillation circuit is output via the frequency dividing means. At this time, the frequency division control unit performs frequency division control of the frequency division unit based on the value of the power supply voltage applied to the signal inverting amplifier, and corrects the frequency fluctuation of the oscillation output generated with the fluctuation of the power supply voltage.
[0033]
By doing so, it is possible to correct frequency fluctuations of the oscillation output with a simple circuit configuration.
[0034]
Here, the frequency division control means is preferably configured as in the seventh embodiment.
[0035]
That is, the oscillation circuit of the seventh embodiment is
In a sixth embodiment subordinate to the second to fourth embodiments,
The frequency division control means includes
Frequency division control data corresponding to a plurality of power supply voltages output from the power supply circuit is set in advance, and based on the frequency division control data corresponding to the value of the power supply voltage to be applied to the signal inverting amplifier, the frequency dividing means is divided. Circumferential control is performed.
[0036]
As described above, by setting the frequency division control data corresponding to a plurality of power supply voltages in advance, it is possible to obtain an oscillation output correction circuit capable of correcting the frequency variation of the oscillation output with a simpler circuit configuration. it can.
[0037]
The eighth embodiment is
In any of the first to seventh embodiments,
A crystal unit having a large Q value is used.
[0038]
As described above, by using a quartz resonator having a large Q value indicating the ease of mechanical vibration, the oscillation state can be stably maintained with less power consumption after stable oscillation. Is possible.
[0039]
The electronic circuit of the ninth embodiment is
The oscillation circuit according to any one of the first to eighth embodiments is provided.
[0040]
The semiconductor device of the tenth embodiment is
It is characterized by including the oscillation circuit according to any one of the first to eighth embodiments or the electronic circuit according to the ninth embodiment.
[0041]
The electronic device according to the eleventh embodiment
It is characterized by including the oscillation circuit according to any one of the first to eighth embodiments or the electronic circuit according to the ninth embodiment.
[0042]
By doing so, it is possible to reduce power consumption of electronic devices such as mobile phones and portable computer terminals, and to reduce power consumption of built-in batteries and secondary batteries such as batteries. Become.
[0043]
The watch of the twelfth embodiment
It is characterized by including the oscillation circuit according to any one of the first to eighth embodiments or the electronic circuit according to the ninth embodiment.
[0044]
By doing so, it is possible to realize a watch with low power consumption. As a result, it is possible to reduce the size of the watch as a whole by using a smaller battery, and a battery with the same capacity can be obtained. When used, the battery life can be extended.
[0045]
【Example】
Next, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0046]
(First embodiment)
FIG. 1 shows a crystal oscillation circuit according to a first preferred embodiment of the present invention, and FIG. 2 shows a timing chart thereof. The crystal oscillation circuit of this embodiment is a crystal oscillation circuit used in a quartz type wristwatch, and the main part of the circuit is formed on a semiconductor substrate.
[0047]
The crystal oscillation circuit of the present embodiment includes a signal inverting amplifier 20, a crystal resonator 10 and a resistor 14 that constitute a feedback circuit. The feedback circuit includes phase compensation capacitors 16 and 18 in addition to the crystal resonator 10 and the resistor 14, and the gate signal VG obtained by inverting the output VD (t) of the signal inverting amplifier 20 by 180 degrees. (t) is a feedback input to the signal inverting amplifier 20.
[0048]
The signal inverting amplifier 20 is connected to a first potential side and a second potential side having a voltage lower than the first potential side, and is configured to be driven by power supply by a potential difference between both potentials. Here, the first potential is set to the ground potential VDD, and the second potential is set to the negative power supply voltage Vreg that is selectively supplied from the power control circuit 60.
[0049]
The signal inverting amplifier 20 includes a first circuit 22 and a second circuit 24.
[0050]
The first circuit 22 includes a P-type field effect transistor 26 that functions as a first semiconductor switching element. The source and drain of the transistor 26 are connected to the ground side and the output terminal side, respectively, and the feedback signal VG (t) is applied to the gate.
[0051]
The second circuit 24 includes an N-type field effect transistor 28 that functions as a second semiconductor switching element. The source and drain of the transistor 28 are connected to the negative power supply voltage Vreg side and output terminal side supplied from the power control circuit 60 (here, connected to the drain of the transistor 26), and the gate thereof is connected to the transistor 28. The feedback signal VG (t) is applied.
[0052]
The crystal oscillation circuit of this embodiment includes a field effect transistor 40 that functions as a power supply switching element, and a signal inversion in order to control on / off of the power supplied to the signal inverting amplifier 20 in synchronization with the output VD (t). And an inverter 64 that applies a switch control signal 100 to the gate of the transistor 40 based on the output VD (t) of the amplifier 20.
[0053]
The transistor 40 is configured by using a P-type field effect transistor, and its source is connected to the ground potential VDD side and its drain is connected to the source side of the transistor 26.
[0054]
As shown in the timing chart of FIG. 2, the inverter 64 outputs a pulse signal S3 of L level when the drain output voltage VD (t) input as the signal S1 exceeds the logic level VGL2, and H level when it falls below the logic level VGL2. . The output S3 is applied to the gate of the transistor 40 as the switch control signal 100, and thereby the transistor 40 is controlled to be turned on / off in synchronization with the output VD (t) of the signal inverting amplifier 20. As a result, the power supply transistor 40 is turned on during the period t to supply power to the signal inverting amplifier 20, and is turned off during the period t ｀ to stop the power supply.
[0055]
Thus, according to the crystal oscillation circuit of the present embodiment, the power supplied to the signal inverting amplifier 20 can be controlled to be turned on / off, and the power consumption can be reduced.
[0056]
In particular, according to the present embodiment, the switch control signal 100 is generated by using the output VD (t) of the signal inverting amplifier 20, the power supply is automatically turned on / off with an appropriate duty ratio, and the power consumption is reduced. Can be achieved.
[0057]
Here, it is preferable to use the crystal unit 10 having a large Q value indicating the ease of mechanical vibration. Thereby, the inertia (free vibration) of the crystal resonator 10 is increased, and even when the signal inverting amplifier 20 is intermittently driven, more stable oscillation can be maintained.
[0058]
In this embodiment, each of the transistors 26 and 28 constituting the signal inverting amplifier 20 is configured by using an enhancement type field effect transistor, and the threshold voltage is set to a small value. As a result, the absolute value of the power supply voltage Vreg required to drive the signal inverting amplifier 20 stably can be reduced, and power consumption can be reduced also from this aspect.
[0059]
Note that if the threshold voltages of the transistors 26 and 28 are set to a small value, even if the enhancement type field effect transistor is used, the leakage current at the time of off-control becomes a large value. In order to solve this problem, in the present embodiment, a power supply field effect transistor 40 having a high threshold voltage is used to thereby reliably reduce the aforementioned off-leakage current. .
[0060]
As a result, the signal inverting amplifier 20 can be driven using the low power supply voltage Vreg, and the off-leakage current can be surely reduced. Therefore, a crystal oscillation circuit that consumes less power and can perform stable oscillation is provided. It can be realized. The transistor 40 used as the power supply semiconductor switching element preferably has a high capability within an allowable range in order to reduce the on-resistance and reduce the voltage drop.
[0061]
Further, in the crystal oscillation circuit of this embodiment, an output cutoff switching element 30 is provided at the output stage of the signal inverting amplifier 20.
[0062]
For example, in the circuit as shown in FIG. 1, when the transistor 40 is turned off, the transistor 28 constituting the signal inverting amplifier 20 is turned on, the crystal resonator 10 is pulled to the L level (Vreg level) potential, and the oscillation is suppressed. It may be done.
[0063]
Therefore, in this embodiment, an output cutoff switching element 30 is provided at the output stage of the signal inverting amplifier 20, and the switching element 30 is also turned off when the transistor 40 is turned off. Thereby, when the transistor 40 is controlled to be off, the vibrator 10 is separated from the circuit of the signal inverting amplifier 20 and can freely vibrate.
[0064]
As a result, according to the crystal oscillation circuit of the present embodiment, the oscillation circuit can be operated more stably when the signal inverting amplifier 20 is intermittently driven by the switch 40. Here, as the output cutoff switching element 30, for example, a transmission gate or the like is preferably used.
[0065]
Further, the power control circuit 60 of this embodiment selects an appropriate power supply voltage Vreg from among a plurality of different power supply voltages Vreg1, Vreg2,... Vreg4 based on the value of the output voltage VD (t) of the signal inverting amplifier 20. By applying the signal to the signal inverting amplifier 20, it is possible to continue the oscillation more stably and reduce the power consumption.
[0066]
The configuration will be described below.
[0067]
The power control circuit 60 of this embodiment includes a power supply voltage generation circuit 66 that outputs a plurality of different power supply voltages Vreg1, Vreg2,... Vreg4, a multiplexer 82 that selectively outputs any one power supply voltage Vreg, and inverters 64 and 62. And a determination control unit 68 that determines the oscillation state of the circuit based on the outputs S3 and S4 of the inverters 64 and 62 and controls the power supply voltage selected by the multiplexer 82.
[0068]
Then, the power supply voltage Vreg (represented as signal S13 in the figure) selected by the multiplexer 82 is applied to the signal inverting amplifier 20 (here, the source side of the transistor 28).
[0069]
The output VD (t) of the signal inverting amplifier 20 is input to the inverter 64 and the inverter 62 as signals S1 and S2, respectively.
[0070]
As shown in the timing chart of FIG. 2, the inverter 64 outputs a pulse signal S3 of L level when the drain output voltage VD (t) exceeds a predetermined logic level VGL2 and H level when the drain output voltage VD (t) falls below. The output S3 is input to the CK terminal of the counter 72 and applied to the gate of the transistor 40 as the switch control signal 100.
[0071]
In the inverter 62, the logic level VGL1 is set to Vreg / 2. As shown in FIG. 2, when the drain output VD (t) input as the signal S2 exceeds the logic level VGL1, the logic level VGL1 is set to Vreg / 2. A level pulse signal S 4 is input to the CK terminal of the counter 70.
[0072]
The determination control unit 68 selects a power supply voltage Vreg according to the voltage of the drain output VD (t) output from the signal inverting amplifier 20 based on the input pulse signals S3 and S4. 82 is controlled to apply the selected power supply voltage Vreg to the signal inverting amplifier 20.
[0073]
As a result, the value of the power supply voltage Vreg applied to the signal inverting amplifier 20 can be controlled to the minimum necessary voltage at which stable oscillation can be continued.
[0074]
The detailed configuration of the power control circuit 60 will be described below.
[0075]
The determination control unit 68 includes the counters 70 and 72, the coincidence detection circuit 74, the gates 75, 76, and 77, and the up / down counter 80.
[0076]
An up / down clock is input as a signal S11 to the reset terminal R of the counters 70, 72 and one terminal of the gates 76, 77. This up / down clock outputs an H level signal at a rate of once every four periods of the oscillation output.
[0077]
A cycle clock S12 is input to the gate 75. This signal S12 outputs an H level signal at a rate of once every six cycles of the oscillation output.
[0078]
Next, the operation of the power control circuit 60 will be described using the timing chart shown in FIG.
[0079]
First, when the drain output VD (t) of the signal inverting amplifier 20 is inputted to the inverter 64 and inverter 62 as signals S1 and S2, the inverter 64 outputs an L level pulse signal S3 every time the signal S1 exceeds the logic level VGL2. The inverter 62 outputs an L level pulse signal S4 every time the input signal S2 exceeds a predetermined logic level (Vreg / 2).
[0080]
The determination control unit 68 compares the two pulse signals S3 and S4, determines the oscillation state of the oscillation circuit, and switches and controls the power supply voltage Vreg selected by the multiplexer 82.
[0081]
Specifically, the output pulse S4 of the inverter 62 is counted by the counter 70, the output pulse S3 of the inverter 64 is counted by the counter 72, and signals S5, S6, S7, and S8 representing the count values of both the counters 70 and 72 are Input to the coincidence detection circuit 74. The count values of both counters 70 and 72 are periodically reset by an up / down clock S11 output at a rate of once every four cycles.
[0082]
The coincidence detection circuit 74 outputs an H level coincidence detection signal S9 when the count values of both counters 70 and 72 coincide, and outputs an L level disparity detection signal S9 when they do not coincide.
[0083]
The output S9 of the coincidence detection circuit 74 functions as a gate signal for opening the gates 77, 76 and 75. When the output S9 is at the H level, the output is increased on condition that the cycle clock S12 is at the H level. The down clock S11 is input to the down count terminal DK of the up / down counter 80. When the output S9 is at the L level, the up / down clock S11 is input to the up count terminal UK of the up / down counter 80.
[0084]
The up / down counter 80 performs an up-count operation by a signal input to the up-count terminal UK, performs a down-count by a signal input to the down-count terminal DK, and uses the count values Q0 and Q1 as a power supply voltage control signal S14. Input to control signal input terminals A and B of the multiplexer 82. Here, since the outputs Q0 and Q1 of the up / down counter 80 have four states of “00”, “01”, “10”, and “11”, the multiplexer 82 has four types corresponding to these states. One of the power supply voltages is selected and output as the power supply voltage Vreg of the signal inverting amplifier 20.
[0085]
The coincidence detection circuit 74 of this embodiment determines that the oscillation is unstable when the number of output pulses S3 of the inverter 64 is smaller than the number of output pulses S4 of the inverter 62, and opens only the gate 77, and up-down The clock S11 is input to the upcount terminal UK of the up / down counter 80. As a result, the outputs Q0 and Q1 of the up / down counter 80 control the multiplexer 82 so as to select the power supply voltage Vreg which is one higher than the current value. As a result, the voltage of the drain output VD (t) output from the signal inverting amplifier 20 increases, and stable oscillation can be maintained.
[0086]
When the count values of both counters 70 and 72 match, that is, when the number of output pulses of both inverters 62 and 64 is the same, the coincidence detection circuit 74 determines stable oscillation, closes gate 77, Open 76. Thereby, when the cycle clock S12 is at the H level, the gate 75 is opened, and the up / down clock S11 is input to the down count terminal DK of the up / down counter 80. As a result, the outputs Q0 and Q1 of the up / down counter 80 control the multiplexer 82 so as to select the power supply voltage Vreg which is one lower than the current value. As a result, the power supply voltage applied to the signal inverting amplifier 20 is reduced, and low power consumption can be achieved.
[0087]
In this way, by adopting a configuration in which the power supply voltage Vreg corresponding to the voltage of the drain output VD (t) output from the signal inverting amplifier 20 is adopted, the crystal oscillation circuit is controlled so as to always have an appropriate supply power. be able to.
[0088]
In particular, according to the present embodiment, even when the capacity (current amplification factor, threshold voltage) of the signal inverting amplifier 20 varies during mass production, optimal power supply control is performed without being affected by this, and low power consumption is achieved. Electricity can be achieved.
[0089]
That is, when the capability of the signal inverting amplifier 20 is high, the power supply voltage Vreg is set to a low value. In this case, since the capability of the signal inverting amplifier 20 is high, its oscillation stability is originally high. Therefore, even if power supply from the power supply is reduced, oscillation can be continued stably, so that power consumption can be reduced.
[0090]
Further, when the capability of the signal inverting amplifier 20 is low, a high value is set as the power supply voltage Vreg. As a result, when the signal inverting amplifier 20 having a low capability is used, sufficient power is supplied and the oscillation stability can be improved.
[0091]
(Second embodiment)
FIG. 3 shows a second embodiment of the crystal oscillation circuit of the present invention, and FIG. 4 shows a timing chart thereof. Note that members corresponding to those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0092]
A feature of the present embodiment is that an oscillation output correction circuit 90 is provided in order to correct the frequency fluctuation of the oscillation output generated when the power supply voltage Vreg applied to the signal inverting amplifier 20 is switched and controlled.
[0093]
The oscillation output correction circuit 90 divides and outputs the frequency fs of the oscillation output S4 output through the inverter 62, and the power supply voltage Vreg applied from the power control circuit 60 to the signal inverting amplifier 20. The memory circuit 94 and the decoder 96 that perform frequency division control of the frequency dividing circuit 92 based on the value are included. Here, the memory circuit 94 and the decoder 96 function as frequency division control means.
[0094]
That is, when the power supply voltage applied to the crystal oscillation circuit changes, the output impedance of the signal inverting amplifier 20 and the parasitic capacitance of the electrostatic protection circuit added to the gate and drain terminals thereof change.
[0095]
Specifically, when the power supply voltage Vreg increases, the output impedance of the signal inverting amplifier 20 decreases, and the parasitic capacitance of the electrostatic protection circuit decreases. As a result, the oscillation frequency fs of the oscillation circuit increases.
[0096]
On the contrary, when the power supply voltage Vreg is lowered, the process reverse to the above is followed and the oscillation frequency fs of the oscillation circuit is lowered.
[0097]
In the crystal oscillation circuit of this embodiment, since the reference oscillation frequency is set to fs = 32768 Hz, frequency correction is performed so that the oscillation frequency does not deviate from the reference oscillation frequency even if the power supply voltage Vreg varies. It will be necessary.
[0098]
In particular, when this crystal oscillation circuit is used for obtaining a reference oscillation frequency of a watch or the like, such frequency correction is extremely important.
[0099]
The feature of the present embodiment is that, when the value of the power supply voltage Vreg varies due to the switching control of the power control circuit 60, the oscillation frequency itself of the oscillation circuit is not adjusted, but the frequency dividing circuit 92 in the next stage is used for the division. The signal to be circulated (signal after 16 kHz) is corrected.
[0100]
Specifically, when the power supply voltage Vreg increases, the signal divided by the next-stage frequency dividing circuit 92 is corrected in the delay direction, and when the power supply voltage Vreg decreases, the divided signal is corrected in the advance direction.
[0101]
The specific configuration will be described below.
[0102]
First, the oscillation output S4 output via the inverter 62 is input to the CK terminal of the frequency dividing circuit 92. Thereby, the frequency dividing circuit 92 divides the reference oscillation frequency fs of the oscillation output S4 and outputs the frequency-divided output to other circuit units.
[0103]
FIG. 4 shows ½ frequency divided output, ¼ frequency divided output, and 1/8 frequency divided output as signals such as F16K, F8K, and F4K in the case of performing a normal frequency dividing operation.
[0104]
In the present embodiment, the frequency correction using the frequency dividing circuit 92 is performed by using a known method called so-called logic steepness.
[0105]
The frequency dividing circuit 92 performs a frequency dividing operation for finally obtaining a signal of 1 Hz in addition to the above-described frequency dividing operations of 1/2, 1/4, and 1/8. In order to simplify the explanation, the case of performing the frequency dividing process using the above-described three frequency dividing operations of 1/2, 1/4, and 1/8 and the logical slow / fast method for this will be described as an example. To do.
[0106]
The frequency dividing circuit 92 includes 1/2 and 1/4 set terminals s｀1 and s｀2 and a 1/8 frequency dividing function reset terminal R3 in order to perform the above-described logic slow / slow frequency correction. And are provided. When correcting the frequency in the advance direction, the reset signal “0” may be input to the highest reset terminal R3. When correcting the frequency in the delay direction, the reset signal “1” is supplied to the highest reset terminal R3. ". Then, the advance amount or the delay amount may be input as set signals corresponding to the respective correction amounts to the lower digit set terminals s 2 and s 1.
[0107]
In this embodiment, four types of power supply voltages Vreg1, Vreg2,... Vreg4 are output from the power supply voltage generation circuit 66 and selectively used as the power supply voltages of the signal inverting amplifier 20. The frequency divider 92 performs frequency correction in the forward direction or the delay direction corresponding to the four types of voltage values.
[0108]
In the storage circuit 94, frequency correction amounts corresponding to the four types of power supply voltages are stored in advance as frequency division control data, and the decoder 96 is based on the power supply voltage control command S14 output from the up / down counter 80. Then, the frequency division control data corresponding to the power supply voltage Vreg to be selected and output is read, and this is output to the respective terminals s｀1, s｀2, and R3 of the frequency dividing circuit 92 as the frequency division control signal S30.
[0109]
That is, in the step of forming the circuit shown in FIG. 3 as an IC circuit on the semiconductor substrate, the above-described frequency division control data is stored in the memory circuit 94 in advance. Specifically, at the time of IC inspection, the IC is put into a test mode state, and the oscillation frequency fs generated when the four types of power supply voltages Vreg1... Vreg4 are sequentially switched and applied to the signal inverting amplifier 20 is measured. And it is grasped | ascertained how much oscillation frequency deviation generate | occur | produces with respect to the reference source oscillation frequency 32768Hz.
[0110]
Then, frequency division control data for correcting the oscillation frequency deviation amount data is written and stored in the storage circuit 94. In particular, by performing such a measurement at the time of IC inspection and writing frequency division control data corresponding to this in the memory circuit 94, it is possible to cope with variations in each constant of the crystal oscillation circuit at the time of IC mass production. An accurate reference signal can be output.
[0111]
Here, the four types of power supply voltages are designated by 2-bit data Q0 and Q1 output from the up / down counter 80 as the signal S14.
[0112]
Therefore, frequency division control data corresponding to the four types of power supply voltages specified by the 2-bit data is supplied to the storage circuit 94 to each terminal s｀1, s｀2, and R3 of the frequency division circuit 92. Each is stored as 3-bit data. The storage circuit 94 can be formed using, for example, an EEPROM, a FUSE cut type memory, an EPROM, a PROM, a DRAM, an SRAM, a flash memory, a ferroelectric memory, or the like as necessary.
[0113]
The decoder 96 receives a signal S20 for determining a frequency correction period. In this embodiment, as the signal S20, pulses a, b,... Are input at a rate of once per predetermined period of the oscillation frequency.
[0114]
The decoder 96 reads the frequency division control data corresponding to the power supply voltage from the storage circuit 94 in synchronization with the signal S20, and outputs this as the frequency division control signal S30.
[0115]
For example, as shown in FIG. 4, when the pulse forming the signal S20 is input at the timing a while the frequency dividing circuit 92 is performing the frequency dividing operation, the decoder 96 supplies power from the memory circuit 94 at this timing. The frequency division control data corresponding to the voltage is called and output to the frequency dividing circuit 92. Here, signals of s∥1 = 1, s∥2 = 1, and R3 = 1 are output as the frequency division control signal S30.
[0116]
As a result, the frequency division outputs F16K, F8K, and F4K of the frequency dividing circuit 92, which should be 0, 0, and 1 as shown by the wavy lines in the figure, become 1, 1, 0 as shown by the solid lines in the figure. Each frequency-divided output is corrected in the delay direction by one cycle of the oscillation frequency of 32 KHz. Here, it is determined that the power supply voltage is high and the oscillation frequency is also high, and the frequency is corrected in the delay direction by the frequency dividing circuit 92.
[0117]
When the signal S20 for determining the correction cycle is input to the decoder 96 at the timing b, here, s 分 1 = 1, s｀2 = 0, R3 = 0 as the frequency division control signal S30 corresponding to the power supply voltage. Is output.
[0118]
As a result, the frequency dividing circuit 92 that originally performs the frequency dividing operation as indicated by the wavy line performs the frequency dividing operation as indicated by the solid line in the figure and advances the 1/2 frequency divided output F16K by one cycle of the oscillation frequency of 32 KHz. Correct in the direction. Here, it is determined that the power supply voltage is lowered and the oscillation frequency is also lowered, and the frequency dividing circuit 92 corrects the frequency in the advance direction.
[0119]
As described above, according to the frequency division output correction circuit 90 of the present embodiment, the frequency deviation generated by switching and controlling the power supply voltage of the signal inverting amplifier 20 can be easily corrected by using the frequency division circuit 92. It is possible to generate an accurate reference frequency signal with a simple circuit.
[0120]
The present invention is not limited to the embodiments described above, and various modifications can be made within the scope of the gist of the present invention.
[0121]
For example, in the above embodiment, the case where the first and second circuits 22 and 24 constituting the signal inverting amplifier 20 are configured by using one transistor 26 and 28, respectively, has been described as an example. Accordingly, it is also possible to configure a circuit by combining elements other than those described above without impairing the functions of the first and second circuits 22 and 24.
[0122]
In the above-described embodiment, the case where the logic slow / rapid correction circuit 90 is used as the oscillation output correction means has been described as an example. However, the present invention is not limited to this, and other correction means may be adopted as necessary. May be.
[0123]
For example, the capacitance of the phase compensation capacitor of the crystal oscillation circuit may be variably controlled to correct the oscillation frequency itself.
[0124]
Specifically, several oscillation frequency correcting capacitors are installed inside the IC so as to be connected in parallel to the phase compensating capacitor 18 connected to the gate side of the crystal oscillation circuit.
[0125]
Then, according to the power supply voltage Vreg of the crystal oscillation circuit, the above-described oscillation frequency correcting capacitor is selected by the capacitance selection circuit and connected in parallel to the capacitor 18. Thereby, the gate capacitance for phase compensation of the crystal oscillation circuit becomes variable, and the oscillation frequency can be corrected.
[0126]
In particular, it is preferable that the capacitance control of the phase compensation capacitor is performed not on the drain-side capacitor 16 but on the gate-side capacitor 18. When the drain capacitance is varied, the oscillation frequency can only be finely corrected, and the current consumption of the oscillation circuit is greatly affected. On the other hand, if the gate capacitance is varied, the current consumption of the crystal oscillation circuit is significantly affected, and the oscillation frequency itself can be greatly corrected. In particular, when the power supply voltage of the oscillation circuit changes, the oscillation frequency varies greatly, so it is preferable to variably control the gate capacitance.
[0127]
Note that it is preferable to grasp the correction amount (connection capacitance value) of the oscillation frequency according to the power supply voltage Vreg at the time of manufacturing the IC, as in the case of the logical slow / fast method.
[0128]
Further, in this embodiment, the case where the crystal oscillation circuit is used for an electronic circuit for a watch has been described as an example. However, the present invention is not limited to this, but other uses such as a portable telephone and a portable computer terminal. It is also extremely effective when used in a wide range of portable electronic devices with limited power supply capacity, such as other portable devices.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first embodiment of a crystal oscillation circuit according to the present invention.
FIG. 2 is a timing chart of the circuit shown in FIG.
FIG. 3 is a circuit diagram of a second embodiment of the present invention.
4 is a timing chart of the embodiment shown in FIG.
[Explanation of symbols]
10 Crystal resonator
20 Signal inverting amplifier
22 First circuit
24 Second circuit
26, 28 transistors
40 Power supply transistor
60 Power control circuit
62, 64 inverter
66 Power supply voltage generation circuit
68 Judgment control unit
70,72 counter
74 Match detection circuit
75, 76, 77 gate
80 Up / Down Counter
82 Multiplexer
90 Oscillation output correction circuit
92 divider circuit
94 Memory circuit
96 decoder

Claims (8)

A signal inverting amplifier;
Power control means for controlling the power supply voltage of the signal inverting amplifier according to the oscillation output;
Including
The power control means includes
A power supply circuit for outputting a plurality of stable oscillation power supply voltages having different voltages after transition to stable oscillation;
A determination control means for determining whether stable oscillation is continued based on the oscillation output, and determining an optimum voltage of the power supply voltage supplied to the signal inverting amplifier required for continuing the stable oscillation;
Switching means for switching and controlling a power supply voltage applied from the power supply circuit to the signal inverting amplifier based on the determination result;
Oscillation output correction means for correcting frequency fluctuations of oscillation output during the power supply voltage control;
Including
The determination control means includes
If stable oscillation has continued for a predetermined time after the transition to stable oscillation, it is determined that the power supply voltage for continuing stable oscillation should be lowered. An oscillation circuit characterized by performing a process of determining to increase the power supply voltage of the circuit. In claim 1,
The oscillation output correction means includes
A frequency dividing means for counting the oscillation frequency;
Frequency division control means for performing frequency division control of the frequency division means based on the value of the power supply voltage applied to the signal inverting amplifier from the power supply circuit;
An oscillation circuit characterized by correcting frequency fluctuations of an oscillation output generated with fluctuations in power supply voltage. In claim 2,
The frequency division control means includes
Frequency division control data corresponding to a plurality of power supply voltages output from the power supply circuit is set in advance, and based on the frequency division control data corresponding to the value of the power supply voltage to be applied to the signal inverting amplifier, the frequency dividing means is divided. An oscillation circuit characterized by performing circumferential control. In any one of Claims 1-3,
A signal inverting amplifier;
It is configured to include a crystal resonator and a resistor that constitute a feedback circuit,
The feedback circuit includes:
An oscillation circuit, wherein the output of the signal inverting amplifier is fed back to the signal inverting amplifier as a signal whose phase is inverted by 180 degrees.   An electronic circuit comprising the oscillation circuit according to claim 1.   A semiconductor device comprising the oscillation circuit according to claim 1 or the electronic circuit according to claim 5.   An electronic apparatus comprising the oscillation circuit according to claim 1 or the electronic circuit according to claim 5.   A timepiece comprising the oscillation circuit according to claim 1 or the electronic circuit according to claim 5.

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