JP3737597B2 - Flip chip mounting circuit board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flip chip mounting wiring board in which a flip chip is connected to a main surface by soldering or the like, and more particularly to a structure of a wiring board such as a ceramic laminated package.
[0002]
[Prior art and its problems]
A wiring board on which a flip chip of an integrated circuit (IC) or other electronic components is mounted on the surface is required to have a flat surface. In addition, the main body may include at least one or more metal plane layers formed over a wide area for power supply or grounding and any number of conductor wiring layers forming a desired circuit. is there.
For example, as shown in FIG. 6A, in order to connect to the flip chip, a plurality of connection terminals 102 provided on the surface 100A of the ceramic substrate 100 are connected to the internal conductor wiring layer 108 and this. Are connected via via wirings 110 which are cylindrical conductors perpendicular to each other. The via wiring 110 passes through the opening 106 provided in the middle metal plane layer 104, and a via cover metallization (hereinafter referred to as a via cover) 112 interposed in the middle of each via wiring 110 is provided in the opening 106. Located in. The via cover 112 absorbs the positional deviation between the upper and lower vias 110a and 110b and connects them. Further, via covers 112 'are also interposed between the vias 110b and 110c and between the vias 110c and 110d, respectively.
A plurality of external terminals 114 are provided on the back surface of the substrate 100.
[0003]
Here, in order to prevent a short circuit between the via covers 112 or between the via covers 112 and the edge 106a of the opening 106, an interval S of about 100 μm is conventionally provided as shown in FIG. Yes.
By the way, the ceramic substrate 100 is formed by using a paste of a high melting point metal such as W or Mo on a plurality of green sheets whose main component is alumina, for example, by screen printing or the like, a required circuit, a metal plane layer, or a pad ( After the terminal is formed, these green sheets are laminated, pressed and fired.
The opening 106 in the metal plane layer 104 is also formed during screen printing. The via wiring 110 is formed by opening pores in each green sheet and forcibly sucking and filling a high melting point metal paste therein, and a via cover 112 is formed at one end of the pores by screen printing. .
[0004]
However, when the flip chip area in which the flip chip connection terminal 102 is provided is located above the opening 106 in the substrate 100, the opening that forms the gap S between the edge 106 a of the opening 106 and the plurality of via covers 112. The periphery of the portion 106 may be crushed in the vertical direction in the pressure bonding and firing process, and a dent H may be generated on the surface 100A of the substrate 100 as shown in FIG. Further, due to the dent H, the flatness of the surface 100A of the substrate 100 is impaired, and there is a problem that the flip chip to be mounted and each connection terminal 102 on the surface 100A cannot be connected.
The number of the metal plane layers 104 formed between the surface 100A of the substrate 100 and the conductor wiring layer 108 increases as the number of via wirings 110 (same cover 112) penetrating through the openings 106 increases. As the thickness increases, or the thickness of the opening 106 increases, it tends to occur more remarkably.
[0005]
In order to reduce this dent H, up to now, (1) a method of reducing the thickness of the metal plane layer and reducing the thickness of the opening itself, or (2) after laminating and sintering the green sheet Thus, a method of polishing and flattening the flip chip area on the surface of the substrate has been used. (3) It has also been studied to fill the opening with an insulating paste.
However, in the above method (1), even if the metal plane layer is thinned, the thickness of all the openings increases as the number of metal plane layers increases. Become. Further, the methods (2) and (3) are not preferable from the viewpoint of productivity because the number of steps of polishing and filling with an insulating paste increases.
[0006]
[Problems to be Solved by the Invention]
The present invention solves the problems of the conventional techniques described above, and can be mounted without increasing the number of processes while having a flat main surface and mounting a flip chip reliably regardless of the number of metal plane layers. An object of the present invention is to provide a wiring board for flip chip mounting.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention reduces the distance (area) between via covers of a plurality of via wirings penetrating through the opening or between each via cover and the edge of the opening in the opening of the metal plane layer. This is made by paying attention to the fact that the generation of the dent can be suppressed.
That is, the flip-chip mounting wiring board of the present invention has a connection terminal for mounting the flip chip on the main surface, and at least one layer is formed in the inside, immediately below the region where the flip chip is mounted. A metal plane layer having an opening and a conductor wiring layer formed on a side farther from the main surface than the metal plane layer, and via a plurality of via covers provided in the opening of the metal plane layer A wiring board having a plurality of via wirings respectively connecting between the connection terminals and the conductor wiring layer, wherein the total area of the plurality of via covers when viewed in plan is 30% of the area of the opening It is the above.
[0008]
As the connection terminal, a connection pad is often used, but an end portion of the via wiring exposed on the main surface may be used as the connection terminal.
In the flip-chip mounting wiring board according to the present invention, the plurality of via covers may be formed in a substantially rectangular shape in a region where the plurality of via wirings are arranged in a substantially lattice shape in plan view. Features.
Furthermore, the shape of each via cover is formed so that the outline of the planar shape formed by the plurality of via covers is substantially similar to the shape of the edge of the opening.
With these configurations, the total cross-sectional area of the plurality of via covers can be easily set to 30% or more of the area of the opening.
[0009]
Further, a flip chip mounting wiring board in which the plurality of via covers and the distance between each via cover and the edge of the opening of the metal plane layer are less than 90 μm is also included.
In addition, said space | interval points out the shortest distance between covers.
In addition, the distance is preferably about 70 m.
According to the above configuration, the interval between the via covers and the interval between the edge of the opening and each via cover can be made as small as possible while maintaining the insulation between them, and also by pressing and firing during the production of the ceramic substrate. It becomes difficult to produce a dent on the main surface of the substrate.
[0010]
Further, the upper limit of the total area of the via cover with respect to the area of the opening in plan view is about 50% in order to maintain insulation between the two. Incidentally, this area ratio in the prior art was 10 to 20%.
Further, a conductive spacer having a thickness substantially the same as that of the metal plane layer is formed between the plurality of via covers in the openings or the edges of the via covers and the edges of the openings. Also included is a flip-chip mounting wiring board disposed with an interval of less than 90 μm.
According to this configuration, the area ratio and / or the interval can be more easily realized.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
In the following, preferred embodiments of the present invention will be described with reference to the drawings.
FIG. 1A shows a partial vertical cross-sectional view of a flip-chip mounting wiring board 1, and a connection pad (terminal) for mounting a flip chip (not shown) such as an IC on its main surface 1A. ) 2 is provided in plural. Further, for example, a metal plane layer 4 for power supply and a plurality of conductor wiring layers 8 forming a desired circuit thereunder are built in the substrate 1. A part of the plurality of connection pads 2 is electrically connected to the metal plane layer 4 via vias (via wirings) 11. The other connection pads 2 are electrically connected to the lower conductor wiring layer 8 via the via 10a, the via cover 12 and the via 10b, or the via wiring 10 including the vias 10a, 10b and 10c and the via covers 12 and 12 '. The
[0012]
In this case, in order to prevent a short circuit between the metal plane layer 4 and the via cover 12, an opening 6 as shown in FIG. 1B is formed in the plane layer 4. The via cover 12 is interposed to connect the upper and lower vias 10 a and 10 b, and the via cover 12 between the vias 10 a and 10 b is located substantially in the opening 6.
The opening 6 has a rectangular shape of approximately 1.07 mm square in plan view, and the interval S between the edge 6a of the opening 6 and the surrounding via cover 12 and the interval S between the via covers 12 are approximately 70 μm. It is. Incidentally, one side of the via cover 12 has a square of about 180 μm, and the ratio of the total area of all the via covers 12 to the area of the opening 6 in plan view is about 45%.
In FIG. 1A, each conductor wiring layer 8 is electrically connected to an external terminal pad 18 provided on the back surface of the substrate 1 through a via 10d or vias 10c and 10d and a via cover 12 '.
[0013]
Such a substrate 1 is manufactured as follows. For example, a plurality of green sheets mainly composed of alumina are prepared, and a refractory metal paste of W or Mo is applied on each sheet by screen printing, and the metal plane layer and the conductor wiring constituting the required various circuits. Form a layer. At the time of printing, the opening 6 is formed in the metal plane layer 4. In addition, each green sheet is previously provided with pores at predetermined positions, and ink metallization similar to that of the metal paste is forcibly sucked and filled using negative pressure or the like to form vias 10a and the like. A via cover 12 is formed on the exposed portion at one end of the screen during the screen printing.
These green sheets are laminated in a predetermined order, pressed, and then fired, whereby the ceramic wiring board 1 can be obtained.
[0014]
Here, the present invention and the prior art will be compared with specific examples. An opening of the same shape and size is provided in the metal plane layer, and the area ratio between the cross-sectional area of the entire via cover and the area of the opening of the via wiring passing through the opening, and the maximum depression on the main surface of the substrate above these Were measured according to the arrangement form of vias. The results are shown in Table 1.
The values shown in Table 1 are according to the following conditions.
{Circle around (1)} The openings are square in both the example of the present invention and the prior art.
(2) In the prior art, the via covers were circular with a diameter of 100 μm, the distance between the via covers was 150 μm, and the distance between the via cover and the edge of the opening was 90 μm. Therefore, the dimension of one side of the opening is 530 μm in 2 × 2 rows, 780 μm in 3 × 3 rows, 1030 μm in 4 × 4 rows, and 1280 μm in 5 × 5 rows.
(3) In the example of the present invention, the interval between the via covers is 70 μm, the interval between the via cover and the edge of the opening is 70 μm, and the via cover has a width of 180 μm in diameter or a square having a side of 180 μm. It was. Therefore, the dimension of one side of the opening is 570 μm in 2 × 2 rows, 820 μm in 3 × 3 rows, 1070 μm in 4 × 4 rows, and 1320 μm in 5 × 5 rows.
[0015]
[Table 1]
[0016]
In Table 1, the area ratio in the prior art is 11 to 12%, while that according to the present invention is 31 to 46.5%. Further, the maximum dent on the surface of the substrate was 10 to 35 μm in the conventional technique, whereas that according to the present invention was 8 to 20 μm, and in the same arrangement, all were lower than the conventional one. Further, flip chips are connected to the connection pads on the surface of the substrate. In the prior art, the recessed portion pads are separated from the solder bumps on the chip side, whereas those according to the present invention are on the chip side. All of the solder bumps were fully connected. From these results, the effect of the present invention can be easily understood, and the significance of defining the area ratio will be understood.
[0017]
FIG. 2 relates to another embodiment of the present invention, and FIG. 2A shows a circular via cover corresponding to the vias 26 in which square openings 22 are provided in the metal plane layer 20 and arranged in a lattice pattern therein. 24 are arranged in three vertical and horizontal directions, and the interval S between the opening 22 and each cover 24 and the interval S between the covers 24 are both set to 70 μm. Vias 26 are respectively connected to the top and bottom of each cover 24.
Incidentally, if the opening 22 is 0.82 mm square, the diameter of each cover 24 is 180 μm, and the interval S is 70 μm, the ratio of the total cross-sectional area of all via covers 24 to the area of the opening 22 in plan view is 34%. is there.
In the case where the vias 26 are arranged in a lattice shape, as shown in FIG. 1B, when the via covers 24 are square or rectangular, the covers 24 are kept in contact with each other while maintaining the intervals S. Can be densely arranged in a lattice pattern, and the gaps S can be made as small as possible. Therefore, the area ratio can be easily increased to around 50%.
[0018]
In FIG. 2B, the metal plane layer 30 is provided with openings 32 each having a plurality of curved edges 33 on the four sides, and round via covers 34 are arranged vertically and horizontally at positions that are concentric with the curved edges 33. They are arranged one by one. Note that the distance S between the curved edge 33 of the opening 32 and each cover 34 and the distance S between the covers 34 are both less than 90 μm, and vias 36 are connected to the top and bottom of each cover 34, respectively.
According to such a configuration, since the outline of the planar shape formed by the plurality of via covers 34 is substantially similar to the opening 32, the ratio of the total cross-sectional area of all the via covers 34 to the openings 32 can be reliably increased to 30% or more. And since each said space | interval S can also be easily reduced to less than 90 micrometers, it is a preferable form when implementing this invention.
[0019]
FIG. 3 relates to still another embodiment of the present invention, and FIG. 3A shows that the metal plane layer 40 is provided with an opening 42 having a plurality of curved edges 43 on its four sides and is concentric with each curved edge 43. In this position, three round via covers 44 are arranged vertically and horizontally, and a diamond-shaped conductive spacer 48 is arranged at a position surrounded by four covers 44 adjacent to each other. The conductive spacer 48 has the same material and thickness as the metal plane layer 40, and a side confronting each cover 44 is provided with a curve concentric with the cover 44, and an interval S less than 90 μm. Is formed. That is, since the spacer 48 can be screen-printed simultaneously with the metal plane layer 40, it can be formed without increasing the manufacturing process. Note that reference numeral 46 in the drawing denotes vias connected to the upper and lower sides of the cover 44.
Therefore, the interval S between the curved edge 43 of the opening 42 and the cover 44 and the interval S between the cover 44 and the conductive spacer 48 can be made as small as possible and are surrounded by the plurality of covers 44 in the opening 42. Even at this position, the step due to the thickness of the metal plane layer 40 can be eliminated, so that the formation of a dent on the main surface of the substrate can be further reliably suppressed. This is effective for a flip chip mounting substrate having a structure in which a large number of vias (via covers) penetrate through one opening.
The spacer 48 may be disposed at a position surrounded by the covers 44 and the curved edges 43 of the openings 42 with the spacing S therebetween.
[0020]
In FIG. 3B, a hexagonal opening 52 having a plurality of curved edges 53 in the periphery is provided in the metal plane layer 50, and a round via cover 54 is located inside and concentrically with each curved edge 53. 7 are arranged in a zigzag pattern. In this case, since the via covers 54 are arranged in a staggered manner, the distance between them can be made relatively small as compared with those arranged in the lattice form. For this reason, it is easy to make the total cross-sectional area of all the via covers 54 with respect to the openings 52 30% or more, which is an effective form for implementing the present invention. Note that reference numeral 56 in the drawing denotes vias connected to the upper and lower sides of the via cover 54.
[0021]
FIG. 4 relates to another embodiment of the present invention, in which a square-shaped opening 62 having rounded corners is formed in the metal plane layer 60, twelve vias 65 are formed along each edge in the opening 62, and the center. In order to concentrate and penetrate the four vias 67, an upper and lower via 65 disposed in the periphery is interposed between the upper and lower vias 65 disposed in the periphery, and an upper and lower via cover 64 disposed in the center is interposed. A substantially octagonal via cover 66 is interposed between the vias 67 in plan view.
Each of the via covers 64 narrows the interval S in the opening 62 and the outline of the planar shape formed by the entirety of the via covers 64 is substantially similar to the opening 62, so that the entire via covers 64 and 66 are completely cut off from the opening 62. The area ratio can be easily set to 30% or more. In addition, by utilizing such an irregularly shaped via cover 64, when there are a plurality of via wirings penetrating up and down a random position in the opening 62, the total cross-sectional area of those via covers can be reliably increased. .
[0022]
FIG. 5 relates to another embodiment of the present invention. FIG. 5A shows that an elliptical opening 72 is formed in the metal plane layer 70, and a pair of via covers 73 are disposed in the opening 72, and those A via 74 is connected to the upper and lower sides. Even when there are only two such vias 74, the occurrence of the dents can be prevented if a flip chip area is present on the main surface directly above them.
In FIG. 5 (B), a polished-shaped opening 76 is formed in the metal plane layer 75, and two large and small via covers 77a and 77b are arranged in the opening 76 with substantially the same spacing S, and Large and small diameter vias 78a and 78b are respectively connected to the upper and lower sides.
In this way, when the diameters of the plurality of vias 78a and 78b are different, by adopting the opening 76 that is substantially similar to the outline shape in plan view formed by the entire via covers 77a and 77b interposed between them, The present invention can be easily implemented.
[0023]
FIG. 5C shows an opening 82 having a substantially L shape in a plan view in the metal plane layer 80, and three types of via covers 84, 86, and 88 having large, medium, and small diameters disposed therein, Large, medium and small diameter vias 85, 87 and 89 are connected to the top and bottom. As described above, even when there are a plurality of types of vias and the arrangement thereof is random, the outline shape in plan view formed by the entire via covers 84, 86, 88 is substantially similar to the shape of the opening 82. Therefore, the total cross-sectional area of all the via covers 84, 86, 88 with respect to the opening 82 is set to 30% or more, or the interval between the opening 82 and each of the via covers 84, 86, 88 and between the via covers 84, 86, 88 are The interval can be easily set to less than 90 mμ.
Further, FIG. 5D shows that a substantially rhombic opening 92 is formed in the metal plane layer 90 in plan view, and a deformed pentagonal via cover 94 is formed vertically in the center of the opening 92 at a predetermined interval. Are arranged symmetrically, and triangular via covers 96 are arranged symmetrically on the left and right, and a large diameter via 95 is provided above and below the central via cover 94, and a small diameter via 97 is provided above and below the left and right via covers 96, respectively. Connected.
The outline shape in plan view formed by each of the via covers 94 and 96 is substantially similar to the opening 92, and thus is one of the forms suitable for the implementation of the present invention.
[0024]
The present invention is not limited to the embodiments described above.
For example, in a wiring board, conductor wiring layers are provided above and below the metal plane layer, and a plurality of via wirings pass through the openings provided in the metal plane layer, or a plurality of metal plane layers and a plurality of conductors. The present invention can also be applied to a substrate having a structure in which wiring layers are alternately provided and a plurality of via wirings penetrate through the openings provided in each metal plane layer.
In addition, the conductive spacers arranged in the openings of the metal plane layer may be arranged in a line shape or a mesh shape that partitions between the plurality of via covers.
Furthermore, the cross-sectional shape of the via itself can be similar to that of an irregularly shaped via cover interposed therebetween, and the conductivity thereof can be enhanced.
As a terminal for connecting to the flip chip, in addition to the connection pad formed by the metallized printing, the end exposed on the main surface of the uppermost via can be used as it is as a connection terminal. .
[0025]
【The invention's effect】
According to the wiring board of the present invention described above, even if a plurality of via wirings penetrates through the opening of the metal plane layer through the via cover, the main surface of the board above them does not or is not likely to be recessed. Therefore, the flip chip can be accurately and reliably mounted on the connection pad on the main surface. In addition, when manufacturing this substrate, it can be easily obtained without increasing the number of steps.
In addition, according to the inventions of claims 2 to 5, it is possible to more reliably prevent the occurrence of the dent.
[Brief description of the drawings]
FIG. 1A is a partial longitudinal sectional view showing one embodiment of a wiring board according to the present invention, and FIG. 1B is an end view taken along line BB in FIG.
FIGS. 2A and 2B are end views similar to FIG. 1B showing another embodiment of the present invention.
FIGS. 3A and 3B are end views similar to FIG. 1B showing different embodiments of the present invention.
FIG. 4 is an end view similar to FIG. 1 (B) showing another embodiment of the present invention.
5 (A) to 5 (D) are end views similar to FIG. 1 (B) showing another embodiment of the present invention.
6A is a partial longitudinal sectional view showing a conventional wiring board, FIG. 6B is an end view taken along line BB in FIG. 6A, and FIG. 6C is a partially enlarged sectional view in FIG. .
[Explanation of symbols]
1 ……………………………………………………………… Wiring board 2, 18 …………………………………………………… ... Pad for connection (terminal)
4,20,30,40,50,60,70,75,80,90 ………………………… Metal plane layer 6,22,32,42,52,62,72,76,82 , 92 …………………………… Opening 6a, 33,43,53 …………………………………………………… Edge / curved edge 8 ………… …………………………………………………… Conductor wiring layer 10,26,36,46,56,65,67,74,78,85,87,89,95,97 ………… Via wiring / via 12,12 ′, 24,34,44,54,64,66,73,77,84,86,88,94,96 …… via cover 48 …………………… ……………………………………… Conductive spacer S ……………………………………………………………… Interval [Table 1]

Claims (5)

Has a connection terminal for mounting the flip chip on the main surface,
A metal plane layer having at least one layer formed therein and having an opening immediately under the flip chip mounting region; and a conductor wiring layer formed on a side farther from the main surface than the metal plane layer; And having
A wiring board having a plurality of via wirings respectively connecting the connection terminals and the conductor wiring layer via a plurality of via covers provided in the openings of the metal plane layer;
A flip-chip mounting wiring board, wherein a total area of the plurality of via covers in a plan view is 30% or more of an area of the opening. In the region where the plurality of via wirings are arranged in a substantially lattice shape in plan view,
The flip-chip mounting wiring board according to claim 1, wherein each of the plurality of via covers is formed in a substantially rectangular shape. The shape of each via cover is formed so that the outline of the planar shape formed by the plurality of via covers as a whole is substantially similar to the shape of the edge of the opening. Flip chip mounting wiring board. 4. The flip-chip mounting wiring board according to claim 1, wherein a distance between the plurality of via covers and each via cover and an edge of the opening of the metal plane layer is less than 90 [mu] m. A conductive spacer having a thickness substantially the same as that of the metal plane layer is less than 90 μm from the surrounding edge of each via cover or opening at a position surrounded by the plurality of via covers or each via cover and the edge of the opening in the opening. 5. The flip-chip mounting wiring board according to claim 1, wherein the flip-chip mounting wiring board is disposed with an interval of.

Images