JP3729032B2 - Shift register, shift register control method, data line driving circuit, scanning line driving circuit, electro-optical panel, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving circuit used for driving an electro-optical panel having a plurality of scanning lines and a plurality of data lines and pixel electrodes and switching elements arranged in a matrix corresponding to the intersections thereof, The present invention relates to a control method, a data line driving circuit and a scanning line driving circuit using the driving circuit, an electro-optical panel, and an electronic apparatus.
[0002]
[Prior art]
In a conventional electro-optical device, for example, a liquid crystal device, a plurality of data lines and a plurality of scanning lines are formed in an image display area, and a thin film transistor ( Thin Film Transistor: hereinafter referred to as TFT). A driving circuit of the liquid crystal device includes a data line driving circuit for supplying a data line signal, a scanning line signal, and the like to the data line and the scanning line at a predetermined timing, a scanning line driving circuit, and the like.
[0003]
These drive circuits generate a selection signal by the following method, and generate a data line signal and a scanning line signal based on the selection signal. The driving circuit firstly transfers the start pulse in accordance with the clock signal and the inverted clock signal obtained by inverting the clock signal, and generates a plurality of shift pulses whose phases are shifted by 1/2 period of the clock signal, and secondly, Each selection signal is generated by calculating the logical product of the shift pulse and the next shift pulse.
[0004]
If the drive circuit operates ideally, each selection signal is exclusively active, but in an actual drive circuit, due to the time delay of the logic circuit and the characteristics of the active element, the active period of the adjacent selection signal May overlap.
[0005]
Therefore, a technique for eliminating the overlap of active periods using an inhibit signal is known. FIG. 20 is a block diagram showing the configuration of a conventional data line driving circuit and its peripheral circuits, and FIG. 21 is a timing chart thereof.
[0006]
As shown in the figure, the data line driving circuit includes shift units U0, U1, U2,. , Un sequentially transfer the start pulse DX based on the X clock signal XCK and the inverted X clock signal XCKB, and output the shift pulses C0, C1, C2,. AND circuits G1, G2,..., Gn calculate logical products of input / output signals of the corresponding shift units U1, U2,..., Un, and output signals Sa1, Sa2,.
[0007]
On the other hand, the inhibit signal INHB is a signal that becomes L level (active) only for a predetermined period around the timing at which the logic levels of the X clock signal XCK and the inverted X clock signal XCKB transition as shown in the figure.
[0008]
Here, the AND circuits G1 ′, G2 ′,... Calculate the logical product of the inhibit signal INHB and the signals Sa1, Sa2,. Therefore, the selection signals SR1, SR2,... Are at the L level during the period when the inhibit signal INHB is at the L level as shown in the figure. This makes it possible to provide an inactive period between adjacent selection signals.
[0009]
The selection signals SR1, SR2,... Generated in this way are supplied to the control input terminals of the switches SW constituting the sampling circuit. In this example, each switch SW is composed of an N-channel transistor. Therefore, when the gate voltage becomes H level, the image signal VID is sampled and supplied to each data line as a data line signal. Since each data line has a wiring capacity, the voltage of the image signal VID is written to the wiring capacity in the sampling process.
[0010]
[Problems to be solved by the invention]
By the way, since the inhibit signal INHB is supplied to the AND circuits G1 ′, G2 ′,... Via the signal supply line LX, the input capacitance of these circuits is attached to the signal supply line LX. For this reason, it is necessary to use an inhibit signal driving circuit that can supply a large current at a high response speed, and there is a problem that the circuit configuration becomes large and a large current consumption is required.
[0011]
Further, if the pulse width of the inhibit signal INHB is wide, the writing time for writing the image signal VID to the data line is shortened, and the image signal VID cannot be sufficiently written depending on the degree. Therefore, it is desirable to narrow the pulse width of the inhibit signal INHB. In particular, in order to display a high-definition image, it is necessary to increase the number of data lines. In this case, the active period of the signals Sa1, Sa2,. It will be necessary. On the other hand, narrowing the pulse width of the inhibit signal INHB means an increase in high frequency components.
[0012]
However, there is a problem that it is difficult to narrow the pulse width because the drive capability of the inhibit signal drive circuit has a certain limit.
[0013]
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to reduce the load on a circuit for driving an inhibit signal, reduce power consumption, and operate with an inhibit signal having a narrow pulse width. It is to provide a driving circuit and the like.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the driving circuit of the present invention includes a plurality of scanning lines, a plurality of data lines, pixel electrodes arranged in a matrix corresponding to the intersections of the scanning lines and the data lines, and A shift register unit, a selection unit, and a logical operation unit are used in an electro-optical panel having a switching element, and the shift register unit sequentially shifts a start pulse based on a clock signal. A plurality of shift unit circuits that respectively output output signals, and the selection unit includes a plurality of control unit circuits provided corresponding to the respective shift unit circuits, and a certain control unit circuit includes: An active period in which at least one of the input signal and the output signal of the corresponding shift unit circuit is active is specified, and the active period is determined from the pulse signal including a plurality of pulses. A selection pulse signal is generated by selecting a pulse generated in a period, and the logic operation unit includes a plurality of operation unit circuits provided corresponding to each shift unit circuit, and a certain operation unit circuit has a corresponding shift A period in which both an input signal and an output signal of a unit circuit are active is specified, and a selection signal for selecting the scanning line or the data line is generated based on the period and the selection pulse signal. .
[0015]
According to the present invention, the selection signal is generated based on the period in which both the input signal and the output signal of the shift unit circuit are active and the selection pulse signal (selection inhibit signal) (for example, the pulse width based on the selection inhibit signal) The period is included in a period in which one of the input signal and the output signal is active. In such a period, the selection unit takes in a pulse signal (inhibit signal) and generates a selection pulse signal. In other words, not all control unit circuits always capture pulse signals, but a certain control unit circuit selectively captures pulses (inhibit pulses) required by the corresponding arithmetic unit circuit. From the viewpoint of the circuit supplying the pulse signal, the control unit circuit does not act as a capacitive load during the period when the control unit circuit does not capture the pulse signal. Can be reduced. In addition, since the capacitive load is small, the pulse width of the pulse signal can be reduced. The pulse signal may be an inhibit signal having a plurality of inhibit pulses or an enable signal having a plurality of enable pulses.
[0016]
Here, the selection unit, the shift register unit, and the logic operation unit are arranged in this order, and the signal supply line for supplying the clock signal and the pulse signal is opposite to the side on which the shift register unit outputs the output signal. It is preferable to arrange on the side. Thereby, the intersection part of wiring can be reduced and it becomes possible to reduce the parasitic capacitance accompanying an intersection part.
[0017]
The clock signal is composed of a first clock signal and a second clock signal obtained by inverting the first clock signal. In each shift unit circuit, the previous stage shift signal is supplied to the input terminal and the output terminal is connected to the connection point. And a first inverter that operates only when the supplied control signal is active, while the output terminal is in a high impedance state when the control signal is inactive, and the output terminal is connected to the connection point. The second inverter that operates only when the supplied control signal is active, while the output terminal is in a high-impedance state when the control signal is inactive, and the input terminal is connected to the connection point. A third inverter having an output terminal connected to the input terminal of the inverter, and the shift unit circuit in the odd-numbered stage includes the first clock; Is supplied as a control signal for the first inverter, the second clock signal is supplied as a control signal for the second inverter, and the second clock signal is supplied to the even-numbered shift unit circuit in the first stage. The one clock signal may be supplied as a control signal for the second inverter while being supplied as a control signal for the inverter.
[0018]
In addition, the control unit circuit shifts the corresponding shift based on the first internal signal extracted from the connection point in the corresponding shift unit circuit and the second internal signal extracted from the connection point in the previous shift unit circuit. It is preferable to specify an active period in which at least one of the input signal and the output signal of the unit circuit is active. In this case, since the active period is specified based on the internal signal not passing through the third inverter, the delay time from the timing when the logic level of the clock signal transitions to the start or end of the active period is shortened. be able to.
[0019]
Further, the control unit circuit may specify an active period in which at least one of these signals is active based on an input signal and an output signal of the corresponding shift unit circuit. As the logic circuit for specifying the period, a NAND circuit or an AND circuit can be used.
[0020]
The control unit circuit is connected to a logic circuit that specifies an active period in which at least one of an input signal and an output signal of the corresponding shift unit circuit is active, and a signal supply line that supplies the pulse signal, It is desirable to include a switch circuit that generates the selection pulse signal by being turned on only when the output signal of the logic circuit is active. In this case, since the switch circuit is turned off when the output signal of the logic circuit is inactive, the switch circuit is disconnected from the signal supply line. Therefore, in such a case, since no capacitance is added to the signal supply line, it is possible to reduce the capacitance associated with the signal supply line.
[0021]
Next, in the drive circuit described above, it is preferable that the shift unit circuit resets the logic level of the shift signal to an inactive level when an externally supplied reset signal becomes active. When the power is fully turned on, the input / output signal of each shift unit circuit may be H level or L level. Therefore, pulse signals may be taken in all control unit circuits. In such a case, since the capacitive load becomes large, if the pulse signal is driven by a circuit having a small driving capability, the voltage level of the signal supply line cannot be changed sufficiently, and eventually the active period by the pulse signal You may not be able to make this restriction. According to the present invention, when the reset signal is activated, the shift signal that is the output signal of the shift unit circuit can be reset, and the capture of the pulse signal can be stopped in all the control unit circuits. . Therefore, by activating the reset signal when the power is turned on, it is possible to supply a pulse signal using a circuit having a small driving capability.
[0022]
More specifically, the clock signal is composed of a first clock signal and a second clock signal obtained by inverting the first clock signal. Each shift unit circuit is supplied with the previous stage shift signal at the input terminal and the output terminal at the connection point. And a first inverter that puts the output terminal in a high impedance state when the supplied control signal is inactive, and an output terminal at the connection point. A second inverter that is connected and operates only when the supplied control signal is active, while the output terminal is in a high impedance state when the control signal is inactive, and one input terminal at the connection point Is connected, the reset signal is supplied to the other input terminal, and supplied to one input terminal when the reset signal is inactive A reset logic circuit that resets the shift signal of the shift unit circuit to an inactive level when the reset signal is active, and an output terminal connected to the input terminal of the second inverter. The odd-numbered shift unit circuit is supplied with the first clock signal as a control signal for the first inverter, while the second clock signal is supplied as a control signal for the second inverter; It is desirable that the even-numbered shift unit circuit is supplied with the second clock signal as a control signal for the first inverter while the first clock signal is supplied as a control signal for the second inverter. Further, it is preferable that a NOR circuit is used as the reset logic circuit when the start pulse is active at the H level, and a NAND circuit is used as the reset logic circuit when the start pulse is active at the L level. Thereby, each shift unit circuit can be reset reliably.
[0023]
Next, a data line side driving circuit according to the present invention includes the above-described driving circuit, and samples an input image signal based on each selection signal output from the driving circuit and supplies it to each data line. And According to the present invention, since the active periods of the selection signals do not overlap, the input image signal can be sampled and supplied to a predetermined data line, and a high-quality image without crosstalk can be displayed.
[0024]
Next, a scanning line side driving circuit according to the present invention includes the above-described driving circuit, and drives each scanning line based on each selection signal output from the driving circuit. According to the present invention, since the active periods of the selection signals do not overlap, a plurality of scanning lines are not simultaneously selected, and a high quality image can be displayed.
[0025]
Next, according to the control method of the present invention, the reset signal is activated for every field or every plurality of fields. In this case, since it is reset for every field or every plurality of fields, since the shift unit circuit is reset in the first field after the power is turned on, even when the power is turned on, the output signal of the shift unit circuit Even if all of them are active and the load when supplying the inhibit signal is very heavy, the load can be reduced by resetting. As a result, the configuration of the circuit for driving the pulse signal can be simplified and the power consumption can be reduced.
[0026]
The reset signal may be active at least during a part of a period from when a power supply voltage is supplied to the driving circuit until the clock signal is supplied. In this case, all the output signals of the shift unit circuit become active even when the power is turned on because the reset is always performed in the period from the supply of the power supply voltage to the supply of the clock signal. Even when the load when supplying the pulse signal is extremely heavy, the load can be reduced by resetting.
[0027]
Next, the electro-optical panel of the present invention includes a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to the intersections of the scanning lines and the data lines. And a data line side driving circuit described above and a scanning line side driving circuit for driving the scanning line. Further, the above-described one may be used as the scanning line side driving circuit. According to these configurations, the drive circuit is built on the electro-optical panel. In this case, it is desirable that the switching element formed in the pixel region is a thin film transistor and the driving circuit is also formed of a thin film transistor.
[0028]
In addition, an electronic apparatus according to the present invention includes the above-described electro-optical panel, and includes, for example, a viewfinder, a mobile phone, a notebook computer, a video projector, and the like used for a video camera.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
<1. First Embodiment>
Embodiments of the present invention will be described below with reference to the drawings.
[0030]
<1-1: Overall Configuration of Electro-Optical Device>
First, a liquid crystal display device will be described as an example of an electro-optical device. FIG. 1 is a block diagram showing an electrical configuration of the liquid crystal display device. As shown in this figure, the liquid crystal display device includes a liquid crystal display panel 100, a timing generator 200, and an image signal processing circuit 300. Among them, the timing generator 200 outputs a timing signal (described later if necessary) used in each unit. The phase expansion circuit 302 in the image signal processing circuit 300 receives a single image signal VID and expands it into an N-phase (N = 6 in the figure) image signal and outputs it in parallel. This corresponds to a serial-parallel conversion circuit that converts image signals into N parallel signals. Here, the reason why the image signal is developed into the N phase is that the sampling time to be described later increases the application time of the image signal at the source electrode of the TFT functioning as a switching element, thereby reducing the writing time for the wiring capacity of the data line. This is to ensure enough.
[0031]
On the other hand, the amplifying / inverting circuit 304 inverts one of the phase-developed image signals that needs to be inverted, and after that, amplifies the signals appropriately and in parallel with the liquid crystal display panel 100 as image signals VID1 to VID6. To supply. In general, regarding whether or not to invert, whether the data signal application method is (1) polarity inversion in units of scanning lines, (2) polarity inversion in units of data signal lines, or (3) pixels It is determined depending on whether the polarity is inverted in units or (4) polarity is inverted in screen units, and the inversion period is set to one horizontal scanning period or one vertical scanning period.
[0032]
Further, the timing of supplying the phase-developed image signals VID1 to VID6 to the liquid crystal display panel 100 is the same in the liquid crystal display device shown in FIG. 1, but may be sequentially shifted in synchronization with the dot clock. The N-phase image signal may be sampled sequentially by a sampling circuit described later.
[0033]
<1-2: Configuration of liquid crystal display panel>
Next, a schematic configuration of the liquid crystal display panel 100 will be described with reference to FIGS. Here, FIG. 2 is a perspective view for explaining the structure of the liquid crystal display panel 100, and FIG. 3 is a partial cross-sectional view for explaining the structure of the liquid crystal display panel 100. As shown in these drawings, the liquid crystal display panel 100 includes an element substrate 101 such as glass or semiconductor on which pixel electrodes 118 or the like are formed, and a transparent counter substrate 102 such as glass on which common electrodes 108 or the like are formed. However, the sealing material 105 mixed with the spacers S is bonded so that the electrode forming surfaces face each other while maintaining a certain gap, and the liquid crystal 106 is sealed in the gap.
[0034]
A driving circuit group 120 such as a scanning line side driving circuit 130, a sampling circuit 140, and a data line side driving circuit 150A, which will be described later, is formed on the opposite surface of the element substrate 101 and outside the sealant 105. . In addition, external connection electrodes (not shown) are formed therein, and various signals from the timing generator 200 and the image signal processing circuit 300 are input thereto. Note that the common electrode 108 of the counter substrate 102 is electrically connected to the wiring extending from the external connection electrode of the element substrate 101 by a conductive material provided in at least one of the four corners of the bonding portion with the element substrate 101. Therefore, conduction is achieved.
[0035]
In addition, the counter substrate 102 is provided with color filters arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal display panel 100, for example, and secondly, for example, A black matrix such as resin black in which a metal material such as chromium or nickel, carbon, titanium, or the like is dispersed in a photoresist is provided, and thirdly, a backlight for irradiating the liquid crystal display panel 100 with light is provided. Particularly in the case of color light modulation, a black matrix is provided on the counter substrate 102 without forming a color filter. In addition, the opposing surfaces of the element substrate 101 and the counter substrate 102 are each provided with an alignment film or the like that is rubbed in a predetermined direction. 103 and 104 are provided. However, if a polymer-dispersed liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 108, the above-described alignment film, polarizing plate, and the like are not required. As a result, the light utilization efficiency is increased. This is advantageous in terms of reducing power consumption.
[0036]
Now, returning to FIG. 1 again, the electrical configuration of the liquid crystal display panel 100 will be described. In the element substrate 101 of the liquid crystal display panel 100, an image display area AA is formed. In the figure, a plurality (m) of scanning lines 112 are formed in parallel along the X direction in the drawing, and a plurality (6n) of scanning lines 112 are formed in parallel along the Y direction perpendicular thereto. A data line 114 is formed. At each intersection of the scanning line 112 and the data line 114, the gate electrode of the TFT 116 is connected to the scanning line 112, while the source electrode of the TFT 116 is connected to the data line 114 and the drain electrode of the TFT 116. Is connected to the pixel electrode 118. Each pixel includes a pixel electrode 118, a common electrode 108 formed on the counter substrate 102, and a liquid crystal 106 sandwiched between the two electrodes. As a result, each of the scanning line 112 and the data line 114 Corresponding to the intersection, they are arranged in a matrix. In addition to this, a storage capacitor (not shown) is provided for each pixel, and is electrically parallel to the liquid crystal layer sandwiched between the pixel electrode 118 and the common electrode 108.
[0037]
Next, the drive circuit group 120 includes a scanning line side drive circuit 130, a sampling circuit 140, and a data line side drive circuit 150A, and is formed on the element substrate 101 as described above. These circuits are formed of TFTs using a manufacturing process common to the pixel TFTs (for example, a high-temperature polysilicon process). This is advantageous in terms of integration and manufacturing costs. In this example, the data line side drive circuit 150A and the sampling circuit 140 are described as separate bodies, but it is needless to say that the data line side drive circuit 150A and the sampling circuit 140 may be regarded as a data line drive circuit that drives the data line 114 together.
[0038]
Now, the scanning line side drive circuit 130 has a shift register, and based on the Y clock signal YCK from the timing generator 200, its inverted Y clock signal YCKB, the Y transfer start pulse DY, etc., the scanning line signals Y1, Y2 ,..., Ym (selection signal) are sequentially output to each scanning line 112, and scanning line signals Y1, Y2,..., Ym are output at the timing at which the pulse DY is shifted according to the clock signal in the shift register. To do.
[0039]
On the other hand, the sampling circuit 140 groups six data lines 114 into one group, and samples and supplies the image signals VID1 to VID6 to the data lines 114 belonging to these groups according to the sampling signals SR1 to SRn. To do. In the sampling circuit 140, a switch 141 made of TFT is provided at one end of each data line 114, and a source electrode of each switch 141 is connected to a signal line to which any one of the image signals VID1 to VID6 is supplied. The drain electrode of each switch 141 is connected to one data line 114. Furthermore, the gate electrode of each switch 141 connected to the data line 114 belonging to each group is connected to one of the signal lines to which the sampling signals SR1 to SRn are supplied corresponding to the group. As described above, since the image signals VID1 to VID6 are supplied at the same time, they are simultaneously sampled by the sampling signal S1.
[0040]
The data line side drive circuit 150A sequentially outputs sampling signals SR1 to SRn (selection signals) based on the X clock signal XCK from the timing generator 200, the inverted X clock signal XCKB, the X transfer start pulse DX, and the like. To do.
[0041]
<1-4: Data Line Side Drive Circuit>
Next, the data line side driving circuit 150A will be described. FIG. 4 is a block diagram showing the overall configuration of the data line side driving circuit. As shown in FIG. 4, the data line side driving circuit 150 </ b> A includes an X shift register 151, a logical operation unit 152, and an inhibit signal selection unit 152.
[0042]
First, the X shift register 151 is configured by cascading shift register unit circuits Ua0 to Uan. Each shift register unit circuit Ua0 to Uan includes clocked inverters 501 and 502 and an inverter 503.
[0043]
Clocked inverters 501 and 502 invert and output each input signal when the control terminal voltage is at the H level, and place the output terminal in a high impedance state when the control terminal voltage is at the L level. Each control terminal is supplied with an X clock signal XCK and an inverted X clock signal XCKB that are active for a predetermined period.
[0044]
For example, in the shift register unit circuit Ua0, when the X clock signal XCK is at the H level, the clocked inverter 501 inverts and outputs the input signal. At this time, since the inverted X clock signal XCKB is at L level, the output terminal of the clocked inverter 502 is in a high impedance state. Therefore, in this case, the input signal is output via the clocked inverter 501 and the inverter 503. On the other hand, when the inverted X clock signal XCKB is at the H level, the clocked inverter 502 inverts and outputs the input signal. At this time, since the X clock signal XCK is at L level, the output terminal of the clocked inverter 501 is in a high impedance state. In this case, the clocked inverter 502 and the inverter 503 constitute a latch circuit.
[0045]
As a result, the shift register unit circuits Ua0 to Uan sequentially shift the X transfer start pulse DX in synchronization with the X clock signal XCK and the inverted X clock signal XCKB to generate shift pulses C0 to Cn. By this shift operation, a certain shift pulse Cj and the next shift pulse Cj + 1 have an active period (H level) that overlaps by a half period of the X clock signal XCK.
[0046]
Next, the logical operation unit 152 includes operation unit circuits Ub1 to Ubn. Each of the arithmetic unit circuits Ub1 to Ubn includes a NAND circuit 504 and a NOR circuit 505 that invert the logical product of the input signals and output signals of the shift register unit circuits Ua1 to Uan and output them as signals S1 to Sn. The NOR circuit 505 outputs sampling signals SR1 to SRn that become H level when X selection inhibit signals XINHB1 to XINNHBn, which will be described later, and signals S1 to Sn are both at L level. That is, during the period in which the X selection inhibit signals XINHB1 to XINNHBn (selection pulse signals) are at the H level by the NOR circuit 505, the sampling signals SR1 to SRn are at the L level even if the signals S1 to Sn are at the L level (active). (Inactive). In other words, the NOR circuit 505 functions as a logic circuit that limits the active period of the sampling signals SR1 to SRn (selection signals).
[0047]
Next, the inhibit signal selection unit 153 includes control unit circuits Uc1 to Ucn, and each control unit circuit Uc1 to Ucn includes a NAND circuit 506, an inverter 507, and transfer gates 508 and 509. Note that the transfer gate 508 is provided close to the signal supply line LX. Therefore, the wiring capacitance between the signal supply line LX and the transfer gate 508 is extremely small and can be ignored in practice.
[0048]
Each of the control unit circuits Uc1 to Ucn selects a predetermined pulse from the X inhibit signal XINHB (pulse signal) supplied via the signal supply line LX, and this is selected as the X selection inhibit signal XINHB1 to XINNHn. The signal is output to the circuit 505. Here, the X inhibit signal XINHB has a plurality of inhibit pulses (pulses) that become H level in a predetermined period centering on the timing at which the levels of the X clock signal XCK and the inverted X clock signal XCKB transition (see FIG. 5). .
[0049]
The transfer gate 508 is turned on only when the control signals N1, N2,. A high impedance state is entered when the level is L. Therefore, the control unit circuits Uc1 to Ucn are disconnected from the signal supply line LX when the control signals N1, N2,. Thereby, the capacity | capacitance accompanying the signal supply line LX can be reduced.
[0050]
On the other hand, the transfer gate 509 is turned on when the control signals N1, N2,..., Nn are at the L level, and outputs the low-order power supply voltage VSSX. The signal line voltage can be fixed at the L level. As a result, noise does not enter the wiring and the NOR circuit 505 does not malfunction.
[0051]
Here, paying attention to a certain control unit circuit Ucj, one input terminal of the NAND circuit 506 is supplied with the internal signal Pj of the connection point Aj corresponding to the control unit circuit Ucj, while the other input terminal is connected to the other input terminal. The internal signal Pj-1 at the previous connection point Aj-1 is supplied. That is, a certain control unit circuit Ucj has a period during which one of the internal signal Pj of the corresponding shift register unit circuit Uaj and the internal signal Pj-1 in the previous shift register unit circuit Uaj-1 is active (this example Then, only at the L level, the X inhibit signal XINNHB is selected to generate the X select inhibit signals XINHB1 to XINNHBn, which are supplied to the logic operation unit 152.
[0052]
The reason why the X selection inhibit signals XINHB1 to XINNHBn are generated in this way is as follows. When the X inhibit signal XINHB is always supplied to all NOR circuits 505 constituting each of the arithmetic unit circuits Ub1 to Ubn, the load becomes heavy due to their input capacitance and wiring capacitance from the signal supply line LX to the NOR circuit 505. However, each active period of the signals S1 to Sn can be limited by using two inhibit pulses generated at the start timing and the end timing. Therefore, a selection period of the X inhibit signal XINHB is provided for each of the signals S1 to Sn, and the X inhibit signal XINNHB is selected according to this.
[0053]
In this case, the selection period needs to include at least a period during which the corresponding signals S1 to Sn are active. Each of the signals S1 to Sn is active during a period in which both the input signal and the output signal of each shift register unit circuit Ua1 to Uan are active. Therefore, the selection period may be determined so as to become active when any one of the input signal and the output signal of each shift register unit circuit Ua1 to Uan becomes active so as to include the period.
[0054]
This selection period can be determined based on the input signal and output signal of each shift register unit circuit Ua1 to Uan, and these signals are given as output signals of the inverter 503 of each shift register unit circuit Ua1 to Uan. It is done. For this reason, it is influenced by the delay time of the inverter 503 and the characteristics of the transistors constituting it. Therefore, in the present embodiment, the control signal Nj indicating the selection period is generated based on the internal signal Pj and the internal signal Pj-1 in the previous stage, and the X inhibit signal XINHB is selected based on the control signal Nj. .
[0055]
<1-5: Operation of Data Line Side Drive Circuit>
Next, the operation of the data line side driving circuit 150A will be described with reference to FIG. FIG. 5 is a timing chart showing the operation of the data line side driving circuit 150A.
[0056]
First, when the X clock signal XCK becomes H level at time T1, the clocked inverter 501 of the 0th shift register unit circuit Ua0 becomes active, and the internal signal P0 at the connection point A0 changes from H level to L level. Fall down.
[0057]
Next, when the inverted X clock signal XCK becomes H level at time T2, the clocked inverter 501 becomes active in the first shift register unit circuit Ua1. At this time, the clocked inverter 501 in the previous stage becomes inactive, but the clocked inverter 502 becomes active and forms a latch circuit together with the inverter 503. Accordingly, the signal P0 maintains the L level at the time T1 even at the time T2, while the signal P1 transits from the H level to the L level.
[0058]
At time T3, since the clocked inverter 501 of the shift register unit circuit Ua0 becomes active again, the signal P0 changes from the L level to the H level. In the shift register unit circuit Ua1, the clocked inverter 501 becomes inactive, while the clocked inverter 502 becomes active and the signal P1 is maintained at the L level. Further, in the next-stage shift register unit circuit Ua2, the clocked inverter 501 becomes active, and the signal P2 changes from the H level to the L level.
[0059]
In this way, each shift register unit circuit Ua0 to Uan sequentially transfers the X transfer start pulse DX in accordance with the X clock signal XCK and the inverted X clock signal XCKB.
[0060]
Here, the NAND circuit 504 of the arithmetic unit circuit Ub1 inverts the logical product of the signals C0 and C1 to generate the signal S1, and the NAND circuit 504 in the next stage similarly outputs the signal S2 based on the signals C1 and C2. Generate. Therefore, the signal S1 is at the L level during the period from time T2 to time T3 as shown in the figure, and the signal S2 is at the L level during the period from time T3 to time T4.
[0061]
Next, in the inhibit signal selection unit 153, the X inhibit signal XINHB is supplied via the signal supply line LX. As shown in the figure, the X inhibit signal XINHB is at the H level in a predetermined period centered on the timing at which the levels of the X clock signal XCK and the inverted X clock signal XCKB transition (for example, times T1, T2,...). .
[0062]
Here, in the control unit circuit Uc1, the NAND circuit 506 generates a control signal N1 that becomes H level when either one of the signal P0 and the signal P1 is L level (active). Since the signal P0 is active during the period from the time T1 to the time T3, the signal P1 is active during the period from the time T2 to the time T4. Therefore, the control signal N1 is transmitted from the time T1 to the time T4 as shown in FIG. Active during the period. Since the transfer gate 508 of the control unit circuit Uc1 is turned on only during this period and the transfer gate 509 is turned on during the other periods, the X selection inhibit signal XINHB1 has four inhibit pulses Q1 as shown in FIG. It will have ~ Q4. When the X selection inhibit signal XINHB1 is supplied to the corresponding NOR circuit 505, the NOR circuit 505 generates a sampling signal SR1 that is active (H level) when both the X selection inhibit signal XINHB1 and the signal S1 are at L level. For this reason, the active period of the sampling signal SR1 is the active period of the signal S1 limited by the inhibit pulses Q2 and Q3 as shown in the figure.
[0063]
Similarly, in the control unit circuit Uc2, since the NAND circuit 506 generates the control signal N2 that is active during the period from the time T2 to the time T5 based on the signal P1 and the signal P2, the X selection inhibit signal is generated. XINHB2 has four inhibit pulses Q2 ', Q3, Q4' and Q5 as shown in the figure. As a result, the active period of the sampling signal SR2 is the one in which the active period of the signal S2 is limited by the inhibit pulses Q3 and Q4 ′ as shown in the figure.
[0064]
Therefore, the sampling signals SR1 and SR2 are both deactivated by the inhibit pulse Q3, so that the active periods do not overlap. The same applies to other sampling signals.
[0065]
Thereby, the sampling signals SR1 to SRn are always exclusively active. Therefore, the same image signals VID1 to VID6 are not simultaneously supplied to adjacent blocks, and the image quality can be improved.
[0066]
Further, the transfer gate 508 is turned on only when the control signals N1, N2,... Become H level (active), and the phase of each control signal N1, N2,. They are shifted by a period, and they become H level in the 3/2 period of the X clock signal XCK. For this reason, if the X shift register 151 is operating normally, the number of control signals that simultaneously become H level is “3” at the maximum. Therefore, if the total value of the wiring capacitance value from the transfer gate 508 to the NOR circuit 505 and the input capacitance value of the NOR circuit 505 is Ca, the value of the parasitic capacitance added to the signal supply line LX is 3Ca at the maximum. . On the other hand, if the inhibit signal selection unit 153 is not provided, the parasitic capacitance value is n · Ca. Therefore, according to this example, the capacitive load when driving the X inhibit signal XINNHB can be reduced, and the power consumption of the circuit driving the signal can be greatly reduced.
[0067]
By the way, the signal supply line LX constitutes a distributed constant type low-pass filter by its resistance component and parasitic capacitance component, but its cutoff frequency can be increased by reducing the parasitic capacitance value. For this reason, even an inhibit pulse having a narrow pulse width and containing a high frequency component can be sufficiently transmitted.
[0068]
<1-6: Other Configuration Example of Data Line Side Drive Circuit>
The data line side drive circuit 150A described above corresponds to the positive logic in which the X transfer start pulse DX becomes active at the H level. The data line side drive circuit 150A ′ of this modification corresponds to negative logic in which the X transfer start pulse DX ′ becomes active at the L level.
[0069]
FIG. 6 is a circuit diagram of the data line side driving circuit 150A ′, and FIG. 7 is a timing chart thereof. The data line side drive circuit 150A ′ uses a NOR circuit 504 ′ instead of the NAND circuit 504 in the logic operation unit 152, a point that uses the NAND circuit 505 ′ instead of the NOR circuit 505, and an inhibit signal selection unit 153. Except that a NOR circuit 506 ′ is used instead of the NAND circuit 506, it is the same as the data line side driving circuit 150A shown in FIG.
[0070]
As shown in FIG. 7, since the X transfer start pulse DX ′ becomes active at the L level, the signals P0, P1,... Become active at the H level. In addition, the control signals N1, N2,... Become active at the L level.
[0071]
Therefore, also in this example, as in the case of the positive logic, a certain control unit circuit Ucj has one of the internal signal Pj at the connection point Aj and the internal signal Pj-1 at the previous connection point Aj-1. The X inhibit signal XINHB is supplied to the logic operation unit 152 only during a period when it becomes active (H level in this example). As a result, the capacitive load when driving the X inhibit signal XINHB can be reduced, the power consumption of the circuit driving the signal can be greatly reduced, and the pulse width of the inhibit pulse can be reduced. .
[0072]
In the data line side driving circuits 150A and 150A ′ described above, as shown in FIG. 4 or FIG. 6, the X clock signal XCK and the inverted X are between the X shift register 151 and the inhibit signal selection units 153 and 153 ′. Although the clock signal supply lines for supplying the clock signal XCKB are respectively arranged, as shown in FIG. 22, the clock signal supply lines La and Lb are respectively arranged on the input side of the inhibit signal selection units 153 and 153 ′. Good.
[0073]
In short, it is desirable to arrange the clock signal supply lines La and Lb and the signal supply line Lb for supplying the inhibit signal XINHB in the direction opposite to the direction in which the sampling signals SR1 to SRn are output from the X shift register 151. As a result, the portion where the wirings intersect can be significantly reduced, and the parasitic capacitance associated with the intersection can be reduced. As a result, power consumption can be reduced and operation speed can be increased.
[0074]
<1-7: Scanning line driving circuit>
Next, the scanning line side driving circuit 130 will be described. FIG. 8 is a block diagram showing a configuration of the scanning line side driving circuit 130. As shown in this figure, the basic configuration of the scanning line side drive circuit 130 is similar to that of the data line side drive circuit 150A, and includes a Y shift register 131, a logical operation unit 132, and an inhibit signal selection unit 133.
[0075]
The Y shift register 131 is provided with a point that the Y clock signal YCK and the inverted Y clock signal YCKB are supplied instead of the X clock signal XCK and the inverted X clock signal XCKB, and that m + 1 shift register unit circuits Ua0 to Uam are provided. This is the same as the X shift register 150A described above. The logical operation unit 132 includes m operation unit circuits Ub1 to Ubm each including a NAND circuit and a NOR circuit. In addition, the inhibit signal selector 133 is the same as the inhibit signal selector 153 described above except that it includes m control unit circuits Uc1 to Ucm that select the Y inhibit signal YINHB.
[0076]
Therefore, the scanning line side drive circuit 130 can reduce the capacitive load when driving the Y inhibit signal YINHB, similarly to the X shift register 150A described above, and greatly reduces the power consumption of the circuit driving the signal. At the same time, the pulse width of the inhibit pulse can be reduced.
[0077]
Needless to say, the scanning line side drive circuit 130 may be configured by the negative logic shown in FIG. Further, similarly to the other configuration example of the data line side driving circuit shown in FIG. 22, supply lines for the Y clock signal YCK and the inverted Y clock signal YCKB may be arranged on the input side of the inhibit signal selection unit 133, respectively. Of course it is good.
[0078]
<1-8: Overall operation of liquid crystal display panel>
Next, the operation of the above-described liquid crystal display panel will be described. First, in the scanning line side drive circuit 130, the Y transfer start pulse DY is supplied at the beginning of the vertical scanning period. The Y transfer start pulse DY is sequentially shifted by the Y clock signal YCK and its inverted Y clock signal YCKB in the scanning line side drive circuit 130 and is output to each scanning line 112. The scanning line signals Y1 to Ym are inactive for a predetermined period centered on the timing at which the levels of the Y clock signal YCK and its inverted Y clock signal YCKB transition by the Y inhibit signal YINHB. There is no overlap of active periods. As a result, the plurality of scanning lines 112 are exclusively selected one by one.
[0079]
On the other hand, when the X transfer start pulse DX is supplied in the data line side drive circuit 150, as described above, the X transfer start pulse DX is sent to the X clock signal XCK and its inverted X in the data line side drive circuit 150A. The signals are sequentially shifted every half cycle of the clock signal XCKB and output as sampling signals SR1 to SRn. Since the X inhibit signal XINHB becomes active and both sampling signals become inactive at the boundary timing when the active period shifts from one sampling signal to the next sampling signal, each sampling signal SR1 to SRn is exclusively active. It becomes.
[0080]
Here, when the sampling signal SR1 is output, the image signals VID1 to VID6 are respectively sampled on the six data lines 114 belonging to this group, and these image signals VID1 to VID6 are selected at the present time. Are written to the six pixels intersecting with the TFT 116, respectively. Thereafter, when the sampling signal SR2 is output, the image signals VID1 to VID6 are sampled on the next six data lines 114, respectively, and these image signals VID1 to VID6 are selected at that time. Are written to the six pixels intersecting with the TFT 116, respectively.
[0081]
Similarly, when the sampling signals SR3, SR4,..., SRn are sequentially output, the image signals VID1 to VID6 are respectively output to the six data lines 114 corresponding to the sampling signals, and these image signals VID1 to VID1 are output. VID6 is written in each of the six pixels that intersect the scan line selected at that time. Thereafter, the next scanning line is selected, sampling signals SR1 to SRn are sequentially output again, and similar writing is repeatedly executed.
[0082]
In such a driving method, the number of stages of the data line side driving circuit 150A for driving and controlling the switch 141 in the sampling circuit 140 is reduced to 1/6 as compared with a method of driving each data line 114 in a dot sequential manner. Further, since the frequency of the Y clock signal YCK to be supplied to the data line side driving circuit 150A and the inverted Y clock signal YCKB is also 1/6 as compared with the method of driving each data line 114 in a dot sequential manner, the number of stages is reduced. In addition to the reduction in power consumption, lower power consumption is also achieved.
[0083]
Furthermore, since the parasitic capacitance value associated with the signal supply line LX that supplies the X inhibit signal XINHB can be reduced, the pulse width of the inhibit pulse can be narrowed. Thereby, the sampling period in the sampling circuit 140 can be made sufficiently long, so that a high-definition image can be displayed with high quality.
[0084]
<2. Second Embodiment>
In the first embodiment described above, based on the corresponding shift register unit circuit and each internal signal in the previous stage, the transfer gate 508 connected to the signal supply line is turned on, and the inhibit signal is taken in for a predetermined period to select the selected inhibit signal. As a result, the capacitance component associated with the signal supply line can be reduced.
[0085]
However, whether the internal signal of each shift register unit circuit becomes H level or L level when power is turned on is a problem of probability. Accordingly, when the power is turned on, the transfer gate 508 may be turned on in all control unit circuits. For this reason, as a drive circuit for driving the inhibit signal, it is necessary to use a circuit that can supply a large current at a high response speed in consideration of a heavy load when the power is turned on.
[0086]
The second embodiment has been made in view of this point, and aims to reduce power consumption when power is turned on.
[0087]
<2-1: Overall configuration of liquid crystal device>
The overall configuration of the liquid crystal device according to the second embodiment is the same as the liquid crystal device of the first embodiment shown in FIG. 1 except for the detailed configuration of the data line side drive circuit 150A and the scanning line side drive circuit 130. Further, the timing generator 200 of the second embodiment generates a reset signal SINT that becomes active at the start of each field.
[0088]
In addition, the scanning line driving circuit of the second embodiment is configured in the same manner as the data line driving circuit described below except for the number of stages, and therefore, detailed description thereof is omitted here.
[0089]
<2-2: Configuration of data line side driving circuit>
FIG. 9 is a circuit diagram showing a detailed configuration of the data line side driving circuit 150B according to the second embodiment. As shown in the figure, the data line side drive circuit 150B includes the logical operation unit 152 and the inhibit signal selection unit 153 described in the first embodiment, and includes an X shift register 151a instead of the X shift register 151. The X shift register 151a is different from the X shift register 151 shown in FIG. 4 in that a NOR circuit 503a is used instead of the inverter 503 in each shift register unit circuit Ua0 to Uan.
[0090]
In each of the shift register unit circuits Ua0 to Uan, the NOR circuit 503a calculates the logical sum of the reset signal SINT and the output signal of the clocked inverter 502, inverts it, and outputs it, so that the reset signal SINT is at the L level. It functions as an inverter that inverts the output signal of the clocked inverter 502. Therefore, the clocked inverter 502 and the NOR circuit 503a function as a latch circuit when the reset signal SINT is at the L level (inactive period).
[0091]
On the other hand, when the reset signal SINT is in the H level (active period), the output signal of the NOR circuit 503a is forcibly reset to the L level. The reset signal SINT is a signal of one field period, and becomes active during a very short period (for example, a part of the vertical blanking period). Therefore, the output signals C0 to Cn of the shift register unit circuits Ua0 to Uan are always reset at the start time of each field and become L level. When either the X clock signal XCK or the inverted X clock signal XCKB becomes active, the internal signals P0 to Pn at the connection points A0 to An become H level. Then, the control signals N1 to Nn output from the NAND circuits 506 are all at the L level. As a result, all the transfer gates 508 are turned off.
[0092]
That is, according to the data line side drive circuit 150B, when the reset signal SINT becomes H level, the output signals of the shift register unit circuits Ua0 to Uan are forcibly reset, so that the signal supply line LX is supplied. It is possible to minimize the value of the accompanying parasitic capacitance at the time of reset.
[0093]
<2-3: Operation of data line side driving circuit>
Next, the operation of the data line side drive circuit 150B will be described with reference to FIGS. FIG. 10 is a timing chart showing the operation of the data line side driving circuit 150B in the vertical scanning period. FIG. 11 is a timing chart showing the operation of the data line side driving circuit 150B in the first horizontal scanning period after the power is turned on.
[0094]
First, as shown in FIG. 10, at the start of one field period, the reset signal SINT becomes active (H level in this example), and thereafter, the Y transfer start pulse DY becomes active. Then, after the Y transfer start pulse DY rises from the L level to the H level, the Y clock signal YCK is generated.
[0095]
Further, a half cycle of the Y clock signal YCK coincides with one horizontal scanning period, and the X transfer start pulse DX, the X clock signal XCK, and the inverted X clock signal XCKB shown in FIG. It is supplied to the data line side driving circuit 150B.
[0096]
Therefore, if power is supplied to the liquid crystal device at time T0 shown in FIG. 10, first, the reset signal SINT is generated, and then the X clock signal XCK and the inverted X clock signal XCKB shown in FIG. It is supplied to the register 151a. In other words, the reset signal SINT is generated prior to the supply of the X clock signal XCK and the inverted X clock signal XCKB to the X shift register 151a, thereby resetting the output signal of each shift register unit circuit to the L level. Subsequently, the internal signals P0 to Pn at the connection points A0 to An are reset to the H level.
[0097]
As described above, each control unit circuit generates the control signals N1 to Nn that are at the L level when the internal signals P0 to Pn that are the input signals of the NAND circuit 506 are at the H level. Therefore, at time T1, the transfer gates 508 of the control unit circuits Uc1 to Ucn are all in a high impedance state.
[0098]
Here, the capacitance value from the input terminal of the NOR circuit 505 to the transfer gate 508 of each of the arithmetic unit circuits Ub1 to Ubn is represented by Ca, and the other wiring capacitances are ignored. In this case, the input capacitance C viewed from the input terminal of the signal supply line LX at the time T1 to the inside of the data line side drive circuit 150B becomes “0” as shown in the figure.
[0099]
Next, when the internal signal P0 of the 0th shift register unit circuit Ua0 changes from H level to L level and becomes active at time T2, the signal N1 changes from L level to H level, and the control unit circuit The transfer gate 508 of Uc1 is turned on. However, at time T2, the internal signals P1, P2,..., Pn in the other shift register unit circuits Ua1 to Uan are still at the H level, so the first to nth control unit circuits Uc1 to Ucn. The transfer gate 508 is in a high impedance state. Therefore, the input capacitance C at time T2 is “Ca” as shown in the figure. This state is maintained until time T3.
[0100]
Next, when time T3 is reached, the internal signal P1 changes to L level, and the signal N2 becomes H level in synchronization therewith. Then, the transfer gate 508 of the control unit circuit Uc2 is turned on. At this time, since the control signal N1 is at the H level, the transfer gate 508 of the control unit circuit Uc1 is also in the ON state. Accordingly, the input capacitance C at time T3 is “2Ca” as shown in the figure.
[0101]
Next, at time T4, since the internal signal P2 becomes L level and the signal N3 becomes H level, the transfer gate 508 of the control unit circuit Uc3 is turned on in addition to the control unit circuits Uc1 and Uc2. Therefore, the input capacitance C at time T4 is “3Ca” as shown in the figure.
[0102]
Next, when time T5 is reached, the internal signal P1 transitions to H level (inactive), so the control signal N1 becomes L level, and the transfer gate 508 of the control unit circuit Uc1 is turned off. At this time, the X transfer start pulse DX is transferred to the third shift register unit circuit Ua3, and the internal signal P3 transitions to the L level. Then, the control signal N4 becomes H level and the transfer gate 508 of the control unit circuit Uc4 is turned on. Therefore, at time T5, the transfer gate 508 is turned on in the second to fourth control unit circuits Uc2 to Uc4. As a result, the input capacitance C becomes “3Ca” as shown in the figure. Thereafter, the control unit circuit in which the transfer gate 508 is turned on is shifted every half cycle of the X clock signal XCK.
[0103]
As described above, according to the data line side drive circuit 150B described above, the control unit circuits Uc1 to Ucn have the inhibit signal XINHB in a predetermined period including a period in which the signals S1 to Sn are active in the respective operation unit circuits Ub1 to Ubn. Is selected and supplied to the respective operation unit circuits Ub1 to Ubn, so that the power consumption can be reduced.
[0104]
Since the output signals C0 to Cn and the internal signals P0 to Pn of the shift register unit circuits Ua0 to Uan are reset for each field by the reset signal SINT, the control unit circuits Uc1 to Ucn are reset. The transfer gate 508 that constitutes is always turned off at the start of the field. Here, considering a drive circuit for supplying the inhibit signal XINHB to the data line side drive circuit 150B, the maximum output current of the drive circuit is determined by the maximum number of transfer gates 508 that are turned on. In this example, since the internal signals P0 to Pn of the shift register unit circuits Ua0 to Uan are reset for each field by the reset signal SINT, the logic level of the internal signals P0 to Pn is H when the power is turned on. Even if there is a level, all the internal signals P0 to Pn can be forcibly reset at the time when the first field after power-on starts.
[0105]
Therefore, it is sufficient for the drive capability of the drive circuit to drive up to three NOR circuits 505. In particular, in a liquid crystal device that displays a high-definition image, the number of data lines 6a increases, and accordingly, the number of control unit circuits also increases. For example, in the SVGA type liquid crystal device, since there are 1024 data lines 6a, if no reset is performed, a maximum of 171 NOR circuits 505 can be driven even if the number of phase expansion '6' is considered. Although it is necessary to use a drive circuit, in the above-described example, it is sufficient to drive the three NOR circuits 505, so that the circuit configuration of the drive circuit can be greatly reduced and the current consumption can be reduced. Become.
[0106]
<2-4: Other Configuration Examples of Data Line Side Drive Circuit>
The data line side drive circuit 150B described above is of positive logic in which the reset signal SINT, the X transfer start pulse DX, etc. are active at the H level, but it is of course possible to configure this with negative logic. is there. The data line side drive circuit 150B ′ corresponding to the negative logic can be configured as shown in FIG. Similar to the data line side drive circuit 150A ′ shown in FIG. 6, the data line side drive circuit 150B ′ includes a logical operation unit 152 ′ and an inhibit selection unit 153 ′, but instead of the X shift register 151 ′, the X shift register The difference is that 151b is used. The X shift register 151B ′ is the same as the X shift register 151 shown in FIG. 6 except that a NAND circuit 503b is used instead of the inverter 503. 7 and 8 are timing charts showing the operation of the data line side driving circuit 150B ′.
[0107]
Also in the data line side drive circuits 150B and 150B ′, the X clock signal XCK, the inverted X clock signal XCKB, and the reset signal SINT are supplied in the same manner as described with reference to FIG. 22 in the first embodiment. Of course, the wiring may be provided on the input side of the inhibit signal selection unit 153 in the same manner as the signal supply line LX.
[0108]
As described above, also in the second embodiment, the supply line for supplying the input signal can be arranged on the opposite side to the output direction of the X shift registers 151a and 151b to reduce the crossing between the wirings. As a result, the parasitic capacitance associated with the intersection can be reduced, and the power consumption can be reduced and the operation speed can be increased.
[0109]
<2-5: Configuration example of reset signal generation circuit>
In this example, the reset signal SINT that becomes active at the start of each field is generated by the timing generation circuit 300 and is supplied to the data line driving circuit 100 and the scanning line driving circuit 200. The reset signal SINT may be generated at a rate of once. Further, it is possible to detect when the power is turned on, generate the reset signal SINT based on the detection result, and not generate the reset signal SINT at the start time of each field. Further, the reset signal SINT may be generated when the power is turned on, and the reset signal SINT may be generated at the start of each field. The point is that the reset signal SINT is in a period from the power-on until the X clock signal XCK and the inverted X clock signal XCKB are generated, or in the period from the power-on to the generation of the Y clock signal YCK and the inverted Y clock signal YCKB. Anything can be used as long as it becomes active.
[0110]
Now, an example of a reset signal generation circuit that detects when the power is turned on and generates the reset signal SINT based on the detection result will be described. This reset signal generation circuit is configured inside the timing generator 200. FIG. 15 is a circuit diagram of the reset signal generation circuit, and FIG. 16 is a timing chart thereof.
[0111]
As shown in FIG. 15, a resistor 311 and a capacitor 312 are connected in series between the high potential power supply VDD and the low potential power supply VSS. The connection point of these elements is connected to the input terminal of the inverter 313, and the output signal is supplied to one input terminal of the exclusive OR circuit 316 via the inverters 314 and 315, The output signal of the inverter 313 is supplied to the other input terminal. The output signal of the exclusive OR circuit 316 is extracted as the reset signal SINT. Note that the threshold voltage of the inverter 313 is Vth.
[0112]
In the above configuration, when the power supply of the liquid crystal device is turned on and the voltage of the high potential power supply VDD rises from the L level to the H level at time T10, charging of the capacitor 312 is started via the resistor 311. Thereafter, when the charging voltage of the capacitor 312 exceeds the threshold voltage Vth at time T11, the output signal of the inverter 313 falls from the H level to the L level. Since this output signal is delayed by the inverters 314 and 315, the output signal of the inverter 315 is as shown in the figure if the delay time and ΔT are used. As described above, the exclusive OR circuit 316 calculates the exclusive OR of the output signal of the inverter 315 and the output signal of the inverter 313, so that the reset signal SINT is at the L level at time T11 as shown in the figure. Rises to H level, maintains H level for the period ΔT, and then falls to L level. In the timing generation circuit 300, the falling edge at which the reset signal SINT falls from the H level to the L level is set as the reference time, and after a predetermined time has elapsed from the reference time, the X clock signal XCK or the inverted X clock A signal XCKB, a Y clock signal YCK, and an inverted Y clock signal YCKB (not shown) are generated.
[0113]
<3. Application example>
<3-1: Enable signal>
In each of the embodiments described above, the inhibit signals XINHB and YINHB including a plurality of inhibit pulses are selected, and the sampling signals SR1 to SRn and the scanning line signals Y1 to Ym are generated using the selected selected inhibit signal. did. Here, the active period of the inhibit signals XINHB and YINHB specifies the inactive period of the signal whose pulse width is to be limited. Conversely, if attention is paid to the inactive period of the inhibit signals XINHB and YINHB, The signal of interest is allowed to be active during the period. Therefore, it goes without saying that the above-described embodiments can be applied to an enable signal that allows a target signal to become active instead of the inhibit signals XINHB and YINHB.
[0114]
<3-2: Configuration of drive circuit>
In each of the embodiments described above, the data line side drive circuits 150A, 150A ′, 150B, and 150B ′ generate the control signals N1 to Nn based on the internal signals P0 to Pn, but the present invention is limited to this. Instead, the control signals N1 to Nn may be generated based on the input signals and output signals of the shift register unit circuits Ua1 to Uan.
[0115]
More specifically, in the data line side drive circuits 150A and 150B shown in FIGS. 4 and 9, an OR circuit is used instead of the NAND circuit 506 of the jth control unit circuit Ucj, and the input of the OR circuit is used. A signal Cj and a signal Cj-1 may be supplied to the terminals.
[0116]
In the data line side drive circuits 150A ′ and 150B ′ shown in FIGS. 6 and 12, an AND circuit is used instead of the NOR circuit 506 ′ of the jth control unit circuit Ucj, and the signal Cj is applied to the input terminal of the AND circuit. And the signal Cj-1 may be supplied.
[0117]
<3-3: Configuration of element substrate>
In each of the above-described embodiments, the element substrate 151 of the liquid crystal panel is formed of a transparent insulating substrate such as glass, and a silicon thin film is formed on the substrate, and a source, a drain, and a channel are formed on the thin film. Although it has been described that the TFTs constitute the pixel switching element (TFT 50), the data line driving circuit 100, and the scanning line driving circuit 200, the present invention is not limited to this.
[0118]
For example, the element substrate 151 is composed of a semiconductor substrate, and a pixel switching element or various circuit elements are composed of insulated gate field effect transistors in which a source, a drain, and a channel are formed on the surface of the semiconductor substrate. Also good. When the element substrate 151 is formed of a semiconductor substrate in this manner, it cannot be used as a transmissive display panel. Therefore, the pixel electrode 9a is formed of aluminum or the like and used as a reflective type. Alternatively, the element substrate 151 may be a transparent substrate and the pixel electrode 9a may be a reflection type.
[0119]
Instead of forming part or all of the peripheral circuits such as the data line side driving circuit 150 and the scanning line side driving circuit 130 on the element substrate 151, for example, they are mounted on a film using a TAB (Tape Automated Bonding) technique. The drive IC chip thus obtained may be electrically and mechanically connected through an anisotropic conductive film provided at a predetermined position of the element substrate 151, or the drive IC chip itself may be connected to a COG (Chip On Grass) technology may be used to electrically and mechanically connect to a predetermined position of the element substrate 151 via an anisotropic conductive film.
[0120]
<3-4: Electronic equipment>
Next, the case where the above-described liquid crystal device is applied to various electronic devices will be described.
[0121]
<3-4-1: Projector>
First, a projector using this liquid crystal device as a light valve will be described. FIG. 17 is a plan view showing a configuration example of the projector.
[0122]
As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.
[0123]
The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal panel described above, and are driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.
[0124]
Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.
[0125]
Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.
[0126]
<3-4-2: Mobile computer>
Next, an example in which the liquid crystal panel is applied to a mobile personal computer will be described. FIG. 18 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal panel 1005 described above.
[0127]
<3-4-3: Mobile phone>
Further, an example in which this liquid crystal panel is applied to a mobile phone will be described. FIG. 19 is a perspective view showing the configuration of this mobile phone. In the figure, a cellular phone 1300 includes a reflective liquid crystal panel 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal panel 100, a front light is provided on the front surface thereof as necessary.
[0128]
In addition to the electronic devices described with reference to FIGS. 17 to 19, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Stations, videophones, POS terminals, devices with touch panels, etc. Needless to say, the present invention can be applied to these various electronic devices.
[0129]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce a load on a circuit that drives an inhibit signal, reduce power consumption, and provide a drive circuit that can operate even with an inhibit signal having a narrow pulse width.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a liquid crystal device according to a first embodiment of the present invention.
FIG. 2 is a perspective view for explaining the structure of a liquid crystal display panel.
FIG. 3 is a partial cross-sectional view for explaining the structure of a liquid crystal display panel.
FIG. 4 is a circuit diagram showing a detailed configuration of a data line side driving circuit 150A of the same device.
FIG. 5 is a timing chart of the data line side driving circuit 150A.
FIG. 6 is a circuit diagram of a data line side drive circuit 150A ′ corresponding to negative logic.
FIG. 7 is a timing chart of the data line side drive circuit 150A ′.
8 is a block diagram illustrating a configuration of a scanning line driving circuit 130. FIG.
FIG. 9 is a circuit diagram showing a detailed configuration of a data line side driving circuit 150B used in the liquid crystal device of the second embodiment.
FIG. 10 is a timing chart showing an operation of the data line side driving circuit 150B in a vertical scanning period.
FIG. 11 is a timing chart showing the operation of the data line side driving circuit 150B in the first horizontal scanning period after power-on.
FIG. 12 is a circuit diagram of a data line side drive circuit 150B ′ corresponding to negative logic.
FIG. 13 is a timing chart showing the operation of the data line side drive circuit 150B ′ in the vertical scanning period.
FIG. 14 is a timing chart showing the operation of the data line side drive circuit 150B ′ in the first horizontal scanning period after power-on.
FIG. 15 is a circuit diagram showing an example of a reset signal generation circuit 310 used in the embodiment.
16 is a timing chart showing an operation of the reset signal generation circuit shown in FIG.
FIG. 17 is a cross-sectional view of a video projector as an example of an electronic apparatus to which the liquid crystal device is applied.
FIG. 18 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal device is applied.
FIG. 19 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal device is applied.
FIG. 20 is a circuit diagram showing a configuration of a conventional shift register.
FIG. 21 is a timing chart showing an operation of the shift register shown in FIG. 20;
FIG. 22 is a block diagram showing another configuration example of the data line side drive circuits 150A and 150A ′ according to the first embodiment.
[Explanation of symbols]
112 ... Scanning line
114 …… Data line
118 …… Pixel electrode
116 …… TFT (switching element)
SR1 to SRn: Sampling signal (selection signal)
VID …… Input image signal
150A, 150B: Data line side drive circuit
152 …… Logic operation section
151, 151 '... X shift register (shift register section)
152, 152 '...... Inhibit signal selection unit (selection unit)
130... Scanning line driving circuit
Ua0 to Uan: Shift register unit circuit (shift unit circuit)
Uc1 ~ Ucn + 2 …… Control unit circuit
INHB …… Inhibit signal
INHB1 to INHBn …… Selected inhibit signal

Claims (16)

A shift register unit used in an electro-optical panel having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines An electro-optical panel drive circuit including a selection unit and a logical operation unit,
The shift register unit is formed by cascading a plurality of shift unit circuits that sequentially output start signals by sequentially shifting start pulses based on a clock signal,
The selection unit includes a plurality of control unit circuits provided corresponding to the shift unit circuits, respectively, and at least one of an input signal and an output signal of the corresponding shift unit circuit is active. The active period is specified, and a pulse signal including a plurality of pulses is selected to generate a selection pulse signal by selecting a pulse generated in the active period.
The logic operation unit includes a plurality of operation unit circuits provided corresponding to each shift unit circuit, and a certain operation unit circuit has a period during which both the input signal and the output signal of the corresponding shift unit circuit are active. A drive circuit for an electro-optical panel, characterized by generating a selection signal that specifies and selects the scanning line or the data line based on the period and the selection pulse signal. The selection unit, the shift register unit, and the logic operation unit are arranged in this order, and the signal supply line that supplies the clock signal and the pulse signal is arranged on the side opposite to the side on which the shift register unit outputs the output signal. The drive circuit for an electro-optical panel according to claim 1. The clock signal includes a first clock signal and a second clock signal obtained by inverting the first clock signal.
Each shift unit circuit
While the previous shift signal is supplied to the input terminal and the output terminal is connected to the connection point, it operates only when the supplied control signal is active, while the output terminal is high impedance when the control signal is inactive A first inverter to be put into a state;
An output terminal connected to the connection point, and a second inverter that operates only when a supplied control signal is active, and sets the output terminal to a high impedance state when the control signal is inactive;
A third inverter having an input terminal connected to the connection point and an output terminal connected to the input terminal of the second inverter;
The odd-numbered shift unit circuit is supplied with the first clock signal as the control signal for the first inverter, while the second clock signal is supplied as the control signal for the second inverter, 2. The unit circuit according to claim 1, wherein the second clock signal is supplied to the unit circuit as a control signal for the first inverter, while the first clock signal is supplied as a control signal for the second inverter. Electro-optical panel drive circuit. The control unit circuit has a corresponding shift unit circuit based on the first internal signal extracted from the connection point in the corresponding shift unit circuit and the second internal signal extracted from the connection point in the previous shift unit circuit. 4. The drive circuit for an electro-optical panel according to claim 3, wherein an active period in which at least one of the input signal and the output signal is active is specified. 2. The electric unit according to claim 1, wherein the control unit circuit specifies an active period in which at least one of these signals is active based on an input signal and an output signal of the corresponding shift unit circuit. Optical panel drive circuit. The control unit circuit is connected to a logic circuit that specifies an active period in which at least one of an input signal and an output signal of the corresponding shift unit circuit is active, and a signal supply line that supplies the inhibit signal, and the logic circuit 2. The electro-optical panel drive according to claim 1, further comprising: a switch circuit that is turned on only when the output signal is active and takes in the pulse signal to generate the selection pulse signal. circuit. 2. The electro-optical panel driving circuit according to claim 1, wherein the shift unit circuit resets the logic level of the shift signal to an inactive level when a reset signal supplied from the outside becomes active. The clock signal includes a first clock signal and a second clock signal obtained by inverting the first clock signal.
Each shift unit circuit
While the previous shift signal is supplied to the input terminal and the output terminal is connected to the connection point, it operates only when the supplied control signal is active, while the output terminal is high impedance when the control signal is inactive A first inverter to be put into a state;
An output terminal connected to the connection point, and a second inverter that operates only when a supplied control signal is active, and sets the output terminal to a high impedance state when the control signal is inactive;
One input terminal is connected to the connection point, the reset signal is supplied to the other input terminal, and when the reset signal is inactive, the signal supplied to one input terminal is inverted and output, and the reset A reset logic circuit that resets the shift signal of the shift unit circuit to an inactive level when the signal is active;
A third inverter having an output terminal connected to the input terminal of the second inverter;
The odd-numbered shift unit circuit is supplied with the first clock signal as the control signal for the first inverter, while the second clock signal is supplied as the control signal for the second inverter, 8. The unit circuit according to claim 7, wherein the second clock signal is supplied to the unit circuit as a control signal for the first inverter, while the first clock signal is supplied as a control signal for the second inverter. Electro-optical panel drive circuit. A NOR circuit is used as the reset logic circuit when the start pulse is active at an H level, and a NAND circuit is used as the reset logic circuit when the start pulse is active at an L level. Item 9. The drive circuit for the electro-optical panel according to Item 8. A drive circuit according to any one of claims 1 to 9,
A data line side driving circuit characterized in that an input image signal is sampled and supplied to each data line based on each selection signal output from the driving circuit. A scanning line side driving circuit comprising the driving circuit according to claim 1 and driving each scanning line based on each selection signal output from the driving circuit. 8. The drive circuit control method according to claim 7, wherein the reset signal is activated for each field or for each of a plurality of fields. 4. The method of controlling a drive circuit according to claim 3, wherein the reset signal is at least active during a part of a period from when a power supply voltage is supplied to the drive circuit until the clock signal is supplied. A method for controlling a drive circuit. A pixel region having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines;
A data line side driving circuit according to claim 10,
An electro-optical panel, comprising: a scanning line side driving circuit for driving the scanning line. A pixel region having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines;
A data line side driving circuit for driving the data line;
An electro-optical panel comprising the scanning line side driving circuit according to claim 11. An electronic apparatus comprising the electro-optical panel according to claim 14.

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