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JP3713206B2 - Automatic gain control circuit - Google Patents

Automatic gain control circuit Download PDF

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Publication number
JP3713206B2
JP3713206B2 JP2001014010A JP2001014010A JP3713206B2 JP 3713206 B2 JP3713206 B2 JP 3713206B2 JP 2001014010 A JP2001014010 A JP 2001014010A JP 2001014010 A JP2001014010 A JP 2001014010A JP 3713206 B2 JP3713206 B2 JP 3713206B2
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Japan
Prior art keywords
gain control
automatic gain
voltage
control voltage
automatic
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Expired - Fee Related
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JP2001014010A
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Japanese (ja)
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JP2002217806A (en
Inventor
祐之 清水
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Kenwood KK
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Kenwood KK
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Description

【0001】
【発明の属する技術分野】
本発明はデジタル地上波放送受信機のフロントエンドなどに使用される自動利得制御回路に関する。
【0002】
【従来の技術】
デジタル地上波放送受信機のフロントエンドなどに使用される従来の自動利得制御回路を含むフロントエンドは、図4に示す如く構成されている。例えば位置を異にした4本のアンテナによって受信した同一チャンネルの信号をそれぞれ高周波選択回路を介して、可変利得増幅器1、4、7、10に各別に供給して増幅し、可変利得増幅器1、4、7、10の増幅出力を可変利得増幅器2、5、8、11に各別に供給して増幅し、可変利得増幅器2、5、8、11の増幅出力をトラッキングフィルタ3、6、9、12に各別に供給して主にイメージ周波数除去を目的として帯域制限を行い、トラッキングフィルタ3、6、9、12によって帯域制限された出力を合成器13に供給して合成し、合成器13の出力をミキサ14と局部発振器15とからなる周波数変換器によって第1中間周波数に周波数変換し、周波数変換された第1中間周波信号を検波器17に供給して検波し、検波出力電圧を第1自動利得制御電圧とし、該電圧に基づいて可変利得増幅器1、4、7、10の利得を制御する自動利得制御を行っている。
【0003】
さらに、第1中間周波数信号はバンドパスフィルタ21に供給して、隣接チャンネル除去および周波数変換により生じた高域成分を除去するなどの帯域制限を行い、バンドパスフィルタ21の出力を増幅器22に供給して増幅し、増幅器22からの増幅出力はバンドパスフィルタ23に供給して帯域制限を行い、バンドパスフィルタ23からの出力は可変利得増幅器24に供給して増幅のうえ、ミキサ25と局部発振器26とからなる周波数変換器によって第2中間周波数に周波数変換し、周波数変換された第2中間周波信号を検波回路27に供給して検波し、検波出力電圧を第2自動利得制御電圧とし、該電圧に基づいて可変利得増幅器24の利得を制御する自動利得制御を行っている。
【0004】
さらにまた、第2中間周波信号は復調器40に導いて復調する。一方、第1自動利得制御電圧をA/D変換器18に導いてデジタル信号に変換し、同様に第2自動利得制御電圧をA/D変換器28に導いてデジタル信号に変換し、A/D変換器18および28の変換出力も復調器40に供給して、復調器40においてA/D変換器18および28の変換出力から入力信号のレベルを判定し、該判定出力をD/A変換器を含む制御回路41に供給してアナログ信号に変換し、該判定出力に基づくアナログ電圧によって可変利得増幅器2、5、8、11の利得を各別に順次、ガードインターバルの期間において独立して変更する自動利得制御を行うことによりダイバーシティ受信を行っている。
【0005】
デジタル地上波放送受信機の場合、デジタル衛星放送受信機と異なって隣接チャンネルや隣隣接チャンネルとのD/U比(desired to undesired power ratio)が大きいため、D/U比が大きいときの感度抑圧や、3次歪みが問題となる。また、変調方式はOFDMのため、歪みによる影響は単なるPSK変調の時よりも大きいことから、デジタル地上波放送受信機におけるフロントエンドの自動利得制御ループを1つのループにすることは難しく、図4に示すように、第1中間周波信号の帯域制限前と帯域制限後とで別々の自動利得制御ループを構成し、初段の増幅器およびミキサによる歪みの発生を抑えている。
【0006】
【発明が解決しようとする課題】
上記した理由により自動利得制御ループが2つ存在するため、ダイバーシティのために使用する入力信号レベル検出用の自動利得制御電圧が2つ存在することから、この2つ存在する自動利得制御電圧をそれぞれA/D変換器でデジタル信号に変換し、後段の復調器で入力信号レベルを判断している。
【0007】
このように、従来ではデジタル地上波放送受信機におけるフロントエンドの自動利得制御回路では、復調器側で入力信号レベルを検出するために、2つのA/D変換器を必要とするとういう問題点があった。
【0008】
本発明は、復調器側で入力信号レベルを検出するためのA/D変換器が1つで済む自動利得制御回路を提供することを目的とする。
【0009】
【課題を解決するための手段】
本発明にかかる自動利得制御回路は、異なる位置に設けられた複数のアンテナから出力される同一チャンネルの信号を各別に増幅する初段可変利得増幅器の利得を、帯域制限前の第1中間周波信号を検波した第1自動利得制御電圧によって制御し、
帯域制限後の第1中間周波信号を周波数変換した第2中間周波信号を検波した第2自動利得制御電圧によって、帯域制限後の第1中間周波信号を増幅する可変利得増幅器の利得を制御し、
第1自動利得制御電圧の(ゲイン/自動利得制御電圧)と第2自動利得制御電圧の(ゲイン/自動利得制御電圧)とを同一にするための演算手段によって(ゲイン/自動利得制御電圧)が同一とされた第1および第2自動利得制御回路の出力を加算した電圧によって復調器への入力レベルを判定し、
該判定された入力レベルに基づいて、前記初段可変利得増幅器にそれぞれ縦続接続され、かつ出力電圧が合成されて合成出力が第1中間周波信号に周波数変換されるダイバーシティ用の可変利得増幅器の利得を、各別に順次独立して制御することを特徴とする。
【0010】
本発明にかかる自動利得制御回路によれば、初段可変利得増幅器の利得は第1自動利得制御電圧により制御され、帯域制限後の第1中間周波信号を増幅する可変利得増幅器の利得は第2自動利得制御電圧により制御され、演算手段により(ゲイン/自動利得制御電圧)が同一とされた第1自動利得制御電圧と第2自動利得制御電圧とを合成した電圧に基づいて入力レベルが判定され、判定された入力レベルに基づいてダイバーシティ用の可変利得増幅器の利得が制御される。したがって、(ゲイン/自動利得制御電圧)が同一とされた第1および第2自動利得制御回路の出力を加算した電圧によって復調器への入力レベルが判定されることになって、入力レベル判定のための信号をA/D変換するA/D変換器は1つで足りることになる。
【0011】
本発明にかかる自動利得制御回路において、(ゲイン/自動利得制御電圧)が同一とされた第1および第2自動利得制御回路の出力を加算した電圧と閾値を比較して比較結果に基づいて受信可能レベルか否かを判定する入力レベル判定回路を備えてもよい。
【0012】
本発明にかかる自動利得制御回路において、入力レベル判定回路を備えたときは、入力レベル判定回路の出力に基づき入力レベルを判定することができる。
【0013】
【発明の実施の形態】
以下、本発明にかかる自動利得制御回路を実施の一形態によって説明する。
【0014】
図1は本発明の実施の一形態にかかる自動利得制御回路を含むデジタル地上波放送受信機におけるフロントエンドの構成を示すブロック図である。
【0015】
本発明にかかる自動利得制御回路において、図4に示した自動利得制御回路と同一の構成要素には同一の符号を付して、重複を避けるため移同一の構成要素の説明は省略する。
【0016】
本発明の実施の一形態にかかる自動利得制御回路は、検波回路17の検波出力電圧すなわち第1自動利得制御電圧を、乗算器20−1と乗算器20−1の出力電圧に乗算およびオフセット加算を行う演算器20−2とからなる演算回路20に供給して演算し、検波回路28のの検波出力電圧すなわち第2自動利得制御電圧を、乗算器42−1と乗算器42−1の出力に乗算およびオフセット加算を行う演算器42−2とからなる演算回路42に供給して演算し、演算回路20の出力電圧と演算回路42の出力電圧とを加算回路43にて加算し、加算回路43の出力電圧をA/D変換器44に供給してデジタル信号に変換し、A/D変換器44にて変換されたデジタル信号を復調器40に供給し、A/D変換器44の出力に基づいて復調器40において入力信号のレベルを判定するようにしてある。
【0017】
乗算器20−1は検波回路17の出力電圧に乗算係数(1/X)を乗算し、演算器20−2は乗算器20−1の出力電圧に乗算係数Bを乗算すると共にオフセット値の加算を行い、乗算器42−1は検波回路27の出力電圧に乗算係数(1/Y)を乗算し、演算器42−2は乗算器40−1の出力電圧に乗算係数Aを乗算すると共にオフセット値の加算を行って、乗算係数(1/X)、B、(1/Y)、Aおよびオフセット値を選択して、演算回路20の出力電圧によるゲイン/自動利得制御電圧(dB/V)と演算回路42の出力電圧によるゲイン/自動利得制御電圧(dB/V)が同一になるように設定する。
【0018】
乗算器20−1、演算器20−2、乗算器42−1、演算器42−2は抵抗分圧器にて構成することができ、乗算器20−1および演算器20−2は第1自動利得制御電圧に乗算係数(B/X)の乗算を行いかつオフセット値を加える演算器で構成とすることもでき、乗算器42−1および演算器42−2は第2自動利得制御電圧に乗算係数(A/Y)の乗算を行いかつオフセット値を加える演算器で構成とすることもできる。
【0019】
演算回路20の出力電圧と演算回路42の出力電圧とは演算増幅器からなる加算回路43にて加算し、A/D変換器44でA/D変換され、復調器40に供給される。加算回路43では出力電圧がA/D変換器44の入力レンジに合うようにそのゲインが設定してある。
【0020】
可変利得増幅器1、4、7、10の利得を制御する検波器17を含む自動利得制御回路の自動利得制御電圧−ゲイン特性は一般に図2(a)の直線aに示すような特性であり、可変利得増幅器24の利得を制御する検波器27を含む自動利得制御回路の自動利得制御電圧−ゲイン特性は一般に図2(a)の直線bに示すような特性であって、ゲイン/自動利得制御電圧(dB/V)は検波器17を含む自動利得制御回路と検波器27を含む自動利得制御回路とでは異なっている。
【0021】
そこで、上記したように演算回路20および42による演算によって、演算回路20の出力電圧−ゲイン特性と演算回路42の出力電圧−ゲイン特性とは等しくなり、加算回路43の出力電圧−ゲイン特性は図2(b)に示すようになって、加算回路43の出力電圧に基づいて入力レベルが判定されて、この判定された入力レベルに基づいて可変利得増幅器2、5、8、11の利得が独立して制御されるダイバーシティが行われる。このようにすることで、フロントエンドのトータルゲインはほぼリニアな形で表現できて、ダイバーシティ用の自動利得制御電圧を1つにすることができる。
【0022】
上記した本発明の実施の一形態にかかる自動利得制御回路によればダイバーシティ用の自動電圧制御電圧を1つにすることができて、復調器40においてダイバーシティのための入力レベルの計算が簡単になる。
【0023】
なお、上記において、ゲイン/自動利得制御電圧(dB/V)を合わせるために演算回路20と42とを備えた場合を説明したが、何れか一方の演算回路によっても合わせることもできる。
【0024】
次に本発明の実施の一形態において入力レベル判定回路を設けた例について説明する。
【0025】
図3は図1に示すフロントエンドに入力レベル判定回路を設けた場合の構成を示すブロック図である。
【0026】
図3に示すように、閾値データをD/A変換器45−1でアナログ電圧に変換し、アナログ電圧に変換された閾値と加算回路43の出力電圧とを比較器45−2で比較し、比較出力を入力レベル判定出力として送出する入力レベル判定回路45が、図1に示すフロントエンドに設けてある。
【0027】
したがって、閾値を受信可能な入力レベルに対応した値に設定しておくことによって、加算回路43の出力電圧が閾値を超えているか、閾値未満であるかに基づいて現在の入力レベルが受信可能な入力レベルであるか否かを判定することができる。
【0028】
【発明の効果】
以上説明したように本発明にかかる自動利得制御回路によれば、(ゲイン/自動利得制御電圧)が同一とされた第1および第2自動利得制御回路の出力を加算した電圧によって復調器への入力レベルが判定されることになって、入力レベル判定のための信号をA/D変換するA/D変換器は1つで足りるという効果が得られる。
【図面の簡単な説明】
【図1】本発明の実施の一形態にかかる自動利得制御回路を含むデジタル地上波放送受信機におけるフロントエンドの構成を示すブロック図である。
【図2】本発明の実施の一形態にかかる自動利得制御回路の作用の説明に供する自動利得制御特性図である。
【図3】図1に示したフロントエンドに入力レベル判定回路を付加した場合のブロック図である。
【図4】従来の自動利得制御回路を含むデジタル地上波放送受信機におけるフロントエンドの構成を示すブロック図である。
【符号の説明】
1、2、4、5、7、8、10、11、および24 可変利得増幅器
13 合成器
14および25 ミキサ
15および26 局部発振器
17および27 検波回路
20および42 演算回路
40 復調器
43 加算回路
45 入力レベル判定回路
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an automatic gain control circuit used for a front end of a digital terrestrial broadcast receiver.
[0002]
[Prior art]
A front end including a conventional automatic gain control circuit used for a front end of a digital terrestrial broadcast receiver is configured as shown in FIG. For example, the signals of the same channel received by four antennas at different positions are supplied to the variable gain amplifiers 1, 4, 7, and 10 via the high frequency selection circuits, respectively, and are amplified. The amplified outputs of 4, 7, and 10 are supplied to the variable gain amplifiers 2, 5, 8, and 11 for amplification, and the amplified outputs of the variable gain amplifiers 2, 5, 8, and 11 are tracked by the tracking filters 3, 6, 9, 12 is separately supplied to perform band limitation mainly for the purpose of image frequency removal, and outputs band-limited by the tracking filters 3, 6, 9, and 12 are supplied to the synthesizer 13 for synthesis. The output is frequency-converted to a first intermediate frequency by a frequency converter comprising a mixer 14 and a local oscillator 15, and the frequency-converted first intermediate frequency signal is supplied to the detector 17 to be detected, and the detection output current is detected. Was the first automatic gain control voltage is performed an automatic gain control for controlling the gain of the variable gain amplifier 1, 4, 7, 10 based on the voltage.
[0003]
Further, the first intermediate frequency signal is supplied to the band pass filter 21 to perform band limitation such as removal of adjacent channels and high frequency components generated by frequency conversion, and the output of the band pass filter 21 is supplied to the amplifier 22. Then, the amplified output from the amplifier 22 is supplied to the band pass filter 23 for band limitation, and the output from the band pass filter 23 is supplied to the variable gain amplifier 24 for amplification, and then the mixer 25 and the local oscillator. The second intermediate frequency signal frequency-converted to the second intermediate frequency by the frequency converter composed of 26, and supplied to the detection circuit 27 for detection, and the detection output voltage as the second automatic gain control voltage, Automatic gain control is performed to control the gain of the variable gain amplifier 24 based on the voltage.
[0004]
Furthermore, the second intermediate frequency signal is guided to the demodulator 40 and demodulated. On the other hand, the first automatic gain control voltage is led to the A / D converter 18 and converted into a digital signal, and the second automatic gain control voltage is similarly led to the A / D converter 28 and converted into a digital signal. The conversion outputs of the D converters 18 and 28 are also supplied to the demodulator 40, and the demodulator 40 determines the level of the input signal from the conversion outputs of the A / D converters 18 and 28, and the determination output is D / A converted. Is supplied to a control circuit 41 including a converter and converted into an analog signal, and the gains of the variable gain amplifiers 2, 5, 8, and 11 are sequentially changed independently in the period of the guard interval by an analog voltage based on the determination output. Diversity reception is performed by performing automatic gain control.
[0005]
In the case of a digital terrestrial broadcast receiver, unlike a digital satellite broadcast receiver, the D / U ratio (desired to undesired power ratio) between adjacent channels and adjacent adjacent channels is large, so sensitivity reduction when the D / U ratio is large And third-order distortion becomes a problem. Also, since the modulation method is OFDM, the influence of distortion is greater than that of mere PSK modulation, so it is difficult to make the front-end automatic gain control loop in a digital terrestrial broadcast receiver into one loop. As shown in FIG. 5, separate automatic gain control loops are formed before and after the band limitation of the first intermediate frequency signal to suppress the occurrence of distortion due to the first-stage amplifier and mixer.
[0006]
[Problems to be solved by the invention]
Since there are two automatic gain control loops for the reasons described above, there are two automatic gain control voltages for detecting the input signal level used for diversity. The digital signal is converted by an A / D converter, and the input signal level is determined by a demodulator at the subsequent stage.
[0007]
As described above, the conventional front-end automatic gain control circuit in the digital terrestrial broadcasting receiver requires two A / D converters to detect the input signal level on the demodulator side. was there.
[0008]
An object of the present invention is to provide an automatic gain control circuit that requires only one A / D converter for detecting an input signal level on the demodulator side.
[0009]
[Means for Solving the Problems]
The automatic gain control circuit according to the present invention uses the gain of the first stage variable gain amplifier that amplifies signals of the same channel output from a plurality of antennas provided at different positions, and the first intermediate frequency signal before band limitation. Controlled by the detected first automatic gain control voltage,
A gain of a variable gain amplifier that amplifies the first intermediate frequency signal after band limitation is controlled by a second automatic gain control voltage obtained by detecting a second intermediate frequency signal obtained by frequency-converting the first intermediate frequency signal after band limitation;
The (gain / automatic gain control voltage) is set by computing means for making the (gain / automatic gain control voltage) of the first automatic gain control voltage and the (gain / automatic gain control voltage) of the second automatic gain control voltage the same. The input level to the demodulator is determined by the voltage obtained by adding the outputs of the first and second automatic gain control circuits that are the same,
Based on the determined input level, the gain of the variable gain amplifier for diversity is connected to the first-stage variable gain amplifiers respectively, and the output voltage is combined and the combined output is frequency converted into the first intermediate frequency signal. In addition, the control is performed independently and independently.
[0010]
According to the automatic gain control circuit of the present invention, the gain of the first stage variable gain amplifier is controlled by the first automatic gain control voltage, and the gain of the variable gain amplifier that amplifies the first intermediate frequency signal after band limitation is the second automatic gain control voltage. The input level is determined based on a voltage obtained by combining the first automatic gain control voltage and the second automatic gain control voltage, which are controlled by the gain control voltage and the same (gain / automatic gain control voltage) is set by the arithmetic means, Based on the determined input level, the gain of the variable gain amplifier for diversity is controlled. Therefore, the input level to the demodulator is determined by the voltage obtained by adding the outputs of the first and second automatic gain control circuits having the same (gain / automatic gain control voltage). Therefore, only one A / D converter for A / D converting the signal for this purpose is sufficient.
[0011]
In the automatic gain control circuit according to the present invention, a voltage obtained by adding the outputs of the first and second automatic gain control circuits having the same (gain / automatic gain control voltage) is compared with a threshold value and received based on the comparison result. You may provide the input level determination circuit which determines whether it is a possible level.
[0012]
When the automatic gain control circuit according to the present invention includes the input level determination circuit, the input level can be determined based on the output of the input level determination circuit.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
An automatic gain control circuit according to the present invention will be described below with reference to an embodiment.
[0014]
FIG. 1 is a block diagram showing a configuration of a front end in a digital terrestrial broadcast receiver including an automatic gain control circuit according to an embodiment of the present invention.
[0015]
In the automatic gain control circuit according to the present invention, the same components as those in the automatic gain control circuit shown in FIG. 4 are denoted by the same reference numerals, and the description of the same components is omitted to avoid duplication.
[0016]
The automatic gain control circuit according to the embodiment of the present invention multiplies the detection output voltage of the detection circuit 17, that is, the first automatic gain control voltage, to the output voltages of the multiplier 20-1 and the multiplier 20-1, and adds an offset. Is supplied to the arithmetic circuit 20 including the arithmetic unit 20-2 for performing the calculation, and the detection output voltage of the detection circuit 28, that is, the second automatic gain control voltage, is output from the multiplier 42-1 and the multiplier 42-1. Is supplied to an arithmetic circuit 42 including an arithmetic unit 42-2 for performing multiplication and offset addition, and an output voltage of the arithmetic circuit 20 and an output voltage of the arithmetic circuit 42 are added by an adder circuit 43, and an adder circuit The output voltage of 43 is supplied to the A / D converter 44 and converted into a digital signal. The digital signal converted by the A / D converter 44 is supplied to the demodulator 40, and the output of the A / D converter 44 is output. Based on demodulator 40 It is so as to determine the level of Oite input signal.
[0017]
The multiplier 20-1 multiplies the output voltage of the detection circuit 17 by a multiplication coefficient (1 / X), and the arithmetic unit 20-2 multiplies the output voltage of the multiplier 20-1 by a multiplication coefficient B and adds an offset value. The multiplier 42-1 multiplies the output voltage of the detection circuit 27 by the multiplication coefficient (1 / Y), and the arithmetic unit 42-2 multiplies the output voltage of the multiplier 40-1 by the multiplication coefficient A and the offset. The value is added, the multiplication coefficient (1 / X), B, (1 / Y), A and the offset value are selected, and the gain / automatic gain control voltage (dB / V) based on the output voltage of the arithmetic circuit 20 And the gain / automatic gain control voltage (dB / V) by the output voltage of the arithmetic circuit 42 are set to be the same.
[0018]
The multiplier 20-1, the computing unit 20-2, the multiplier 42-1, and the computing unit 42-2 can be configured by resistance voltage dividers, and the multiplier 20-1 and the computing unit 20-2 are first automatic. An arithmetic unit that multiplies the gain control voltage by a multiplication coefficient (B / X) and adds an offset value may be used. The multiplier 42-1 and the arithmetic unit 42-2 multiply the second automatic gain control voltage. An arithmetic unit that multiplies the coefficient (A / Y) and adds an offset value can also be used.
[0019]
The output voltage of the arithmetic circuit 20 and the output voltage of the arithmetic circuit 42 are added by an adder circuit 43 comprising an operational amplifier, A / D converted by an A / D converter 44, and supplied to a demodulator 40. In the adder circuit 43, the gain is set so that the output voltage matches the input range of the A / D converter 44.
[0020]
The automatic gain control voltage-gain characteristic of the automatic gain control circuit including the detector 17 for controlling the gain of the variable gain amplifiers 1, 4, 7, 10 is generally as shown by the straight line a in FIG. The automatic gain control voltage-gain characteristic of the automatic gain control circuit including the detector 27 for controlling the gain of the variable gain amplifier 24 is generally as shown by the straight line b in FIG. The voltage (dB / V) is different between the automatic gain control circuit including the detector 17 and the automatic gain control circuit including the detector 27.
[0021]
Therefore, as described above, the output voltage-gain characteristic of the arithmetic circuit 20 and the output voltage-gain characteristic of the arithmetic circuit 42 are equalized by the calculation by the arithmetic circuits 20 and 42, and the output voltage-gain characteristic of the adder circuit 43 is As shown in FIG. 2 (b), the input level is determined based on the output voltage of the adder circuit 43, and the gains of the variable gain amplifiers 2, 5, 8, 11 are independent based on the determined input level. And controlled diversity. By doing so, the total gain of the front end can be expressed in a substantially linear form, and the automatic gain control voltage for diversity can be made one.
[0022]
According to the automatic gain control circuit according to the embodiment of the present invention described above, the automatic voltage control voltage for diversity can be made one, and the demodulator 40 can easily calculate the input level for diversity. Become.
[0023]
In the above description, the case where the arithmetic circuits 20 and 42 are provided in order to match the gain / automatic gain control voltage (dB / V) has been described. However, any one of the arithmetic circuits may be used.
[0024]
Next, an example in which an input level determination circuit is provided in one embodiment of the present invention will be described.
[0025]
FIG. 3 is a block diagram showing a configuration when an input level determination circuit is provided in the front end shown in FIG.
[0026]
As shown in FIG. 3, the threshold data is converted into an analog voltage by the D / A converter 45-1, the threshold converted to the analog voltage and the output voltage of the adder circuit 43 are compared by the comparator 45-2, An input level determination circuit 45 for sending a comparison output as an input level determination output is provided in the front end shown in FIG.
[0027]
Therefore, by setting the threshold value to a value corresponding to the receivable input level, the current input level can be received based on whether the output voltage of the adder circuit 43 exceeds the threshold value or less than the threshold value. It can be determined whether or not the input level.
[0028]
【The invention's effect】
As described above, according to the automatic gain control circuit of the present invention, the demodulator is supplied with the voltage obtained by adding the outputs of the first and second automatic gain control circuits having the same (gain / automatic gain control voltage). Since the input level is determined, the effect that only one A / D converter is required to perform A / D conversion on the signal for determining the input level is obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a front end in a digital terrestrial broadcast receiver including an automatic gain control circuit according to an embodiment of the present invention.
FIG. 2 is an automatic gain control characteristic diagram for explaining the operation of the automatic gain control circuit according to the embodiment of the present invention.
FIG. 3 is a block diagram when an input level determination circuit is added to the front end shown in FIG. 1;
FIG. 4 is a block diagram showing a configuration of a front end in a digital terrestrial broadcast receiver including a conventional automatic gain control circuit.
[Explanation of symbols]
1, 2, 4, 5, 7, 8, 10, 11, and 24 Variable gain amplifier 13 Synthesizer 14 and 25 Mixer 15 and 26 Local oscillator 17 and 27 Detection circuit 20 and 42 Operation circuit 40 Demodulator 43 Addition circuit 45 Input level judgment circuit

Claims (2)

異なる位置に設けられた複数のアンテナから出力される同一チャンネルの信号を各別に増幅する初段可変利得増幅器の利得を、帯域制限前の第1中間周波信号を検波した第1自動利得制御電圧によって制御し、
帯域制限後の第1中間周波信号を周波数変換した第2中間周波信号を検波した第2自動利得制御電圧によって、帯域制限後の第1中間周波信号を増幅する可変利得増幅器の利得を制御し、
第1自動利得制御電圧の(ゲイン/自動利得制御電圧)と第2自動利得制御電圧の(ゲイン/自動利得制御電圧)とを同一にするための演算手段によって(ゲイン/自動利得制御電圧)が同一とされた第1および第2自動利得制御回路の出力を加算した電圧によって復調器への入力レベルを判定し、
該判定された入力レベルに基づいて、前記初段可変利得増幅器にそれぞれ縦続接続され、かつ出力電圧が合成されて合成出力が第1中間周波信号に周波数変換されるダイバーシティ用の可変利得増幅器の利得を、各別に順次独立して制御することを特徴とする自動利得制御回路。
The gain of the first stage variable gain amplifier that amplifies signals of the same channel output from a plurality of antennas provided at different positions is controlled by a first automatic gain control voltage obtained by detecting the first intermediate frequency signal before band limitation. And
A gain of a variable gain amplifier that amplifies the first intermediate frequency signal after band limitation is controlled by a second automatic gain control voltage obtained by detecting a second intermediate frequency signal obtained by frequency-converting the first intermediate frequency signal after band limitation;
The (gain / automatic gain control voltage) is set by computing means for making the (gain / automatic gain control voltage) of the first automatic gain control voltage and (gain / automatic gain control voltage) of the second automatic gain control voltage the same. The input level to the demodulator is determined by the voltage obtained by adding the outputs of the first and second automatic gain control circuits that are the same,
Based on the determined input level, the gain of the variable gain amplifier for diversity is connected to the first-stage variable gain amplifiers respectively, and the output voltage is combined and the combined output is frequency converted into the first intermediate frequency signal. An automatic gain control circuit characterized by being controlled independently and independently for each.
請求項1記載の自動利得制御回路において、(ゲイン/自動利得制御電圧)が同一とされた第1および第2自動利得制御回路の出力を加算した電圧と閾値を比較して比較結果に基づいて受信可能レベルか否かを判定する入力レベル判定回路を備えたことを特徴とする自動利得制御回路。2. The automatic gain control circuit according to claim 1, wherein a voltage obtained by adding the outputs of the first and second automatic gain control circuits having the same (gain / automatic gain control voltage) is compared with a threshold value and based on the comparison result. An automatic gain control circuit comprising an input level determination circuit for determining whether or not the level is a receivable level.
JP2001014010A 2001-01-23 2001-01-23 Automatic gain control circuit Expired - Fee Related JP3713206B2 (en)

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JP2007068143A (en) * 2005-08-05 2007-03-15 Matsushita Electric Ind Co Ltd Antenna matching unit and high frequency receiving device using the same
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