JP3712156B2 - Pseudo-noise code synchronization acquisition apparatus and reception apparatus - Google Patents

Description

[0001]
【table of contents】
The present invention will be described in the following order.
[0002]
TECHNICAL FIELD OF THE INVENTION
Conventional technology (Fig. 9)
Problems to be solved by the invention
Means for solving the problem
BEST MODE FOR CARRYING OUT THE INVENTION
(1) Outline of CDMA system
(2) Configuration of receiving apparatus (FIG. 1)
(3) First embodiment
(3-1) Configuration of synchronization acquisition device (FIG. 2)
(3-2) Configuration of PN code generator (FIGS. 3 to 5)
(3-3) Operation and effect
(4) Second embodiment
(4-1) Configuration of synchronization acquisition apparatus (FIGS. 6 and 7)
(4-2) Configuration of PN code generator (FIG. 8)
(4-3) Operation and effect
(5) Other embodiments
The invention's effect
[0003]
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-noise code synchronization acquisition apparatus and reception apparatus, for example, pseudo noise provided in a reception apparatus of a CDMA (Code Division Multiple Access) type cellular telephone system (hereinafter referred to as CDMA cellular). The present invention is suitable for application to a code acquisition device (hereinafter referred to as PN code: Pseudo random Noise sequence code).
[0004]
[Prior art]
Conventionally, in a CDMA cellular system, an independent PN code having a bit collocation pattern and a different phase is used as a spreading code to spread the spectrum of a carrier wave of a transmission signal, thereby increasing communication capacity and enabling multiple access.
[0005]
In this CDMA cellular system, a transmission side (for example, a base station) performs primary modulation (for example, QPSK (Quadrature Phase Shift Keying) modulation) with transmission data at the time of transmission, and multiplies this primary modulated carrier by a PN code. By doing so, the secondary modulation is performed and the frequency spectrum of the carrier wave is spread and transmitted.
[0006]
On the receiving side (for example, a mobile station), the primary modulation output is obtained by performing despreading by multiplying the received signal by a PN code having the same bit collocation pattern and the same phase as those used on the transmitting side. Thus, the received data is restored by demodulating the primary modulation output.
[0007]
That is, the receiving side has a PN code generating unit that generates a PN code having the same bit queuing pattern as the PN code multiplied on the transmitting side, and the PN code generating unit uses the same bit queuing pattern and the same phase as those of the transmitting side. A PN code is generated and multiplied by the received signal.
[0008]
By the way, when the receiving side receives a transmission signal sent from the transmitting side when the power is turned on, the phase of the PN code multiplied by the transmitting side is not known. Therefore, on the reception side, it is necessary to synchronize the phase of the PN code used on the transmission side by the synchronization acquisition device and the phase of the PN code generated by the PN code generation unit on the reception side. Such a synchronization acquisition device will be described next.
[0009]
As shown in FIG. 9, reference numeral 1 denotes a conventional synchronization acquisition apparatus as a whole, which is obtained by multiplying a reception signal received via an antenna (not shown) by a demodulation carrier having the same frequency as the carrier of the reception signal. Unnecessary high frequency components are removed, a baseband signal is taken out, and received data D1 obtained by analog / digital conversion of the baseband signal is input to the multiplier 2. Here, the reception data D1 is PN code data subjected to spectrum spread on the transmission side.
[0010]
The PN code generation unit 3 generates a PN code composed of a code sequence having the same bit collocation pattern as that of the transmission side based on the control of the controller 4 and moves the phase of the PN code to sequentially multiply the PN codes D2 having different phases. Output to 2. The multiplier 2 multiplies each bit of the PN code D2 supplied from the PN code generator 3 and each bit of the corresponding received data D1, and sends the multiplication result D3 to the adder 5.
[0011]
At this time, when the phase of the received data D1 and the phase of the PN code D2 supplied from the PN code generator 3 match, despreading is established and the signal level of the multiplication result D3 increases. Therefore, as long as the phase of the received data D1 and the phase of the PN code D2 supplied from the PN code generator 3 do not match, the signal level of the multiplication result D3 does not increase.
[0012]
The adder 5 is supplied with the previous cumulative addition output D4 held by the addition value holding circuit 6, adds the cumulative addition output D4 to the multiplication result D3, and sequentially sends it to the addition value holding circuit 6. . In this way, the addition value holding circuit 6 sends the cumulative addition result D5 calculated by cumulatively adding all the multiplication results D3 for one cycle of the PN code D2 to the memory 7 under the control of the controller 4, and next In order to calculate the cumulative addition result, the cumulative addition data held so far is cleared. The memory 7 sequentially stores the cumulative addition result D5 for one period sent in this way as a correlation value.
[0013]
As described above, the synchronization acquisition device 1 calculates the correlation value with the reception data D1 for each of the plurality of PN codes D2 having different phases, and sequentially stores them in the memory 7. When the correlation value of the cumulative addition output D4 stored in the memory 7 exceeds a predetermined reference value, the controller 4 determines the phase of the PN code when the correlation value is obtained as the PN code used on the transmission side. The phase information S10 is detected as the phase.
[0014]
As a result, the phase information S10 of the PN code on the transmission side detected by the synchronization acquisition device 1 is supplied to the demodulator on the receiving side and the phase synchronized with the transmission side by the PN code generator in the demodulator. The received signal can be demodulated by despreading using the PN code.
[0015]
[Problems to be solved by the invention]
By the way, in the synchronization acquisition device having such a configuration, in order to synchronize with the phase of the PN code multiplied on the transmission side, the correlation values between the plurality of PN codes D2 generated from the PN code generator 3 and the received data D1 are sequentially calculated. However, it is necessary to continue calculating the correlation value until the correlation value exceeds a predetermined reference value.
[0016]
Therefore, the synchronization acquisition device sequentially calculates the correlation value between the PN code D2 and the reception data D1 for each phase until the correlation value exceeds a predetermined reference value, particularly when synchronization is acquired for the first time when the receiver is turned on. There is a problem that it takes a lot of time to acquire synchronization.
[0017]
In addition, as a receiving device, if it takes a long time to acquire synchronization in the internal synchronization acquisition device, the waiting time from when the power is turned on until the call becomes ready becomes longer, and unnecessary power consumption is required until synchronization is acquired. There was a problem that occurred.
[0018]
The present invention has been made in consideration of the above points, and an object of the present invention is to propose a pseudo-noise code synchronization acquisition apparatus and reception apparatus that can detect the phase of a pseudo-noise code in a short time with a simple configuration.
[0019]
[Means for Solving the Problems]
In order to solve such a problem, in the present invention, the phase is respectively determined via one offset generator and a plurality of delay elements based on the code sequence having the same bit sequence pattern as the first pseudo-noise code transmitted from the transmission side. And a plurality of second pseudo-noise codes generating means for generating a plurality of second pseudo-noise codes, and a plurality of second pseudo-noise codes selected at respective timings obtained by time-dividing one chip in the received first pseudo-noise code. And a selector means for outputting the first pseudo-noise code and a plurality of second pseudo-noise codes supplied from the selector means, and a multiplication result obtained by the multiplication means. 2 are sequentially added for each phase of the two pseudo-noise codes, and each of the first pseudo-noise code and the second pseudo-noise code is added to calculate a cumulative addition result for one period. Storage means for storing a plurality of cumulative addition results as correlation values for each phase; and a phase of a second pseudo-noise code corresponding to a correlation value exceeding a predetermined reference value among the plurality of correlation values, And detecting means for detecting the phase of the pseudo-noise code.
[0020]
As a result, a plurality of second pseudo noise codes having different phases can be obtained by a simple configuration comprising one offset generator and a plurality of delay elements based on a code sequence having the same bit sequence pattern as the first pseudo noise code. In addition to being able to be generated, a plurality of second pseudo-noise codes and first pseudo-noise codes are combined into a set of multiplication means and addition means at respective timings obtained by time-dividing one chip in the first pseudo-noise code. Therefore, the correlation values can be calculated and synchronized in a short time with a simple configuration.
[0021]
In the present invention, the receiving means for receiving the transmission data spread by the first pseudo-noise code and obtaining the received data, and the code having the same bit sequence pattern as the first pseudo-noise code included in the received data Pseudo-noise code generating means for generating a plurality of second pseudo-noise codes having different phases through one offset generator and a plurality of delay elements based on the sequence, and within one chip in the first pseudo-noise code Correlation calculating means for calculating in parallel each correlation value with a plurality of second pseudo-noise codes at respective timings obtained by time-division, and the phase of the first pseudo-noise code based on the signal level of the correlation values A phase detecting means for detecting the second pseudo noise code, and a demodulator for demodulating the received data by despreading based on the second pseudo noise code detected by the phase detecting means. To be provided and means.
[0022]
As a result, a plurality of second pseudo noise codes having different phases can be obtained by a simple configuration comprising one offset generator and a plurality of delay elements based on a code sequence having the same bit sequence pattern as the first pseudo noise code. In addition to being generated, a plurality of second pseudo-noise codes and first pseudo-noise codes are calculated in parallel at respective timings obtained by time-dividing one chip in the first pseudo-noise code, Detecting a second pseudo-noise code synchronized with the phase of the first pseudo-noise code based on the signal level of the correlation value, and demodulating the received data by despreading based on the second pseudo-noise code Therefore, the received data can be demodulated in a short time with a simple configuration.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0024]
(1) Outline of CDMA system
In the CDMA cellular network, the forward link (from the base station to the mobile station) channel is configured by four channels: a pilot channel, a sync channel, a paging channel, and a traffic channel.
[0025]
Of these, the pilot channel is a channel that repeatedly transmits only the PN code, and is used for acquiring and maintaining synchronization of the PN code and for clock reproduction on the receiving side. Incidentally, communication data is not transmitted in this pilot channel.
[0026]
The sync channel is a channel used to synchronize the system clock between the base station and the mobile station. The paging channel is a channel that transmits information necessary for handoff and terminal call information at the time of incoming call. is there. Further, the traffic channel is a channel for transmitting actual communication data such as voice information.
[0027]
Therefore, in an actual CDMA cellular, a transmission signal consisting only of a PN code is always output from the transmission side via the pilot channel, and when the power is turned on, the transmission signal is first received via this pilot channel and received. The phase of the PN code used on the transmission side is detected by calculating the correlation value between the received signal and a plurality of PN codes having different phases generated in the PN code generator. Subsequently, on the receiving side, despreading is performed by multiplying the received signal received by another sync channel, paging channel, traffic channel, etc. by a PN code synchronized with the phase of the PN code used on the transmitting side. And then demodulating.
[0028]
(2) Configuration of receiving device
In FIG. 1, reference numeral 10 denotes a receiving apparatus of the present invention as a whole in a CDMA cellular system, and a pilot channel received signal S 1 received via an antenna 11 is input to a high-frequency circuit 12. The high-frequency circuit 12 multiplies the reception signal S1 by a demodulation carrier wave having the same frequency as the carrier wave of the reception signal S1, thereby removing unnecessary high-frequency components and taking out a baseband signal, and performing analog / digital conversion on the baseband signal. Thus, the received data D10 is obtained and sent to the synchronization acquisition device 13. Here, the reception data D10 is PN code data subjected to spectrum spread.
[0029]
The synchronization acquisition device 13 detects the phase information S11 of the reception data D10 based on the control of the control circuit 15, and outputs the phase information S11 to the control circuit 15. The control circuit 15 is a CPU (Central Processing Unit) and supplies the phase information S11 to the demodulation circuit 14.
[0030]
Thereafter, the receiving apparatus 10 performs predetermined signal processing on the received signal S1 received via another traffic channel, for example, by the high frequency circuit 12, and sends the obtained received data D10 to the demodulating circuit 14. Based on the phase information S11 supplied from the control circuit 15 to the reception data D10, the demodulation circuit 14 generates a PN code whose phase is synchronized with that of the transmission side by an internal PN code generator. By using the received data D10 for despreading and demodulating, the audio information S2 is restored from the received data D10 and the audio is output from the speaker (not shown) at the subsequent stage via the output terminal 16. Yes.
[0031]
(3) First embodiment
(3-1) Configuration of synchronization acquisition device
Next, FIG. 2 shows a circuit configuration of the synchronization acquisition device 13 of the present invention, and the received data D10 is inputted to four multipliers 21 to 24 one bit at a time. The PN code generation unit 25 simultaneously generates four types of PN codes D21 to D24 having the same bit sequence pattern as the PN code used on the transmission side under the control of the controller 26, which is a micro computer, and having different phases. The PN codes D21 to D24 are output to the multipliers 21 to 24 one bit at a time.
[0032]
Multipliers 21 to 24 multiply the given PN codes D21 to D24 and received data D10 in parallel one bit at a time, and output the multiplication results D31 to D34 to adders 27 to 30, respectively. Here, the multiplication results D31 to D34 increase in signal level when the phases of the reception data D10 and the PN codes D21 to D24 coincide. The adders 27 to 30 add the inputted multiplication results D31 to D34 and the previous addition value output given from each of the addition value holding circuits 31 to 34, and add the addition results D37 to D40 to the addition value holding circuits 31 to 31. 34 respectively.
[0033]
The addition value holding circuits 31 to 34 are controlled by the controller 26. When all the multiplication results for one period of the PN codes D21 to D24 are cumulatively added by the adders 27 to 30, the cumulative addition results D41 to D41 are added. D44 is stored in the memory 35 as the correlation value between the received data D10 and the PN codes D21 to D24, and the accumulated addition data held so far is cleared.
[0034]
When the controller 26 detects a correlation value exceeding a predetermined reference value among the correlation values stored in the memory 35 for each phase, the phase information S11 of the PN code corresponding to the correlation value is used on the transmission side. The phase of the PN code is determined and output to the control circuit 11 at the subsequent stage. By the way, the PN codes D21 to D24 are quaternary (one cycle is 15 (2 ^Four Next, the detailed configuration of the PN code generator will be described assuming that it is an M-sequence code of -1) bit).
[0035]
(3-2) Configuration of PN code generator
As shown in FIG. 3, the PN code generator 25 includes a PN code generator 51 and four offset generators 52-55. The PN code generator 51 supplies the PN code D50 generated based on the clock CLK1 supplied from the controller 26 in parallel to the offset generators 52 to 55 via the 4-bit width bus.
[0036]
The offset generators 52 to 55 can arbitrarily set the phase based on the control data D51 to D54 respectively supplied from the controller 26 via the 4-bit width bus, and are supplied from the PN code generator 51. On the basis of the PN code D50, four types of PN codes D21 to D24 having arbitrarily different phases are simultaneously generated and output one bit at a time.
[0037]
Accordingly, the PN code generation unit 25 simultaneously generates and outputs four types of PN codes D21 to D24, and then supplies the next control data D51 to D54 from the controller 26. Four types of PN codes having a phase different from that of D24 are similarly generated and output.
[0038]
As described above, the PN code generation unit 25 can arbitrarily set and output the phase according to the 4-bit control data D51 to D54 supplied from the controller 26.
[0039]
Next, the circuit configuration of the PN code generator 51 and the offset generator 52 will be described. Here, the offset generators 53 to 55 are omitted because they are the same as the circuit configuration of the offset generator 52.
[0040]
In practice, as shown in FIG. 4, the PN code generator 51 has four stages of cyclic shift registers SR1 to SR4 and one exclusive OR circuit EX4 corresponding to the period of the PN code (15 bits). Based on the clock signal CLK1 supplied from the controller 26, the data stored in the shift registers SR1 to SR4 are sequentially shifted adjacently (in the direction of the arrows) and output to the offset generator 52, respectively.
[0041]
The offset generator 52 includes four-stage AND circuits A1 to A4 and three-stage exclusive OR circuits EX1 to EX3. The offset generator 52 receives the data supplied from the shift registers SR1 to SR4 of the PN code generator 51. The data is input to one of the input terminals A1 to A4, and 4-bit control data D51 for determining the phase offset amount is input from the controller 26 to the other input terminal.
[0042]
The offset generator 52 supplies AND outputs of the AND circuits A1 to A4 to one or the other input terminals of the exclusive OR circuits EX1 to EX3, and outputs an output of the exclusive OR circuit EX3 to one input of the exclusive OR circuit EX2. The output of the exclusive OR circuit EX2 is output to one input terminal of the exclusive OR circuit EX1, and the output from the exclusive OR circuit EX1 is output as a final code sequence of the PN code D21. Yes.
[0043]
As described above, the PN code generator 25 has the same bit sequence pattern based on the data output from the shift registers SR1 to SR4 of the PN code generator 51 and the control data D51 supplied from the controller 26. A PN code D21 whose phase is arbitrarily set in the code sequence is generated by an offset generator 52 and output.
[0044]
For example, FIG. 5 shows a 4-bit data string output simultaneously from the shift registers SR1 to SR4 of the PN code generator 51 to the offset generator 52. When (0, 0, 0, 1) is input as an initial value to the shift registers SR1 to SR4, the PN code generator 51 sequentially shifts the data to the next at the timing of the clock CLK1, and also to the offset generator 52. By outputting, the data string changes to (1, 1, 0, 0), (0, 1, 1, 0)... For each clock CLK1, and different data strings are output until one cycle (15 patterns). Is done.
[0045]
Accordingly, in the PN code generation unit 25, these data strings are changed in 15 ways by the PN code generator 51, and the AND circuits A1 to A4 of the offset generator 52 and the exclusive OR circuit EX1 according to the change. The calculation result calculated by .about.EX3 is output bit by bit as a PN code D21 having an arbitrarily set phase.
[0046]
Subsequently, when the next control data D51 is supplied from the controller 26 to the offset generator 52, the PN code generator 25 outputs a PN code D21 whose phase is offset by several bits in accordance with the control data D51. . Thus, the PN code generation unit 25 can arbitrarily move the phase of the PN code D21 by arbitrarily setting the control data D51.
[0047]
(3-3) Operation and effect
In the above configuration, the synchronization acquisition device 13 simultaneously generates four types of PN codes D21 to D24 having different phases by the PN code generator 25, and multiplies the PN codes D21 to D24 and the received data D10 by multipliers 21 to 21. 24, the adders 27 to 30 and the addition value holding circuits 31 to 34 respectively perform multiplication and accumulation processing in parallel, and store these accumulation addition results D41 to D44 in the memory 35 as correlation values.
[0048]
As a result, the synchronization acquisition device 13 can calculate the correlation value used when detecting the phase information S11 of the PN code used on the transmission side at a speed four times that of the related art. Therefore, the synchronization acquisition device 13 can detect the phase information S11 of the PN code used on the transmission side in a time shortened to ¼ compared with the conventional one, and thus the processing time of the receiving device 10 as a whole is 1 / 4.
[0049]
According to the above configuration, the receiving apparatus 10 simultaneously generates four types of PN codes D21 to D24 having different phases by the synchronization acquisition apparatus 13, and the correlation value between the PN codes D21 to D24 and the received data D10. Since the correlation values used for synchronization detection can be calculated at a speed four times faster, the phase information S11 of the PN code used on the transmission side is thus shortened to ¼. Can be detected.
[0050]
As a result, by shortening the processing time until the acquisition of synchronization, the receiving apparatus 10 can reduce the waiting time from when the power is turned on until the telephone becomes ready, and also reduce power consumption.
[0051]
(4) Second embodiment
(4-1) Configuration of synchronization acquisition device
In FIG. 6, in which parts corresponding to those in FIG. 2 are assigned the same reference numerals, reference numeral 60 denotes a synchronization acquisition device according to the second embodiment, and the synchronization acquisition device 13 according to the first embodiment has four sets of multipliers. Whereas it is constituted by 21 to 24 and adders 27 to 30, it is constituted by a set of multiplier 61 and adder 62.
[0052]
The PN code generation unit 63 is a code sequence having the same bit sequence pattern as that of the PN code used on the transmission side in the same manner as the PN code generation unit 25 in the first embodiment, and four types of PN having different phases. Codes D71 to D74 are simultaneously generated and output to the selector 64.
[0053]
The controller 65 is a microcomputer, and by controlling the selector 64, the multiplier 61 has a period until one bit data of the received data D10 next changes as shown in FIG. 7 (hereinafter, this is called one chip). ) Sequentially select and output four types of PN codes D71 to D74. That is, the controller 65 divides one chip into four, outputs 1 bit of the PN code D71 to the multiplier 61 at the first 1/4 chip, and multiplies 1 bit of the PN code D72 at the second 1/4 chip. 61, 1 bit of the PN code D73 is output to the multiplier 61 at the third 1/4 chip, and 1 bit of the PN code D74 is output to the multiplier 61 at the last 1/4 chip.
[0054]
Further, the controller 65 controls the multiplexer 66 and the addition selector 67, and outputs the multiplication result D81 of the PN code D71 and the reception data D10 to the addition value holding circuit 31 through the multiplexer 66. Is added to the adder 62 via the addition selector 67 during the first quarter chip.
[0055]
Thus, the controller 65 accumulates the multiplication result D81 by the multiplier 61 and the addition value held by the addition value holding circuit 31 by the adder 62 during the first 1/4 chip. The addition result is held in the addition value holding circuit 31.
[0056]
Similarly, the controller 65 sends the multiplication result D82 obtained by the multiplier 61 and the addition value held by the addition value holding circuit 31 by the adder 62 during the second quarter chip. Accumulated addition is performed, and the addition result is held in the added value holding circuit 32.
[0057]
The controller 65 repeats the same processing during the third quarter chip and during the last quarter chip, so that the received data D10 and the PN codes D71 to D74 for each phase are obtained during one chip. And multiplication and addition processing. As a result, the synchronization acquisition device 60 apparently performs the multiplication and addition processing of the reception data D10 and the PN codes D71 to D74 in parallel in one chip.
[0058]
When the controller 65 completes the multiplication and addition processing for one cycle, the accumulated addition results D91 to D94 held in the added value holding circuits 31 to 34 are stored in the memory 35 as correlation values, and the accumulated values held so far are stored. Clear the added data.
[0059]
When the controller 65 detects a correlation value exceeding a predetermined reference value among the correlation values stored in the memory 35 for each phase, the phase information S11 of the PN code corresponding to the correlation value is used on the transmission side. The phase of the PN code is determined, and this is output to the control circuit 15 at the subsequent stage.
[0060]
(4-2) Configuration of PN code generator
Next, the configuration of the PN code generator 63 is shown in FIG. As shown in FIG. 8, the PN code generator 63 includes the PN code generator 51 and the offset generator 52 in the first embodiment, and three delay elements 73 to 75.
[0061]
As in the first embodiment, the PN code generator 51 generates a PN code D50 based on the clock CLK1 supplied from the controller 65, and supplies it to the offset generator 52 via a 4-bit width bus.
[0062]
The offset generator 52 outputs the PN code D21 having a phase arbitrarily set based on the control data D51 supplied from the controller 65 via the 4-bit width bus, bit by bit, and sequentially to the delay elements 73 to 75. Supply. As a result, the offset generator 52 can simultaneously output the PN codes D21 to D24 whose phases are offset one bit at a time via the delay elements 73 to 75, one bit at a time. Note that the circuit configurations of the PN code generator 51 and the offset generator 52 are the same as those in FIG. 4 shown in the first embodiment, and are omitted here.
[0063]
(4-3) Operation and effect
In the above configuration, the synchronization acquisition device 60 simultaneously generates four types of PN codes D71 to D74 having different phases by the PN code generator 63, and each of the 1/4 chips obtained by dividing one chip into four by the selector 64. Since the multiplication and addition processing of the PN codes D71 to D74 and the reception data D10 is performed during the period, the reception data D10 and the PN having four types of phases are obtained by the one set of multiplier 61 and adder 62. The multiplication results D81 to D84 with the codes D71 to D74 can be calculated in parallel.
[0064]
In this way, the synchronization acquisition device 60 performs multiplication and addition processing of the reception data D10 and the PN codes D71 to D74 having four types of phases in one chip by one set of multiplier 61 and adder 62. By doing so, the multiplication and addition processing of the PN codes D71 to D74 and the received data D10 are performed in parallel using four sets of multipliers and adders, as in the synchronization acquisition device 13 in the first embodiment. The correlation value can be calculated four times faster than the conventional method.
[0065]
Therefore, the synchronization acquisition device 60 can detect the phase information S11 of the PN code used on the transmission side in a time shortened to ¼ compared to the conventional case, and thus the processing time of the entire receiving device 10 is 1 / 4.
[0066]
In addition, the synchronization acquisition device 60 can calculate a correlation value at a speed four times that of the conventional one by using a set of multiplier 61 and adder 62, so that the circuit can be compared with the synchronization acquisition device 13 in the first embodiment. The configuration can be further simplified and reduced in size, and the power consumption can be reduced.
[0067]
According to the above configuration, the receiving apparatus 10 performs the multiplication and addition processing of the four types of PN codes D71 to D74 and the received data D10 in one chip by the synchronization acquisition apparatus 60, so that synchronization is achieved. The correlation value used for detection can be calculated at a fourfold speed, and thus the phase information S11 of the PN code used on the transmission side can be detected in a time reduced to ¼.
[0068]
As a result, by shortening the processing time until the acquisition of synchronization, the receiving apparatus 10 can reduce the waiting time from when the power is turned on until the telephone becomes ready, and also reduce power consumption.
[0069]
(5) Other embodiments
In the first and second embodiments described above, the case where the PN code generation units 25 and 63 generate four types of PN codes having different phases has been described. Not limited to this, n types of PN codes having different phases may be generated simultaneously. In this case, the processing time until the correlation value is calculated can be reduced to 1 / n as in the first and second embodiments described above.
[0070]
In the first embodiment described above, the PN code generator 25 having a configuration including the PN code generator 51 and the four offset generators 52 to 55 as shown in FIG. 3 is used. However, the present invention is not limited to this, and a configuration comprising a PN code generator 51, an offset generator 52, and three delay elements 73 to 75 as in the PN code generator 63 in the second embodiment. (FIG. 8) may be used.
[0071]
Further, in the second embodiment described above, a PN code generator 63 having a configuration comprising a PN code generator 51, an offset generator 52, and three delay elements 73 to 75 as shown in FIG. Although the present invention has been described above, the present invention is not limited to this, and a configuration comprising a PN code generator 51 and four offset generators 52 to 55 as in the PN code generator 25 in the first embodiment. (FIG. 3) may be used.
[0072]
Further, in the first and second embodiments described above, the case where a PN code having a 15-bit period is used has been described. However, the present invention is not limited to this, and a larger number of bits can be used in one period. The synchronization acquisition devices 13 and 60 of the present invention may be applied to a reception device using the PN code.
[0073]
Furthermore, in the above-described first and second embodiments, the case where the cumulative addition result for all one period of the PN code is calculated as the correlation value has been described, but the present invention is not limited to this, and is not necessarily limited to this. It is not necessary to perform multiplication and addition processing for one period, and the controller 26 and 65 may use a cumulative addition result obtained by calculating only a predetermined number of upper bits in one period of the reception data D10 as a correlation value. good. Thereby, the calculation time until calculating the correlation value can be further shortened.
[0074]
Further, in the first and second embodiments described above, the phase information of the PN code corresponding to the correlation value when the correlation value exceeds a predetermined reference value by the controllers 26 and 65 as the phase detection means. Although the case where S11 is detected as being synchronized with the phase of the PN code used on the transmission side has been described, the present invention is not limited to this, and the phase information of the PN code corresponding to the maximum correlation value is transmitted. The phase may be detected as the phase of the PN code used on the side.
[0075]
Furthermore, in the second embodiment described above, the case where the PN code generator 63 generates and outputs the PN codes D21 to D24 whose phases are offset by one bit at the same time has been described. The PN codes D21 to D24 whose phases are offset by several bit intervals may be simultaneously generated and output by changing the setting of the offset amount by the delay elements 73 to 75.
[0076]
Furthermore, in the above-described embodiment, the case where the synchronization acquisition devices 13 and 60 of the present invention are applied to the reception device in the case of performing wireless communication using the antenna 11 and the high-frequency circuit 12 as reception means has been described. The present invention is not limited to this, and may be applied to a receiving device using wired communication instead of a receiving device using wireless communication.
[0077]
【The invention's effect】
As described above, according to the present invention, a plurality of components having different phases can be obtained by a simple configuration including one offset generator and a plurality of delay elements based on a code sequence having the same bit sequence pattern as the first pseudo-noise code. In addition to being able to generate a second pseudo-noise code, a plurality of second pseudo-noise codes and first pseudo-noise codes are assigned 1 at each timing obtained by time-dividing one chip in the first pseudo-noise code. Since it can be apparently calculated in parallel only by a set of multiplication means and addition means, a pseudo-noise code synchronization acquisition device capable of calculating a correlation value and acquiring synchronization in a short time with a simple configuration can be realized. .
[0078]
Further, according to the present invention, a plurality of second phases having different phases can be obtained by a simple configuration comprising one offset generator and a plurality of delay elements based on a code sequence having the same bit sequence pattern as the first pseudo-noise code. In addition to being able to generate a pseudo-noise code, a plurality of second pseudo-noise codes and first pseudo-noise codes are respectively connected in parallel at respective timings obtained by time-division within one chip of the first pseudo-noise code. Calculating, detecting a second pseudo-noise code synchronized with the phase of the first pseudo-noise code based on the signal level of the correlation value, and despreading the received data based on the second pseudo-noise code Therefore, it is possible to realize a receiving apparatus that can demodulate received data in a short time with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the overall configuration of a receiving apparatus according to the present invention.
FIG. 2 is a block diagram showing a configuration of a synchronization acquisition device according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a PN code generation unit in the first embodiment of the present invention.
FIG. 4 is a circuit diagram showing configurations of a PN code generator and an offset generator according to the first embodiment of the present invention.
FIG. 5 is a schematic diagram showing a data string of a PN code generator according to the first embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration of a synchronization acquisition device according to a second embodiment of the present invention.
FIG. 7 is a schematic diagram illustrating time division processing according to the second embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a PN code generation unit in the second embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of a conventional synchronization acquisition device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 13, 60 ... Synchronization acquisition device, 2, 21-24, 61 ... Multiplier, 3, 25, 63 ... PN code generation part 4, 26, 65 ... Controller, 5, 27-30, 62... Adder, 6, 31 to 34... Addition value holding circuit, 7, 35... Memory, 51... PN code generator, 52 to 55.

Claims (2)

A plurality of second pseudo noise codes having different phases from each other through one offset generator and a plurality of delay elements based on a code sequence having the same bit sequence pattern as the first pseudo noise code transmitted from the transmission side. Pseudo-noise code generating means for generating,
Selector means for selecting and outputting the plurality of second pseudo-noise codes at respective timings obtained by time-dividing one chip in the received first pseudo-noise code;
Multiplying means for sequentially multiplying the first pseudo-noise code and the plurality of second pseudo-noise codes supplied from the selector means bit by bit;
The multiplication results of the multiplication means are sequentially accumulated and added for each phase of the second pseudo noise code, and the cumulative addition results up to one cycle of the first pseudo noise code and the second pseudo noise code are obtained. Adding means for calculating each;
Storage means for storing a plurality of cumulative addition results as correlation values for each phase;
Detecting means for detecting a phase of the second pseudo noise code corresponding to a correlation value exceeding a predetermined reference value among the plurality of correlation values as a phase of the first pseudo noise code. A pseudo-noise code synchronization acquisition apparatus. Receiving means for receiving the transmission data spread by the first pseudo-noise code and obtaining the received data;
A plurality of second pseudo-noise codes having different phases from each other through one offset generator and a plurality of delay elements based on a code sequence having the same bit-sequence pattern as the first pseudo-noise code included in the received data Pseudo-noise code generating means for generating
Correlation calculating means for calculating the correlation values with the plurality of second pseudo noise codes in parallel at respective timings obtained by time-sharing within one chip of the first pseudo noise code;
Phase detection means for detecting a second pseudo noise code synchronized with the phase of the first pseudo noise code based on the signal level of the correlation value;
Demodulating means for demodulating the received data by despreading based on the second pseudo noise code detected by the phase detecting means.

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