JP3710066B2 - Electronic still video camera - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an electronic still video camera that performs A / D conversion on a still image signal captured by a CCD to form a digital video signal and records it on an external recording medium such as an IC memory card. The present invention relates to a digital electronic still video camera that performs signal processing.
[0002]
[Prior art]
An electronic still camera that records an analog image signal obtained by converting an object image into an electric image signal using a CCD or other electronic image sensor on a recording medium such as a video floppy instead of a conventional silver salt film camera Was developed. Thereafter, analog video signals from the image pickup device are once A / D converted into digital signals from the point that the image degradation after recording is remarkable and the diversion to other image systems such as computers is difficult. A digital still video camera (hereinafter abbreviated as DSC) that uses a digital signal as an external digital recording medium such as a memory card has been developed and partly put on the market.
[0003]
A configuration example of these conventional DSCs is shown in the block diagram of FIG. The video signal from the CCD 201 undergoes CDS and AGC processing, and pre-processing such as signal processing for generating RGB signals, luminance, and color difference signals is performed by the pre-processing unit 202, and then A / D conversion is performed by the A / D conversion unit 203. Then, the digital video data is temporarily stored in the image dedicated buffer memory unit 204 such as a frame memory. Thereafter, the image data is recorded on the IC memory card 206 after being compressed by an image compression processing unit 205 represented by, for example, the JPEG (Joint Photograghic Experts Group) method.
[0004]
Further, in order to control these sequences, a system control unit 210 is provided separately, and is composed of a CPU, a program memory (normal ROM), a work memory (normal RAM), and a parallel I / O. Further, the system control unit 210 may be constituted by a CPU, a ROM, a RAM, and an I / O integrated one-chip microcomputer. A good example of such a prior art is Japanese Patent Laid-Open No. 63-122392. In this specification (1), the CCD color image signal is stored in a built-in buffer for one frame for every other line of the CCD color filter array in the horizontal direction, and is recorded after being compressed in a removable memory pack. The featured DSC is written. Among these, a buffer memory for storing A / D converted image data is prepared separately from the system control unit 210, and after detecting the end of image data capture, the image data is read from the image data storage buffer memory. It is then highly efficient encoded by the image encoder and recorded in the memory pack.
[0005]
As described above, the electronic still video camera has a dedicated image memory unit, and additionally has a work memory for the control CPU and a memory for temporarily storing compressed / decompressed data. Here, as the dedicated memory for images, for example, a special-purpose size such as an NTSC field memory, or a general-purpose SRAM or DRAM is generally used. However, when using a special-purpose size such as NTSC, it is not suitable for handling a CCD image having a different number of pixels, and is generally expensive, so when using a general-purpose DRAM or SRAM. There are many. When a general-purpose DRAM or SRAM is used, the memory capacity is usually set every four times, such as 256 Kbytes, 1 Mbyte, 4 Mbyte, etc. Further, in the case of DRAM, a row address is set. And the column address setting are set in the form of 2 to the nth power, such as 256 × 256, 512 × 512, or 1024 × 1024. On the other hand, the image size in NTSC is not necessarily in the form of 2 n, such as 768 × 488 when a 4 fsc sampling clock is used. As shown in the image memory, the dedicated image memory unit has an unused memory area indicated by the perspective portions a) and b). Here, a) shows an example in which each line data is continuously recorded, and b) gives a new row address for each line on the assumption that the image memory is left.
[0006]
However, since the entire size of the image memory portion is large, the unused area portion on the image memory is large. For example, when recording the above-mentioned NTSC image as 8-bit data by A / D conversion, it is 1024 × 1024 ×. If an image memory unit composed of multiple DRAMs of 4 bits (4 Mbytes) is used, (1024-768) x (1024-488) = 137,216 bytes per component, approximately 400 Kbytes when 3 components such as RGB are used The general-purpose memory is wasted. Although this amount of memory is sufficient as a work area and program memory for the CPU, it cannot be used from the CPU because it is a dedicated image memory unit.
[0007]
On the other hand, there is a remarkable improvement in the performance of CPUs in recent years, and even at the time of filing of the present invention, there are some embedded RISC chips that achieve performance of 10 to 40 MIPS at a relatively low price. Under such circumstances, even for a process that could not be obtained with a hardware configuration in the past, it can be processed within a satisfactory time by using a CPU with high processing capability. Became. Therefore, it is no longer necessary to dedicate a memory control unit for image data by hardware control such as a color process and compression / decompression processing as in the prior art.
[0008]
[Problems to be solved by the invention]
In view of the drawbacks of the prior art, the present invention does not use a dedicated expensive memory as described above, and allocates more memory than necessary to the buffer memory unit without generating a non-use area. The purpose of the present invention is to provide an electronic still video camera in which an optimal buffer memory amount is set.
[0009]
[Means for Solving the Problems]
The object is stored in the image sensor, an A / D converter that converts the signal obtained by the image sensor into a digital signal, a memory unit that stores the digital signal, and a memory unit. In an electronic still video camera comprising: a signal processing means for performing signal processing on the digital signal; a recording medium for recording the digital signal processed by the signal processing means; and a CPU for performing system control. Including the signal processing means , performing signal processing by software, and storing an amount of memory for recording a digital signal obtained from the image sensor and an amount of working memory for performing the signal processing on the memory unit. A memory area setting means for setting, and a digital signal obtained by the image sensor according to the shooting mode setting of the camera; It is achieved by an electronic still video camera, characterized in that the changeable memory quota capturing.
[0010]
As its actual state, (a) DRAM, SRAM or multi-port RAM is used as the memory constituting the memory unit. (B) The signal processing performed by the CPU is luminance / color difference separation processing . (C) CPU The signal processing performed is a high-efficiency encoding process . (D) The memory unit includes a stack area necessary for the operation of the CPU . (E) The memory unit can be expanded from the outside. It is an aspect.
[0011]
[Action]
In order to solve the above-mentioned problems, the present invention uses a digital still video image memory, a CPU working memory, and a buffer memory as one memory for various purposes, and uses the image size of the input CCD output, the transfer speed of the output memory, This is solved by the CPU selectively setting each memory allocation amount according to the system configuration such as the capacity of the entire built-in memory.
[0012]
As a means for solving the problems, the present invention comprises a memory unit composed of at least one screen of an image to be photographed that can be transferred by a CCD digital data transfer unit of an A / D conversion unit, and the memory Is a digital still video camera that can be read and written from an image processing means to be processed into an image, and can also be used as a work area of the system control means, and each area setting is variable.
[0013]
The present invention differs from the prior art as follows.
[0014]
The difference from the above-mentioned specification (1) is that there is no description that the system control means such as a CPU can be used as the work area as described above, and the present invention further provides a dedicated hardware for compression and CCD signal processing. It is possible to find structural features even in the absence of wear.
[0015]
Another known example is JP-A-60-203091. What is described in this specification (2) is an image processing apparatus for an endoscope. Among them, it is described that the memory unit of the image processing apparatus is constituted by a plurality of memory planes in the gradation direction, and the memory planes are distributed according to the necessary information amount of each color. However, in this specification, there is no description that the system control means such as CPU can be used as the work area, and the main feature of the present invention is the distribution of the number of memory planes in the gradation direction. Rather, it is the setting of the allocated amount of bytes or words in the total amount of built-in memory.
[0016]
In addition to the above conventional techniques, an example of a general-purpose personal computer (PC) can also be given. For example, this is the case where image data captured by a video capture board is compressed by the CPU of the PC main body and recorded on a hard disk or a display memory. A good example of a video capture board is “Production of a color image input board for PC9801” described on pages 481 to 490 of the August 1989 issue of “Transistor Technology” published by CQ Publisher. This document provides a board in which a PC can handle this data by decomposing a video signal into RGB signals and inputting them into a PC. As is clear in this example, a dedicated SRAM is prepared in the video capture board, and image data is stored in the dedicated SRAM and then taken into the PC. There is also an example of a display memory that transfers image data to a video RAM mounted on a memory map of a PC and displays it on the display, but the peripheral memory composed of DRAM is not the same in terms of hardware, Since the memory is arranged on the video display board, which is hardware, the image data to be displayed in a state where it is mounted in the memory space of the PC is transferred to a region other than the set area to obtain a desired operation. Therefore, it can be said that this is also a dedicated memory for the display, and its purpose and contents are different from those of the present invention.
[0017]
【Example】
A block circuit diagram shown in FIG. 1 will be used as an example of the configuration of the present invention. Based on this block diagram, a signal flow until a digital still camera records a subject video on a recording medium such as a memory card will be described.
[0018]
Image information that has passed through the optical lens is converted into an electrical signal by the CCD 101. A signal output from the CCD 101 is first subjected to preprocessing processing 102 such as CDS or AGC, and then converted to a digital signal by an A / D converter 103. The digitized CCD signal is recorded in the memory block unit 105 by a timing signal generated by the memory control unit 104.
[0019]
Here, the memory fetch timing when the DRAM module is used as a basic component of the memory block unit 105 will be described. FIG. 2 shows the entire memory timing of the CCD image and FIG. 3 shows the detailed operation of the memory timing. A blank signal and a field index signal corresponding to the imaging unit are generated from the timing generator 106 shown in FIG. 1 as shown in FIG. 2 by the enable signal of the CPU 107 and input to the memory control unit 104.
[0020]
Here, the field index signal is used for encoding the memory address. The memory or CPU 107 obtains information such as the image size of the image pickup unit and the CCD filter array in advance via the internal register of the timing generator 106. When the CPU 107 outputs a shooting command to the timing generator 106 by the release operation of the photographer, the timing generator 106 issues a write frame signal synchronized with the frame signal to the memory controller 104 as shown in FIG. The memory control unit 104 creates a transfer request signal for the CPU 107 from the write frame signal and the blank signal in the memory control unit 104, creates a bus hold signal in combination with the memory refresh signal, and outputs it to the CPU 107. Upon receiving this bus hold, the CPU 107 ends the memory access (memory request) being processed, and then releases the CPU bus and outputs a bus hold acknowledge signal to the memory control unit 104. This signal delivery is shown in FIG. In this figure, a thing when a bus hold request is made during the memory access of the CPU 107 is shown. If a bus hold request occurs during the memory request of the CPU, the current memory request processing is completed and then a bus hold signal is accepted and a bus hold acknowledge is output. However, here the CPU 107 always releases the bus within a certain time. Not done.
[0021]
After generating the bus hold request signal, the memory control unit 104 generates the RAS and CAS signals of the DRAM according to the generation timing of the image data. At the same time, an enable signal of image data not shown is generated for the image bus 1 / F in FIG. When this signal is received, the image bus 1 / F converts the 8-bit A / D converted CCD signal data into 16 bits and delays the data by a predetermined number of clocks to sweep it out to the CPU bus in synchronization with the CAS timing. Here, 16 bits are used to match the CPU bus capacity and to increase the apparent operating speed of the DRAM. As shown in FIG. 3, high-speed page transfer is used for writing image data into the memory, but the row address is reset at the switching point of each page, that is, at the change point of the row address.
[0022]
Thereafter, when a series of CCD signal line data transfer ends, the memory control unit 104 returns a bus hold request signal, and in response to this, the CPU 107 returns a hold acknowledge signal. Thereafter, the CPU 107 obtains the right to use the CPU bus by itself.
[0023]
The CCD signal obtained in this way in the memory block unit 105 (hereinafter also referred to as a buffer memory) is taken into the CPU 107 and subjected to CCD signal processing by software. The CPU 107 performs appropriate signal processing to generate RGB signals and luminance / color difference signals, but the signal processing method differs depending on the color filter on the CCD 101. Here, an example of a complementary color checkered filter as shown in FIG. 4 that is generally used will be described.
[0024]
In the case of a complementary color filter, a luminance signal close to the spectral characteristic of the NTSC standard can be obtained for each field by the following calculation.
[0025]
Yn = (Mg + Cy) + (G + Ye) ≈2R + 3G + 2B
Yn + 1 = (G + Cy) + (Mg + Ye) ≈2R + 3G + 2B
The color difference signal is obtained by the following equation.
[0026]
Cn = (Mg + Cy) − (G + Ye) ≈2R−G≈B−Y
Cn + 1 = (G + Cy) − (Mg + Ye) ≈2R + G≈− (B−Y)
In this way, a signal close to the spectral characteristic of the color difference signal of the NTSC standard is obtained in a line sequential manner. However, since the color reproduction is not good as it is, actually the Y, RY, BY signals are once separated into RGB signals, subjected to white balance adjustment, and γ processing as shown in the process signal processing circuit of FIG. Then, Y, (R−Y), and (B−Y) signals are generated again. In order to make Y, RY, and BY from RGB, the following equations are used.
[0027]
Y = 0.30R + 0.59G + 0.11B
RY = 0.70R-0.59G-0.11B
BY = -0.30R + -0.59G + 0.89B
In FIG. 5, Y (YH) directly produced from the output of the CCD 101 and Y (YL) produced from the RGB signal are added together. This is because the ratio of YH containing a lot of high frequency components to the color components is high. This is because the Y signal with good color reproduction and high resolution can be obtained by adding the correct YL. These signals are now stored in a temporary buffer memory. Next, each signal thus obtained is compressed and encoded for recording on a recording medium such as a memory card. FIG. 6 shows a block diagram of compression encoding using DCT known in the JPEG system. The DCT operation is performed on the image data cut out from the buffer memory into 8 × 8 pixel blocks, and the converted coefficient values are quantized into integer values using a quantization table. Finally, Huffman coding is performed and recorded again in the buffer memory. The compression code is performed for each block of 8 × 8 pixels, but of course, it is performed for each signal of Y, RY, and BY for one screen. Finally, the data recorded in the buffer memory is recorded in a recording medium such as a memory card, and the photographing sequence is completed.
[0028]
FIG. 7 shows an operation at the time of a memory refresh request. The memory refresh request signal is generated internally by setting a refresh timer not described here in the memory control unit. The refresh request is generated in accordance with the request order by measuring signal arbitration with other memory control requests. FIG. 7 shows a case where a memory refresh request is generated during a CPU memory request and a bus hold request is generated accordingly. When a bus hold request occurs during the CPU memory request, the CPU 107 ends the current memory request processing and outputs a bus hold acknowledge with a bus hold signal. Upon receiving this bus hold acknowledge signal, the memory control unit 104 enters a refresh cycle, generates a refresh operation by CAS before RAS, and returns a bus hold request. Thereafter, the CPU returns a bus hold acknowledge signal to obtain the bus use right. The above is a rough flow of the image signal until the subject is recorded on the recording medium in the digital still camera.
[0029]
Next, FIG. 8 shows an example of use of the camera buffer memory for proceeding with these operations. In the initial state, only the temporary stack pointer base and work area of the CPU are determined, and the memory address point is reset according to various necessary memory amounts. First, the CPU first measures the amount of installed internal memory. The installation amount is measured by performing OOH write / read and FFH write / read at an arbitrary point for each expansion unit, but here it is performed at the head of the expansion unit. Thus, after detecting the amount of built-in memory, the CPU reads the pixel size and filter arrangement of the CCD image from the information set in the internal register in the timing generator 106 in FIG. 1, and stores the CCD image. The amount of work memory for calculating the amount and CCD process is calculated. Similarly, the CPU 107 checks the type of the IC memory card 109 via the IC memory card controller 108 of FIG. 1 and calculates the compressed code buffer amount after compression. For example, in the case of an SRAM card, the compressed code buffer amount is set to a relatively small value, and when a slow card such as a flash card or a hard disk or a Nimi disk is inserted, the set amount of the code buffer is increased. At the same time, the setting of the camera itself is also monitored. If the field setting is used, the CCD signal fetch memory allocation amount is set to the half of the frame. Set. Here, when the amount of built-in memory does not reach the required amount of memory for CPU processing, a memory shortage warning is issued to prompt the photographer to add memory.
[0030]
In FIG. 8, for the sake of explanation, the process proceeds in the frame single-shot mode. As described above, the CPU sets the base point of the image data and the vertical and horizontal sizes of the image to the memory control unit 104 in FIG. Further, the stack area may be moved as necessary. The memory control unit 104 takes in the CCD signal data as described above according to the base point and size of the image data. FIG. 8B shows a state in which the CCD signal data is captured. Here, for the sake of explanation, the base pointer for image capture is set at the head, but it can be set at an arbitrary place as described above.
[0031]
Thereafter, the CPU 107 performs the CCD signal processing as described above, and creates component data such as Y, (BY), (RY) from the pixel data of the complementary color CCD, for example. This state is shown in FIG. 8C. After Y, (B−Y), and (R−Y) data are created from the CCD data, they are destructively placed on the CCD image. Y data is overwritten. Thereafter, the compressed signal processing is performed, and the state is shown in FIG. 8D. Here, the compression code buffer is set separately for saving the original image data, but it is not necessary to save this when there is little memory or when it is not necessary to save the original image. The area may be overwritten.
[0032]
When a certain amount of compressed code, such as 512 bytes or 1024 bytes, has been accumulated as described above, the interval between processes can be determined by using the CPU's DMA (direct memory access) transfer function or the like in the IC memory card controller 108. Are transferred to the IC memory card 109 by a certain number of blocks.
[0033]
FIG. 9 is an external view of the DSC of the present invention. The expansion memory module 121 can be installed in the memory expansion unit 120 of the DSC main body 100. Further, the image pickup unit 131 is also detachable. For example, the NTSC is a product at the time of introduction, and in addition, it can be replaced with a product such as HDTV, PAL, VGA, SVGA. FIG. 10 shows an example of the camera display unit 140 provided in the DSC main body 100. In this example, the shutter speed, the aperture amount, the current number of shots, and the like are shown. Further, MEM indicates the current amount of built-in memory, and for example, the initial value of 1 Mbyte is displayed as 2, 3,... Further, “MODE” is the image size of the image pickup unit, N is NTSC, S is SVGA,.
[0034]
As an embodiment of the present invention, a DRAM configuration is taken as an example, but the present invention is not limited to this. For example, it can be easily analogized and implemented that an SRAM or a dual port memory with a serial port can be configured.
[0035]
【The invention's effect】
As an effect of the present invention, firstly, the built-in memory capacity can be reduced, and the price can be reduced and the apparatus can be downsized. A second advantage is that the image size and processing of the imaging system can be adaptively changed by adding memory. In other words, when an electronic still video camera is introduced, even if it is compatible only with the NTSC imaging system, there is an advantage that it will be introduced at a low price. Can be expanded. Further, by varying the amount of image code buffer such as compression according to the speed of the external recording medium and the amount of built-in memory, it is possible to perform processing efficiently without CPU wasteful waiting time.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the configuration of the present invention.
FIG. 2 is an overall sequence diagram of the timing for taking in a CCD image memory;
FIG. 3 is a transfer operation diagram of memory image data.
FIG. 4 shows an arrangement example of complementary color checkered filters.
FIG. 5 shows a block circuit diagram for performing process signal processing.
FIG. 6 is a block diagram of compression encoding.
FIG. 7 is an operation diagram at the time of a memory refresh request.
FIG. 8 shows an example of using a camera buffer memory.
FIG. 9 is an external view of a DSC according to the present invention.
FIG. 10 shows an example of a camera display unit.
FIG. 11 is a block diagram illustrating a configuration example of a conventional DSC.
FIG. 12 shows an example of use of a conventional image memory.
[Explanation of symbols]
100 DSC body
101 CCD
102 Preprocessing
103 A / D conversion
104 Memory controller
105 memory blocks
106 Timing generator
107 CPU
108 Memory card controller
109 IC memory card
121 Additional memory
131 Imaging unit
140 Camera display

Claims (6)

An image sensor, an A / D converter that A / D converts a signal obtained by the image sensor into a digital signal, a memory unit that stores the digital signal, and a digital signal stored in the memory unit In an electronic still video camera having signal processing means for performing signal processing, a recording medium for recording a digital signal processed by the signal processing means, and a CPU for performing system control,
The CPU includes the signal processing means, performs signal processing by software, and also stores an amount of memory for recording a digital signal obtained from the imaging device and an operation for performing the signal processing on the memory unit. An electronic still video camera comprising memory area setting means for setting a memory amount, wherein a memory allocation amount for taking in a digital signal obtained by the image sensor can be changed according to a shooting mode setting of the camera.   2. The electronic still video camera according to claim 1, wherein a DRAM, an SRAM, or a multi-port RAM is used as a memory constituting the memory unit.   3. The electronic still video camera according to claim 1, wherein the signal processing performed by the CPU is luminance / color difference separation processing.   The electronic still video camera according to claim 1, wherein the signal processing performed by the CPU is high-efficiency encoding processing.   The electronic still video camera according to claim 1, wherein the memory unit includes a stack area necessary for the operation of the CPU.   The electronic still video camera according to claim 1, wherein the memory unit can be expanded from outside.

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