JP3796911B2 - Solid-state image sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, in particular, an amplification type composed of a pixel MOS transistor having a function of accumulating signal charges obtained by photoelectric conversion under a gate and modulating a channel current in accordance with the accumulated signal charge amount. The present invention relates to a solid-state image sensor.
[0002]
[Prior art]
Solid-state imaging devices using MOS transistors or CCDs (Charged Couple Devices) are widely used in imaging devices. This utilizes charges accumulated by photoelectric conversion, and transfers charges in an array to output a planar image. Recently, a color type of 1/4 type and 380,000 pixels has been commercialized, and improvements are being made to small size, small imaging area, and multiple pixels.
[0003]
By the way, the smaller the imaging device and the larger the number of pixels, the smaller the light receiving area per unit pixel. Therefore, in order to perform noise-resistant imaging correctly, the sensitivity of the photoelectric conversion element per unit pixel is high. Will be required.
[0004]
As described above, the solid-state imaging device is required to be smaller and lighter. For this purpose, it is desired to further improve the sensitivity so that the sensitivity does not decrease even if the area of the light receiving portion is reduced.
[0005]
[Problems to be solved by the invention]
On the other hand, it has a function of performing photoelectric conversion by incident light, accumulating signal charges obtained by photoelectric conversion under the gate, and modulating a channel current (so-called source-drain current) according to the amount of accumulated signal charges. There has been proposed an amplification type solid-state imaging device in which a plurality of MOS transistors (hereinafter referred to as pixel MOS transistors) serving as unit pixels are arranged in a matrix, for example.
[0006]
FIG. 5A and FIG. 5B show an example of a pixel MOS transistor that constitutes a unit pixel of the amplification type solid-state imaging device constituted by a pixel MOS transistor having functions of photoelectric conversion, signal charge accumulation, and channel current modulation.
5A is a plan view, and FIG. 5B is a cross-sectional view in the gate length direction.
[0007]
The pixel MOS transistor 30 includes, for example, a gate insulating film 38 formed on the surface of the semiconductor substrate 36 in a region isolated by an element isolation region 37 by a selective oxide layer in a p-type semiconductor substrate 36. A gate electrode 32 having a rectangular planar shape of an effective gate is formed, and has a conductivity type opposite to that of the semiconductor substrate 36 formed by introducing impurities in the vicinity of the surface of the semiconductor substrate 36 on both sides of the gate electrode 32. For example, an n-type source region 31 and a drain region 33 are formed.
A sensor region 34 into which an impurity of the same conductivity type as that of the semiconductor substrate 36, for example, p-type is introduced, is formed at a position below the gate 32 between the source region 31 and the drain region 33. In the sensor region (light receiving unit) 34, signal charges photoelectrically converted by incident light transmitted through the gate electrode 32 are accumulated.
Further, an overflow barrier (OFB) region 35 is provided in the semiconductor substrate 36 below the source region 31, the drain region 33 and the sensor region 34, and this overflow barrier region 35 sweeps out the signal charge formed and accumulated in the sensor. For the reset operation, the source region 31 and the drain region 33 are formed of the same conductivity type, for example, an n-type region into which an n-type impurity is introduced.
[0008]
A plurality of the pixel MOS transistors 30 are arranged in a matrix, for example, to form an amplification type solid-state imaging device.
In the pixel MOS transistor 30, light passes through the gate electrode 32 and enters the sensor region 34 below the gate electrode 32, so that signal charges (holes in this example) are generated by photoelectric conversion and accumulated in the sensor region 34. The The signal charge modulates the potential of the surface channel of the pixel according to the amount of charge. For this reason, for example, when a driving pulse is applied to the gate electrode 32 through a vertical selection line (not shown) from the vertical shift register and the pixel MOS transistor 30 is turned on, the channel current between the source and drain is modulated. Thus, the source potential when the capacitive load operation or the source follower operation is performed is modulated, and this source potential modulation is read out as a signal. This signal is read out to the signal output line by sequentially driving the switch elements by, for example, horizontal drive pulses from a horizontal shift register (not shown).
[0009]
Incidentally, the pixel MOS transistor 30 having the above-described configuration has the following problems.
First, since the potential distribution in the sensor region 34 is relatively flat, the position where the signal charge is accumulated varies from pixel to pixel, which causes variations in characteristics.
[0010]
FIG. 6 shows the potential distribution of the pixel MOS transistor 30 configured as described above.
FIG. 6A is a diagram illustrating positions corresponding to effective gates.
FIG. 6B is a diagram showing a potential distribution in the effective gate width (corresponding to channel width) direction W.
FIG. 6C is a diagram showing a potential distribution in the effective gate length (corresponding to channel length) direction L. FIG.
[0011]
From FIG. 6C, the potential distribution in the length direction L of the gate 32 is such that the central portion O is deeply recessed and signal charges are easily accumulated in the central portion.
On the other hand, as shown in FIG. 6B, the potential change in the width direction W of the gate 32 is small, and the distribution is relatively flat. Since the potential distribution of the central portion ROS in the longitudinal direction of the gate 32 is relatively flat, when the accumulated signal charge is small, the position where the signal charge is accumulated is not concentrated near the point O, and the length direction It is accumulated at a non-constant position between ROs or OSs which are the central part of L.
[0012]
In this case, the position where the signal charge is accumulated varies from pixel to pixel, resulting in variations in characteristics from pixel to pixel.
[0013]
Further, since the position where the signal charge is accumulated (between ROS) is separated from the source region 31, the influence of the accumulated charge on the source potential at the time of reading is small and the sensitivity is lowered.
[0014]
In order to solve the above-described problems, the present invention provides a solid-state imaging device with good sensitivity and little variation in characteristics of each pixel by regulating the position where signal charges are accumulated.
[0015]
[Means for Solving the Problems]
In the solid-state imaging device of the present invention, a plurality of pixel MOS transistors having a function of accumulating signal charges obtained by photoelectric conversion and modulating a channel current according to the amount of accumulated signal charges are arranged. The gate width on the drain side is narrower than the gate width on the source side, and the signal charge accumulation position is biased toward the source side.
[0016]
According to the above-described configuration of the present invention, the gate width is narrower on the drain side than on the source side, so that a narrow channel effect is generated, the potential on the drain side of the gate becomes shallow, and the gate width direction is reduced. The gradient of the potential distribution becomes steep, and the signal charge is likely to be concentrated in the deepest part.
Furthermore, since the position where the signal charge is accumulated is biased toward the source side, the influence of the accumulated charge on the source potential can be increased.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, a plurality of pixel MOS transistors having a function of accumulating signal charges obtained by photoelectric conversion and modulating a channel current according to the amount of accumulated signal charges are arranged, and the gates of the pixel MOS transistors are arranged on the drain side. The solid-state imaging device is formed in a shape in which the gate width is narrower than the gate width on the source side, and the signal charge accumulation position is biased toward the source side.
[0018]
According to the present invention, in the solid-state imaging device, the gate has a trapezoidal shape with the drain side and the source side as bottoms.
[0019]
According to the present invention, in the solid-state imaging device, the edge of the gate other than the source side and the drain side in the shape of the gate is formed with a convex or concave curve.
[0020]
Hereinafter, a solid-state imaging device of the present invention will be described with reference to the drawings.
1 and 2 are schematic configuration diagrams of an embodiment of an amplification type solid-state imaging device according to the present invention, particularly a pixel MOS transistor constituting a unit pixel thereof. FIG. 1 is a plan view, and FIG. 2 is a sectional view in the length direction of the gate.
[0021]
The pixel MOS transistor 10 performs photoelectric conversion by incident light as described above, accumulates signal charges obtained by the conversion under the gate, and generates a channel current (so-called source−) according to the amount of accumulated signal charges. It is composed of a MOS transistor having a function of modulating (drain current).
[0022]
That is, the pixel MOS transistor 10 has a gate insulating film 8 formed on the surface of the semiconductor substrate 6 in a region isolated by, for example, a device isolation region 7 by a selective oxide layer in the p-type semiconductor substrate 6. The gate electrode 2 is formed, and near the surface of the semiconductor substrate 6 on both sides of the gate electrode 2, the source region 1 and the drain region 3 of n type conductivity opposite to the semiconductor substrate 6 formed by introducing impurities. Is formed. The gate electrode 2 is formed of a conductive material layer that can transmit light, for example, a thin polycrystalline silicon layer.
A sensor region (light receiving portion) 4 into which an impurity of the same conductivity type as that of the semiconductor substrate 6, for example, p-type is introduced, is formed at a position below the gate electrode 2 between the source region 1 and the drain region 3. In the sensor region (light receiving portion) 4, signal charges photoelectrically converted by incident light transmitted through the gate electrode 2 are accumulated.
Further, an overflow barrier (OFB) region 5 is provided in the semiconductor substrate 6 below the source region 1, the drain region 3, and the sensor region 4, and this overflow barrier region 5 sweeps out signal charges that have been formed and accumulated in the sensor. For the reset operation, the source region 1 and the drain region 3 are formed of the same conductivity type, for example, an n-type region into which an n-type impurity is introduced.
[0023]
In FIG. 2, the OFB region 5 is provided at a position corresponding to the active region formed inside the element isolation region 7 by the source region 1, the sensor region 4, and the drain region 3. May be formed under the element isolation region 7 or may be formed in common with other unit pixels.
[0024]
In this embodiment, the effective especially as the drain 3 of the gate 2 of the width (i.e. corresponding to the channel width) W _D is narrower than the width (i.e. corresponding to the channel width) W _S of the gate 2 of the source side 1 An effective gate 2 having a trapezoidal shape with the source 1 side and the drain 3 side as bottoms is formed.
[0025]
A plurality of the pixel MOS transistors 10 are arranged, for example, in a matrix form. Although not shown, for example, a signal line is connected to the source region 1 of the pixel MOS transistor 10 corresponding to each column, and a power source line is connected to the drain region 3. The vertical selection line from the vertical shift register is connected to the gate electrode 2 of the pixel MOS transistor 10 so as to be orthogonal to the signal line, and the signal line is switched on and off by the horizontal drive pulse from the horizontal shift register. An amplification type solid-state imaging device is configured by being connected to the signal output line via the device.
[0026]
In the pixel MOS transistor 10, light passes through the gate electrode 2 and enters the sensor region 4 below the gate electrode 2, thereby generating signal charges (holes in this case) due to photoelectric conversion, which are accumulated in the sensor region 4. The The signal charge modulates the potential of the surface channel of the pixel MOS transistor according to the amount of charge. For this reason, when a drive pulse from the vertical shift register is applied to the gate electrode 2 through the vertical selection line and the pixel MOS transistor 10 is turned on, the channel current between the source and drain is modulated. When the follower operation is performed, the source potential is modulated, and the horizontal shift register is sequentially operated using the source potential modulation as a signal to be read out to the signal output line.
[0027]
In the present embodiment, among the gate electrode 2, the effective gate 2 located on the sensor area 4, the gate width W _D of the drain 3 side is formed in a trapezoidal shape is narrower than the source 1 side As a result, a narrow channel effect is produced, and the potential on the drain 3 side in the sensor region 4 becomes shallow as will be described later.
Therefore, the accumulation position of the signal charge in the sensor region 4 can be brought closer to the source 1 side and to the center of the width of the gate electrode 2, the influence of the accumulated charge on the source potential can be strengthened, and a highly sensitive solid-state imaging device Can be obtained.
[0028]
FIG. 3 shows the potential distribution of the pixel MOS transistor 10 of the present embodiment.
FIG. 3A is a diagram showing a position corresponding to the effective gate 2. 3B shows an effective potential distribution in the direction W of the width of the gate 2 (corresponding to the channel width), and FIG. 3C shows an effective potential distribution in the direction L of the length of the gate 2 (corresponding to the channel length).
[0029]
From FIG. 3C, the potential distribution in the length direction L of the gate 2 shows that the potential at the point Q on the drain 3 side is shallower than the potential at the point P on the source 1 side. It is deeply recessed and signal charges are easily accumulated here.
3B, since the potential change in the width direction W of the gate 2 is larger than that in the example shown in FIG. 6B, the potential distribution of the deepest portion EFG in the length direction L of the gate 2 is relatively large and accumulated. Even when the signal charge is small, the position where the signal charge is accumulated concentrates near the point F and is accumulated at a constant position.
[0030]
As a result, the position where the signal charge is accumulated is substantially constant for each pixel, so that there is no variation in characteristics between pixels.
In addition, since there is no variation in characteristics among pixels, signal processing can be made common to a plurality of pixels or all pixels, and the configuration for signal processing can be simplified.
[0031]
In the amplification type solid-state imaging device configured by the pixel MOS transistor 10 described above, the potential of the sensor region 4 becomes shallower on the drain 3 side due to the narrow channel effect, so that the signal charge accumulation position can be brought closer to the source 1 side. As a result, the influence of the accumulated charge on the source potential can be strengthened, and a highly sensitive imaging device can be obtained.
In addition, since the potential also has a gradient in the gate width direction W due to the narrow channel effect, signal charges are collected in the central portion F in the gate width direction W, thereby aligning the charge storage position of each pixel, and the characteristics for each pixel. Can be suppressed.
Therefore, the problem of insufficient sensitivity can be solved for the sensor region of the pixel MOS transistor having a rectangular shape or a gate shape similar to that shown in FIG.
[0032]
As a result, even if the total charge amount under the gate 2 is the same, the influence of the signal charge on the source 1 becomes larger, and therefore the degree of modulation of the source potential accompanying the signal charge becomes larger. The effect of increasing the sensitivity is obtained that the output can be increased with the same amount of light.
[0033]
FIG. 4 shows another embodiment of the pixel MOS transistor according to the present invention.
In the pixel MOS transistor 20, the gate width W _D on the drain 3 side is narrower than the gate width W _S on the source 1 side, and an effective gate edge 2C other than the source 1 side and the drain 3 side is an element isolation region. 7 is formed with a convex curve.
In this pixel MOS transistor, the edge 2C of the gate is a convex curve, but the same effect can be obtained even if the edge 2C of the gate is a concave curve.
[0034]
As a result, as in the pixel MOS transistor 10 of the above-described embodiment, a narrow channel effect is generated, so that the accumulation position in the sensor region 4 can be brought closer to the source side and to the center of the gate width. It is possible to increase the influence of the charge on the source potential and obtain high sensitivity.
[0035]
Further, in each of the above-described embodiments, the edge of the gate electrode 2 on the source 1 side and the drain side 3 is a straight line, but the edge may be formed by a convex or concave curve.
[0036]
The solid-state imaging device of the present invention can be applied to imaging devices such as area sensors and line sensors.
[0037]
The solid-state imaging device of the present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.
[0038]
【The invention's effect】
According to the above-described present invention, the gate has a shape in which the width on the drain side is narrower than the width on the source side, whereby the potential on the drain side becomes shallow due to the narrow channel effect, and the signal charge accumulation position is biased toward the source side. As a result, the influence of the accumulated charge on the source potential can be strengthened, and the sensitivity of the solid-state imaging device can be improved.
[0039]
Also, by reducing the gate width on the drain side, the gradient of the potential distribution in the width direction of the gate increases, and the signal charge is more concentrated in the center in the width direction of the gate. No variation occurs in the distribution.
Therefore, variation in characteristics for each pixel can be suppressed.
[0040]
In addition, since there is no variation in characteristics among pixels, signal processing can be made common to a plurality of pixels or all pixels, and the configuration for signal processing can be simplified.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram (plan view) of a unit pixel according to an embodiment of a solid-state imaging device of the present invention.
FIG. 2 is a cross-sectional view in the length direction of the gate in FIG.
3 is a potential distribution diagram of the pixel MOS transistor of FIG. 1. FIG.
It is a figure which shows the position in A effective gate.
B is an effective potential distribution diagram in the width direction of the gate.
C is a potential distribution diagram in an effective gate length direction. FIG.
FIG. 4 is a schematic configuration diagram (plan view) of a unit pixel according to another embodiment of the solid-state imaging device of the present invention.
FIG. 5 is a plan view of a unit pixel of a solid-state imaging device composed of a pixel MOS transistor having a rectangular planar gate.
5B is a cross-sectional view in the length direction of the gate in FIG. 5A.
6 is a potential distribution diagram of the pixel MOS transistor of FIG. 5. FIG.
It is a figure which shows the position in A effective gate.
B is an effective potential distribution diagram in the width direction of the gate.
C is a potential distribution diagram in an effective gate length direction. FIG.
[Explanation of symbols]
1 source region, 2 gate electrode, 3 drain region, 4 sensor region (light receiving portion), 5 OFB (overflow barrier) region, 6 semiconductor substrate, 7 element isolation region, 8 gate insulating film, 10, 20, 30 pixel MOS transistor , 31 source region, 32 gate electrode, 33 drain region, 34 sensor region (light receiving part), 35 OFB (overflow barrier) region, 36 semiconductor substrate, 37 element isolation region, 38 gate insulating film, W gate width direction, L Gate length direction

Claims (3)

A plurality of pixel MOS transistors having a function of accumulating signal charges obtained by photoelectric conversion and modulating a channel current according to the amount of accumulated signal charges are arranged,
The gate of the pixel MOS transistor is formed in a shape in which the gate width on the drain side is narrower than the gate width on the source side,
The solid-state imaging device, wherein the signal charge accumulation position is biased toward the source side. 2. The solid-state imaging device according to claim 1, wherein the gate has a trapezoidal shape with the drain side and the source side as bottoms. 2. The solid-state imaging device according to claim 1, wherein an edge of the gate other than the source side and the drain side in the shape of the gate is formed by a convex or concave curve.

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