JP3793808B2 - Method for manufacturing field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a field effect transistor such as a metal oxide semiconductor (MOS) transistor or a metal insulator semiconductor (MIS) transistor, which is a basic element of an LSI (large scale integrated circuit).
[0002]
[Prior art]
Conventionally, as such a field effect transistor, for example, a double gate nMOS transistor as shown in a sectional view in FIG. 1 has been proposed. This field effect transistor includes a substrate 1, an insulating layer 2 provided thereon, a gate electrode 3 and a gate insulating film 4 provided thereon, and an insulation surrounding the gate electrode 3 and the gate insulating film 4. Provided on the film 5, the p-type region 6 provided on the gate insulating film 4, the N ^{+ -type} source 7 and the N ⁺ -type drain 8 provided on both sides of the p-type region 6, and the p-type region 6, respectively. The silicide portions 11, 12, 13 that are electrically connected to the gate insulating film 9 and the gate electrode 10, the N ^{+ -type} source 7, the gate electrode 10 and the N ⁺ -type drain 8, the silicide portions 11, 12, and the silicide And an insulating portion 14 between the portions 12 and 13. The silicide portions 11 and 13 constitute a source electrode and a drain electrode, respectively.
[0003]
In this case, the gate electrodes 3 and 10 are at the same potential, and by applying a positive voltage to the gate electrodes 3 and 10, the interface between the gate insulating film 4 and the p-type region 6 and the gate insulating film 9 and p. A channel is formed at the interface with the shaped region 6, and a drain current flows between the drain electrode 13 and the source electrode 11. The drain current that flows when the field effect transistor is turned on is referred to as the on-current.
[0004]
[Problems to be solved by the invention]
However, in the conventional field effect transistor, in order to obtain a desired on-current, it is necessary to set the width of the gate electrode to a predetermined value or more, or to form a plurality of gate electrodes on the same plane. The area occupied by the transistors increases, which hinders improvement in circuit integration density.
[0005]
Further, the parasitic capacitance between the gate electrode and the substrate increases as the width of the gate electrode increases. As a result, in the conventional field effect transistor in which the width of the gate electrode is set to a predetermined value or more, the parasitic capacitance increases, which causes an obstacle to speeding up the switching operation.
[0006]
Furthermore, it is necessary to increase the width of the drain electrode by forming a plurality of gate electrodes on the same plane, but the parasitic capacitance between the drain electrode and the substrate increases as the width of the drain electrode increases. . As a result, even in a conventional field effect transistor in which a plurality of gate electrodes are formed on the same plane, the parasitic capacitance increases, which causes an obstacle to speeding up the switching operation.
[0007]
An object of the present invention is to provide a method of manufacturing a field effect transistor capable of improving the integration density of a circuit and performing a switching operation at a high speed.
[0008]
[Means for Solving the Problems]
A method of manufacturing a field effect transistor according to the present invention includes:
Three or more stacked gate regions that are electrically connected to each other, and two or more gate insulating films that are interposed between these gate regions to form a channel, and have the same width. A first step of providing a single crystal silicon region on an insulating film provided on a semiconductor substrate;
A source region and a drain region, each of which is connected to both ends of the single crystal silicon region and is made of single crystal silicon, are provided on the insulating film, a source electrode connected to the source region, and a drain connected to the drain region A second step of providing an electrode and a gate electrode provided on the uppermost layer of the gate region,
The first step includes
A step of epitaxially growing Si and SiGe so as to be alternately stacked;
And a step of selectively removing SiGe using an etching solution having a higher SiGe etching rate than Si .
[0009]
According to the field effect transistor manufactured according to the present invention , the gate region and the semiconductor region are on the same cross section by three or more gate regions parallel to each other and two or more semiconductor regions interposed between the gate regions. They are alternately formed in the vertical direction. The number of semiconductor regions is one less than the number of gate regions, and the semiconductor region becomes a p-type region when the field effect transistor is an nMOS transistor, and becomes an n-type region when the field effect transistor is a pMOS transistor.
[0010]
As a result, four or more channels are formed in the vertical direction, and the on-current per unit gate width (1 μm) is larger than that of a conventional field effect transistor having two channels at the maximum. As a result, it is not necessary to set the width of the gate electrode to a predetermined value or more or to form a plurality of gate electrodes on the same plane in order to obtain a desired on-current, thereby increasing the area occupied by the field effect transistor. This eliminates the necessity and improves the integration density of the circuit.
[0011]
Further, since the parasitic capacitance is not increased due to the increase in the width of the gate electrode or the drain electrode, the switching operation can be performed at high speed.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a field effect transistor and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. Note that the drawings are not exactly as shown in the drawings, and some of the drawings are exaggerated.
FIG. 2 is a perspective view of a field effect transistor according to the present invention. The field effect transistor as an nMOS transistor shown in FIG. 2 includes a silicon substrate 20, a buried SiO ₂ layer 21 formed thereon, insulating layers 22 and 23 formed thereon, a source portion 24, a gate portion 25, and And a drain part 26. The source part 24, the gate part 25, and the drain part 26 are each silicided on the n ⁺ polycrystalline Si surface.
[0013]
3A is a diagram showing a cross section taken along line II ′ of FIG. 2, and FIG. 3B is a diagram showing a cross section taken along line II-II ′ of FIG. In FIG. 3B, four gate electrodes 31, 32, 33, 34 having the same potential parallel to each other are electrically connected to each other in the gate portion 25, and the four gate electrodes 31, 32, 33, 34 are connected to each other. Three p-type regions 35, 36, and 37 are interposed therebetween, and gate oxide films 38, 39, and 40 are formed in the p-type regions 35, 36, and 37, respectively. Further, as will be described later, N ^{+ -type} sources 35a, 36a, and 37a and N ⁺ -type drains 35b, 36b, and 37b are arranged on both sides of the p-type regions 35, 36, and 37, respectively. .
[0014]
The source part 24 and the drain part 26 have a source electrode 41 and a drain electrode 42 that connect six channels formed at the interface between the p-type regions 35, 36, and 37 and the insulating layers 38, 39, and 40, respectively.
[0015]
The operation of this embodiment will be described.
When a positive voltage is applied to the gate electrodes 31, 32, 33, 34, the six channels are formed, and a drain current flows between the drain part 26 and the source part 24 through these channels. Thereby, the on-current of the field effect transistor is obtained as the sum of the currents flowing through these six channels.
[0016]
Compared with the conventional field effect transistor as shown in FIG. 1, when the width of the planar gate electrode is the same, the drain current is, for example, about 2 to 3 times, which is necessary as an on-current. In order to obtain the drain current, it is not necessary to set the width of the gate electrode to a predetermined value or more or to form a plurality of gate electrodes on the same plane, so it is not necessary to increase the occupied area of the field effect transistor, and the circuit The integration density can be improved.
[0017]
In addition, since there is no increase in parasitic capacitance due to an increase in the width of the gate electrode or the drain electrode, the switching operation can be performed at high speed. In this case, the parasitic capacitance is, for example, about 1 / 2-1 / 3 as compared with the conventional field effect transistor as shown in FIG.
[0018]
FIG. 4 is a cross-sectional view of another field effect transistor according to the present invention. This cross section is a cross section corresponding to the II-II ′ cross section of FIG. 2, and the gate electrodes 41, 42, 43, 44 are electrically connected only on one side in the cross section. Thereby, the parasitic capacitance between the gate electrodes 41, 42, 43, 44 and the substrate 45 is further reduced.
[0019]
Next, a method for manufacturing the field effect transistor shown in FIG. 2 will be described. As will be described later, a part of the manufacturing process is performed using a CVD (chemical vapor deposition) apparatus shown in FIG. 5 also shows a wafer 46 on which CVD described later is performed.
[0020]
In describing the manufacturing process with reference to FIG. 6-17, FIGS. 6, 7, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A correspond to the II ′ cross section of FIG. 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, and 17B correspond to the II-II ′ cross section of FIG.
[0021]
First, an SOI (silicon on insulator) having a buried SiO ₂ layer 52 formed on a silicon substrate 51 and an ultrathin Si single crystal layer 53 formed on the buried SiO ₂ layer 52 is prepared (FIG. 6). . The ultrathin Si single crystal layer 53 is, for example, 10 nm.
[0022]
Next, the SiGe layer 55, the Si layer 56, the SiGe layer 57, the Si layer 58, the SiGe layer 59, and the Si layer 60 are epitaxially grown so as to be alternately stacked (FIG. 7). The thickness of each of these SiGe layer 55, Si layer 56, SiGe layer 57, Si layer 58, SiGe layer 59 and Si layer 60 is set to 30-50 nm, for example.
[0023]
For example, in forming a SiGe layer of 18% Ge, the growth rate is 70 × under conditions of Ge ₂ H ₂ (germane) 0.2 Pa, SiH ₄ (silane) 6 Pa, H ₂ (hydrogen) 30 Pa, and a temperature of 550 ° C. 10 ⁻¹⁰ m / min. Therefore, the formation time of the 35 nm thick SiGe layer is 5 minutes.
[0024]
In forming the Si layer, the growth rate is 10 × 10 ⁻¹⁰ m / min under the conditions of SiH ₄ (silane) 6 Pa, H ₂ (hydrogen) 30 Pa, and temperature 550 ° C. Therefore, the formation time of the 35 nm thick Si layer is 35 minutes.
[0025]
Next, the SiGe layer 55, the Si layer 56, the SiGe layer 57, the Si layer 58, the SiGe layer 59, and the Si layer 60 are processed by RIE (reactive ion etching) to partially remove them (FIG. 8). At this time, an ultrathin SiO ₂ film 61 and a Si ₃ N ₄ film 62 are sequentially formed, and used together with the resist as a mask during RIE.
[0026]
Next, the wafer shown in FIG. 8 is accommodated in the furnace 63 shown in FIG. 5, and a SiO ₂ film 64 is deposited to a thickness of about 500 nm using a CVD method, and then the SiO ₂ film 64 is planarized using a CMP technique ( FIG. 9).
[0027]
Next, after removing the Si ₃ N ₄ film 62 by etching with a hot phosphoric acid solution, a resist pattern is formed using a lithography technique, and wet etching (dilute hydrofluoric acid or the like) is performed using the formed resist pattern as a mask. The SiO ₂ film 64 is partially removed, and the SiO ₂ film 64 is separated from the side surfaces of the SiGe layer 55, the Si layer 56, the SiGe layer 57, the Si layer 58, the SiGe layer 59, and the Si layer 60 (FIG. 10). ). Note that RIE may be performed together with wet etching.
[0028]
Next, for example, anisotropic etching using an etchant in which the etching rate of SiGe such as HNO ₃ : H ₂ O: HF = 60: 60: 1 is remarkably faster than Si is performed, and the SiGe layers 55, 57, 59 is removed. At this time, the Si layers 53, 56, 58 and 60 are hardly etched.
[0029]
Next, SiO ₂ films are formed on the Si layers 53, 56, 58 and 60 by thermal oxidation. At this time, a SiO ₂ film having a thickness of 20 nm is formed by wet O _{2 at} 700 ° C., for example. At this time, the Si layer 53 is completely oxidized. Thereafter, the formed SiO ₂ film having a thickness of 20 nm is removed with a diluted hydrofluoric acid etching solution (FIG. 11).
[0030]
Next, thermal oxidation is performed to form SiO ₂ films 61, 62, and 63 as gate insulating films. For example, the SiO ₂ films 61, 62, 63 have the same thickness of about 1-15 nm (FIG. 12). As the gate insulating film, in addition to SiO ₂ , a SiON film or a silicon nitride film by plasma nitridation or the like may be used.
[0031]
Next, the wafer shown in FIG. 12 is accommodated in the furnace 63 shown in FIG. 5, phosphorus-doped amorphous Si 64 is deposited using the CVD method, and then the Si film 64 is planarized using the CMP technique (FIG. 13). . The amount of phosphorus added is, for example, 1 × 10 ²⁰ cm ⁻³ or more.
[0032]
Next, a silicon nitride film 65 is formed with a thickness of, for example, about 10 to 100 nm by ECR sputtering, CVD, or the like. Thereafter, a resist pattern corresponding to the gate portion 25 in FIG. 2 is formed by using a lithography technique. Thereafter, the silicon nitride film 65, phosphorus-added amorphous Si 64, Si layers 56, 58, and 60 and thin SiO ₂ films 61, 62, and 63 are processed by RIE using this resist pattern as a mask (FIG. 14).
[0033]
Next, thermal oxidation is performed. At this time, since the oxidation rate of the phosphorus-added amorphous Si 64 is remarkably faster than the oxidation rate of the Si layers 56, 58 and 60, the SiO ₂ film 66-73 formed on the surface of the phosphorus-added amorphous Si 64 has the Si layer 56, 73. It is thicker than the SiO ₂ film formed on 58 and 60. Thereafter, the SiO ₂ film formed on the Si layers 56, 58 and 60 is removed by plasma etching (FIG. 15). Thereafter, if necessary, phosphorus is ion-implanted from an oblique direction, annealing is performed, and the implanted ions are activated. For example, a dose of 2 × 10 ¹⁵ cm ⁻² phosphorus is ion-implanted at 30 keV.
[0034]
Next, phosphorus-doped amorphous Si is deposited and planarized by CMP. The amount of phosphorus added is, for example, 1 × 10 ²⁰ cm ⁻³ or more. Thereafter, the silicon nitride film 65 is removed with hot phosphoric acid or the like. Next, a resist pattern corresponding to the source part 24, the gate part 25, and the drain part 26 in FIG. 2 is formed using a lithography technique. Thereafter, phosphorus-doped amorphous Si is processed by RIE using this resist pattern as a mask. Then, by using the CVD method, SiO ₂ film is formed corresponding to the SiO ₂ film 23 of FIG. 2, then planarized by CMP. Thereafter, a heat treatment to diffuse phosphorus in the Si layer 56, 58, 60, to form the ^{N +} -type source 74, 75, 76 and ^{N +} forms a drain 77, 78, 79 (FIG. 16). Up to this stage, the phosphorus-added amorphous Si becomes polycrystalline silicon.
[0035]
Next, a silicide part 80 constituting a part of the source electrode of the field effect transistor shown in FIG. 2, a silicide part 81 electrically connected to the gate electrode, and a silicide part 82 constituting a part of the drain electrode are converted into a conventional method. Thus, the field effect transistor shown in FIG. 2 is completed.
[0036]
Next, another method for manufacturing the field effect transistor shown in FIG. 2 will be described. In this case as well, part of the manufacturing process is performed using a CVD (chemical vapor deposition) apparatus shown in FIG.
[0037]
In describing the manufacturing process with reference to FIGS. 18-22, FIGS. 18, 19A, 20A, 21A, and 22A correspond to the II ′ cross section of FIG. 2, and FIGS. 19B, 20B, 21B, and 22B correspond to FIG. This corresponds to the II-II ′ cross section.
[0038]
First, two SOI substrates are wafer bonded, and only the silicon substrate of one SOI substrate is removed by etching or the like. Thereafter, another SOI substrate is wafer-bonded to a substrate in which _two ultra-thin Si layers are alternately laminated with embedded SiO ₂ layers, and the silicon substrate of the other SOI substrate is removed. As a result, a substrate is formed in which ultrathin Si layers 91, 92, 93 are alternately laminated with SiO ₂ layers 94, 95, 96 (FIG. 18).
[0039]
Next, after the Si ₃ N ₄ film 98 is further formed after the formation of the thin SiO ₂ film 97, a part of the ultra-thin Si layers 91, 92, 93 and the SiO ₂ layers 94, 95, 96 are formed by lithography and RIE. It is removed (FIG. 19).
[0040]
Next, the wafer shown in FIG. 19 is accommodated in the furnace 63 shown in FIG. 5, and a SiO ₂ layer 99 is deposited using a CVD method, and then the SiO ₂ film 99 is polished and planarized using a CMP technique. (FIG. 20).
[0041]
Next, a part of the SiO ₂ film 99 is removed by using a lithography technique and RIE, and the SiO ₂ film 99 is converted into ultra-thin Si layers 91, 92, 93, SiO ₂ layers 95, 96, and an Si ₃ N ₄ film. It separates from the side surface of 98 (FIG. 21).
[0042]
Next, the SiO ₂ layers 95 and 96 and a part of the SiO ₂ layer 94 below the ultra-thin Si layer 91 are etched using an etchant such as dilute hydrofluoric acid. Thereafter, the Si ₃ N ₄ film 98 is etched with hot phosphoric acid or the like (FIG. 22).
[0043]
The subsequent steps are the same as the steps after the step of forming the SiO ₂ film on the Si layers 53, 56, 58, 60 by the thermal oxidation, but the SiO ₂ films 61, 62, 63 are formed as the gate oxide films. Thermal oxidation to completely oxidize the Si layer 53 before performing is not essential, and even if thermal oxidation is performed, it may be thin.
[0044]
The present invention is not limited to the above-described embodiment, and many changes and modifications can be made.
For example, in the above embodiment, the case of an nMOS transistor has been described. However, the present invention can also be applied to a case of a pMOS transistor or other types of transistors such as a MIS transistor.
[0045]
In addition, a field effect transistor having a structure other than the structure shown in FIGS. 2, 3 and 4 can be formed. For example, the number of gate electrodes can be any number of three or more, and two or more semiconductor regions, that is, the gate electrode can be formed. The number can be one less than the number.
[0046]
Furthermore, a manufacturing method other than the manufacturing method of the field effect transistor described in the above embodiment can be used. For example, in the process of obtaining the wafer shown in FIG. 10, the SiGe layer 55, the Si layer 56, the SiGe layer 57, the Si A part of one side of the layer 58, the SiGe layer 59, and the Si layer 60 is removed by etching, whereby the field effect transistor having the structure shown in FIG. 4 can be manufactured. Further, in the process of obtaining the wafer shown in FIG. 21, a part of one side of the ultrathin Si layers 91, 92, 93, the SiO ₂ layers 95, 96 and the Si ₃ N ₄ film 98 is removed by etching. A field effect transistor having the structure shown in FIG. 4 can be manufactured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a conventional field effect transistor.
FIG. 2 is a perspective view of a field effect transistor according to the present invention.
3 is a cross-sectional view of the field effect transistor of FIG.
FIG. 4 is a cross-sectional view of another field effect transistor according to the present invention.
FIG. 5 is a view showing a CVD apparatus used in the method of manufacturing a field effect transistor according to the present invention.
FIG. 6 is a diagram showing a first step of a method for manufacturing a field effect transistor according to the present invention.
FIG. 7 is a diagram showing a second step of the method of manufacturing a field effect transistor according to the present invention.
FIG. 8 is a diagram showing a third step in the method of manufacturing a field effect transistor according to the present invention.
FIG. 9 is a diagram showing a fourth step in the method of manufacturing a field effect transistor according to the present invention.
FIG. 10 is a diagram showing a fifth step in the method of manufacturing a field effect transistor according to the present invention.
FIG. 11 is a diagram showing a sixth step of the method of manufacturing a field effect transistor according to the present invention.
FIG. 12 is a diagram showing a seventh step of the method of manufacturing a field effect transistor according to the present invention.
FIG. 13 is a diagram showing an eighth step of the method of manufacturing a field effect transistor according to the present invention.
FIG. 14 is a diagram showing a ninth step of the method of manufacturing a field effect transistor according to the present invention.
FIG. 15 is a diagram showing a tenth step of the method of manufacturing a field effect transistor according to the present invention.
FIG. 16 is a diagram showing an eleventh step of the method for manufacturing a field effect transistor according to the present invention.
FIG. 17 is a drawing showing a twelfth step of the method of manufacturing a field effect transistor according to the present invention.
FIG. 18 is a diagram showing a first step in another method of manufacturing a field effect transistor according to the present invention.
FIG. 19 is a diagram showing a second step of another method of manufacturing a field effect transistor according to the present invention.
FIG. 20 is a diagram showing a third step in another method of manufacturing a field effect transistor according to the present invention.
FIG. 21 is a diagram showing a fourth step in another method of manufacturing the field effect transistor according to the present invention.
FIG. 22 is a diagram showing a fifth step of another method of manufacturing a field effect transistor according to the present invention.

Claims (1)

Three or more stacked gate regions that are electrically connected to each other, and a gate insulating film interposed between these gate regions to form a channel, and two or more gates having the same width. A first step of providing a single crystal silicon region on an insulating film provided on a semiconductor substrate;
A source region and a drain region, each of which is connected to both ends of the single crystal silicon region and is made of single crystal silicon, are provided on the insulating film, a source electrode connected to the source region, and a drain connected to the drain region A second step of providing an electrode and a gate electrode provided on the uppermost layer of the gate region,
The first step includes
A step of epitaxially growing Si and SiGe alternately stacked;
And a step of selectively removing SiGe using an etchant having a higher etching rate of SiGe than that of Si.

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