JP3782119B2 - Semiconductor memory device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a dynamic semiconductor memory device (DRAM) in which a memory cell is constituted by one MOS transistor and one capacitor.
[0002]
[Prior art]
In recent years, there has been a remarkable increase in DRAM integration. Various so-called stacked capacitor cells in which capacitors are stacked on transistors as memory cell structures have been proposed for further high integration of DRAMs. This type of memory cell is attracting attention because it can take a large capacitor area and can be formed without digging a groove in the substrate like a trench type, and therefore, process inspection at the time of manufacture is easy.
FIG. 10 shows a cross-sectional view of a conventional stacked DRAM memory cell.
[0003]
In the figure, 104₁, 104₂Is a word line (gate electrode), and has a structure in which a capacitor protrudes thereon. The capacitor is formed on the Si substrate 101 separated by the field insulating film 102, and includes a plate electrode 110, a capacitor insulating film 109, and a capacitor base electrode layer (storage electrode) 107, and is opened in the interlayer insulating film 106. N through contact holes⁺ It is connected to the mold diffusion layer 108.
[0004]
On the other hand, the MOS transistor has a gate insulating film 103 and a gate electrode 104.₁, 104₂, N^- Mold diffusion layer 105, n⁺ It is configured as a mold diffusion layer 108 and adopts an LDD structure. Then, the bit line 112 is n through the contact hole opened in the interlayer insulating films 106 and 111.⁺ It is connected to the mold diffusion layer 113.
However, the conventional stack type memory cell configured as described above has the following problems.
[0005]
First of all, when the integration is advanced, for example, when the integration degree is about 256M bits, the storage electrode (Cs) is increased to increase the height of the storage electrode or to be cylindrical. Ingenuity is required. When such a method is used, the final depth of the contact hole is about 2 μm. For example, the contact ratio of 0.3 μm diameter has an aspect ratio of 6 or more. As a result, contact holes having various aspect ratios from deep to shallow depths are mixed, resulting in a problem that the manufacturing yield is remarkably lowered.
[0006]
Second, n on the Si substrate side⁺ Since the type diffusion layers 113 and 108 exist, these n⁺ There is a problem that junction leakage exists between the mold diffusion layers 113 and 108 and the Si substrate 101, and it is difficult to improve the pause characteristics of the DRAM.
[0007]
Third, due to miniaturization, various contacts have become unable to afford to align with each electrode, and some self-alignment method has been used. However, there is a problem that the manufacturing yield is very complicated and the manufacturing yield is lowered.
[0008]
Fourth, in order to increase the area of the capacitor electrode, it is desirable to form the capacitor electrode on the bit line 112, but the word line 104₁, 104₂It is difficult to make contact with the diffusion layer in a self-aligning manner with both the bit line 112 and the bit line 112, which is difficult to realize.
[0009]
[Problems to be solved by the invention]
As described above, in order to further increase the integration density of the stack type DRAM having the conventional structure, firstly, a very deep contact hole and a shallow contact hole are mixed, so that the manufacturing yield is remarkably lowered. Junction leakage cannot be reduced because the diffusion layer of the concentration penetrates deeply. Third, the self-alignment technology to the gate electrode and the bit line electrode is complicated and the manufacturing yield is lowered. Fourth, the word line and the bit line are applied to both electrodes. There was a problem that it was difficult to self-align.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device that can be easily highly integrated.
[0010]
[Means for Solving the Problems]
  In order to achieve the above object, a semiconductor memory device of the present invention includes a first MOS transistor formed on a semiconductor substrate and having a first impurity diffusion layer and a second impurity diffusion layer, and the semiconductor substrate. Provided on each of the first impurity diffusion layer and the second impurity diffusion layer of the first MOS transistor.The spacer layer of the gate electrode of the first MOS transistor is exposed at the lower part of the side surface and is exposed to the spacer layer.An interlayer insulating film having a contact hole formed in a self-aligned manner;SaidOn the first impurity diffusion layerSaidProvided in interlayer insulation filmSaidContact holeOf the lower side of the exposed portion of the spacer layerFillingAnd in contact with the first impurity diffusion layerFirst conductive filmAs semiconductor layerWhen,SaidOn the first impurity diffusion layerSaidProvided in interlayer insulation filmSaidSo as to fill the contact holeSaidFormed on the first conductive film;SaidFormed higher than the gate electrode of the first MOS transistor.A second conductive film,Extending outside the upper opening surface of the contact holeAnd the height at the edge of the upper opening surface is the same as the interlayer insulating filmA second conductive film;SaidFormed on the second conductive film;SaidAnd a capacitor electrically connected to the first impurity diffusion layer.
[0011]
[Action]
In the semiconductor memory device of the present invention, an epitaxial layer having an impurity concentration higher than that of the first impurity diffusion layer and the second impurity diffusion layer is provided on the first impurity diffusion layer and the second impurity diffusion layer. It has been. As a result, junction leakage can be reduced, the short channel effect of the transistor can be suppressed, and reliability can be improved. Further, by attaching a silicide layer to the surface of the epitaxial layer, metal contact Schottky contact can be prevented, and ohmic contact can be realized. In addition, the contact margin can be increased by extending the epitaxial layer on the field.
[0012]
In the semiconductor memory device of the present invention, the filling layer is formed in the same process as the wiring layer. In other words, by using the wiring layer as the filling layer, the deep contact hole in the peripheral circuit region brought about by the stacked memory cell becomes shallower by the filling layer. For this reason, when the contact is made later, the contact hole has the same depth, and at the same time, the base material is prepared, so that a high yield contact can be realized.
[0013]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0014]
FIG. 1 is a diagram showing a schematic configuration of a memory cell of a stacked DRAM according to an embodiment of the present invention. FIG. 1 (a) is a plan view and FIG. 1 (b) is a diagram of the memory cell of FIG. It is AA 'sectional drawing. 2A and 2B are a BB ′ sectional view and a CC ′ sectional view, respectively, of the memory cell of FIG. 1A. FIG. 3 is a diagram showing a schematic configuration of the peripheral circuit of the stacked DRAM. FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line AA ′ of the peripheral circuit of FIG. FIG.
In the stack type DRAM of this embodiment, the Al wiring layer 29 is used as the shunt layer of the word line 4, and the following four points are different from the conventional one of FIG.
[0015]
First, the first difference is that there is n on the Si substrate side connected to the bit line layer 14.^- Type or p^- Type impurity diffusion layers 7 and 7a (first impurity diffusion layers) having a low impurity concentration are formed, and these impurity diffusion layers 7 and 7a are n⁺ Type or p⁺ A high impurity concentration epitaxial Si layer 9 is lifted above the Si substrate 1 and a silicide layer 10 is formed on the surface of the epitaxial Si layer 9. As a result, junction leakage can be reduced, the short channel effect of the transistor can be suppressed, and reliability can be improved. The silicide contact 10 prevents the Schottky contact of the metal contact, and realizes ohmic contact to the high impurity concentration n-type and p-type diffusion layers. Further, since the silicide layer 10 is formed on the surface of the epitaxial Si layer 9, it is possible to prevent the silicide layer 10 from entering the Si substrate 1 non-uniformly in the subsequent thermal process or the like, thereby breaking the junction. Yield can be improved.
[0016]
The second difference is that the Al wiring layer 29 of the peripheral circuit is not in direct contact with the low-concentration diffusion layer 7a, and the lower bit line 14 in the memory cell region is not contacted.₁, Upper bit line layer 14₂These lower bit lines 14 are formed in the same process as₁, Upper bit line layer 14₂A packed bed 14 made of the same material as_1a, 14_2aIt is in contact through. Therefore, a deep contact hole in the peripheral circuit region provided by the stacked memory cell is formed in the filling layer 14._1a, 14_2aAs a result, the contact hole becomes shallower. For this reason, when the contact is made later, the depth of the contact hole is reduced and the base material is also prepared, so that a contact with a high yield can be realized.
[0017]
The third difference is that the self-aligned contact to the gate electrode 4 or the bit line 14 is made of Si provided on the surface or side surface of each electrode._ThreeN_FourThis is done by using only the gate cap layer 5 or the bit line cap layer 15 and the spacer layer 8 made of a film as a stopper layer.
[0018]
The fourth difference is that the capacitor electrode portion (polycrystalline Si films 20, 22 and plate electrode 24) is low in concentration through the epitaxial Si layer 9 and the plug layer 12 (conductive layer) formed on the silicide layer 10. This is in contact with the impurity diffusion layer 7 ′ (second impurity diffusion layer).
[0019]
That is, the low-concentration impurity diffusion layer 7 ′ is effectively lifted to a position above the gate electrode 4. For this reason, in the stack type memory cell by the plug layer 12 in which the bit line is formed before the storage electrode, it is sufficient to perform self-alignment only to the bit line when forming the capacitor electrode contact in a later step. Can be greatly simplified, and the manufacturing yield can be remarkably improved.
Next, a method of manufacturing a DRAM having such characteristics will be described with reference to FIGS.
[0020]
First, as shown in FIGS. 4A and 4B (corresponding to the plan view of FIG. 1A and the cross-sectional view of FIG. 1B, respectively, the same applies to FIGS. 10¹⁵cm^-3A p-well is formed in the n-channel transistor region and an n-well is formed in the p-channel transistor region on the (100) plane of the p-type or n-type Si substrate 1. Next, for example, a trench is formed in the Si substrate 1 using reactive ion etching (RIE), and the insulating film 2 is buried, so-called trench isolation or Si_ThreeN_FourThe field insulating film 2 is formed by a so-called LOCOS method using a film. Here, the channel stopper layer is not shown, but is formed if necessary.
[0021]
Next, after exposing the surface of the Si substrate 1 in the element formation region, a gate oxide film 3 having a thickness of about 10 nm is formed, and a gate electrode 4 is formed on the gate oxide film 3. The gate electrode 4 employs a so-called polycide structure in order to reduce the resistance, but it may be a simple polycrystalline Si layer only. The lower layer of the gate electrode 4 is a polycrystalline Si layer 4 doped with impurities such as phosphorus having a thickness of about 100 nm.₁The upper layer is tungsten silicide (WSi) having a thickness of about 150 nm.₂) Layer 4₂It is.
[0022]
Then this WSi₂Layer 4₂On top of this, a Si nitride film (Si_ThreeN_Four), A resist pattern (not shown) is formed on the gate gap layer 5, and then the gate gap layer 5 and the silicide layer 4 are formed using the resist pattern as a mask.₂Polycrystalline Si layer 4₁Is continuously processed. Next, in order to improve the breakdown voltage between the gate electrode 4 and the low-concentration impurity diffusion layer 7, for example, 800 ° C., O 2₂A so-called post oxide film 6 is formed by performing thermal oxidation in an atmosphere for about 30 minutes.
[0023]
Thereafter, in order to form an LDD structure, a resist pattern (not shown) is formed, and n-type impurity ions are implanted into a desired surface of the Si substrate 1 through the post-oxide film 6 to selectively reduce the concentration of n. A type impurity diffusion layer 7 is formed. Similarly, a low-concentration p-type impurity diffusion layer is formed in the p-channel transistor region by ion implantation. The ion implantation concentration is 5 × 10 5 for both n channel and p channel.¹³cm^-2To the extent.
Next, as shown in FIGS. 5A and 5B, an impurity diffusion layer having a high impurity concentration, which is one of the features of the present invention, is formed.
[0024]
That is, first, Si having a thickness of about 50 nm is formed on the entire surface._ThreeN_FourAfter the film is deposited by the CVD method, the entire surface is etched by the RIE method, and the Si film having a width of about 50 nm is formed on the side wall of the gate electrode 4._ThreeN_FourA spacer layer 8 made of a film is formed. At this time, the surface of the Si substrate 1 in the region of the low-concentration impurity diffusion layer 7 is exposed. Next, an epitaxial Si layer 9 having a thickness of about 200 nm is selectively grown on the exposed surface of the Si substrate 1.
[0025]
Thereafter, for example, a dose of 5 × 10 5 is applied to the epitaxial Si layer 9 in the n-channel region.¹⁵cm^-2About n-arsenic ions are implanted so that the epitaxial Si layer 9 in the n-channel region functions as a high-concentration n-type impurity diffusion layer. Similarly, for example, a dose of 5 × 10 5 is applied to the epitaxial Si layer 9 of the impurity diffusion layer 7 in the p-channel region.¹⁵cm^-2About BF₂ ⁺ So that the epitaxial Si layer 9 in the p-channel region functions as a high-concentration p-type impurity diffusion layer.
[0026]
Next, a silicide layer 10 is formed only on the surface of the epitaxial Si layer 9. The silicide layer 10 is formed by, for example, forming Ti on the entire surface by sputtering to a thickness of about 50 nm, followed by heat treatment for silicidation (eg, 600 ° C., N₂, 30 minutes heat treatment), and finally, the unreacted Ti layer on the gate gap layer 5 and the spacer layer 8 is removed. As a result, the silicide layer (TiSi) is formed only on the surface of the exposed epitaxial Si layer 9.₂) 10 can be selectively formed. As another silicide material, for example, nickel silicide, kobald silicide, or the like may be used.
Next, as shown in FIGS. 6A and 6B, a plug layer is formed using a self-aligned etching technique for the capacitor electrode portion, which is one of the features of the present invention.
[0027]
That is, first, as an interlayer insulating film 11, for example, a BPSG film is deposited by a CVD method to a thickness of about 600 nm, and then the entire surface of the substrate is chemically and mechanically polished on the gate electrode 4 using a so-called chemical mechanical polishing method. Planarization etching is performed so that the film thickness of the interlayer insulating film 11 is about 200 nm. Here, another planarization method, for example, a so-called resist etch-back method in which a resist is applied and the base is planarized, and then the etching is performed under the condition that the etching rates of the resist and the insulating film are almost equal to each other. good.
[0028]
Next, a resist pattern for contact holes (not shown) for making contact between the capacitor electrode portion and the low-concentration impurity diffusion layer 7 ′ is formed on the interlayer insulating film 11, and this is used as a mask to form the interlayer insulating film 11. Is selectively etched to expose the silicide layer 10 and open a contact hole. This selective etching of the interlayer insulating film 11 is performed using, for example, RIE, and the etching conditions are the spacer layer 8 (Si_ThreeN_FourBPSG film etching rateFast conditionTo. For example, CHF as an etching gas_ThreeIt can be realized with a vacuum of about 6 mTorr using a mixed gas of CO and CO. The above etching conditions can be realized even with other setting conditions.
[0029]
In this way, the interlayer insulating film 11 (BPSG film) is etched, but the gate gap layer (Si_ThreeN_Four) 5 and the spacer layer (Si_ThreeN_Four) 8 is not etched, and a short circuit between the capacitor electrode portion and the gate electrode 4 to be formed in a later process can be prevented. That is, a new etching stopper layer is not required, and the contact hole can be formed in a self-aligned manner without using a complicated process.
[0030]
Next, a polycrystalline Si layer doped with, for example, arsenic is deposited on the entire surface until the contact hole is completely filled. For example, in the case of a contact hole having a diameter of 0.4 μm, a film thickness of about 400 nm is deposited and etched back using a chemical dry etching (CDE) method to fill the contact hole with a polycrystalline Si layer. For this, a chemical mechanical polishing method may be used. By such a process, the plug layer 12 made of a polycrystalline Si layer electrically connected to the low concentration impurity diffusion layer 7 ′ can be formed at a position above the gate electrode 4. This is a structure that works very effectively when the capacitor electrode portion is formed in a later step.
[0031]
Although an example in which a BPSG film is used as the interlayer insulating film 11 is shown here, other films such as a plasma oxide film, ozone (O_Three) -TEOS film or other insulating film that can be formed at as low a temperature as possible._ThreeN_FourAny insulating film may be used as long as etching is faster than the film.
Next, as shown in FIGS. 7A and 7B, the process proceeds to a step of reducing the depth of the contact hole in the peripheral circuit portion, which is one of the features of the present invention.
[0032]
That is, as an interlayer insulating film 13 on the entire surface for insulating the plug layer 12, for example, a SiO film having a thickness of about 100 nm is formed by a CVD method.₂Deposit a film. Next, a contact hole for making contact between the low-concentration impurity diffusion layer 7 and the bit line layer 14 is formed using a normal lithography process.
[0033]
This contact hole is also formed in the same way as in the step of FIG.₂Film and Si_ThreeN_FourSelf-alignment is performed using the difference in etching rate with the film. That is, the interlayer insulating films 11 and 13 (SiO₂Film) is etched, but Si_ThreeN_FourRIE is performed under the etching conditions such that the gate cap layer 5 and the spacer layer 8 made of are hardly etched. In addition, SiO₂And Si_ThreeN_FourIt is desirable that the etching selectivity is 10 or more.
At this time, a contact hole to the low-concentration impurity diffusion layer 7a in the peripheral circuit is simultaneously opened.
[0034]
That is, in the region where the low-concentration impurity diffusion layers 7 and 7 ′ formed in the process of FIG. 5, the epitaxial Si layer 9 formed thereon, and the silicide layer 10 formed thereon are stacked. Contact holes are formed simultaneously. In other words, a contact hole for the low concentration impurity diffusion layers 7 and 7 'of the memory cell and a contact hole for the low concentration impurity diffusion layer 7a of the peripheral circuit are formed simultaneously.
[0035]
At this time, as can be seen from FIG. 8 (see also FIG. 2), the epitaxial Si layer 9 extends and spreads on the field insulating film 2 and serves to widen the contact margin with the field edge. That is, it is possible to make contact even on the field insulating film 2.
[0036]
Thereafter, the bit line layer 14 is formed. As the material of the bit line layer 14, it is desirable to use a metal material in order to reduce the wiring resistance and to reduce the resistance of the lift contact. For example, a tungsten (W) film formed by a CVD method is used.
[0037]
In this case, the underlying interlayer insulating film 13 (SiO₂) And the W film, the TiN film or the W film formed by sputtering is used as the lower bit line layer 14.₁Used as
[0038]
That is, first, after opening a contact hole, the lower bit line layer 14 having a thickness of 50 nm and made of TiN is formed by CVD.₁Subsequently, the upper bit line layer 14 made of W having a thickness of 100 nm is formed using the CVD method.₂Form. Next, as the gate cap layer 15, for example, a plasma nitride film (Si_ThreeN_Four), A resist pattern is sequentially formed thereon using a normal lithography technique. Then, using this resist pattern as a mask, the gate cap layer 15 and the upper bit line layer 14 are formed.₂, Lower bit line layer 14₁Are sequentially processed by RIE.
[0039]
The structure of the memory cell portion is a bit line pre-fabrication type in a stacked memory cell, but in the peripheral circuit portion, the contact hole of the impurity diffusion layer 7a is formed in the gate electrode 4 in a self-aligned manner, and once the memory cell Area bit line layer 14₁, 14₂Same packed bed 14_1a, 14_2aIt becomes a structure lifted by.
[0040]
Further, although not shown in FIG. 8, the contact to the gate electrode 4 is simultaneously made to the bit line layer 14.₁, 14₂Same packed bed 14_1a, 14_2aThe impurity diffusion layer 7a and the gate electrode 4 in the peripheral circuit portion are all raised by the bit line layer 14₁, 14₂Same packed bed 14_1a, 14_2aIt will be lifted up once by the layer. As a result, the depths of the contact holes in forming the metal wiring after the memory cell portion and the peripheral circuit portion are uniform, and the disadvantages of memory cells having deep contact holes such as stacked memory cells can be avoided.
[0041]
As shown in FIG. 8, a bit line 14 such as a W film or a TiN film is used.₁, 14₂In order to improve the oxidation resistance / heat resistance of the surface of the metal material, it is very effective to form the surface protective film 16 by performing, for example, plasma nitriding.
Next, as shown in FIGS. 9A and 9B, a process of forming a capacitor electrode using the plug layer 12 which is one of the features of the present invention will be described.
[0042]
That is, as the interlayer insulating film 17 of the bit line layer 14, for example, an ozone-TEOS oxide film which can be formed at a low temperature of about 350 ° C. by a CVD method, for example, about 500 nm is deposited.
[0043]
Next, the entire surface is flattened by a chemical mechanical polishing method or the like, and an interlayer insulating film 17 is left on the bit line layer 14 by about 100 nm, and then a Si film having a thickness of about 50 nm is formed on the entire surface._ThreeN_FourFilm 18 is deposited by CVD.
[0044]
Then Si_ThreeN_FourA contact hole resist pattern (not shown) for connection to the plug layer 12 is formed on the film 18 by an ordinary lithography method, and then this is used as a mask by RIE to form Si_ThreeN_FourThe film 18 and the interlayer insulating films 17 and 13 are sequentially etched to form contact holes.
[0045]
At this time, as in the steps of FIGS.₂The film is more Si_ThreeN_FourEtching under etching conditions such that the etching rate is about 10 times faster than the film, for example, even if a contact hole is applied to the bit line 14 due to misalignment during lithography, the gate cap layer on the bit line 14 (Si_ThreeN_Four) The etching stops at 15. In addition, even if the etching reaches the plug layer 12, the plug layer 12 is at a position above, for example, about 400 nm from the gate electrode 4, so that a short circuit with the gate electrode 4 can be prevented.
[0046]
Next, Si_ThreeN_FourFor example, after the film 19 is deposited to a thickness of about 50 nm, the entire surface is etched by RIE to form Si only on the side wall of the contact hole._ThreeN_FourThe film 19 is left so that the surface of the plug material 12 is exposed, and the exposed side surface of the bit line 14 is insulated and separated from the capacitor electrode formed in a later process. Next, a polycrystalline Si film 20 doped with arsenic as a capacitor base electrode (storage electrode) is deposited on the entire surface, for example, to a thickness of about 70 nm.₂The film 21 is deposited, for example, to a thickness of about 500 nm, and the capacitor electrode is formed of SiO.₂The film 21 is etched by the RIE method. At this time, the etching is stopped at the polycrystalline Si film 20.
[0047]
Next, the etching gas conditions are changed to change the underlying polycrystalline Si film 20 into SiO 2.₂Etching is performed in the same shape as the film 21. At this time, etching is performed on the underlying Si_ThreeN_FourStop at membrane 18. Then, a polycrystalline Si film 22 as a capacitor base electrode layer is again deposited on the entire surface to a thickness of about 500 nm. At this time, arsenic is angled from four directions (for example, about 30 degrees) in order to ensure low electrical resistance between the polycrystalline Si film 22 and the polycrystalline Si film 20 as the capacitor base electrode layer. (Ion implantation angle). Alternatively, the electrical connection may be reliably maintained by using phosphorus-doped polycrystalline Si.
[0048]
Next, RIE is performed on the entire surface under the polycrystalline Si etching conditions, and SiO 2₂The polycrystalline Si film 22 is left on the side surfaces of the film 21 and the polycrystalline Si film 20. In this way, the size of the capacitor electrode can be made larger than the size determined by lithography. That is, the area of the capacitor electrode can be increased and the storage capacity (Cs) can be increased. If the capacitance (Cs) is the same, the height of the polycrystalline Si film 22 can be reduced. This is very effective in reducing the overall level difference.
[0049]
Then SiO₂The membrane 21 is formed, for example, by NH_FourIt removes using etching solutions, such as F liquid. At this time, the underlying Si_ThreeN_FourThe film 18 allows NH_FourEtching of the underlying interlayer insulating film 17 by the F solution can be prevented.
Next, a capacitor forming process is entered. There are two methods for forming a capacitor insulating film.
The first method is to use a normal so-called NO film.
[0050]
That is, first, a natural oxide film on the surface of the polycrystalline Si layers 20 and 22 as the capacitor base electrode is converted into silane gas (SiH_Four) And then the surface of the polycrystalline layers 20 and 22 in the same vacuum._ThreeN_FourThe film is heated at a high temperature (eg 800 ° C.) with ammonia gas (NH_ThreeFor example, about 1 nm.
[0051]
Thereafter, Si is formed as a capacitor insulating film 23 on the entire surface._ThreeN_FourA film is deposited to a thickness of about 60 nm, and the surface is oxidized for about 60 minutes in an atmosphere of 800 ° C., HCl, 10%, for example, to form a so-called top oxide film of about 2 nm. Next, a polycrystalline film to be the plate electrode 24 is deposited on the entire surface, and this is patterned to form the plate electrode 24.
[0052]
Next, as an interlayer insulating film 25 thereon, for example, a plasma-TEOS film (SiO₂Film) is deposited on the entire surface by about 100 nm, and then an ozone-TEOS film 26 is deposited on the entire surface by about 1000 nm, for example. Then, the surface is flattened by using a chemical mechanical polishing technique or the like, and a plasma-TEOS film is deposited on the entire surface thereof as an interlayer insulating film 27 serving as a base of the Al wiring 29 to a thickness of about 100 nm.
[0053]
In the second method, a high dielectric film such as a tantalum oxide film (Ta₂O_FiveFilm). Other high dielectric films such as strontium titanate (SrTiO_Three) The same applies to the film, etc., but it is necessary to devise and use the electrode material and surface treatment in consideration of the reaction of each film with the capacitor electrode.
[0054]
As an example, Ta₂O_FiveThe case of a film will be described. First, as in the case of the NO film, the natural oxide film on the surface of the polycrystalline Si films 20 and 22 as the capacitor base electrode is removed by, for example, a silane reduction method, and then the Si film is formed on the surface._ThreeN_FourA film is formed about 1 nm.
[0055]
Next, Ta is formed on the entire surface as a capacitor insulating film₂O_FiveAfter the film is formed by the CVD method, Ta₂O_FiveIn order to improve the dielectric constant of the film, N of about 750 ° C.₂Annealing is performed.
[0056]
Next, a titanium nitride film (TiN) film, carbon film (C), or nickel (Ni) film is formed as the plate electrode 24. Alternatively, a W film or an Al film may be simultaneously formed on the surface in order to reduce the resistance of the plate electrode 24 or prevent peeling.
[0057]
Then, as in the case of the previous NO film, plasma-TEOS films (SiO₂Membrane), ozone (O_Three) -TEOS films are deposited on the entire surface of about 100 nm and 1000 nm, respectively, and then uniformly planarized over the entire surface of the substrate by a chemical mechanical polishing method or the like.
[0058]
The above is an example of a capacitor forming method in the case of using a NO film or a high dielectric film, but Sr (TiO_Three), A Ta / Pt stacked type electrode may be used as the electrode in order to prevent reaction with the electrode.
[0059]
In the subsequent steps, as shown in FIGS. 1, 2 and 3, a contact hole for the bit line 14 or the plate electrode 24 is opened, and, for example, a selective growth of a W film 28 is performed in the contact hole. Or after depositing a W film over the entire surface, a W film 28 is buried in the contact hole by an etch back method, and a low resistance metal material is buried in the contact hole. As a result, the resistance of the contact plug can be reduced.
[0060]
Finally, a TiN film 29 as a barrier metal material₁Al film 29 as the main wiring₂As a result, the memory cell and the peripheral circuit part are completed. At this time, the wiring 29 may be used as a shunt material for the word line layer 4 in the memory cell portion. If necessary, another layer of Al wiring may be formed.
[0061]
In this embodiment, the mutual relationship between a plurality of memory cells adjacent in the direction of the word line 4 is not shown. However, only passage of the word line when the memory cell arrangement is a folded bit line system is on the field. It is shown. Of course, the present invention can be applied to a DRAM having an open bit line configuration. In addition, various modifications can be made without departing from the scope of the present invention.
[0062]
【The invention's effect】
As described above, according to the present invention, the epitaxial layer having an impurity concentration higher than the impurity concentration of the first impurity diffusion layer and the second impurity diffusion layer is the first impurity diffusion layer and the second impurity diffusion. Since it is provided over the layer, junction leakage can be reduced and the short channel effect of the transistor can be suppressed.
[0063]
In addition, by using the wiring layer as a filling layer, the deep contact hole in the peripheral circuit region brought about by the stacked memory cell becomes shallower by the amount of the filling layer, which reduces the yield due to contact failure. Can be prevented.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic configuration of a memory cell of a stacked DRAM according to an embodiment of the present invention.
2 is a cross-sectional view of the memory cell of the stacked DRAM of FIG. 1 taken along the line BB ′.
3 is a diagram showing a schematic configuration of a peripheral circuit of the stacked DRAM of FIG. 1;
FIG. 4 is a cross-sectional view of a manufacturing process of a stacked DRAM memory cell according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view of a manufacturing process of a stacked DRAM memory cell according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view of a manufacturing process of a stacked DRAM memory cell according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view of a manufacturing process of a peripheral circuit portion of a stacked DRAM according to an embodiment of the present invention.
FIG. 8 is a cross-sectional view of a manufacturing process of a stacked DRAM memory cell according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a manufacturing process of a stacked DRAM memory cell according to an embodiment of the present invention.
FIG. 10 is an element cross-sectional view of a memory cell of a conventional stacked DRAM.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,101 ... Si substrate, 2,102 ... Field insulating film, 3,103 ... Gate insulating film, 4,104 ... Gate electrode, 5 ... Gate camp layer, 8 ... Spacer layer, 7, 105 ... Impurity diffusion layer, 9 ... Epitaxial Si layer, 10 ... Silicide layer, 12 ... Plug layer, 14,112 ... Bit line layer, 14₁, 14₂... Filled layer, 11, 13, 17, 25, 26, 27, 106, 111, 114 ... Interlayer insulating film, 20, 22, 107 ... Polycrystalline Si film, 23, 109 ... Capacitor insulating film, 24, 110 ... Plate Electrode, Al wiring ... 29.

Claims (11)

A first MOS transistor formed on a semiconductor substrate and having a first impurity diffusion layer and a second impurity diffusion layer;
The gate electrode of the first MOS transistor is provided on the semiconductor substrate, formed on each of the first impurity diffusion layer and the second impurity diffusion layer of the first MOS transistor, and below the side surface of the gate electrode of the first MOS transistor. An interlayer insulating film having a contact hole exposed in a self-aligned manner with respect to the spacer layer ,
Among the contact hole formed in the interlayer insulating film on the first impurity diffusion layer, filling the lower side of the portion where the spacer layer is exposed, a first conductive contact with the first impurity diffusion layer A semiconductor layer as a film;
Formed on the first conductive film so as to fill the contact hole formed in the interlayer insulating film on the first impurity diffusion layer, high are formed than the gate electrode of said first MOS transistor The second conductive film does not extend outside the upper opening surface of the contact hole , and the height at the edge of the upper opening surface is the same as that of the interlayer insulating film . A conductive film;
Wherein formed on the second conductive film, a semiconductor memory device characterized by comprising comprises a said first capacitor which is electrically connected to the impurity diffusion layer. The semiconductor memory device according to claim 1, wherein the first MOS transistor is formed in a memory cell region of the semiconductor substrate. Billing semiconductor film as the first conductive film, which is a first epitaxially layer having a higher impurity concentration than the impurity concentration of the first impurity diffusion layer and said second impurity diffusion layer Item 14. The semiconductor memory device according to Item 1. 4. The semiconductor memory device according to claim 3, wherein the first epitaxial layer is formed lower than a gate electrode of the first MOS transistor. A second MOS transistor formed in a circuit region of the semiconductor substrate;
Provided on the impurity diffusion layer of the second MOS transistor, according to claim 2, characterized by being provided with a second epitaxial layer having a higher impurity concentration than the impurity concentration of the impurity diffusion layer Semiconductor memory device. Said first MOS transistor the interlayer insulating wiring layer formed on the film while filling the second contact hole on the impurity diffusion layer of,
It is formed in the same step as the wiring layer, a semiconductor according to claim 5, further comprising a second MOS transistor the impurity diffusion layer conductive formed while filling the contact hole on the layer of Storage device. The semiconductor film as the first conductive film is a first epitaxial layer having an impurity concentration higher than that of the first impurity diffusion layer and the second impurity diffusion layer. 6. The semiconductor memory device according to claim 5, wherein the layer and the second epitaxial layer are formed simultaneously. Comprising a wiring layer formed on the contact hole on the second impurity diffusion layer of the first MOS transistor,
The capacitor, a semiconductor memory device according to claim 1 or 5, characterized in that it is insulated from the wiring layer. A gate cap layer provided on the gate electrode of the first MOS transistor, wherein the wiring layer is between the gate electrode and the second impurity diffusion layer via the gate cap layer and the spacer layer; 9. The semiconductor memory device according to claim 8, wherein the semiconductor memory device is formed in the contact hole on the layer . The semiconductor film as the first conductive film is a first epitaxial layer having an impurity concentration higher than that of the first impurity diffusion layer and the second impurity diffusion layer. A silicide layer is formed between a layer and the second conductive film, and a silicide layer formed simultaneously with the silicide layer is formed between the second epitaxial layer and the conductive layer. The semiconductor memory device according to claim 6 .   The semiconductor memory device according to claim 1, wherein the capacitor includes a storage electrode, a capacitor insulating film, and a plate electrode.

Images