JP3776652B2 - Vector arithmetic unit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a vector arithmetic apparatus, and more particularly to a vector arithmetic apparatus that can perform high-precision arithmetic processing by reducing an error due to exponent matching when performing vector summation.
[0002]
[Prior art]
FIG. 5 shows a conventional vector arithmetic apparatus that performs vector summation. As shown in FIG. 5, the conventional vector operation device includes a vector register 111 that stores vector data, an adder 121 that performs a sum operation process, and a vector register 112 that stores an operation result. In FIG. 5, when a sum instruction, that is, an instruction word 300 is issued from an instruction control unit (not shown), vector data is transferred from the vector register 111 designated by the RR field 302 that designates a read register in the instruction word 300. Read out and input to the adder 121. The adder 121 performs a sum operation process on the input data, and stores the final result in the vector register 112 designated by the WR field 303 that designates the write register in the instruction word 300. The summation processing method in the adder 121 is as follows.
[0003]
First, one vector data is read every clock from the vector register 111 storing vector data, and sequentially input to the adder 121. The adder 121 is configured such that an addition result other than the final result is input to the adder 121 again and added to the vector data read from the vector register.
[0004]
FIG. 6 is a schematic diagram showing processing in the adder 121 of the vector arithmetic apparatus shown in FIG. For example, if the processing time in the adder 121 is 4 clocks, the elements read from the vector register 111 are input to the adder 21 and added again after 4 clocks.
[0005]
Here, the vector data are a1, a2, a3, a4, a5, a7, a6, a7, a8. . . And The data a1 is read from the vector register 111 at the first clock, and is input to the addition process 1 in the adder 121 at the second clock, and is added with the immediate value “0”. In-adder processing 2 and 3 are sequentially performed, and the result of a1 + 0 is obtained by in-adder processing 4 at the fifth clock. Then, at the next clock (sixth clock), the result a1 + 0 is input to the adder processing 1 again.
[0006]
On the other hand, the data a5 is read from the vector register 111 at the fifth clock, and this data a5 is input to the adder internal processing 1 at the sixth clock, and added again with the input a1 + 0, and a1 + a5 Processing is performed. Similarly to the case of a1, the data a2, a3, and a4 are also added to the immediate value 0 in the adder processing (a2 + 0, a3 + 0, a4 + 0), and the result is added again at the seventh, eighth, and ninth clocks. The result is input to the internal process 1, and the results of a2 + a6, a3 + a7, a4 + a8 are obtained.
[0007]
Here, if the addition results of a1 + a5, a2 + a6, a3 + a7, and a4 + a8 are S1, S2, S3, and S4, respectively, S1 and a9 at the 10th clock, and S2 and a10, 12 at the 11th clock. S3 and a11 are input to the clock, S4 and a12 are input to the 13th clock, and the results of S1 + a9, S2 + a10, S3 + a11, and S4 + a12 are obtained.
[0008]
Although there are various methods for calculating the final result, the method shown in FIG. 7 is used here. FIG. 7 shows a method of calculating the final result when the number of vector processing elements is eight. S1, S2, S3, and S4 are calculated by the method described above. It is assumed that S1 is input to the in-adder process 1 at the timing when S3 is input to the in-adder process 1, and is controlled in the arithmetic unit so that S1 + S3 = S5 is calculated. Similarly, at the timing when S4 is input to the in-adder process 1, the arithmetic unit is controlled so that S2 is input to the in-adder process 1, and S2 + S4 = S6 is calculated. In addition, it is assumed that S5 is input to the in-adder process 1 at the timing when S6 is input to the in-adder process 1, and is controlled in the arithmetic unit so that S5 + S6 = sum is calculated.
[0009]
Thus, one total result is finally obtained, and the result is stored in the vector register 12. In general, the summation process in the vector arithmetic unit is designed to speed up the process by regressing data in the adder as described above. When performing scalar processing, it is usually added in element order starting from a1, but when it is processed by a vector arithmetic unit, it is not added in element order, so the order of addition is different from that during scalar processing. However, in the addition process, it is necessary to perform the following index matching before the addition process as is well known.
[0010]
Floating-point data handled on a computer is usually represented by a hexadecimal number and can be represented by an exponent part and a mantissa part. In addition processing, in general, index matching is performed by adjusting the smaller index to the larger index. Since the mantissa having the smaller exponent is shifted to the right by the difference between the exponents of the two data to be added, the shifted out bits are discarded. Thus, since it is necessary to perform exponent matching in the addition processing, if the exponent difference between the two data to be added is large, the number of bits shifted out increases and the addition result includes an error. .
[0011]
This error will be briefly described below by representing data handled on a computer in decimal. A specific operation when the number of significant digits of the adder is assumed to be 5 digits after the decimal point and the number of vector processing elements is 8 will be described. a1 = 1.000000E + 00, a2 = 2.00000E + 00, a3 = 3.00000E + 00, a4 = 4.00000E + 00, a5 = 5.000000E + 00, a6 = 1.00000E + 00, a7 = 2.00000E + 00, Assuming that a8 = 1.00000E + 06, S1 to S6 as intermediate addition results and the final result (total) are as follows.
S1 = a1 + a5 = 1.00000E + 00 + 5.00000E + 00 = 6.00000E + 00
S2 = a2 + a6 = 2.00000E + 00 + 1.00000E + 00 = 3.00000E + 00
S3 = a3 + a7 = 3.00000E + 00 + 2.00000E + 00 = 5.00000E + 00
S4 = a4 + a8 = 4.00000E + 00 + 1.00000E + 06 = 0.00000E + 06 + 1.00000E + 06 = 1.00000E + 06
S5 = S1 + S3 = 6.00000E + 00 + 5.00000E + 00 = 1.1000E + 01
S6 = S2 + S4 = 3.00000E + 00 + 1.00000E + 06 = 0.00000E + 06 + 1.00000E + 06 = 1.00000E + 06
Sum = S5 + S6 = 1.10000E + 01 + 1.00000E + 06 = 0.00001E + 06 + 1.00000E + 06 = 1.00001E + 06
The final result of the summation process is 1.00001E + 06.
[0012]
When the same calculation is processed with a scalar, since a1 to a8 are added in element order, the final result (sum) is as follows.
a1 + a2 = 1.00000E + 00 + 2.00000E + 00 = 3.00000E + 00 ... S1
S1 + a3 = 3.00000E + 00 + 3.00000E + 00 = 6.00000E + 00 ... S2
S2 + a4 = 6.00000E + 00 + 4.00000E + 00 = 1.00000E + 01… S3
S3 + a5 = 3.00000E + 01 + 5.00000E + 00 = 1.50000E + 01… S4
S4 + a6 = 3.00000E + 01 + 1.00000E + 00 = 1.60000E + 01… S5
S5 + a7 = 1.60000E + 01 + 2.00000E + 00 = 1.80000E + 01… S6
S6 + a8 = 1.80000E + 01 + 1.00000E + 06 = 1.00002E + 06 ... Sum In this way, although depending on the input data, the final sum result may vary between vector processing and scalar processing depending on the order of addition. .
[0013]
[Problems to be solved by the invention]
However, if the summation processing results are different between the scalar processing and the vector processing, the result of the scalar processing is assumed to be correct in most cases. This is because, in the program, it is written to add in the order of elements, so that an error caused by exponent matching at the time of scalar processing is unavoidable. In this way, when the sum processing results are different, it is possible to perform the scalar processing only at the place where the sum processing occurs in the program source. However, in this case, there is a problem that the processing time is slow because a portion that can be processed by the vector operation is intentionally processed by the scalar.
[0014]
In addition, when a calculation result with higher accuracy than that at the time of scalar processing is required, it is possible to reduce errors due to exponent matching by rearranging the processing target elements in ascending order and then performing processing with the scalar. However, in this case, a program source for rearranging the processing elements is required, which requires labor and slows down the processing time.
[0015]
As described above, in the vector calculation process, the sum calculation process is speeded up, so the addition order during the sum process is different from the scalar process. However, in the conventional vector calculation device, during the vector sum process, Since the order of addition cannot be changed, there is a problem that the accuracy of the summation result of the vector processing is inferior to the summation result of the scalar processing depending on the data to be processed. Furthermore, since there is no means for rearranging input data, it is not possible to expect a calculation result with higher accuracy than that performed by scalar processing.
[0016]
The present invention has been made to solve the above-described problem. A vector arithmetic apparatus capable of obtaining a high-precision summation processing result by rearranging input data in ascending order during vector summation processing and further performing addition in element order. The purpose is to provide.
[0017]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, a vector operation device according to the present invention is a vector processing device comprising at least one vector register and an adder that performs a sum operation on vector data in the vector register. A data rearrangement unit for rearranging vector data, and the data rearranged by the data rearrangement unit are sequentially input to the adder, and the sum is calculated by adding the data in the order of elements having the smallest key value. It is characterized by.
[0018]
With such a configuration, addition processing can be performed in order from the smallest data, so that errors caused by index matching can be suppressed. For this reason, a highly accurate summation processing result can be obtained.
[0019]
Further, in the vector operation device of the present invention, the data rearrangement means stores the data sort means for rearranging the vector data, the data storage means for storing the data rearranged by the data sort means, and the data storage means. Data read timing instruction means for reading vector data at a predetermined timing and sending it to the adder is provided.
[0020]
Further, in the vector operation device according to the present invention, the adder is configured so that an intermediate addition result other than the final addition result is input again to the adder, and the data read timing instruction means includes the addition result of the preceding element. Is input to the adder again, and at the same time, the next element is read from the data storage means and instructed to be input to the adder.
[0021]
By configuring in this way, vector data can be rearranged, and then the data can be read out and sent to the adder in synchronization with a predetermined timing, particularly the operation timing in the adder. Processing can be executed.
[0022]
The vector arithmetic unit of the present invention includes a first data line for directly sending the vector data in the vector register to the adder, and a second data line for sending the vector data to the adder via the data rearranging means. And a data supply switching means for switching a supply line of vector data to the adder between the first data line and the second data line.
[0023]
As described above, when it is not necessary to rearrange the vector data, the data can be added in the order as they are, so that an appropriate addition process corresponding to the case can be performed.
[0024]
In the vector operation device of the present invention, the vector data is rearranged in ascending order.
[0025]
In this way, by rearranging the vector data in ascending order, addition processing can be performed in order from the smallest data, so that an error caused by index matching can be reduced.
[0026]
Also, the vector arithmetic unit of the present invention is characterized in that an instruction signal for determining whether or not the vector data is rearranged is set in an instruction word created by a compiler.
[0027]
The vector operation device of the present invention is characterized in that an instruction signal for determining whether or not the vector data is rearranged is set in a process state word.
[0028]
With this configuration, the program executor can rearrange the data in ascending order only for the summation process at an arbitrary location, so that a highly accurate result can be obtained without extremely slowing the execution time of the entire program. [0029]
In the vector operation device of the present invention, a part of the sum operation performed in the operation device is specified, and the specified portion is subjected to vector sum operation processing via the rearranging means. It is characterized by that.
[0030]
With this configuration, it is possible to execute high-precision summation processing without extremely delaying the execution time of the entire program.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
The vector processing apparatus of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of the first exemplary embodiment of the present invention. The vector processing apparatus of the present invention includes a vector register 11 for storing vector data, an adder 21 for processing a summation operation, an input switching means 30 for switching whether or not to rearrange vector data, vector data Are arranged in ascending order, and a vector register 12 for storing operation results.
[0032]
The input switching unit 30 switches whether the vector data read from the vector register 11 is directly input to the adder 21 or supplied to the adder 21 via the data rearrangement unit 40 according to the data sort instruction signal 50. The data rearranging unit 40 includes a data sorting unit 41, a data storage unit 42, and a read timing control unit 43. The data sorting unit 41 rearranges the vector data of a plurality of elements sent via the input switching unit 30 in ascending order, and stores the result in the data storage unit 42. The vector data in the data storage means 42 is read by the read timing instruction means 43 and then supplied to the adder 21. The read timing instruction means 43 instructs the timing for reading each vector data from the data storage means 42. This timing is determined by the processing time in the adder 21, and the addition result of the preceding element is input to the adder 21. At the same time, the next element is read from the data storage means 42 and instructed to be input to the adder 21. The adder 21 is configured so that intermediate results other than the final operation result are input to the adder 21 again and only the final result is stored in the vector register 12.
[0033]
FIG. 2 is a diagram showing instruction words in the vector processing apparatus of the present invention. In the instruction word 100, an OP field 101 indicates an operation code indicating an instruction, an RR field 103 specifies a vector register from which data is read, and a WR field 104 specifies a vector register into which an operation result is written. The sort instruction bit 102 is a bit that designates whether the input data should be rearranged in ascending order or whether normal summation processing is performed without rearrangement.
[0034]
When normal summation processing is performed without data rearrangement, the source instruction bit 102 is designated as “0”, and when input data is rearranged, “1” is designated. This bit specifies “0” or “1” when the compiler generates an instruction word. When a compiler instruction line is written in a part of the program, the rearrangement is performed only on the sum calculation instruction of the designated part. On the other hand, when it is specified by a compile option or the like, it can be rearranged for all the sum operation instructions in the program. When this sort instruction bit 102 is “0”, the data sort instruction signal 50 shown in FIG. 1 is “0”, the normal summation processing is performed, and when the sort instruction bit 102 is “1”, the sort is performed. The instruction signal is “1”, and the arithmetic processing is executed by rearranging the data.
[0035]
In the above-described embodiment, the sort instruction signal 50 is determined by the sort instruction bit in the instruction word 100. For example, a sort instruction signal is provided in the process state word 200 as shown in FIG. It may be set as a set value so as to target the previous sum operation instruction.
[0036]
Next, the operation flow of the vector processing apparatus according to the present invention will be described with reference to FIGS. In FIG. 1, when a sum operation instruction is issued from an instruction control unit (not shown), the vector register 11 is designated by the RR field 103 in the instruction word 100 (see FIG. 2), and vector data is read from this register. It is. Next, when the data sort instruction signal 50 is “0”, the data switching unit 30 switches the data rate so that the vector data read from the vector register 11 is directly input to the adder 21. On the other hand, when the data sort instruction signal 50 is “1”, the route is switched to the data rearrangement unit 40 and the vector data is input to the data rearrangement unit 40.
[0037]
When the data sort signal 50 is “1”, the vector data from the vector register 11 is sent to the data rearrangement means 40, and the data sort means 41 rearranges the data of a plurality of elements in ascending order. This result is stored in the data storage means 42. The data is read from the data storage means 42 according to the timing signal to the read timing instruction means 43 and input to the adder 21. The timing at which the read timing means 43 reads the vector data is determined by the processing time in the adder 21, and the next element is read from the data storage means 42 at the same time as the addition result of the preceding element is input to the adder 21. , And input to the adder 21. The intermediate result other than the final result in the adder 21 is input to the adder 21 again, and only the final result is sent to the vector register designated by the WR field 104 in the instruction word 100, in this case the vector register 12, and stored. .
[0038]
When the data sort signal 50 is “0”, that is, when the vector data read from the vector register 11 is directly input to the adder 21, the description is omitted here because it is the same as the conventional summation process. Further, since the addition method in the floating point addition in the adder 21 is known, the description thereof is omitted here.
[0039]
Next, the processing operation in the adder 21 of the present invention when the sort instruction signal 50 is “1” will be described in detail with reference to FIG. Here, assuming that the processing time in the adder 21 is 4 clocks, the data rearranged in the ascending order by the data rearranging means 40 are A1, A2, A3, A4. . . And
[0040]
As shown in FIG. 4, the first element (A1) is read from the data storage means 42 at the clock 1 and input to the adder internal processing 1 at the next clock 2. At this time, the adder 21 adds A1 to the immediate value “0”. Next, through the adder processes 2 and 3, the result of A1 + 0 is obtained in the adder process 4 at the fifth clock. This result is input again to the in-adder process 1 at the next clock (sixth clock). Since it is possible to predict in advance that the result of A1 + 0 is input to the adder processing 1 at the sixth clock, the read timing instruction means 43 reads A2 from the data storage means 42 at the fifth clock, The next element (A2) is input to the adder processing 1 at the sixth clock. That is, the read timing instruction unit 43 reads data from the data storage unit 42 every four clocks.
[0041]
As shown in FIG. 4, A1 + A2 (= S1) is obtained in the adder process 1 at the sixth clock. Thereafter, similarly, the third element (A3) is read from the data storing means 42 at the ninth clock, and S1 and A3 are input to the adder processing 1 at the tenth clock, and the adder processing 2, 3 are performed. Then, S1 + A3 (= S2) is calculated at the 13th clock. In this manner, the vector data rearranged in the ascending order by the data sorting means 41 is added to the data in ascending order to perform the sum operation processing, and the finally obtained sum is stored in the vector register 12.
[0042]
【The invention's effect】
As described above, according to the vector processing device of the present invention, the vector data to be summed can be rearranged in ascending order, and then addition processing can be performed in ascending order, so that errors caused by index matching can be suppressed. Can do. For this reason, a highly accurate calculation result can be obtained.
[0043]
In addition, since the program executor can rearrange the data for only the sum calculation processing at an arbitrary place and perform the calculation processing, a highly accurate result can be obtained without extremely slowing the execution time of the entire program. be able to.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a vector arithmetic apparatus according to the present invention.
FIG. 2 is a diagram showing instruction words in the vector operation device of the present invention.
FIG. 3 is a diagram showing process state words in the vector operation device of the present invention.
FIG. 4 is a diagram showing a processing operation in an adder of the vector arithmetic apparatus according to the present invention.
FIG. 5 is a block diagram showing a configuration of a conventional vector operation device.
FIG. 6 is a diagram illustrating a processing operation in an adder of a conventional vector operation device.
FIG. 7 is a diagram showing another processing operation in the adder of the conventional vector arithmetic apparatus.
[Explanation of symbols]
11, 12, 111, 112 Vector register 21, 121 Adder 30 Input switching means 40 Data rearranging means 41 Data sorting means 42 Data storage means 43 Read timing instruction means 50 Data sort signal 100 Command word 101, 301 OP field 102 Sort instruction Bit 103, 303 RR field 104, 304 WR field 200 Process status word 201 Sort instruction bit 300 Instruction word

Claims (6)

A vector that includes at least one vector register and an adder that changes the addition order of vector data by regressing an addition output, and performs summation processing on the vector data in the vector register using the adder In the processing device,
Data sorting means for rearranging vector data in the vector register ;
Data storage means for storing the data rearranged by the data sorting means;
Data reading for reading out the next element of the rearranged vector data stored in the data storage means at a timing according to the operation timing of the adder, sending it to the adder, and adding it to the regressed addition output And a timing instruction means . 2. The vector arithmetic unit according to claim 1 , wherein the adder is configured so that a halfway addition result other than the final addition result is input again to the adder, and the data read timing instruction means includes a preceding element. A vector arithmetic unit characterized in that at the same time when the addition result is inputted again to the adder, the next element is read from the data storage means and inputted to the adder. In a vector processing apparatus comprising at least one vector register and an adder that performs a sum operation on the vector data in the vector register using a floating-point operation ,
Data rearranging means for rearranging vector data in the vector register;
First data line to feed vector data in the vector register to said adder,
A second data line for sending the vector data to the adder via the data rearranging means ;
Comprising a data supply switching means for switching between said first data line and the second data lines supply lines of the vector data to the adder,
When the second data line is designated , the vector arithmetic apparatus is characterized in that the data rearranged by the rearranging means is sequentially input to the adder, and the data is added in ascending order to perform a sum operation process . In the vector calculation apparatus according to any one of claims 1 to 3, the vector operation unit, wherein the vector data reordering is performed in ascending order. And one vector register even without low, the vector data using a floating-point operation in said vector register, the vector processing device comprising an adder for summation processing,
Data rearranging means for rearranging vector data in the vector register; and input switching means for switching whether the vector data is input directly from the vector register to the adder or input via the data rearranging means,
The input switching means sequentially inputs vector data to the adder via the data rearranging means when an instruction signal for rearranging the vector data is set in an instruction word created by a compiler. A vector arithmetic apparatus characterized in that the data are added in ascending order to perform summation processing . And one vector register even without low, the vector data using a floating-point operation in said vector register, the vector processing device comprising an adder for summation processing,
Data rearranging means for rearranging vector data in the vector register, and input switching means for switching whether the vector data is input directly from the vector register to the adder or input via the data rearranging means,
The input switching means sequentially inputs vector data to the adder via the data rearranging means when an instruction signal for rearranging the vector data is set in the process state word . A vector arithmetic apparatus characterized in that the data is added in ascending order to perform a sum operation process .

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