JP3772178B2 - Error correction device - Google Patents

Description

  The present invention relates to an error correction apparatus that performs error correction on information data composed of error correction codes.

(First conventional example)
For example, FIG. 39 shows a conventional example of an error correction apparatus used in a disk reproducing apparatus for reproducing a disk as a recording medium such as a DVD. The receiving circuit 1 is configured by a RAM or the like via an arbiter 2 when receiving and decoding information data including an error correction code read from a disk by an optical pickup (none of which is shown). The data is written in the temporary storage unit 3 (reception processing).

The error correction circuit 4 reads the information data written in the temporary storage unit 3 by the receiving circuit 1 and performs error detection of the information data. When a correctable error is detected, the error correction circuit 4 corrects the data including the error. The data is written back to the temporary storage unit 3 via the arbiter 2 (correction process).
The transmission circuit 5 reads the information data corrected by the error correction circuit 4 from the temporary storage unit 3 via the arbiter 2, and transmits the information data to a reproduction system (not shown) for reproducing the information data into video or audio. (Transmission processing). The arbiter 2 is a memory interface that arbitrates access to the temporary storage unit 3 by each of the reception circuit 1, the error correction circuit 4, and the transmission circuit 5.

  Here, FIG. 40 conceptually shows a storage area inside the temporary storage unit 3. The storage area inside the temporary storage unit 3 is divided into three areas A, B, and C. The size of each area A, B, and C is a single data (block) capacity that completes the error correction code. Is set equal to. As shown in FIG. 41, for example, when the area A is a data write target in the reception process, the reception data written in the area C in the previous phase becomes the correction target. The data in area B that has been corrected in the previous phase is the target of transmission processing.

  In the next phase, the area B is subjected to reception processing, the area A is subjected to correction processing, and the area C is subjected to transmission processing, and each area is switched as an object of three processes while circulating. In this case, the reception circuit 1 outputs a status signal indicating that reception processing has been completed for one block of data to the error correction circuit 4 and the transmission circuit 5. After confirming that a signal has been given, each process is performed on a new area.

In this method, since reception processing, correction processing, and transmission processing can be performed in a time-sharing manner, it is not necessary to increase the processing speed of each circuit so much. However, the storage capacity of the temporary storage unit 3 is at least a data block capacity. There is a problem that the circuit scale becomes large because three times as much is required.
In order to solve such a problem, the inventor of the present invention, for example, as shown in FIG. 42, instead of the temporary storage unit 3, the storage capacity is twice the data block capacity (only areas A and B). It has been considered that the temporary storage unit is used to alternately switch one area A or B as the object of reception processing and the other area B or A as the object of correction processing and transmission processing.

  However, in this method, the storage capacity of the temporary storage unit can be reduced, but correction processing and transmission processing must be executed serially and completed within the time required for reception processing. There is a problem that it is necessary to improve the processing speed of the error correction circuit 4 and the transmission circuit 5, and the conditions for configuring both circuits become difficult.

(Second conventional example)
For example, the inventor of the present invention has conceived the configuration shown in FIG. 43 as an error correction device used in a disc playback device that plays back a disc as an information recording medium such as a CD or a DVD. In FIG. 43, the receiving circuit 6 receives and decodes the information data composed of the error correction code read from the disk by an optical pickup (none of which is shown), and then passes through the arbiter 7. The data is written in a temporary storage unit 8 composed of a RAM or the like.

The error correction circuit 9 reads the information data written in the temporary storage unit 8 by the receiving circuit 6 and performs error detection of the information data. When a correctable error is detected, the error correction circuit 9 corrects the data including the error, The data is written back to the temporary storage unit 8 via the arbiter 7.
The transmission circuit 10 reads the information data after error correction by the error correction circuit 9 from the temporary storage unit 8 via the arbiter 7, and transmits the information data to a reproduction system (not shown) for reproducing the information data into video or audio. It is supposed to be. The arbiter 7 is a memory interface that arbitrates access to the temporary storage unit 8 by each of the reception circuit 6, the error correction circuit 9, and the transmission circuit 10.

The syndrome calculation circuit 11 obtains information data directly from the reception circuit 6, calculates a syndrome from the error correction code, and outputs the calculation result to the error correction circuit 9.
For example, a CD or DVD employs a product code (Reed-Solomon) product code that constitutes two series of error correction code sequences consisting of C1 code, C2 code, PI (inner) code, and PO (outer) code as error correction codes. ing. For this reason, conventionally, the error correction circuit 9 performs error correction by reading the received data from the temporary storage unit 8 after the reception circuit 6 has written all the received data sufficient to complete the product code in the temporary storage unit 8. It is like that.

  Therefore, assuming the configuration shown in FIG. 43, the syndrome calculation circuit 11 pre-calculates, for example, a syndrome for the C1 or PI code string, so that the error correction circuit 9 can receive information for completing the product code by the reception circuit 6. Before the data is written in the temporary storage unit 8, the correction process for the first C1 or PI code string can be started, and the time required for the correction process can be shortened.

However, in such a system, when the reception sequence on the receiving circuit 6 side is disturbed and data reception is interrupted, the syndrome calculation circuit 11 cannot obtain the number of information symbols in units necessary for the calculation of the syndrome. There is a problem that syndrome calculation is not performed correctly.
In this case, since the data is not received on the temporary storage unit 8 and data that has been written in the past and is already meaningless at that time remains, the calculation result of the illegal syndrome When the value becomes a correctable value, the error correction circuit 9 causes erroneous correction that corrects meaningless data on the temporary storage unit 8.

  When such a miscorrection occurs, for example, in the case of audio data, unpleasant noise occurs, or in the case of file data, a file that should have been correctly loaded for the user is opened and displayed on a display or the like. And the contents of the file may be corrupted. Since these phenomena are captured as operations whose causal relationship is unknown to the user, there is a problem that the reliability of the product is lowered.

(Third conventional example)
FIG. 44 shows a conventional example of an error correction apparatus used in a disk reproducing apparatus for reproducing a disk as a recording medium such as a CD or a DVD. FIG. 45 is a flowchart showing a series of processes performed by each component of the error correction apparatus shown below. When the receiving circuit 12 receives and decodes the information data composed of the error correction code read from the disk by an optical pickup (none of which is shown) (step S1), the RAM or the like is passed through the arbiter 13. Is written in the temporary storage unit 14 (step S2).

The error correction circuit 15 reads the information data written in the temporary storage unit 14 by the receiving circuit 12 (step S3), performs error detection of the information data, and if a correctable error is detected, the data including the error Is corrected and written back to the temporary storage unit 14 via the arbiter 13 (step S4).
The transmission circuit 16 reads the information data after the error correction by the error correction circuit 15 from the temporary storage unit 14 via the arbiter 13 (step S5), and reproduces the information data as video or audio (not shown). The data is transmitted to the reproduction system (step S6). In addition, the data destruction circuit 17 overwrites arbitrary data via the arbiter 13 so that the error correction circuit 15 becomes uncorrectable immediately after the transmission circuit 16 reads the data from the temporary storage unit 14 and completes transmission. By doing so, the data is destroyed (step S7).

  The data destruction process by the data destruction circuit 17 is not updated on the temporary storage unit 14 even when data cannot be written to the temporary storage unit 14 due to disturbance of the data reception state in the reception circuit 12. This is performed in order to prevent erroneous determination and correction by the error correction circuit 15 by destroying the data written in. The arbiter 13 is a memory interface that arbitrates access performed by the reception circuit 12, the error correction circuit 15, the transmission circuit 16, and the data destruction circuit 17 to the temporary storage unit 14.

  However, in the method of providing the data destruction circuit 17 and destroying the transmitted data one by one as in the third conventional example, a data writing process is added for that purpose, and the data processing speed is kept at a constant level. In order to maintain, there is a problem that the data transfer rate to the temporary storage unit 8 must be set high.

(Fourth conventional example)
FIG. 46 shows a conventional example of an error correction apparatus used in a disk reproducing apparatus for reproducing a disk as a recording medium such as a CD or a DVD. When the RF circuit 18 receives the information data composed of the error correction code read from the disk 19 by the optical pickup 20, the RF circuit 18 equalizes the data signal waveform to synchronize the separation circuit 21, the PLL circuit 22, and the servo circuit. 23 is output.

  The PLL circuit 22 generates a reproduction clock signal from the data signal waveform and supplies it to the synchronization separation circuit 21 and the decoding circuit 24. The synchronization separation circuit 21 is included in the data signal based on the reproduction clock signal. The synchronizing signal is separated and given to the decoding circuit 24. When the decoding circuit 24 decodes the information data from the given data signal, the decoding circuit 24 writes the information data in the temporary storage unit 26 constituted by a RAM or the like via the arbiter 25.

The error correction circuit 27 reads out the information data written in the temporary storage unit 26 by the decoding circuit 24 and performs error detection of the information data. When a correctable error is detected, the error correction circuit 27 corrects the data including the error, The data is written back to the temporary storage unit 26 via the arbiter 25.
The transmission circuit 28 reads the information data after the error correction is performed by the error correction circuit 27 from the temporary storage unit 26 via the arbiter 25, and reproduces the information data as video or audio according to the type of the disk 19. Therefore, it is transmitted to a processing system (not shown). The arbiter 25 is a memory interface that arbitrates access to the temporary storage unit 26 by each of the decoding circuit 24, the error correction circuit 27, and the transmission circuit 28.

  The servo circuit 23 controls driving of the motor 30 that rotates the disk 19 and driving of the pickup 20. The processing of the servo circuit 23, the error correction circuit 27, and the transmission circuit 28 is performed based on the clock signal supplied from the system reference clock circuit 31, and the servo circuit 23 is input to the servo circuit 23 from the system controller 32 by a user operation. A reproduction speed control signal corresponding to the above is given.

  As the information storage system of the disk 19 in the reproduction system as described above, the CLV (Constant Liner Velocity) system in which the linear velocity is constant, and the ZCLV (Zone CLV) system in which the linear velocity between zones (predetermined areas) is constant. Alternatively, there is a ZCAV (Zone Constant Angler Velocity) method in which the angular velocity between Zones is constant, and the disk reproducing device reads and reproduces data according to various methods.

  For example, in the case of the CLV method, as shown in FIG. 47, the servo circuit 23 controls the motor 30 and the pickup 20 to rotate the disk 19 at a constant linear velocity, and the pickup 20 is moved from the inner circumference side of the disk to the outer circumference. The data recorded on the disk 19 is read and written to the temporary storage unit 26 as described above. In this way, by temporarily writing the data read from the disk 19 to the temporary storage unit 26, it is possible to absorb to some extent fluctuations in data read by the motor 30.

In recent years, when the disk 19 is, for example, a CD-ROM or DVD-ROM, the disk playback device plays back data at a higher speed in order to improve the search speed of large-capacity data and ensure a good user experience. Is required to do.
As shown in FIG. 47, when data stored on the disk 19 is randomly reproduced at a high speed, the pickup 20 is quickly moved to an arbitrary track, and then the disk 19 is rotated at a constant linear velocity. There is a need. In this case, it is relatively easy to move the pickup 20 to an arbitrary track quickly, but since the rotation of the motor 30 cannot respond instantaneously due to inertia, the rotational speed of the disk 19 becomes a constant linear speed. Until this period, the data reproduction speed fluctuates. If such a fluctuation in reproduction speed cannot be absorbed by the temporary storage unit 26, there is a problem that data reproduction becomes impossible.

In order to enhance the response, it may be possible to use a motor 30 having a high torque characteristic, but there is a limit because the current consumption of the servo circuit 29 increases. Furthermore, in order to reduce the control burden of the motor 30, there are some which rotate the disk by the CAV method, but it is impossible to apply to a device premised on the CLV method.
As described above, for a disk playback device for computer use in which the disk 19 is a CD-ROM, DVD-ROM, or the like, the period during which the data reading speed from the disk changes is transmitted in accordance with the reading speed. A system was also devised to send data. In other words, in the case of music CDs, the data read speed must always be kept constant at CLV in accordance with the sampling rate of 44.1 KHz, but there is no such restriction for the above computer use. is there.

  An example of the prior art of the above method is shown in FIG. This prior art assumes that the clock signal supplied to the error correction circuit 27 and the transmission circuit 28 is obtained by dividing the clock signal supplied from the system reference clock circuit 31 by the frequency dividing circuit 32, and the temporary storage unit 26 of the decoding circuit 24. The speed comparison circuit 33 monitors the write address with respect to, so that the frequency division ratio of the frequency divider circuit 32 is changed according to the remaining capacity of the temporary storage unit 26, and the speed at which the transmission data is read from the temporary storage unit 26 is changed. It follows the writing speed.

In this method, in order to increase the reproduction speed (reading speed of transmission data), it is necessary to increase the clock signal frequency of the system reference clock circuit 31, which causes problems such as unnecessary radiation and increased power consumption.
In the prior art shown in FIG. 49, the clock signal supplied to the error correction circuit 27 and the transmission circuit 28 is divided by the frequency dividing circuit 34 from the clock signal generated from the received data string by the PLL circuit 22. It is.

  In this method, since the change in the reproduction speed is directly linked to the change in the operation clock signal of the error correction circuit 27 and the transmission circuit 28, it is not necessary to absorb the time axis fluctuation by the motor 30 by the temporary storage unit 26, but the read speed If the PLL circuit 22 is out of synchronization due to an abrupt change, the frequency of the output recovered clock signal may increase rapidly. In this case, the operating speed of the temporary storage unit 26, the error correction circuit 27, or the transmission circuit 28 may be reduced. The system may malfunction if the limit is exceeded.

  Further, as shown in FIG. 50, the clock signal output from the system reference clock circuit 31 is supplied to the error correction circuit 27 and the transmission circuit 28, and the decoding circuit 24 writes the received data in the temporary storage unit 26, and the transmission. There is a circuit that compares the speed at which the circuit 28 reads transmission data from the temporary storage unit 26 with the speed comparison circuit 35 and changes the interval at which the transmission circuit 28 reads transmission data from the temporary storage unit 26 according to the result.

  In this case, the clock signal supplied to the error correction circuit 27 and the transmission circuit 28 is set to be faster than the speed at which the decoding circuit 24 writes the received data in the temporary storage unit 26. The error correction circuit 27 and the transmission circuit 28 start data processing when a predetermined amount of data (for example, one block of error correction code in the case of a DVD) is stored in the temporary storage unit 26, and end the processing. After that, the processing is stopped until a predetermined amount of next data is stored.

  In this method, the upper limit of the reproduction speed is determined by the frequency of the clock signal from the system reference clock circuit 31, and the frequency of the operation clock of the error correction circuit 27 and the transmission circuit 28 is constant and both operations are guaranteed. Since the error correction circuit 27 and the transmission circuit 28 always operate at a high frequency, as in the case of FIG. 45, there is a problem in unnecessary radiation and an increase in power consumption.

  The object of the present invention is, for example, when the reception state of the information data in the receiving means is disturbed and the data reception is interrupted, or when an unupdated code string remains in the area where writing on the storage means has not been performed However, unlike the prior art, an error correction device capable of preventing erroneous correction when unupdated data remains in the storage means while eliminating the need for a data destruction circuit on the storage means that has already been transmitted. Is to provide.

The error correction apparatus of the present invention includes a receiving means for receiving information data composed of error correction codes, a storage means for writing and storing information data received by the receiving means, and a storage means stored in the storage means. An error correction unit that reads out the information data, detects an error in the information data based on the error correction code, performs a correction process, and writes the information data after the correction process in the storage unit, and is written in the storage unit In what is provided with a transmission means for reading and transmitting information data after correction processing,
Determination means for determining whether or not information data of the number of symbols necessary for error correction has been written to the storage means by measuring the number of symbols of information data received by the reception means and written to the storage means When,
An update position information generating means for generating update position information for a code string of information data written in the storage means based on the determination by the determination means;
The error correction means does not correct a code string of an error correction code whose information data has not been updated based on the update position information generated by the update position information generation means.

  According to the present invention, for example, when the reception state of the information data in the receiving unit is disturbed and the reception of the data is interrupted, an unupdated code string remains in the area where the writing on the storage unit has not been performed. However, the error correction means does not perform the correction process for the code string of the error correction code whose information data has not been updated based on the update position information generated by the update position information generation means. Even without providing a means for destroying the transmitted data on the storage means, it is possible to prevent the error correction means from erroneously correcting uncorrected data or erroneously determining error position information. It is not necessary to increase the data transfer rate with the means, and the configuration of the error correction means and the transmission means becomes easy.

(First embodiment)
A first embodiment in which the error correction apparatus of the present invention is applied to a DVD data reproducing apparatus will be described with reference to FIGS. Note that the same parts as those in FIG. 39 are denoted by the same reference numerals, description thereof is omitted, and only different parts will be described below. In FIG. 1, the temporary storage unit 3 in FIG. 39 is a temporary storage unit (storage means) 41 (FIG. 2) composed of a RAM having storage areas A and B each having a capacity of at least one block of information data. Has been replaced by

Here, for example, in FIGS. 4A and 4B, the storage areas A and B are shown in parallel, but in reality, both are continuous areas in the temporary storage unit 41, and the first address of the storage area B is stored. It is set as an address that follows the last address in area A.
The error correction circuit 4 is replaced with an error correction circuit (error correction means) 42. In the error correction circuit 42, the speed at which correction processing is performed on one block of data is set to be slightly higher than the speed at which the reception circuit 1 performs reception processing on one block of reception data. Other configurations are the same as those shown in FIG.

  Note that the error correction code adopted in the DVD is two codes: an 8-bit symbol (182) PI (inner) code and a PO (outer) code of 208 codes in one code string. It consists of a Reed-Solomon product code consisting of a sequence, and the capacity of one block is 182 × 208 bytes.

  Next, the operation of the present embodiment will be described with reference to FIGS. FIG. 3 is a time chart showing a state in which the storage areas are switched and used when the reception process, the correction process, and the transmission process are performed on the two storage areas A and B of the temporary storage unit 41. FIG. 5 and FIG. 6 show the state of processing performed for each area of the temporary storage unit 41 at the time points a, b, and c shown in FIG.

First, in FIG. 3, for example, in the phase (1), the storage area A is used as a reception data storage area, and the reception circuit 1 is read from the DVD disk by an optical pickup (none of which is shown). After receiving and decoding the information data composed of the error correction code, it is written in the storage area A.
At this time, the storage area B is used as a correction data storage area, and the error correction circuit 42 uses the one block of information data stored in the storage area B that was the reception data storage area in the previous phase. , PI and PO are corrected for two code sequences. When the processing for one block of information data is completed and the process proceeds to phase (2), the storage area B is used as a received data storage area and the storage area A is used as a correction data storage area. In this way, both are used interchangeably.

  Further, as shown in FIG. 3, the speed at which the error correction circuit 42 performs correction processing on one block of information data is set higher than the speed at which the receiving circuit 1 writes one block of received data. As a result, the process ends quickly by time Tm. The time Tm is not always constant and changes according to the fluctuation of the received data writing speed of the receiving circuit 1. However, even when the writing speed reaches the maximum, the time Tm does not become “0”, but a predetermined positive value. It is set to ensure more than the value.

  Here, the time Tm is, for example, an average of one sector (DVD) between the address where the transmission circuit (transmission means) 5 reads and transmits the transmission data and the address where the reception circuit 1 writes the reception data. The time is set to about 2 Kbytes in the data format.

  In addition, in the phase (1), the transmission circuit 5 receives the data in the storage area A that has been corrected in the previous phase at the address preceding the address where the reception circuit 1 has written the data. Reading out. FIG. 2 shows the state of phase (1). When the error correction circuit 42 gives a status signal indicating that the correction processing has been completed for one block of information data, the transmission circuit 5 immediately receives the correction data storage area (for example, phase) immediately after the correction processing is completed. In (1), data transmission is started from the beginning of storage area B) (in phase (2)).

  FIG. 4 shows the state (time point a) in the phase (1). That is, for the storage area B, immediately after the correction process is completed, the transmission circuit 5 starts data transmission from the head address, and the reception circuit 1 writes the received data to the end portion of the storage area A. ing. At this time, the error correction circuit 42 is in a state of waiting for the receiving circuit 1 to finish writing the received data for the storage area A, and no correction processing is performed.

  Next, FIG. 5 shows a state at a time point b immediately after the transition to the phase (2). In other words, the address of the transmission process to the storage area B by the transmission circuit 5 proceeds first, and the reception data is written by the reception circuit 1 from the head address of the storage area B that has already been subjected to the transmission process. Be started. In this case, the interval between the read address of the transmission data and the write address of the reception data is about one sector according to the time Tm as described above. At the same time, correction processing by the error correction circuit 42 for the storage area A is started.

FIG. 6 shows a state at the time point c in the phase (2). In other words, the address of the transmission process for the storage area B by the transmission circuit 5 proceeds further, and the reception circuit 1 follows, and overwrites the received data on the address of the storage area B that has already been transmitted. At this time, the correction process performed by the error correction circuit 42 is performed at least once for each of the two series of PI and PO for one block of information data in the storage area A. It is not shown whether the process is being performed.
As described above, when one of the two storage areas A and B of the temporary storage unit 41 is a correction data storage area, the other storage area is used as both a transmission data reading area and a reception data storage area. It has become.

  As described above, according to the present embodiment, correction processing is performed on the temporary storage unit 41 having two storage areas A and B each having a capacity of at least one block of the error correction code and one block of the error correction code. The transmission circuit 5 includes an error correction circuit 42 whose time is shorter by the time Tm than the time when the reception circuit 1 performs reception processing on one block of reception data, and the transmission circuit 5 includes information data after the error correction circuit 42 performs correction processing of one block. As soon as writing to the correction data storage area is completed, the correction data storage area is used as a transmission data reading area, and the information data after the correction processing is read out from the head address and transmitted.

  Therefore, the reception circuit 1 can share one area as a transmission data read area and a reception data storage area by writing the reception data to an address after the transmission circuit 5 has already transmitted data in the transmission data reading area. Therefore, the temporary storage unit 41 may be provided with a capacity for at least two blocks of information data without providing an independent transmission data storage area. 2/3.

  In addition, by making the correction processing time of the error correction circuit 42 shorter by the time Tm than the reception processing time, it is sufficient to secure a time that the transmission processing by the transmission circuit 5 slightly precedes the reception processing. It is not necessary to provide a configuration for shortening the processes of the correction circuit 42 and the transmission circuit 5 within the reception processing time, and the configuration of the error correction circuit 42 and the transmission circuit 5 becomes easy.

(Second embodiment)
7 to 9 show a second embodiment of the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals and the description thereof is omitted, and only different parts will be described below. In FIG. 7 showing the electrical configuration, in the configuration of the second embodiment, the transmission circuit 5 in the configuration of the first embodiment is replaced with a transmission circuit (transmission means) 43, and other configurations are the same as in the first embodiment. It is.

  Here, as shown in FIG. 8, the speed at which the receiving circuit 1 writes the received data in the temporary storage unit 41 is Vin, and the speed at which the transmission circuit 43 reads the transmission data from the temporary storage unit 41 is Vout. The writing speed Vin varies, for example, when DVD data is played back at high speed or when the data reading linear speed is changed when searching for specific data, or when the tracking position of the pickup is moved. As shown in FIG. 9, the reading speed Vout of the transmission circuit 43 is set to a value higher than the maximum speed Vin (max) of the fluctuating writing speed Vin (Vout> Vin (max)).

  According to the second embodiment configured as described above, even when the reception circuit 1 writes the reception data at the address after the data has already been transmitted by the transmission circuit 43 in the transmission data reading area, the transmission circuit 43 Since the read speed Vout is always faster than the write speed Vin of the receiving circuit 1, even if the write speed Vin fluctuates, the former read address does not catch up with the latter write address, and the data before transmission is destroyed. Can be reliably prevented.

(Third embodiment)
FIG. 10 shows a third embodiment of the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Only different parts will be described below. In FIG. 10 showing the electrical configuration, in the configuration of the third embodiment, the transmission circuit 5 in the configuration of the first embodiment is replaced with a transmission circuit (transmission means) 44.

  A control signal for controlling the data reading speed Vout is compared by referring to the data writing speed Vin of the receiving circuit (receiving means) 1 'and the data reading speed Vout of the transmitting circuit 44 and comparing them. A speed comparison circuit (reading speed control means) 45 that outputs to 44 is provided, and the transmission circuit 44 changes the reading speed Vout according to the control signal. Other configurations are the same as those of the first embodiment.

  Next, the operation of the third embodiment will be described. The speed comparison circuit 45 compares the write speed Vin with the read speed Vout so that the read speed Vout is always higher than the write speed Vin even when the write speed Vin varies as shown in FIG. 9 of the second embodiment. A control signal is given to the transmission circuit 44 so as to increase the speed. Since the transmission circuit 44 dynamically changes the reading speed Vout according to the given control signal, for example, it is possible to perform control so that the speed difference between the two is always maintained constant.

According to the third embodiment configured as described above, the speed comparison circuit 45 gives a control signal to the transmission circuit 44 so that the read speed Vout is always higher than the write speed Vin, so that the write speed Vin varies. Even in this case, the former read address is not caught up with the latter write address, and it is possible to reliably prevent the data before transmission from being destroyed as in the second embodiment.
Further, since the transmission circuit 44 dynamically changes the read speed Vout in accordance with the control signal given from the speed comparison circuit 45, unlike the second embodiment, the read speed Vout is set to the maximum speed Vin of the write speed Vin. It is not necessary to set a constant value so as to be faster than (max), and power consumption and unnecessary radiation can be further reduced.

(Fourth embodiment)
FIG. 11 shows a fourth embodiment of the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. Only different parts will be described below. In FIG. 11 showing the electrical configuration, in the configuration of the fourth embodiment, the receiving circuit 1 is replaced with a receiving circuit (receiving means) 46, and the received data write address to the temporary storage unit 41 of the receiving circuit 46 is shown. And an address comparison circuit (write stop means) 47 for comparing the transmission data with reference to the read address of the transmission data from the temporary storage unit 41 of the transmission circuit 5.

The address comparison circuit 47 refers to and compares the write address of the received data and the read address of the transmission data, and monitors whether the interval between both addresses is maintained at a predetermined value (for example, one sector) or more. It is supposed to be. That is, if the data reception, correction and transmission processes are normally performed, the interval between both addresses is maintained at a predetermined value or more.
When the interval between both addresses falls below a predetermined value, the data in the temporary storage unit 41 that has not been transmitted after correction processing may be destroyed. A write stop signal is output (storage control), and the receiving circuit 46 stops receiving data when a write stop signal is given.

  Further, the address comparison circuit 47 outputs a status signal indicating whether or not the data reception processing in the receiving circuit 46 is normally performed to the system microcomputer 48. The system microcomputer 48 receives the status signal. For example, user interface processing or the like is performed. The system microcomputer 48 controls the entire system in the DVD playback apparatus. Other configurations are the same as those of the first embodiment.

  According to the fourth embodiment configured as described above, for example, when the reception circuit 46 cannot receive the sector ID or the like of the reception data due to the disturbance of the reception sequence, the temporary storage unit 41 of the reception circuit 46, for example. When the write address for the address flew to approach the read address of the transmission circuit 5 and the interval between both addresses falls below a predetermined value, the address comparison circuit 47 stops writing the received data by the reception circuit 46. It is possible to prevent the unsent data from being destroyed.

(5th Example)
FIG. 12 shows a fifth embodiment of the present invention. The same parts as those in the first or fourth embodiment are denoted by the same reference numerals and description thereof is omitted, and only different parts will be described below. In FIG. 12 showing the electrical configuration, in the configuration of the fifth embodiment, the received data write address to the temporary storage unit 41 of the reception circuit 1 and the transmission data read address from the temporary storage unit 41 of the transmission circuit 5 are set. An address comparison circuit (data destruction determination means) 49 for comparison with reference is provided.

As with the address comparison circuit 47 in the fourth embodiment, this address comparison circuit 49 refers to and compares the write address of the received data and the read address of the transmission data, and whether the former address is equal to the latter address. Alternatively, in the case of preceding, it is determined that the untransmitted information data after the correction process in the temporary storage unit 41 has been destroyed.
The address comparison circuit 49 outputs a status signal to the system microcomputer 50 when it is determined that the untransmitted information data is destroyed, and the system microcomputer 50 responds to the status signal by, for example, a user interface. Processing is to be performed. Other configurations are the same as those of the first embodiment.

  According to the fifth embodiment configured as described above, for example, when the write address of the reception circuit 1 is equal to or precedes the read address of the transmission circuit 5 due to some cause, the temporary storage unit 41 Therefore, the address comparison circuit 49 determines that the data has been destroyed, so that the external processing system existing after the system microcomputer 50 and the transmission circuit 5 Based on the determination result, it is possible to appropriately handle the destroyed data (for example, reread the corresponding data portion).

The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The arbiter in each embodiment may be integrated with the storage means. The arbiter function may be distributed to the receiving means, error correcting means, and transmitting means, and the access arbitration may be performed by mutually giving access requests to the storage means.

The storage means in the first to fifth embodiments need only have at least one block of error correction code as the capacity of each storage area, and may have a capacity larger than one block.
In addition, the storage means in the first to fifth embodiments is not necessarily configured by one storage element (RAM or the like). For example, two storage elements having a capacity of at least one block of error correction code The access from the receiving means, error correcting means, and transmitting means may be arbitrated.

The address comparison circuit 47 in the fourth embodiment may also have a function as data destruction determination means in the fifth embodiment.
The present invention is not limited to a DVD data reproducing apparatus, and can be applied to any apparatus that reproduces data composed of block-complete error correction codes.
The error correction code is not limited to a product code and may be one series.

(Sixth embodiment)
FIGS. 13 to 15 show a sixth embodiment in which the error correction apparatus of the present invention is applied to a DVD data reproducing apparatus. The same parts as those in FIG. Only different parts will be described below.
The receiving circuit (receiving means) 6 receives a signal optically read from a DVD disk by a pickup (not shown). The receiving circuit 6 receives a synchronization signal arranged at the head of every frame in the DVD data format.

  Further, the receiving circuit 6 latches the latch pulse so as to coincide with the input timing of 182 bytes of data per two frames in the PI series based on the clock signal generated from the received data string by the built-in PLL circuit (not shown). A signal is generated, and each 182 byte data (one byte unit symbol) is latched by the latch pulse signal to perform reception processing. Thereafter, the received data is subjected to 8-16 demodulation (the data converted to 16 bits when data is recorded on the disk is returned to the original 8-bit data) and the like, and then written into the temporary storage unit 8.

  In FIG. 13, a measurement / determination circuit (syndrome determination means) 51 that receives these various signals via the reception circuit 6 is provided. The measurement / judgment circuit 51 counts the number of output latch pulses from the time when the synchronization signal is output, so that the reception circuit 6 determines whether the count value is 182 (predetermined value) per two frames. It is determined whether or not 182 symbols are correctly received per two frames, and an invalid determination signal (determination information) is output to an error correction circuit (error correction means) 52.

The PI syndrome calculation circuit (syndrome calculation means) 53 obtains information data directly from the reception circuit 6 and calculates the syndrome from the PI series error correction code in the DVD data so as to output the calculation result to the error correction circuit 52. It has become.
FIG. 14 shows a data arrangement for one block of error correction codes employed in DVD data. The source data of DVD constitutes one sector with 2K bytes as a unit, and an error correction code is added every 16 sectors, and one block is constituted by 32K bytes of source data.

The error correction code of one block includes an inner code PI having parameters (m = 8, n = 182, k = 172, d = 11) and parameters (m = 8, n = 208, k = 192, d = 17) and a Reed-Solomon product code consisting of two code sequences with an outer code PO.
Here, each parameter indicates the following contents.
m: Code length of 1 symbol n: Number of symbols in one code string k: Number of symbols other than parity in the number of symbols in one code string d: Minimum distance between codes In other words, they are arranged in the column direction in FIG. The inner code PI (d0,0, d0,1, d0,2,..., D0,181,...) Is a code sequence in which 182 symbols having a code length of 8 bits are arranged. Of the (bytes), the main data is 172 symbols, and the parity generated from these main data is 10 symbols.

  Further, in the outer code PO (d0,0, d1,0, d2,0,..., D207,0,...) Arranged in the row direction in FIG. 14, 208 symbols having a code length of 8 bits are arranged. The code series includes 192 symbols for main data and 16 symbols for parity. The main data excluding the parity is 172 × 192 = 32.25 (K bytes), and 0.25 K bytes other than the source data are the sector ID, the EDC that is the parity, and the reserve.

  The correction capability of the error correction code configured as described above can be corrected up to 5 symbols for the inner code PI and up to 8 symbols for the outer code PO depending on the calculation result of the syndrome in its own code sequence. . Further, by using error detection position information obtained from the syndrome calculation result in the other code sequence as an erasure pointer, erasure correction is performed up to 10 symbols for the inner code PI and up to 16 symbols for the outer code PO. be able to.

  The actual data reception order is as follows: d0,0, d0,1, d0,2,..., D0,181, d1,0, d1,1, d1,2, ..., d207,180, d207,181 For the inner code PI, the actual data reception order and the error correction code sequence are the same.

  Next, the operation of the sixth embodiment will be described with reference to FIG. FIG. 15 is a flowchart showing the control content of the correction processing performed by the error correction circuit 52. In FIG. 15, the error correction circuit 52 first calculates the calculation results of syndromes SI0 to SI9 of the PI code string output from the PI syndrome calculation circuit 53 depending on whether or not the invalidity determination signal is output from the measurement / determination circuit 51. It is determined whether or not can be used as valid (step X1).

  If the calculation result of the syndrome is valid, it is determined from the calculation results of the syndromes SI0 to SI9 whether or not there is an error in the symbol data (step X4). If the calculation results of all the syndromes SI0 to SI9 are "0", there is no error in the symbol data of the code string, and the process proceeds to step X8. If all 208 columns have not been processed and if this is the first correction process for the PI code (step X8a), the process proceeds to step X1.

  Further, in the measurement / determination circuit 51, when the number of latch pulses output from the time when the synchronization signal is output is not “182” per two frames (for example, “182 due to partial omission of symbol data”). When the value is smaller than “or” or when the noise is superimposed on the latch pulse and larger than “182”, an invalid determination signal is output from the measurement / determination circuit 51, and the syndromes SI0 to SI9 are calculated. The result is shown to be invalid. In this case, the error correction circuit 52 determines “NO” in step X1, and proceeds to step X7 without performing determination / correction based on the calculation results of the syndromes SI0 to SI9.

  On the other hand, if it is determined in step X4 that there is an error, the error correction circuit 52 determines whether or not the error can be corrected from the values of the syndromes SI0 to SI9 (step X5) and can be corrected. In this case, the error size and error position (error position) are obtained based on the syndromes SI0 to SI9. These calculation results are written and stored in a RAM (work area) (not shown) built in the error correction circuit 52.

  Then, the error correction circuit 52 reads the symbol data corresponding to the error position after the reception circuit 6 finishes writing the received data on the temporary storage unit 8, and adds the error magnitude value to the data value. As a result, the data is corrected and written back on the temporary storage unit 8 (step X6). If the data is uncorrectable, error position information indicating that there is an uncorrectable error in the PI code string is set (step X7).

  If all 208 columns of the PI code string of one block are processed and “YES” is determined in step X8, correction processing is performed for 182 columns of the PO code string in steps X9 to X16. In this PO code string correction process, erasure correction can be performed using the error position information of the PI code string set in step X7 (steps X12 and X13).

  When processing is performed for all 182 columns of the PO code string of one block and “YES” is determined in step X15, it is determined whether or not correction processing is further performed in the next step X16, and the correction processing is continued. Then, the error correction circuit 52 reads the data of the PI code string from the temporary storage unit 8, and calculates syndromes SI0 to SI9 based on the read data (steps X2 and X3).

  That is, the error correction circuit 52 refers to the PI code string syndromes SI0 to SI9 given from the PI syndrome calculation circuit 53 only in the correction process of the first PI code string. In the second and subsequent correction processes, the data of the PI code string is read from the temporary storage unit 8 (determined as “NO” in step X8a), and the syndromes SI0 to SI9 are calculated by themselves based on the read data. This is because there is a possibility that the symbol data corrected by the correction processing of the first PI code string may exist, so the syndromes SI0 to SI9 are calculated based on the data read from the temporary storage unit 8 after the second time. This is because the possibility of correcting the data is higher.

  As described above, according to the sixth embodiment, the measurement / judgment circuit 51, based on the data reception state in the reception circuit 6, specifically, the reception circuit 6 receives 182 symbols of data per two frames. If the invalidity determination signal is not output from the measurement / determination circuit 51, the error correction circuit 52 uses the syndromes SI0 to SI9 calculated by the PI syndrome calculation circuit 53 as the first PI code string. The error determination and correction are performed by using the correction process, and when the invalid determination signal is output, the correction process is not performed on the code string.

  Therefore, the error correction circuit 52 uses the PI series syndromes SI0 to SI9 calculated in advance by the PI syndrome calculation circuit 53, so that the first correction process of the PI code string temporarily stores received data for one block. The process can be started without waiting until all the data is written in the unit 8, and the time required for the correction process can be shortened. The error correction circuit 52 reads the PI code string data from the temporary storage unit 8 in the second and subsequent correction processes of the PI code string, and calculates the syndromes SI0 to SI9 by itself based on the read data. The possibility of correction can be further increased.

  Further, the error correction circuit 52 uses the invalidity determination signal output from the measurement / determination circuit 51 to determine the validity of the syndromes SI0 to SI9 calculated in advance by the PI syndrome calculation circuit 53 (whether the calculation is based on the correct number of symbols). Therefore, the past meaningless data remaining on the temporary storage unit 8 is not erroneously determined or corrected by the calculated values of the syndromes SI0 to SI9 that are not calculated in the correct state. Therefore, for example, noise is not suddenly generated in the reproduction of video or musical sound using DVD data, and the reliability can be further improved.

(Seventh embodiment)
FIGS. 16 and 17 show a seventh embodiment in which the error correction apparatus of the present invention is applied to a CD data reproducing apparatus. The same parts as those in FIG. Only different parts will be described below. The receiving circuit (receiving means) 54 receives a signal optically read from a CD disk by a pickup (not shown). The receiving circuit 54 receives a synchronization signal arranged at the head of each frame (588 channel bits) in the CD data format.

One frame in the CD data format is
Frame synchronization signal: 24 bits
Sub-coding: 14 bits (1 symbol)
Data and parity: 14 x 32 bits (32 symbols)
Bits for combining symbols: A total of 3 × 34 bits or more is 588 channel bits.

  The receiving circuit 54 generates a latch pulse signal so as to coincide with the input timing of 32 bytes of data per frame based on a clock signal generated from received data by a built-in PLL circuit (not shown). On the basis of the latch pulse signal, each 32-byte data (symbol in 1-byte units) is latched to perform reception processing. Thereafter, the received data is subjected to EFM (Eight to Fourteen Modulation) demodulation (the data converted to 14 bits when recorded on the disk is restored to the original 8-bit data) and the like, and then written to the temporary storage unit 8 It is.

  In FIG. 16, a measurement / determination circuit (syndrome determination means) 55 for receiving these various signals via the reception circuit 54 is provided. The measurement / determination circuit 55 determines whether or not the reception circuit 54 has correctly received a 32-byte symbol per frame from these various signals, and outputs an invalid determination signal (determination information) to a switching circuit (syndrome output). (Switching means) 56.

When the C1 syndrome calculation circuit (syndrome calculation means) 57 obtains the information data directly from the reception circuit 54 and calculates the syndromes S10 to S13 from the C1 sequence error correction code in the CD data, the calculation result is output to the switching circuit 56. It is like that.
When the invalidity determination signal is not output from the measurement / determination circuit 55, the switching circuit 56 outputs the syndrome value calculated by the C1 syndrome calculation circuit 53 to the error correction circuit (error correction means) 58 as it is. When the invalidity determination signal is output, an arbitrary uncorrectable syndrome value held in advance by itself is output to the error correction circuit 58 instead of the syndrome value calculated by the C1 syndrome calculation circuit 57. It is supposed to be.

  Note that the error correction code employed in the CD data includes a C1 code string having parameters (m = 8, n = 32, k = 28, d = 5) and parameters (m = 8, n = 28, k = 24, d = 5) and a Reed-Solomon product code consisting of two code sequences with a C2 code string. That is, in any code string, error correction can be performed up to two symbols (= (d−1) / 2 = (5-1) / 2).

  Further, since the C2 code string is a (interleaved) series of data of 32 symbols of one frame of the C1 code string every four frames (first frame first symbol-fifth frame second symbol -...), the C1 series The error position information obtained in the error correction can be used as an erasure pointer for erasure correction of the C2 code string. Conversely, the error position information obtained in the correction process of the C2 sequence is the C1 code. Cannot be used for column erasure correction. Therefore, erasure correction of up to 4 symbols can be performed only for the C2 sequence.

  Next, the operation of the seventh embodiment will be described with reference to FIG. When the measurement / determination circuit 55 obtains the synchronization signal for each frame of the CD data and the latch pulse signal generated inside the reception circuit 54 via the reception circuit 54, the measurement / determination circuit 55 generates the latch pulse signal from the time when the synchronization signal is output. The number of outputs is counted, and whether or not the count value is “32 (predetermined value)”, that is, whether or not the latch pulse signal is output for 32 symbols before the synchronization signal of the next frame is output. Thus, it is determined whether or not 32 symbols of data can be received per frame.

  If data of 32 symbols per frame can be received, the syndrome calculated by the C1 syndrome calculation circuit 57 should be calculated based on the data of these 32 symbols, and it is determined that the calculation result is correct. be able to. In this case, since the measurement / determination circuit 55 does not output an invalid determination signal, the switching circuit 56 outputs the syndrome value calculated by the C1 syndrome calculation circuit 57 to the error correction circuit 58 as it is.

  On the other hand, data reception is not normally performed due to some disturbance in the reception process in the reception circuit 54, and the number of latch pulse signals output from the time when the synchronization signal is output in the measurement / determination circuit 55 is 32. If they do not match, the syndrome calculated by the C1 syndrome calculation circuit 57 is not calculated based on the data of 32 symbols, and it can be determined that the calculation result is not correct.

In this case, the measurement / determination circuit 55 outputs an invalid determination signal to the switching circuit 52. Then, the switching circuit 56 outputs an uncorrectable syndrome to the error correction circuit 58 based on the invalidity determination signal.
Here, FIG. 17 is a flowchart showing the contents of the correction processing of the error correction circuit 58. When the error correction circuit 58 obtains the calculation results of the C1 series syndromes S10 to S13 calculated in advance by the C1 syndrome calculation circuit 57 (step Y1), whether or not there is an error in the symbol data from the calculation result of the syndromes. Is determined (step Y4).

  The subsequent processing is basically changed to processing contents adapted to the data format of the CD based on the flowchart shown in FIG. As described above, the error correction code employed in the CD data is a so-called incomplete type in which the C2 code string is interleaved with the C1 code string. That is, there is no concept of “block” as in the case of error correction code (complete type) in DVD data.

One C2 code string is completed when 109 C1 codes (frames) are aligned (when written in the temporary storage unit 8). Therefore, in the case of CD data, the correction processing of the C1 code string and the C2 code string is performed alternately one by one, and the processes corresponding to steps X8, X8a, and X15 in FIG. 15 are deleted.
In addition, the process corresponding to step X14 is also deleted. This is also because the error position information obtained by the C2 sequence correction process cannot be used for erasure correction of the C1 code string as described above.

  In the flowchart of FIG. 17, when data is not normally received, the measurement / determination circuit 55 outputs an invalid determination signal, and the switching circuit 52 outputs an uncorrectable syndrome to the error correction circuit 58. The error correction circuit 58 determines “YES” in step Y4 and “NO” in step Y5, and sets error position information indicating that there is an uncorrectable error in the C1 code string (step Y7).

As described above, according to the seventh embodiment, the measurement / determination circuit 55 determines whether or not the reception circuit 54 is receiving 32 symbols of data per frame, and the switching circuit 56 is the measurement / determination circuit. If the invalidity determination signal is not output from 55, the syndrome calculated by the C1 syndrome calculation circuit 57 is output to the error correction circuit 58 as it is, and if the invalidity determination signal is output, the syndrome is previously held by itself. Any syndrome that cannot be corrected is output to the error correction circuit 58.
Accordingly, the error correction circuit 58 does not perform erroneous correction on past meaningless data remaining in the temporary storage unit 8, and thus, for example, noise is suddenly generated in the reproduction of a musical sound or the like using CD data. The reliability can be further improved.

(Eighth embodiment)
FIG. 18 shows an eighth embodiment of the present invention. The same parts as those in the seventh embodiment are designated by the same reference numerals and the description thereof is omitted. Only the different parts will be described below. In FIG. 18, the switching circuit 56 is deleted from the configuration of the seventh embodiment shown in FIG. 16, and the syndrome value output from the C1 syndrome calculation circuit 57 and the invalidity determination signal output from the measurement / determination circuit 55 are Is also provided directly to an error correction circuit (error correction means) 58 '. Other configurations are the same as those of the seventh embodiment.

  Next, the operation of the eighth embodiment will be described. The operation of the eighth embodiment is to perform the flowchart shown in FIG. 15 of the sixth embodiment in accordance with the data format of the CD. That is, the error correction circuit 58 ′ does not perform error correction based on the syndrome value output from the C1 syndrome calculation circuit 57 when the invalidity determination signal is output from the measurement / determination circuit 55.

  According to the eighth embodiment configured as described above, the error correction circuit 58 ′ does not perform unnecessary error correction processing by directly obtaining the invalidity determination signal output from the measurement / determination circuit 55. Processing can be performed more efficiently. Further, since the switching circuit 56 in the seventh embodiment is not required, the whole can be configured in a small size.

(Ninth embodiment)
FIG. 19 shows a ninth embodiment of the present invention. The same parts as those in the seventh embodiment are designated by the same reference numerals and the description thereof is omitted. Only the different parts will be described below. In FIG. 19, the measurement / determination circuit 55 in the configuration of the seventh embodiment shown in FIG. 16 is replaced with a determination circuit (syndrome determination means) 59. Other configurations are the same as those of the seventh embodiment.

  The determination by the determination circuit 59 is different from the measurement / determination circuit 55 in the seventh embodiment, and the clock signal generated by the PLL circuit from the received data indicates the reception interval of the synchronization signal received for each frame by the reception circuit 54. Whether or not the data reception processing by the reception circuit 54 is normal is determined based on whether or not the reception interval is 588 channel bits. Other operations are the same as in the seventh embodiment. Also in the ninth embodiment configured as described above, the same effects as in the sixth embodiment can be obtained.

The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The arbiter in each embodiment may be integrated with the storage means. The arbiter function may be distributed to the receiving means, error correcting means, and transmitting means, and the access arbitration may be performed by mutually giving access requests to the storage means.

In the sixth embodiment, the correction process of the PO code string in steps X9 to X16 may be performed first, and then the PI code string in steps X1 to X8 may be corrected. Similarly, in the seventh embodiment, the correction process for the C1 code string in steps Y1 to Y8 may be performed after the correction process for the C2 code string in steps Y9 to Y15 is first performed.
In the sixth embodiment, the error correction circuit 52 first performs correction processing of the PO code string, and uses the calculation results of the syndromes SI0 to SI9 of the PI code string as the erasure pointer to obtain the first PO code string. It may be used for erasure correction in correction processing. With such a configuration, it is possible to correct more symbol data from the first correction process.

In the sixth embodiment, the calculation result of the syndrome may be given to the error correction circuit 52 via the switching circuit 56 as in the seventh embodiment.
Further, in the sixth and eighth embodiments, the calculation processing up to the correction of the symbol data is performed by the syndrome calculation means, and the error correction means has only a function of writing the corrected data back to the storage means. May be. In this case, when an invalidity determination signal is output by the determination unit, the error correction unit stops writing back the corrected data in the storage unit.

The ninth embodiment may be applied to a DVD, and the calculation result of the syndrome may be determined depending on whether or not a synchronization signal for each frame is received for every 1488 channel bits of the received data string.
When the correction process for one error correction code string is performed only once, when steps X2, X3, X8 and X16 are deleted from the flowchart shown in FIG. 15 and “NO” is determined in step X8, It is sufficient to move directly to step X1. Similarly, in the case of the flowchart shown in FIG. 17, steps Y2, Y3, and Y16 may be deleted.

The present invention is not limited to DVD and CD data reproducing apparatuses, and can be applied to any apparatus that reproduces data composed of error correction codes.
The error correction code is not limited to a product code and may be one series.

(Tenth embodiment)
FIGS. 20 to 27 show a tenth embodiment in which the error correction apparatus of the present invention is applied to a DVD data reproducing apparatus. The same parts as those in FIG. Only different parts will be described below. First, an error correction code employed in DVD data will be described with reference to FIG.

FIG. 21 shows an arrangement for one block of the error correction code. The source data of DVD constitutes one sector with 2K bytes as a unit, and an error correction code is added every 16 sectors, and one block is constituted by 32K bytes of source data.
The error correction code of one block includes an inner code PI having parameters (m = 8, n = 182, k = 172, d = 11) and parameters (m = 8, n = 208, k = 192, d = 17) and a Reed-Solomon product code consisting of two code sequences with an outer code PO.

Here, each parameter indicates the following contents.
m: Code length of 1 symbol n: Number of symbols in one code string k: Number of symbols other than parity in the number of symbols in one code string d: Minimum distance between codes In other words, they are arranged in the column direction in FIG. The inner code PI (d0,0, d0,1, d0,2,..., D0,181,...) Is a code sequence in which 182 symbols having a code length of 8 bits are arranged. Of the (bytes), the main data is 172 symbols, and the parity generated from these main data is 10 symbols. In the outer code PO (d0,0, d1,0, d2,0,..., D207,0,...) Arranged in the row direction in FIG. 21, 208 symbols having a code length of 8 bits are arranged. The code series includes 192 symbols for main data and 16 symbols for parity.

The main data excluding the parity is 172 × 192 = 32.25 (K bytes), and 0.25 K bytes other than the source data are the sector ID, the EDC that is the parity, and the reserve.
The correction capability of the error correction code configured as described above is based on the calculation result of the syndrome in its own code sequence, up to 5 symbols (1/2 of the number of parity symbols) for the inner code PI, and for the outer code PO. Can correct errors up to 8 symbols (1/2 of the number of parity symbols).

  In addition, the product code has a property that error detection position information obtained from the syndrome calculation result in one code sequence can be used as erasure pointer for erasure correction in the other code sequence. By utilizing this property, erasure correction can be performed up to 10 symbols (the same number as the number of parity symbols) for the inner code PI and up to 16 symbols (the same number as the number of parity symbols) for the outer code PO.

The actual data reception order is as follows: d0,0, d0,1, d0,2,..., D0,181, d1,0, d1,1, d1,2, ..., d207,180, d207,181 For the inner code PI, the actual data reception order and the error correction code sequence are the same.
In FIG. 20 showing the functional blocks of the electrical configuration, the data destruction circuit 17 is deleted from the conventional configuration shown in FIG. The error correction circuit 15 is replaced with an error correction circuit (error correction means) 60.

  The receiving circuit (receiving means) 12 receives a synchronizing signal arranged at the head of every frame (91 bytes) in the DVD data format. The receiving circuit 12 generates a latch pulse signal so as to coincide with the input timing of 182 bytes of data per two frames based on a clock signal generated from received data by a built-in PLL circuit (not shown). On the basis of the latch pulse signal, each 182-byte data (symbol) is latched to perform reception processing.

The measurement / determination circuit (determination means) 61 obtains a synchronization signal and a latch pulse signal via the reception circuit 12, and counts the number of latch pulse signals, whereby 182 bytes of data are received per two frames (PI code string). It is determined whether or not it has been performed, and the determination result is output to an update position information generation circuit (update position information generation means) 62.
Based on the determination result from the measurement / determination circuit 61, the update position information generation circuit 62 has received data normally for each of the 208 symbol PI code strings per block, that is, the temporary storage unit ( Storage means) 14 generates update position information indicating whether or not the data on 14 is updated, and outputs it to the error correction circuit 60. The error correction circuit 60 performs error correction as described below based on the given update position information.

  Next, the operation of the tenth embodiment will be described with reference to FIGS. FIG. 22 is a flowchart showing the content of the correction process performed by the error correction circuit 60. First, the error correction circuit 60 refers to the update position information generated by the update position information generation circuit 62, determines whether or not the data in the first column of the PI code has been updated (step A1), and the data Is updated, the PI code in the first column is read from the temporary storage unit (RAM) 14 (step A2).

  Then, correction calculation is performed by calculating ten syndrome calculation formulas SI0 to SI9 for the PI code in the first column (step A3), and correction processing is performed based on the result. If all the calculation results of the syndrome calculation formulas SI0 to SI9 are "0", there is no error in all the symbols in the first column, so no correction is necessary, and the process proceeds from step A4 to step A8. If all the calculation results of the syndrome calculation formulas SI0 to SI9 are not "0", there is an error in any of the symbols in the first column, so that the process proceeds to step A5 to determine whether or not the error can be corrected. to decide.

  When error correction is possible, that is, when the number of symbols with errors is 5 or less, the syndrome calculation formula SI0 calculates the error magnitude (if there are multiple symbols with errors) Error vector e, which is the sum (ei + ej +...)), And by adding the calculation results of the syndrome calculation formulas SI1 to SI9, the error position i indicating the position of the symbol in which the error has occurred, and the error If there are a plurality of symbols in which the error occurs, the magnitude of error for each symbol is obtained.

  Then, the error can be corrected by adding the magnitude ei of the error to the value di 'of the received symbol in which the error has occurred (di = di' + ei). If the error can be corrected, the corrected symbol data is written in the temporary storage unit (RAM) 14 (step A6). Next, in step A8, it is determined whether or not all the 208 columns of PI codes have been processed. If all of the PI codes have been processed, the process proceeds to step A9 and correction processing for the PO code sequence is started. If all 208 columns have not been processed, the process proceeds to step A1, and correction processing is performed on the next column of the PI code.

  On the other hand, if it is determined in step A1 that the data has not been updated and if it is determined in step A5 that error correction is impossible, for example, a storage area for error position information in the work area (memory) of the error correction circuit 60 Is set to error position information indicating that an error exists in the code string (step A7), and the process proceeds to step A8.

  Subsequent steps A9 to A15 basically perform the processing of steps A2 to A8 for the 182 columns of PO codes. However, in steps A12 and A13, in addition to error correction based on the calculation results of the 16 syndrome calculation formulas SO0 to SO15, the error position information obtained in the PI code string correction processing (step A7) is erased. Erasure correction can also be performed as a pointer. In the erasure correction, even if the number of symbols is unknown up to 16, if the position of the unknown is known, the unknown value is obtained by solving the 16-ary simultaneous equations composed of 16 syndromes SO0 to SO15. It is something that can be done.

  In step A13, the number of correction columns is counted every time error correction is performed. After all 182 columns have been processed, it is determined whether the number of corrected columns exceeds the error correction capability “5” of the PI code (step A16). If it exceeds “5”, update is performed. When the updated position information generated by the position information generation circuit 62 is cleared (step A17) and the correction process is continued, the process proceeds from step A18 to step A1, and the correction process is performed again on the PI code string. If the number of correction columns does not exceed “5”, the process proceeds to step A18.

  In the correction process for the PI code string again, based on the error position information obtained in the PO code string correction process (step A14), the number of symbols up to 10 can be calculated using 10 syndrome calculation formulas SI0 to SI9. Erasure correction can also be performed. It should be noted that the number of times the correction process is repeated in step A18 may be appropriately set according to the margin of the correction process time, the degree of required symbol data reliability, and the like.

  Here, the data correction capability in the tenth embodiment will be described more specifically with reference to FIGS. 23 and 24 show an example of a processing form according to the tenth embodiment. For convenience of illustration, the number of symbols of the PI code is 20, and the number of symbols of the PO code is 16. Although the sizes of the areas are different in each figure, areas A and C indicate areas where there is an error in symbol data, and area B indicates an unupdated area where symbol data has not been updated. In each figure, it is assumed that only a code string having only a portion related to the area B where the areas A and C do not exist can be corrected in the PO code string.

  First, in the state shown in FIG. 23, the PI code 4 columns in the region B are not updated, and the updated position information indicating the unupdated state generated by the update position information generating circuit 62 is assigned in advance to the four columns. Has been. Then, it is assumed that the number of correction strings in the PO code string correction process is “3” (see FIG. 23B). In this case, since the number of correction columns “3” is (≦ 5), the error correction circuit 60 determines “NO” in step A16, and updates the PI code 4 columns in the region B in the next step A1. It is determined as “NO” based on the position information, and correction is not performed. Accordingly, erroneous determination does not occur (see FIG. 23C).

  In FIG. 24, as in FIG. 23, update position information indicating an unupdated state is assigned to the PI code 4 columns in the region B. However, the number of correction columns in the PO code string correction process is “8”. Suppose that there was (refer FIG.24 (b)). In this case, since the number of correction columns “8” is (> 5), the error correction circuit 60 determines “YES” in step A16 and clears the update position information in the next step A17 for the reason described later. Like to do. Therefore, in this case, correction is performed based on the error position information. However, since error correction is impossible, correction is not performed even if correction processing is performed normally without referring to the update position information. The determination does not occur (see FIG. 24C).

  In the case of FIG. 24, in order to simply prevent erroneous determination / correction, it is sufficient to always prohibit the correction process by referring to the update position information. However, when the number of correction data in the PO code string is very large. In the next correction process in the PI code string, since there is a possibility of correction even for unupdated data, the correction process is performed as usual without referring to the update position information.

Here, for comparison, FIG. 25 and FIG. 26 do not use the data destruction circuit 17 and the update position information generation circuit 62 in this embodiment in the error correction device in the same state as FIG. 23 and FIG. In addition, an example of a processing form when steps A16 and A17 are not included in the flowchart of FIG. 22 is shown.
In FIG. 25, since the number of correction strings in the correction process of the PO code string is “3”, when the correction process is next performed on the PI code string, since the area B has not been updated, the correction has already been performed in the previous time. Since 3 symbols have been corrected for each column from the state in which processed data remains, that is, the state where there was no error originally, the PI code sequence is within a range where error correction is possible. Accordingly, the data is further corrected and the data is returned to the original unupdated state, and the error position information becomes “O”. However, since the unupdated data is only restored, an erroneous determination is made (FIG. 25C). reference).

  In FIG. 26, since the number of correction strings in the correction process of the PO code string is “8 (> 5)”, when the correction process is next performed on the PI code string, the region B is not updated and originally contains an error. Since 8 symbols are corrected for each column from the state where there is no error, error correction in the PI code sequence is impossible. Therefore, in this case, the result is the same as that shown in FIG. 24 (see FIG. 26C).

  As described above, according to the tenth embodiment, the reception state of the information data in the reception circuit (reception means) 12 is disturbed, the data reception is interrupted, and the data on the temporary storage unit 14 is not written. Even if data of an unupdated PI code string remains in the area, the error correction circuit 60 determines the PI code string whose information data has not been updated based on the update position information generated by the update position information generation circuit 62. Did not make corrections.

Therefore, unlike the prior art, it is possible to prevent erroneous correction of data and erroneous determination of erroneous position information without providing a data destruction circuit 17 that destroys data that has already been transmitted on the temporary storage unit 14. Accordingly, it is not necessary to increase the access speed to the temporary storage unit 14, and the configuration of the error correction circuit 60 and the transmission circuit 16 becomes easy.
Further, according to the tenth embodiment, the correction process is performed only when the code string for which the information data has not been updated is a PI code sequence in which the order of data reception and the error correction code are substantially the same. Since the correction is not performed for the PO code series if correction is possible based on the error correction code, the possibility of data correction can be further improved.

  Furthermore, according to the tenth embodiment, when the number of correction columns in the PO code sequence exceeds the error correction capability in the PI code sequence, an error correction circuit can be used in normal correction processing without referring to the update position information. Error correction by 60 is not performed, and erroneous correction at that time is prevented. In addition, when a large amount of correction data for the PO code sequence is performed and the correction process for the PI code sequence is repeated two or more times, the code string that has not been updated in the PI code sequence is also used for the next and subsequent times. Since there is a possibility that correction is performed in the correction process, the possibility of correcting unupdated data can be further increased.

  In addition, according to the tenth embodiment, the measurement / determination circuit 61 obtains a synchronization signal and a latch pulse signal via the reception circuit 12, and counts the number of latch pulse signals to obtain two frames (PI code string). ) And whether or not 182 bytes of data have been received and the determination result is output to the update position information generation circuit 62, it is possible to reliably determine whether or not the data has been correctly received. it can.

(Eleventh embodiment)
FIG. 27 is a flowchart of the correction process performed by the error correction circuit 60 according to the eleventh embodiment of the present invention. In the eleventh embodiment, the correction process for the PO code sequence is first performed in the first half steps B1 to B9, and then the correction process for the PI code sequence is performed in the second half steps B10 to B18. Is different. In the case of a product code, the result is the same regardless of which code sequence is used for correction processing. Therefore, according to the eleventh embodiment configured as described above, the same effect as the tenth embodiment can be obtained.

(Twelfth embodiment)
FIG. 28 is a flowchart of the correction processing by the error correction circuit 60 showing the twelfth embodiment of the present invention. The flowchart of the twelfth embodiment is different from the flowchart of the tenth embodiment (see FIG. 22) in that the determination step A1 of “Is data updated” is moved between steps A3 and A4. ing.

That is, in the twelfth embodiment, the error correction circuit 60 reads the symbol data uniformly to determine whether or not the symbol data in the temporary storage unit 14 has been updated for the first time. The syndrome is calculated (steps A2 and A3).
Thereafter, the process proceeds to step A1 to determine whether or not the symbol data has been updated. If it is determined in step A1 that the symbol data has been updated as a result of referring to the updated position information, the process proceeds to step A4. If the symbol data has not been updated in step A1, the process proceeds to step A7 to set error position information.

  According to the twelfth embodiment as described above, after the error correction circuit 60 uniformly calculates the syndrome for one of the PI code strings of the symbol data written in the temporary storage unit 14 regardless of the update position information, Reference is made to the update position information generated by the update position information generation circuit 62, and if the symbol data has not been updated, the error position information is set as the correction target of the code string, so that erroneous data correction Thus, the same effect as that of the tenth embodiment can be obtained without performing erroneous determination.

(Thirteenth embodiment)
FIG. 29 is a flowchart of the correction processing by the error correction circuit 60 showing the thirteenth embodiment of the present invention. The flowchart of the thirteenth embodiment is different from the flowchart of the eleventh embodiment (see FIG. 27) in that the determination step B10 of “Is data updated?” Is moved between steps B12 and B13. ing.
Accordingly, if “NO” is determined in steps B8 and B17, the process proceeds to step B11. According to the thirteenth embodiment as described above, the same effects as in the eleventh embodiment can be obtained.

(14th embodiment)
FIG. 30 shows a fourteenth embodiment of the present invention. The same parts as those in the tenth embodiment are denoted by the same reference numerals and the description thereof will be omitted. Only the different parts will be described below. In FIG. 27, the measurement / determination circuit 61 in the configuration of the tenth embodiment shown in FIG. 20 is replaced with a synchronization detection interval measurement circuit (syndrome determination means) 63. Other configurations are the same as those of the tenth embodiment.

  The determination by the synchronization detection interval measurement circuit 63 is different from the measurement / determination circuit 51 in the sixth embodiment, and the PLL circuit generates the reception interval of the synchronization signal received every frame by the reception circuit 12 from the received data. It is measured based on the clock signal, and it is determined whether or not the data reception processing by the reception circuit 12 is normal depending on whether or not the reception interval is 1488 channel bits (according to the DVD data standard). It is like that. In the fourteenth embodiment configured as described above, the same effects as in the tenth embodiment can be obtained.

The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The arbiter in each embodiment may be integrated with the storage means. The arbiter function may be distributed to the receiving means, error correcting means, and transmitting means, and the access arbitration may be performed by mutually giving access requests to the storage means.

  The tenth to fourteenth embodiments may be applied to a CD data reproducing apparatus. In the flowchart of FIG. 22 in the tenth embodiment, steps A16 and A17 are arranged between steps A13 and A15, and the update position information is cleared each time correction processing is performed on one column of the PO code string. A determination regarding the number of correction columns may be made. Also in the flowchart of FIG. 24 in the eleventh embodiment, steps B8 and B9 may be arranged between steps B5 and B7.

Steps A16 and A17 and steps B8 and B9 may be omitted.
In the flowchart of FIG. 25 in the twelfth embodiment, when “NO” is determined in the step A4, the process may be arranged to move to the step A1. In this case, if “YES” is determined in the step A5, the process proceeds to the same determination step A1 ′. Similarly, in the flowchart of FIG. 29 in the thirteenth embodiment, step B10 may be arranged so as to be shifted when it is determined “NO” in step B13. In this case, “YES” is determined in step B14. In the case where it is determined that the process proceeds to the same determination step B10 ′.
The present invention is not limited to DVD and CD data reproducing apparatuses, and can be applied to any apparatus that reproduces data composed of error correction codes.
The error correction code is not limited to a product code and may be one series.

(15th embodiment)
FIG. 31 to FIG. 35 show the data reproducing apparatus of the present invention that can reproduce data from various disks (information storage disks, recording media) such as CDs, CD-ROMs, DVDs, and DVD-ROMs. The fifteenth embodiment is shown in the case of being applied to FIG. 48. The same parts as those in FIG. 48 are denoted by the same reference numerals and the description thereof is omitted. Only the different parts will be described below.

  In the configuration shown in FIG. 48, the clock signal generated from the received data string by the PLL circuit 22 is supplied to the error correction circuit (error correction means) 27 and the transmission circuit (transmission means) 28. In the configuration of FIG. 28 in the example, a clock signal from a clock generation circuit (clock signal supply means) 64 is supplied instead of the clock signal.

  FIG. 32 is a functional block diagram showing a detailed configuration of the clock generation circuit 64. The reference clock signal output from the reference clock circuit 64b and the oscillation signal of the VCO 64e are supplied to the input terminal of the phase comparison circuit 64a via the programmable counter (frequency setting means) 64c. The output signal of the phase comparison circuit 64a is supplied as a frequency control voltage to the control input terminal of the VCO 64e via the low pass filter 64d.

  The programmable counter 64c has a frequency control signal (that is, the programmable counter 64c) that determines the frequency division ratio of the oscillation signal of the VCO 64e from a system controller (system control means) 32a that comprehensively controls the system of the multi-disc player. By giving a counter value and a set value to be set, an oscillation signal of the VCO 64e can be output as a variable frequency clock signal.

  In this case, if the frequency of the reference clock signal output from the reference clock 64b is f0 and the counter value set in the programmable counter 64c is n, the frequency f of the clock signal from the clock generation circuit 64 is f = n · f0. . That is, the above constitutes a so-called frequency synthesizer (frequency control means) which is a kind of PLL circuit, and the frequency f is feedback controlled so as to be n times the frequency f0. Other configurations are the same as those in FIG. The RF circuit 18, the synchronous separation circuit 21, the PLL circuit 22, and the decoding circuit 24 constitute a receiving unit.

  Next, the operation of the fifteenth embodiment will be described with reference to FIGS. First, as an example, an error correction code employed in DVD data will be described with reference to FIG. FIG. 33 shows an arrangement for one block of the error correction code. The source data of DVD constitutes one sector with 2K bytes as a unit, and an error correction code is added every 16 sectors, and one block is constituted by 32K bytes of source data.

The error correction code of one block includes an inner code PI having parameters (m = 8, n = 182, k = 172, d = 11) and parameters (m = 8, n = 208, k = 192, d = 17) and a Reed-Solomon product code consisting of two code sequences with an outer code PO.
Here, each parameter indicates the following contents.
m: Code length of 1 symbol n: Number of symbols in one code string k: Number of symbols other than parity in number of symbols in one code string d: Minimum distance between codes In other words, they are arranged in the column direction in FIG. The inner code PI (d0,0, d0,1, d0,2,..., D0,181,...) Is a code sequence in which 182 symbols having a code length of 8 bits are arranged. Of the (bytes), the main data is 172 symbols, and the parity generated from these main data is 10 symbols. Further, in the outer code PO (d0,0, d1,0, d2,0,..., D207,0,...) Arranged in the row direction in FIG. 33, 208 symbols having a code length of 8 bits are arranged. The code series includes 192 symbols for main data and 16 symbols for parity. The main data excluding the parity is 172 × 192 = 32.25 (K bytes), and 0.25 K bytes other than the source data are the sector ID, the EDC that is the parity, and the reserve.

  The correction capability of the error correction code configured as described above can be corrected up to 5 symbols for the inner code PI and up to 8 symbols for the outer code PO depending on the calculation result of the syndrome in its own code sequence. . Further, by using error detection position information obtained from the syndrome calculation result in the other code sequence as an erasure pointer, erasure correction is performed up to 10 symbols for the inner code PI and up to 16 symbols for the outer code PO. be able to.

  The actual data reception order is as follows: d0,0, d0,1, d0,2,..., D0,181, d1,0, d1,1, d1,2, ..., d207,180, d207,181 For the inner code PI, the actual data reception order and the error correction code sequence are the same.

  FIG. 34 conceptually shows the usage state (in the case of DVD) of the storage area in the temporary storage unit 26. The storage area inside the temporary storage unit 26 is divided into three areas A, B, and C, and the capacity of each area A, B, and C is equal to the capacity of one block of the error correction code. As shown in FIG. 35, for example, when the area A is a data write target in the reception process, the reception data written in the area C in the previous phase is the correction process target. At the same time, the data in area B that has been corrected in the previous phase is the target of transmission processing.

In the next phase, the area B is subjected to reception processing, the area A is subjected to correction processing, and the area C is subjected to transmission processing, and each area is switched as an object of three processes while circulating.
In this case, the decoding circuit 24 outputs a status signal indicating that the reception processing has been completed for one block of data to the error correction circuit 27 and the transmission circuit 28. After confirming that a signal has been given, each process is performed on a new area of one block.

When the disk is set in a storage unit (not shown), the system controller 32a determines the type of the disk, and the upper limit of the reproduction speed according to the determined disk type, that is, the programmable counter of the clock generation circuit 64. The counter value to be set at 64c is determined and set.
For example, when playing a disc that is important to play data as fast as possible (eg, 4x speed, 8x speed, etc.) such as DVD-ROM and CD-ROM, set the upper limit of the playback speed high. When playing a disc that does not need to be played back at a speed higher than a predetermined speed defined by the standard, such as a DVD that stores MPEG data or a CD that records real audio, according to the required playback speed. Set the upper limit relatively low.

  As shown in FIG. 35, the time for the error correction circuit 27 and the transmission circuit 28 to process one block of data is always constant based on the frequency of the clock signal supplied from the clock generation circuit 64. When the reception data writing time by the decoding circuit 24 is long, the time during which the error correction circuit 27 and the transmission circuit 28 wait for the start of processing for the next one block becomes long, and the reception data writing by the decoding circuit 24 becomes long. When the time is short, the time during which the error correction circuit 27 and the transmission circuit 28 are waiting for the start of the next processing is shortened. That is, the upper limit of the reproduction speed is defined by the frequency of the clock signal supplied from the clock generation circuit 64.

As described above, according to the fifteenth embodiment, the clock signal from the clock generation circuit 64 configured independently of the system reference clock circuit 31 and the PLL circuit 22 is sent to the error correction circuit 27 and the transmission circuit 28. I tried to supply.
Therefore, unlike the prior art, the error correction circuit 27 and the transmission circuit 28 do not need to set the frequency of the system reference clock signal high according to the correction processing side and the transmission processing side, and suppress power consumption and unnecessary radiation. Can do. In addition, since the error correction circuit 27 and the transmission circuit 28 can be operated without depending on a low-stability clock signal generated from the received data string by the PLL circuit 22, it is possible to prevent the occurrence of malfunction.

  Further, according to the fifteenth embodiment, the clock generation circuit 64 is operated based on the reference clock signal output from the reference clock circuit 64a separate from the system reference clock circuit 31 and the count value set in the programmable counter 64c. The system controller 32a is configured to change the upper limit value of the data reproduction speed by setting a count value in the programmable counter 64c in accordance with the type of disk to be reproduced.

  Therefore, the clock generation circuit 64 performs feedback control so that the frequency of its output clock signal detected by the phase comparison circuit 64b approaches a value corresponding to the count value set in the programmable counter 64c by the system controller 32a. The upper limit value of the data reproduction speed can be appropriately set according to the type of disc that differs depending on the application.

(Sixteenth embodiment)
FIG. 36 shows a sixteenth embodiment of the present invention. The same parts as those of the fifteenth embodiment are denoted by the same reference numerals, and the description thereof is omitted. Only the different parts will be described below. In FIG. 36 showing the electrical configuration, the system controller 32a shown in FIG. 31 is replaced with a system controller (system control means) 32b. The system controller 32b obtains the reception data decoded by the decoding circuit 24. Other configurations are the same as those in the fifteenth embodiment.

  Next, the operation of the sixteenth embodiment will be described. For example, an input operation for instructing the cueing of an audio or video data track stored on a disk in a CD or DVD or a search for various data in a CD-ROM or DVD-ROM by a user. When the operation is performed, the system controller 32b gives a control signal to the servo circuit 23 to suddenly change the tracking position on the disk 19 of the pickup (data reading means) 20.

  When the tracking position of the pickup 20 changes abruptly, the data reception speed also changes abruptly by adopting the CLV method as described above. That is, due to the fact that the change in the rotation speed of the motor 30 cannot follow, the data reception speed becomes relatively faster when the disk is changed to the inner circumference side, and is relatively higher when the disk is changed to the outer circumference side. Become slow. At this time, the system controller 32b includes sub-coding data included in the data on the disk 19 (information indicating which position on the disk is currently read) from the reception data decoded by the decoding circuit 24. Data).

  Then, the system controller 32b sets a counter value in the programmable counter 64c of the clock generation circuit 64 according to the tracking position indicated by the sub-coding data. That is, the system controller 32b dynamically changes the frequency of the clock signal output from the clock generation circuit 64 during reproduction of the disk 19.

  As described above, according to the sixteenth embodiment, the system controller 32b changes the frequency of the clock signal output from the clock generation circuit 64 in accordance with the tracking position of the pickup 20 that reads information data from the disk 19, so that tracking is performed. The speed of the correction process and the transmission process performed by the error correction circuit 27 and the transmission circuit 28 can be changed in accordance with the reception processing speed of different information data depending on the position, and optimal speed control can be performed.

(Seventeenth embodiment)
FIG. 37 shows a seventeenth embodiment of the present invention. The same parts as those of the fifteenth embodiment are designated by the same reference numerals and the description thereof is omitted. Only the different parts will be described below. In FIG. 37 showing the electrical configuration of the clock generation circuit (clock signal supply means, frequency control means) 64 ′, the phase comparison circuit 64b of the clock generation circuit 64 ′ shown in FIG. 32 is replaced with the reference clock circuit 64a. The system clock signal of the system reference clock circuit 31 is provided by dividing it by m through an m-ary counter 65. Other configurations are the same as those in the fifteenth embodiment.

  The frequency f of the clock signal output from the clock generation circuit 64 ′ is f = (n / m) · fs, where fs is the frequency of the system clock signal output from the system reference clock circuit 31.

  According to the seventeenth embodiment configured as described above, the phase comparison circuit 64b of the clock generation circuit 64 'is divided into the clock signal output by itself by n and the system clock signal of the system reference clock circuit 31. Therefore, it is not necessary to set the frequency of the system clock signal high in accordance with the processing speed on the correction processing and transmission processing side. The same effect as in the fifteenth embodiment can be obtained.

(Eighteenth embodiment)
FIG. 38 shows an eighteenth embodiment of the present invention. The same parts as those of the fifteenth embodiment are designated by the same reference numerals and the description thereof is omitted. Only the different parts will be described below. FIG. 38 shows an electrical configuration of the clock generation circuit (clock signal supply means) 66. The clock generation circuit 66 includes a VCO (Voltage Controlled Oscillator) 66a and a series circuit of a variable resistor (frequency setting means) 66b and a resistor 66c for connecting the control power source Vcc and the ground.

The voltage control terminal of the VCO 66a is connected to the common connection point of the variable resistor 66b and the resistor 66c, and the clock signal supplied to the error correction circuit 27 and the transmission circuit 28 is output from the output terminal of the VCO 66a. It has become. Other configurations are the same as those in the fifteenth embodiment.
Next, the operation of the eighteenth embodiment will be described. In the data reproducing apparatus in the eighteenth embodiment, the type of the disk 19 to be reproduced is fixed (single disk player), and therefore the upper limit of the reproduction speed is predetermined. In this case, for example, in the manufacturing stage of the playback device, the resistance value (setting value) of the variable resistor 66b of the clock generation circuit 66 is manually set, thereby allowing the control power supply Vcc to be applied to the voltage control terminal of the VCO 66a. Adjust the divided potential.

Then, since the VCO 66a changes the frequency of the output signal in accordance with the potential applied to the voltage control terminal, the error correction circuit 27 and the error correction circuit 27 and the reproduction target disk 19 are determined in advance for each reproducing apparatus. It is possible to set the frequency of the clock signal supplied to the transmission circuit 28 to a desired value.
As described above, according to the eighteenth embodiment, the frequency of the clock signal output from the clock generation circuit 66 is changed by manually setting the resistance value of the variable resistor 66b. Is one and the upper limit of the reproduction speed can be fixedly set, the clock generation circuit 66 can be configured easily.

The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The arbiter in each embodiment may be integrated with the storage means. The arbiter function may be distributed to the receiving means, error correcting means, and transmitting means, and the access arbitration may be performed by mutually giving access requests to the storage means.

By combining the configuration of the fifteenth embodiment and the configuration of the sixteenth embodiment, the system control means sets the upper limit of the playback speed according to the type of the disc, and also at the tracking position of the pickup during playback of the disc. Accordingly, the upper limit of the playback speed may be set dynamically.
Instead of the phase comparison circuit 64a in the fifteenth to seventeenth embodiments, a frequency comparison circuit may be used.

  In the configuration of the clock generation circuit of the fifteenth to seventeenth embodiments, instead of the system controller 32, 32a or 32b setting the counter value in the programmable counter 64c, for example, setting the counter value in the programmable counter 64c When a dip switch (frequency setting means) is provided and applied to a single disc player as in the eighteenth embodiment, the upper limit value of the reproduction speed may be set by manually setting the dip switch. good.

In the seventeenth embodiment, the m-ary counter 65 may also be a programmable counter. With this configuration, the frequency f of the system clock signal of the system reference clock circuit 31 changes in accordance with the equation f = (n / m) · fs according to the counter value m. Compared to the case, the frequency f can be changed more variously.
The eighteenth embodiment is applied to the case of a single disc player. However, even in the case of a multi-disc player, for example, the frequency of the clock generation circuit 66 is set in accordance with the highest playback speed of the plurality of discs 19. In addition, by providing the speed comparison circuit 35 shown in FIG. 50, a disk with a low reproduction speed may be dealt with by widening the data transmission interval from the transmission circuit 28.

Further, for example, by providing the speed comparison circuit 35 in the configuration of the fifteenth embodiment, the system controller 32a sets the frequency of the clock generation circuit 64 according to the one having the highest reproduction speed in the initial processing, and thereafter The data transmission interval may be adjusted by the speed comparison circuit 35 in the same manner as described above.
The fifteenth through eighteenth embodiments are not limited to the disk 19 such as a CD or a DVD, but can be applied to a device that reproduces a hard disk, a floppy disk, a magnetic tape, etc., as long as the recording medium stores data composed of error correction codes. It may be applied. In that case, a magnetic head may be used as the data reading means.
The present invention is not limited to the CLV system, and may be applied to a ZCLV or ZCAV data reproducing apparatus.
The error correction code is not limited to a product code and may be one series.

Functional block diagram of electrical configuration showing a first embodiment when the present invention is applied to a DVD data reproducing apparatus. The figure which shows the storage area of a temporary memory part A time chart showing a state in which each area is switched and used when performing reception processing, correction processing, and transmission processing for the two storage areas A and B of the temporary storage unit The figure which shows the state of the process performed to each area | region of a temporary memory part in FIG. FIG. 3 is a diagram corresponding to FIG. FIG. 3 is a diagram corresponding to FIG. FIG. 1 equivalent view showing a second embodiment of the present invention. 2 equivalent diagram Diagram showing the relationship between the transfer rate of received data and the transfer rate of transmitted data FIG. 1 equivalent view showing a third embodiment of the present invention. FIG. 1 equivalent view showing a fourth embodiment of the present invention. FIG. 1 equivalent view showing a fifth embodiment of the present invention. Functional block diagram of an electrical configuration showing a sixth embodiment when the present invention is applied to a DVD data reproducing apparatus. The figure which shows the data format of the error correction code employ | adopted as DVD Flow chart showing correction processing contents of error correction circuit FIG. 13 is a diagram corresponding to FIG. 13 showing a seventh embodiment when the present invention is applied to a CD data reproducing apparatus. Figure 15 equivalent FIG. 16 equivalent view showing an eighth embodiment of the present invention. FIG. 13 equivalent diagram showing a ninth embodiment of the present invention. Functional block diagram of an electrical configuration showing a tenth embodiment when the present invention is applied to a DVD data reproducing apparatus. The figure which shows the data format of the error correction code employ | adopted as DVD Flow chart showing correction processing contents of error correction circuit The figure which shows an example of the correction process in 10th Example (the 1) The figure which shows an example of the correction process in 10th Example (the 2) The figure which shows an example of the correction process at the time of not using a data destruction circuit in the conventional correction processing system (the 1) The figure which shows an example of the correction process at the time of not using a data destruction circuit in the conventional correction processing system (the 2) FIG. 22 equivalent diagram showing the eleventh embodiment of the present invention. FIG. 22 equivalent diagram showing the twelfth embodiment of the present invention. FIG. 22 equivalent diagram showing the thirteenth embodiment of the present invention. FIG. 20 equivalent view showing the fourteenth embodiment of the present invention. Functional block diagram of an electrical configuration showing a fifteenth embodiment when the present invention is applied to a multi-disc player. The figure which shows the detailed electric constitution of the clock generation circuit The figure which shows the data format of the error correction code employ | adopted as DVD The figure which shows notionally the use condition of each area | region of a temporary memory part Time chart showing usage status of each area of temporary storage FIG. 31 equivalent diagram showing the sixteenth embodiment of the present invention. FIG. 32 equivalent view showing the seventeenth embodiment of the present invention. FIG. 32 equivalent diagram showing an eighteenth embodiment of the present invention. 1 equivalent diagram showing the prior art 2 equivalent diagram 3 equivalent view (part 1) Figure 3 equivalent (part 2) 13 equivalent diagram FIG. 20 equivalent diagram Flow chart showing the flow of each process of reception, correction and transmission 31 equivalent view (part 1) The figure which shows the change of the data reproduction speed when a pickup changes the tracking position on a disk rapidly in a CLV system. 31 equivalent view (2) 31 equivalent view (part 3) 31 equivalent view (part 4)

Explanation of symbols

Reference numerals 1 and 1 'are reception circuits (reception means), 5 is a transmission circuit (transmission means), 6 is a reception circuit (reception means), 8 is a temporary storage unit (storage means), 10 is a transmission circuit (transmission means), 12 Is a reception circuit (reception means), 14 is a temporary storage unit (storage means), 16 is a transmission circuit (transmission means), 18 is an RF circuit (reception means), 19 is a disk (information storage disk, recording medium), and 20 is Pickup (data reading means), 21 is a sync separation circuit (receiving means), 22 is a PLL circuit (receiving means), 24 is a decoding circuit (receiving means), 26 is a temporary storage unit (storage means), and 27 is an error correction circuit. (Error correction means), 28 is a transmission circuit (transmission means), 31 is a system reference clock circuit, 32a and 32b are system controllers (system control means), 41 is a temporary storage unit (storage means), and 42 is an error correction circuit. Error correction means), 43 and 44 are transmission circuits (transmission means), 45 is a speed comparison circuit (read speed control means), 46 is a reception circuit (reception means), 47 is an address comparison circuit (write stop means), and 49 is Address comparison circuit (data destruction determination means), 51 is a measurement / determination circuit (syndrome determination means), 52 is an error correction circuit (error correction means), 53 is a PI syndrome calculation circuit (syndrome calculation means), and 54 is a reception circuit ( Receiving means), 55 is a measurement / determination circuit (syndrome judgment means), 56 is a switching circuit (syndrome output switching means), 57 is a C1 syndrome calculation circuit (syndrome calculation means), and 58 and 58 'are error correction circuits (error correction). Means), 59 is a judgment circuit (syndrome judgment means), 60 is an error correction circuit (error correction means), and 61 is a measurement / judgment circuit (judgment). Means), 62 is an update position information generation circuit (update position information generation means), 63 is a synchronization detection interval measurement circuit (determination means), 64 and 64 'are clock generation circuits (clock signal supply means, frequency control means), 64a Is a phase comparison circuit, 64b is a reference clock circuit, 64c is a programmable counter (frequency setting means), 66 is a clock generation circuit (clock signal supply means), and 66b is a variable resistor (frequency setting means).

Claims (7)

Receiving means for receiving information data composed of error correction codes, storage means for storing information data received by the receiving means, and storing the information data stored in the storage means for reading the error data An error in the information data is detected and corrected based on the correction code, the error correction means for writing the information data after the correction process to the storage means, and the information data after the correction process written in the storage means is read out. In an error correction device comprising a transmission means for transmitting,
Determination means for determining whether or not information data of the number of symbols necessary for error correction has been written to the storage means by measuring the number of symbols of information data received by the reception means and written to the storage means When,
An update position information generating means for generating update position information for a code string of information data written in the storage means based on the determination by the determination means;
The error correction unit does not correct a code string of an error correction code whose information data has not been updated based on the update position information generated by the update position information generation unit. .   The error correction means is characterized in that, for a code string of an error correction code whose information data has not been updated, correction is not performed when the reception order of the data and the arrangement of the error correction code are substantially the same. The error correction apparatus according to claim 1. Receiving means for receiving information data composed of error correction codes, storage means for storing information data received by the receiving means, and storing the information data stored in the storage means for reading the error data An error in the information data is detected and corrected based on the correction code, the error correction means for writing the information data after the correction process to the storage means, and the information data after the correction process written in the storage means is read out. In an error correction device comprising a transmission means for transmitting,
Determination means for determining whether or not information data of the number of symbols necessary for error correction has been written to the storage means by measuring the number of symbols of information data received by the reception means and written to the storage means When,
An update position information generating means for generating update position information for a code string of information data written in the storage means based on the determination by the determination means;
The error correction means refers to the update position information generated by the update position information generation means during the correction, so that the code string of the error correction code whose information data has not been updated is not subject to correction. An error correction apparatus characterized in that a determination is made.   The error correction means determines that the code sequence of the error correction code whose information data has not been updated is excluded from correction when the data reception order and the error correction code array are substantially the same. The error correction apparatus according to claim 3. The information data is composed of a plurality of error correction codes,
Error correction means, the number of columns take corrective for code sequence of a particular error correcting code sequence to said information data, when exceeded should not be correctable number of errors in the other error correcting code sequence, the other the error correction code sequences, the error correction apparatus according to any one of claims 1 to 4, characterized in that information data can not rope rows corrections with the code sequence that has not been updated.
  The determination means measures the number of symbols of the information data received by the reception means, and determines whether or not information data of the number of symbols necessary for error correction has been written in the storage means based on the measured number of symbols. The error correction apparatus according to claim 1, wherein the error correction apparatus is an error correction apparatus. The determining means detects the synchronization signal included in the information data received by the receiving means, and based on the detection interval of the synchronization signal, whether the information data of the number of symbols necessary for error correction is written in the storage means. 6. The error correction apparatus according to claim 1, wherein the error correction apparatus determines whether or not.

Images