JP3771645B2 - Focus detection device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a focus detection device mounted on an optical apparatus such as a camera.
[0002]
[Prior art and its problems]
A so-called phase difference type focus detection device, which is one of camera autofocus devices, divides a subject image into two, receives a pair of subject images with a CCD line sensor, and converts them into electrical signals with a CCD line sensor. To do. Then, the phase difference between the subject images is detected based on the pair of subject image signals regarding the pair of subject images, and the focus state (defocus) is detected based on the phase difference.
[0003]
Here, since detection of the phase difference and defocus is normally performed by a CPU (microcomputer), the subject image signal is converted into a digital signal that can be processed by the CPU. This A / D conversion is usually performed by an A / D converter with a built-in CPU.
[0004]
In general, the sensitivity range of a CCD line sensor is narrower than the subject luminance range that can be photographed. Therefore, the CCD line sensor is controlled regardless of the brightness of the subject by controlling the light reception time (integration time) of the CCD line sensor according to the brightness of the subject, or by adjusting the amplification factor of the output voltage of the CCD line sensor. An output voltage close to the saturation output voltage is obtained.
[0005]
However, there are various CCD line sensors, and the saturation output voltage is also different. Therefore, the saturation output voltage of a certain CCD line sensor is more than half of the full range of the A / D converter, but the saturation output voltage of a certain CCD line sensor is less than half of the full range of the A / D converter. There is. When a CCD line sensor whose saturation output voltage is less than half of the full range of the A / D converter is used, the range of the data after conversion is narrow, and the performance of the CCD line sensor cannot be sufficiently obtained.
[0006]
OBJECT OF THE INVENTION
The present invention has been made in view of the problem of the focus detection device having the CCD line sensor of the conventional camera described above. By increasing the resolution of the A / D converter, the high-precision focus can be obtained regardless of the CCD line sensor. An object of the present invention is to provide a focus detection device capable of detection.
[0007]
SUMMARY OF THE INVENTION
The present invention that achieves this object includes a CCD line sensor that receives a subject image and outputs a signal voltage corresponding to the luminance, and an A / D converter that A / D converts the output voltage of the CCD line sensor. In the focus detection apparatus provided with the control means, the control means converts the output voltage of the CCD line sensor from the A / D converter at the maximum resolution, and further converts the digital data converted at the maximum resolution. The CCD line sensor Saturation The output voltage of the A / D converter full range If it is 1/2 or more of the above, the control means processes, Lower resolution than the maximum resolution Converted into digital data, and the saturated output voltage is converted into that of the A / D converter. full range Is less than the maximum resolution of the A / D converter and is converted into digital data having a resolution higher than the resolution processed by the control means.
According to this configuration, since it can be converted into digital data with a constant accuracy regardless of the saturation output voltage of the CCD line sensor, a constant accuracy can be maintained even when a CCD line sensor having a different saturation output voltage is used.
[0008]
In the present invention, when the control means mounted on the camera includes an A / D converter with 10-bit accuracy, digital data converted with 10-bit accuracy is converted into 9-bit or 8-bit digital data according to the saturation output voltage of the CCD line sensor. Can be configured to convert to data. Further, according to the present invention, when the saturation output voltage of the CCD line sensor is less than half of the full range of the A / D converter, the 10-bit digital data converted by the A / D converter is converted to the 9-bit digital data. When the saturation output voltage is ½ or more of the full range, the 10-bit digital data converted by the A / D converter can be converted to the 8-bit digital data.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of an automatic focus (AF) single-lens reflex camera to which the present invention is applied. This AF single-lens reflex camera includes a camera body 11 and an AF-compatible photographic lens 51 that can be attached to and detached from the camera body 11. The camera body 11 includes so-called multipoint autofocus means (multipoint focus detection means) and automatic focus adjustment means.
[0010]
Most of the subject luminous flux incident into the camera body 11 from the photographing lens 51 is reflected by the main mirror 13 toward the pentaprism 17 constituting the finder optical system, and is reflected by the pentaprism 17 and exits from the eyepiece. A part of the reflected light reflected by the main mirror 13 enters the light receiving element of the photometry IC 18. On the other hand, a part of the subject luminous flux incident on the half mirror portion 14 of the main mirror 13 is transmitted therethrough, reflected downward by the sub mirror 15 and incident on the multi-focus detection sensor unit 21.
[0011]
The photometric IC 18 logarithmically compresses the electrical signal photoelectrically converted in accordance with the amount of received light, and inputs it as a photometric signal to the main CPU 35 via the peripheral control circuit 23. The main CPU 35 executes a predetermined exposure calculation based on the photometry signal and the film sensitivity information, and calculates an appropriate shutter speed and aperture value for exposure. Then, based on these shutter speed and aperture value, photographing processing, that is, the exposure mechanism (shutter mechanism) 25 and the aperture mechanism 27 are driven to expose the film. Further, the peripheral control circuit 23 drives the mirror motor 31 via the motor drive circuit 29 to perform up / down processing of the main mirror 13 during the photographing process, and drives the film winding motor 33 after the exposure is completed. Roll up the film by one frame.
[0012]
The multi-focus detection sensor unit 21 is a so-called phase difference type distance measuring sensor. Although not shown, the multi-focus detection sensor unit 21 divides a subject light beam that forms a subject image included in a plurality of distance measuring zones in a photographing screen into two parts. The system includes sensors 212 </ b> A to 212 </ b> C that receive and integrate (photoelectric conversion and accumulation of charges thereof) each of the subject light beams divided into two.
[0013]
The main CPU 35 calculates the defocus amount by a predetermined calculation based on the integration data corresponding to each focus detection zone input from the multi-focus detection sensor unit 21. Then, based on these defocus amounts, the defocus amounts to be used and the priority order are set, and the rotation direction and the number of rotations of the AF motor 39 (number of pulses output by the encoder 41) are calculated. The main CPU 35 drives the AF motor 39 via the AF motor drive circuit 37 based on the rotation direction and the number of pulses. During this driving, the main CPU 35 detects and counts the pulses output from the encoder 41 in conjunction with the rotation of the AF motor 39, and stops the AF motor 39 when the count value reaches the number of pulses.
[0014]
The main CPU 35 can perform constant speed control by PWM control of the AF motor 39 based on the DC drive and the output pulse interval of the encoder 41 before stopping. The AF motor 39 transmits the rotation to the photographing lens 51 side through a connection between a joint 47 provided on the mount portion of the camera body 11 and a joint 57 provided on the mount portion of the photographing lens 51. Then, the focus adjustment lens 53 is moved forward and backward through the lens driving mechanism 55.
[0015]
The main CPU 35 includes a ROM 35a storing programs and the like, a RAM 35b temporarily storing predetermined data for calculation and control, a reference timer 35c for timing, a hard counter 35d, and an A / D converter 35e. An EEPROM 43 as an external memory means is connected. In addition to various constants specific to the camera body 11, the EEPROM 43 stores predetermined values necessary for integral control of the present invention.
[0016]
Further, the main CPU 35 includes a metering switch SWS that is turned on when a release button (not shown) is half-pressed, a release switch SWR that is turned on when the release button is fully pressed, an auto-focus switch SWAF that switches between automatic focus control and manual focus control, A main switch SWM for turning on / off the power to peripheral devices is connected. The main CPU 35 displays the set AF, exposure, shooting mode, shutter speed, aperture value, and the like on the display 45. The display unit 45 usually includes displays provided at two locations within the outer surface of the camera body 11 and the viewfinder field.
[0017]
The main CPU 35 functions as a control unit that comprehensively controls the camera body and the photographing lens, and constitutes an integration control unit with the multi-focus detection sensor unit 21, the peripheral control circuit 23, and the like, and an AF motor 39. Etc. constitute lens driving means.
[0018]
On the other hand, the photographic lens 51 is provided with a focus adjustment mechanism 55 for driving the focus adjustment lens 53 in the optical axis direction and a mount portion of the photographic lens 51, and is connected to the joint 47 of the camera body 11. A lens-side joint 57 that transmits the rotation to the focus adjustment mechanism 55 and a lens CPU 61 are provided.
[0019]
The lens CPU 61 is connected to the peripheral control circuit 23 of the camera body 11 through the connection of the electrical contact groups 59 and 49, and predetermined data is transmitted to the main CPU 35 through the peripheral control circuit 23. Execute communication. The data transmitted from the lens CPU 61 to the peripheral control circuit 23 includes a controllable open aperture value Av (apex converted value of open F value), maximum aperture value Av (apex converted value of minimum aperture F value), lens There are position, K value data, and the like. The K value data is the number of pulses (AF) output by the encoder 41 while the image plane formed by the photographing lens 51 is moved by a unit distance (for example, 1 mm) in the optical axis direction by driving the AF motor 39. The number of rotations of the motor 39).
[0020]
This single-lens reflex camera starts AF processing when the photometric switch SWS is turned on. In the AF process, first, the multi-focus detection sensor unit 21 starts integration. After the integration is completed, the main CPU 35 inputs the integration data, calculates the defocus amount and the drive pulse number based on the data, and drives the AF motor 39 based on the drive pulse number.
[0021]
Although not shown in detail in the multi-focus detection sensor unit 21, as is well known, the subject light incident from the photographing lens 51, transmitted through the central half mirror portion 14 of the main mirror 13, and reflected by the sub mirror 15 is incident. To do. The subject light incident on the multi-focus detection sensor unit 21 forms an image on the secondary imaging plane conjugate with the film surface or on the front and back positions thereof, and is formed at a plurality of positions on the mask arranged on the secondary imaging plane. The light is transmitted through the three windows and formed on different light receiving means (see FIG. 2). Each of the three windows regulates the focus detection zone, and each light beam contained in each focus detection zone is divided into two by a splitting optical system (not shown) and is received by each light receiving means arranged on the re-imaging plane. Imaged.
[0022]
The multi-focus detection sensor unit 21 has a CCD line sensor as a sensor, and the configuration thereof will be described in more detail with reference to FIG. The multi-focus detection sensor unit 21 includes one CCD transfer unit 211 and three light receiving units that are adjacent to the CCD transfer unit 211 and spaced apart from each other in the longitudinal direction of the CCD transfer unit 211. A sensor 212A, B sensor 212B, and C sensor 212C. Each of the A, B, and C sensors 212A, 212B, and 212C includes a pair of light receiving portions A1 and A2, B1 and B2, and C1 and C2. A subject image divided into two by the dividing optical system is formed on each of the pair of light receiving portions A1 and A2, B1 and B2, and C1 and C2. Each of the light receiving portions A1 and A2, B1 and B2, and C1 and C2 is formed of, for example, a photodiode array (pixel array) provided in a line at regular intervals.
In the illustrated embodiment, three pairs of light receiving portions A1 and A2, B1 and B2, and C1 and C2 are shown apart from each other, but a pair of light receiving portions A1 and A2, B1 and B2, and C1 and C2 are shown. Each may have a continuous configuration.
[0023]
Although not shown in detail, each sensor 212A, 212B, and 212C has an independent charge for each photodiode that is photoelectrically converted by the photodiodes of the light receiving portions A1 and A2, B1 and B2, and C1 and C2. A storage unit that integrates (accumulates) and a memory unit that temporarily stores charges accumulated in the storage unit when integration is completed. In other words, photodiodes photoelectrically convert after receiving subject light, and the charges photoelectrically converted by each photodiode are integrated in the storage unit, and the charges integrated in the storage unit are transferred to the memory unit and held when integration is completed. Is done. When the integration of all the sensors 212A, 212B, and 212C is completed, the charges held in the respective memory units are transferred to the CCD transfer unit 211 all at once. A number of electrodes (not shown) are formed in the CCD transfer unit 211 at regular intervals, and charges are transferred stepwise in pixel units by two-phase transfer clocks φ1 and φ2 applied to these electrodes. The voltage is converted and output in units of pixels from the output conversion unit (reading unit) 213 of the transfer unit 211.
[0024]
The voltage signal output from the output conversion unit 213 is amplified by the amplifier 226, and is output by the clamp circuit 227 as a video signal VIDEO converted into a voltage signal that drops from the video reference level. The output video signal VIDEO is captured by the CPU 35, converted into a digital signal by the A / D converter 35e, stored in the RAM 35b in pixel units, read from the RAM 35b, and used for the defocus calculation.
[0025]
FIG. 3 shows an outline of an example of the A / D converter 35e of the CPU 35 in blocks. The video signal VIDEO input to the input circuit 351 is held by the sample-and-hold circuit 352, is sequentially compared with the voltage output from the D / A converter 354 by the comparator 353, and the comparison result is written to the successive approximation register 355. It is. This D / A converter 354 has a resolution of 10 bits, and the full range is the reference voltage AVCC. When the comparison for 10 bits is completed, the contents of the successive approximation register 355 are transferred to the data register 356 and written to a predetermined address in the RAM 35b via the data bus.
[0026]
Conversion from 10 bits to 9 bits and 8 bits in this embodiment can be processed as a full range of 8-bit A / D conversion values even when the maximum level of the video signal VIDEO is less than half of the full range of the A / D converter 35e. The purpose is to be. Therefore, the 10-bit data in the data register 355 is multiplied by 1/2 or 1/4 (1 bit, 2 bits below) In place Shift Below) The 8th digit is obtained as 8bit or 9bit precision data. For example, when the saturation output voltage of the sensor satisfies the full range of the A / D converter 35e, the AGC level (integration end level VRM is set so that the output of the subject image with uniform brightness is about 70% of the saturation output. ) To obtain an 8-bit precision A / D conversion value. When the saturation output voltage of the sensor does not satisfy the full range of the A / D converter 35e, it is assumed that the saturation output voltage is ½ of the full range of the A / D converter 35e, and an object image with uniform brightness is output. AGC level (integration end level VRM) is set so as to be about 70% of the assumed saturation output, and an A / D conversion value with 9-bit accuracy is obtained. Even if the saturation output voltages of the multi-focus detection sensor unit 21 do not match, it is possible to use the full range (0 to FFH) of 8-bit A / D conversion values.
[0027]
The above A / D conversion processing is executed for the video signals VIDEO of all the pixels of the sensors 212A to 212C.
[0028]
In order to control the integration time (end of integration) of each of the sensors 212A to 212C in accordance with the brightness of the subject, the integration values (each of the sensors 212A, 212B, and 212C adjacent to each of the sensors 212A, 212B, and 212C ( A monitor sensor MA, B monitor sensor MB, and C monitor sensor MC are provided for monitoring the amount of received light. Further, a monitor dark sensor MD is provided adjacent to the first light receiving part B1 of the B sensor 212B. The monitor sensors MA, MB, and MC are sensors that receive subject light and output integrated values in the same manner as the sensors 212A, 212B, and 212C. The integrated values are detected by the integration control circuits 225A, 225B, and 225C. The On the other hand, the monitor dark sensor MD is a sensor that obtains a signal for removing dark current components of the monitor sensors MA, MB, and MC, and is shielded from light.
[0029]
The monitor sensors MA, MB, and MC of this embodiment are monitor sensors M1 to M5, M6 to M10, and M11 that receive light by dividing one of the light receiving portions A2, B2, and C2 of the sensors 212A, 212B, and 212C into 5 parts, respectively. Including M15.
[0030]
Integration operation (charge accumulation) of the A, B, C sensors 212A, 212B, 212C, transfer of charges (integral value) from the A, B, C sensors 212A, 212B, 212C to the CCD transfer unit 211, CCD transfer unit The charge transfer in 211, the conversion from charge to voltage in the output conversion unit 213, the clamp processing by the clamp circuit 227, and the like are performed by a clock (pulse signal) output from the CCD control circuit 221, the timing generation circuit 222, and the driver circuit 223. Made.
[0031]
The integral control processing of this single-lens reflex camera is started on condition that the photometry switch SWS is turned on. When the photometric switch SWS is turned on, the CCD control circuit 221 raises the integration start signal φINT based on the communication data output from the CPU 35, and the sensors 212A, 212B, 212C and the monitor sensors MA, MB, MC start integration.
[0032]
The integration control circuits 225A to 225C detect that the integration values of the monitor sensors MA to MC exceed a preset integration end level VRM, and the detected integration control circuits 225A to 225C detect the integration end signal END-A to When END-C is output, the corresponding sensors 212A to 212C end the integration. In this embodiment, when any one of the five monitor sensors M1 to M5, M6 to M10, and M11 to M15 of the monitor sensors MA, MB, and MC reaches the integration end level VRM, The integration control circuits 225A, 225B, and 225C end the integration of the corresponding sensors 212A, 212B, and 212C. The integration end level VRM is a signal determined by the reference signal (VAGC) output from the main CPU 35 and the dark current MD output from the monitor dark sensor MD.
[0033]
On the other hand, when the integration of all the sensors 212A to 212C is not completed within the preset maximum integration time, that is, the integration value of any of the monitor sensors MA, MB, MC within the preset maximum integration time. When the integration end level has not been reached, the integration of all the sensors 212A to 212C that have not completed integration is forcibly terminated when the maximum integration time has elapsed. The forced termination of integration is executed when the CCD control circuit 221 outputs a forced integration end signal FENDint to each of the integration control circuits 225A to 225B, and the integration control circuits 225A to 225B output an integration end signal. The CPU 35 starts measuring the integration time from the start of integration, inputs the integration end signals (END-A to END-C) output from the integration control circuits 225A to 225C, and inputs the integration control circuits 225A to 225C. Measure integration time.
[0034]
When integration of all the sensors 212A, 212B, and 212C is completed, the driver circuit 223 outputs a transfer pulse φTG, and the signal charges integrated by the sensors 212A, 212B, and 212C are transferred to the CCD transfer unit 211. Each signal charge transferred to the CCD transfer unit 211 is transferred to the CCD transfer unit 211 in pixel units by transfer / readout clocks φ1 and φ2 generated in synchronization with the reference clock φM. Each charge is converted into a voltage for each pixel by the output conversion unit 213 and output (read), amplified by the amplifier 226, clamped by the clamp circuit 227, and output as a video VIDEO signal for each pixel. The clamp circuit 227 samples and holds the output in synchronization with the sample and hold pulse φSH and outputs it as a video signal VIDEO.
[0035]
The CPU 35 converts the input video signal VIDEO into a 10-bit digital signal with the built-in A / D converter 35e, and further halves or folds to convert the data into 8-bit or 9-bit precision data. Write to RAM 35b.
[0036]
The integration process in the focus adjustment operation of the AF single-lens reflex camera provided with the multipoint autofocus device will be further described with reference to FIGS.
[0037]
"Main processing"
FIG. 4 is a flowchart regarding the main process of the single-lens reflex camera. In this main processing, the system waits for the photometry switch SWS to be turned on, and when the photometry switch SWS is turned on, the photometry and exposure calculation processing (AE processing) is performed to obtain the optimum aperture value and shutter speed, and the focus detection processing and lens A drive process (AF process) is executed to focus, and when the release switch SWR is turned on, an exposure process is executed with the aperture value and shutter speed obtained in the AE process.
[0038]
This main process is entered when a battery is loaded. When entering this process, the RAM 35b is first initialized (S101). Then, the power supply to the circuits and components other than the CPU 35 is cut off, and waiting for the photometric switch SWS to turn on (S103, S105). When the photometric switch SWS is turned on, power supply to the peripheral device is started and VDD loop processing is executed (S107).
[0039]
When the VDD loop process is started, the VDD loop time timer is started (S111), the state of each switch is checked (S113), and predetermined lens communication is executed with the lens CPU 61 to set the maximum aperture value and the minimum value. Lens data such as aperture value and focal length data is input (S115).
[0040]
Then, an AE calculation process is executed (S117), and a display relating to photographing such as a shutter speed obtained by the calculation is performed (S119). The AE calculation process is a process in which subject brightness is measured by the photometry IC 18, and an appropriate shutter speed and aperture value are obtained by calculation in a predetermined exposure mode, for example, a program exposure mode, based on subject brightness data and film sensitivity data.
[0041]
When the shutter speed and the aperture value are obtained, the focus adjustment lens 53 is moved, and AF processing for focusing on the subject whose focus is detected is executed (S121). This AF process is repeatedly executed until the loop time elapses (S123).
[0042]
When the loop time elapses, the state of the photometry switch SWS is checked, and if it is on, the process returns to the VDD loop process (S125, S111). If the metering switch SWS is off, it is checked whether the power hold flag is set. If it is not set, the power hold timer is started, and the power hold timer is set after the power hold flag is set. The VDD loop process is repeated until it is increased (S125, S127, S129, S131, S133, S111). When the power hold time elapses, the power hold flag is cleared and the process returns to the power down process (S133, S135, S103).
[0043]
"AF processing"
The AF process in S121 will be described in more detail with reference to FIG. When the AF process is started, first, it is checked whether or not the photometric switch SWS is in an ON state (S201). If the photometric switch SWS is off, the AF lock flag is cleared and the process returns (S201, S203). The AF lock flag is a flag that is set when the subject is once focused, and is a flag that enables a so-called focus lock that maintains a focused state for the subject once the subject is focused.
[0044]
If the photometry switch SWS is on, it is checked whether the AF lock flag is set. If the AF lock flag is set, the process returns. However, if the AF lock flag is not in focus, it is not set, so the integration of all the sensors 212A, 212B, 212C is started (S205, S207). When the integration is completed, CCD video data is input (S209), and the defocus calculation is executed for the selected focus detection zone to obtain the defocus amount (S211). Then, it is checked whether or not the calculated defocus amount is in focus. If not in focus, the AF pulse number is calculated from the defocus amount and K value data, and the AF motor 39 is based on the calculated AF pulse number. Is driven (S213, S215, S217, S219). If it is in focus, the AF lock flag is set and the process returns (S215, S221).
[0045]
"Integration start processing"
The integration start process in S207 will be described in more detail with reference to FIG. This integration start process is a process in which the multi-focus detection sensor unit 21 starts integration and ends integration with an appropriate integration value.
[0046]
When the integration start process is entered, first, the maximum integration time elapsed flag and the forced end flag are cleared (S301). The maximum integration time elapsed flag indicates that the integrated value did not reach the integration end level VRM even when the sensors 212A to 212C to be used (corresponding to the monitor sensors MA to MC) passed the predetermined maximum integration time. The flag for forcibly ending the integration) and the forcible end flag identify that the integration was forcibly ended even though the integration values of the monitor sensors MA to MC did not reach the integration end level VRM. It is a flag to do. In this embodiment, all the sensors 212A, 212B, and 212C are used.
[0047]
Next, the maximum integration time is set in the RAM, the integration permission sensors 212A to 212C are set, and the AGC level (VAGC) is set (S303, S305, S307). Then, integration is started and integration time counting is started (S309, S311).
[0048]
Then, it waits for the integration of all permitted sensors 212A to 212C to end or for the maximum integration time to elapse (S313 to S323). That is, an integration time check process for checking the integration end and integration time of the sensors 212A to 212C that have permitted the integration is executed (S313), and it is checked whether the forced integration end flag is set (S315). If not, it is checked whether or not the maximum integration time has passed (S317), and if it has not passed, it is checked whether or not all of the sensors 212A to 212C that have allowed integration have ended (S319). If the integration of 212A to 212C has not been completed, the process returns to S313.
[0049]
When all the sensors 212A to 212C that have permitted the integration have completed the integration, the process returns as it is (S319). When the forced termination flag is set or when the forced termination flag is not set but the maximum integration time has elapsed, the maximum integration termination process is executed (S315, S321 or S315, S317, S321) and integration The integration of all the sensors 212A to 212C that have not ended is forcibly terminated and the process returns (S323).
[0050]
"CCD data input processing"
Next, the CCD data input process in S209 will be described in detail with reference to the flowchart shown in FIG.
[0051]
In this embodiment, an analog video signal in units of pixels that is sequentially output from the clamp circuit 27 and input to the CPU 35 is converted into digital video data by the A / D converter 35e built in the CPU 35. If the data is converted into video data, if the forced integration has not been completed and integration has been completed before the maximum integration time has elapsed, the ratio of the reference output and the video data are multiplied, and the multiplied value is stored as video data in the RAM 35b. To memory. Since the video data for which the forced integration has been completed or the maximum integration time has passed has already been gain-controlled in the amplifier 226, the value is stored in the RAM 35b as video data.
[0052]
The above processing is executed for video signals for all pixels of all the sensors 212A to 212C. In this embodiment, the video signal is first converted into 10-bit digital data by the A / D converter 35e. Furthermore, it is converted into 9-bit or 8-bit digital data according to the accuracy used for the focus detection calculation.
[0053]
In the CCD data input process, first, the A / D converter 35e is set to the 10-bit mode, and the number of bits (number of pixels) for A / D conversion is set in the built-in counter (S601, S603). Waiting for the A / D conversion synchronization signal ΦAD to fall to the low level, and when it falls to the low level, the A / D converter 35e starts A / D conversion (S605, S607, S609). When the A / D conversion is completed, the converted digital data is input and inverted (S609, S611). This inversion process is a process of converting the video signal so as to increase as the video signal becomes brighter since the signal falls as it becomes brighter from the video reference value, that is, the signal becomes smaller as it becomes brighter.
[0054]
In S619, it is checked whether or not the accuracy is 9 bits. Whether 9-bit accuracy or 8-bit accuracy is set according to the maximum output voltage of the multi-focus detection sensor unit 21, the performance of the camera, etc., is stored in the EEPROM 43 at the time of manufacture.
[0055]
If 9-bit precision is set, the 10-bit conversion value is divided by 2 and converted to 9-bit data (S619, S621), and it is checked whether 9-bit data exceeds FFh (hexadecimal, 255 in decimal). . If it exceeds FFh, limit processing is performed to make FFh, and the data is stored as video data in the RAM 35b (S623, S625, S633). For example, when the full range of the A / D converter 35e is 4 volts, the limit process is a process of cutting the maximum video data (input voltage) by a value corresponding to 2V. If the 9-bit data is less than or equal to FFh, the data is stored in the RAM 35b.
[0056]
On the other hand, if 8-bit precision is set, the 10-bit conversion value is divided by 4 and converted to 8-bit data (S619, S627), and it is checked whether the converted data exceeds the saturation output level. In such a case, a limit is applied at the saturation output level, and the limited value is stored as video data in the RAM 35b (S627, S629, S631, S633). The saturation output level in this embodiment corresponds to, for example, 2.7 V (ACh). When the data converted into 8-bit data does not reach the saturation output level, the converted data is stored as video data in the RAM 35b (S627, S629, S633).
[0057]
When the video data memory is completed, 1 is subtracted from the bit number of the counter. If the bit number after the subtraction is not 0, the process returns to S605 and repeats the processes of S605 to S635. In other words, the processing of S605 to S635 described above is executed for all the video signals VIDEO of all the sensors 212A to 212C to be used, and the process returns.
[0058]
By adjusting the accuracy of the above A / D conversion, for example, even when the saturation output voltage of the sensors 212A to 212C does not satisfy the full range of the A / D converter 35e, the saturation output voltage is set to 1 of the full range of the A / D converter 35e. Assuming / 2, the AGC level is set and the 9-bit A / D conversion value is obtained, thereby expanding the range and increasing the accuracy. The accuracy in this case is that the AGC level is set so that the saturation output voltage is about 70% of the full range when the saturation output voltage of the sensor satisfies the full range of the A / D converter 35e. The accuracy is equivalent to that obtained by the conversion by the converter 35e.
[0059]
The present invention has been described based on the embodiment applied to the CPU 35 incorporating the 10-bit A / D converter 35e. However, the present invention is not limited to this embodiment, and the A / D having an accuracy of 16 bits or more. A converter is also applicable.
[0060]
【The invention's effect】
As is apparent from the above description, the invention according to claim 1 includes a CPU incorporating a CCD line sensor for detecting a subject image and an A / D converter for A / D converting the output voltage of the CCD line sensor. Since the accuracy of the A / D converter can be switched in accordance with the saturation output voltage of the CCD line sensor, the output voltage of the CCD line sensor is kept constant regardless of the saturation output voltage of the CCD line sensor. Can be obtained with the accuracy of In other words, the difference between the full range of the A / D converter and the saturation output voltage of the CCD line sensor switches the A / D conversion accuracy. That As a result, the saturation output voltage of the CCD line sensor can be processed as data at a level close to the full range of the A / D converter. Therefore, even if the saturation output voltage of the CCD line sensor is different, it is possible to detect the focus with the same accuracy with the same CPU.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the main configuration of an embodiment in which a focus detection apparatus of the present invention is applied to a single-lens reflex camera.
FIG. 2 is a diagram illustrating an example of a multi-focus detection sensor of a single-lens reflex camera.
FIG. 3 is a block circuit diagram showing an outline of an A / D converter built in a CPU of a single-lens reflex camera.
FIG. 4 is a flowchart illustrating main operations of the single-lens reflex camera.
FIG. 5 is a flowchart related to AF processing of a single-lens reflex camera.
FIG. 6 is a flowchart related to integration start processing of the single-lens reflex camera.
FIG. 7 is a flowchart related to CCD data input processing of the single-lens reflex camera.
[Explanation of symbols]
11 Camera body
13 Main mirror
14 Half mirror
15 Submirror
21 Multi-focus detection sensor unit
211 CCD transfer unit
212A A sensor
212B B sensor
212C C sensor
221 CCD control circuit
222 Timing generator
223 Driver circuit
224 AGC control circuit
225A A integral control circuit
225B B integration control circuit
225C C integration control circuit
226 amplifier
35 Main CPU (control means)
35b RAM
35e A / D converter
MA A monitor sensor
MB B monitor sensor
MCC monitor sensor

Claims (2)

In a focus detection apparatus including a CCD line sensor that receives a subject image and outputs a signal voltage corresponding to luminance, and a control unit that includes an A / D converter that performs A / D conversion on the output voltage of the CCD line sensor. ,
The control means performs A / D conversion on the output voltage of the CCD line sensor at the maximum resolution by the A / D converter, and further converts the digital data converted at the maximum resolution to a saturation output voltage of the CCD line sensor. Is equal to or more than half of the full range of the A / D converter, it is converted into digital data having a resolution lower than the maximum resolution processed by the control means, and the saturation output voltage is converted into the A / D converter. If less than half of the vessels of the full range is that the a lower resolution than the maximum resolution of the a / D converter, for converting the digital data of higher resolution than the resolution of said control means for processing, the Feature focus detection device. 2. The focus detection apparatus according to claim 1, wherein the A / D converter has a maximum resolution of 10 bits, digital data converted by the 10 bits is further converted to the saturation output voltage of the CCD line sensor. When it is ½ or more of the full range of the converter, it is converted to 8-bit digital data, which is the resolution processed by the control means , and when the saturation output voltage is less than ½ of the full range of the A / D converter A focus detection device for converting to 9-bit digital data.

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