JP3768143B2 - Magnetic memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a magnetic memory device, and more particularly to a magnetic memory device including a storage element exhibiting a ferromagnetic tunnel effect.
[0002]
[Prior art]
Conventionally, an MRAM (Magnetic Random Access Memory), which is a non-volatile memory that records data using magnetism, is known. Regarding this MRAM, NIKKEI ELECTRONICS 1999.11.15 (no.757) pp. 49-56 and the like.
[0003]
18 and 19 are schematic views for explaining the structure of the memory element of the MRAM disclosed in the above-mentioned literature. Referring to FIG. 18, a memory element 110 of a conventional MRAM includes a ferromagnetic layer 101, a ferromagnetic layer 103, and a nonmagnetic layer 102 disposed between the ferromagnetic layers 101 and 103. .
[0004]
The ferromagnetic layer 101 is more difficult to reverse than the ferromagnetic layer 103. Here, ferromagnetism means magnetism in the case where a magnetic atom or a free atom of a metal forms a spontaneous magnetization by aligning magnetic moments in parallel by positive exchange interaction. Is called a ferromagnetic material. The ferromagnetic layers 101 and 103 are made of this ferromagnetic material. Conventionally, as the nonmagnetic layer 102, a GMR (Giant Magnetoresistance) film using a metal is used. In recent years, a TMR (Tunneling Magneto Resistance) film using an insulator as the nonmagnetic layer 102 has been developed. This TMR film has the advantage that the resistance is higher than that of the GMR film. Specifically, the MR ratio (resistance change rate) of the GMR film is on the order of 10%, whereas the MR ratio (resistance change rate) of the TMR film is 20% or more. The memory element 110 made of the TMR film is hereinafter referred to as a TMR element 110.
[0005]
Next, the storage principle of the MRAM using the conventional TMR element 110 will be described with reference to FIGS. First, as shown in FIG. 18, a state in which the magnetizations of the two ferromagnetic layers 101 and 103 are in the same direction (parallel) is associated with data “0”. Further, as shown in FIG. 19, the state in which the magnetizations of the two ferromagnetic layers 101 and 103 are opposite (antiparallel) is associated with data “1”. Here, the TMR element 110 has a resistance (R) when the magnetization directions are parallel.₀) Is small and antiparallel, resistance (R₁) Is large. Using the property that the resistance of the TMR element 110 differs depending on whether the magnetization direction is parallel or antiparallel, it is determined whether it is “0” or “1”.
[0006]
FIG. 20 is a block diagram showing the overall configuration of an MRAM in the case where a memory cell is configured by one conventional TMR element and one transistor. The configuration of the conventional MRAM 150 will be described below with reference to FIG.
[0007]
The memory cell array 151 includes a plurality of memory cells 120 arranged in a matrix (only four memory cells 120 are shown in FIG. 20 for the sake of simplicity). One memory cell 120 is composed of one TMR element 110 and one NMOS transistor 111.
[0008]
In each memory cell 120 arranged in the row (row) direction, the gate of the NMOS transistor 111 is connected to a common read word line RWL.₁~ RWL_nIt is connected to the. In each memory cell 120 arranged in the row (row) direction, a rewrite word line WWL is placed on one ferromagnetic layer of the TMR element 110.₁~ WWL_nIs arranged.
[0009]
In each memory cell 120 arranged in the column direction, one ferromagnetic layer of the TMR element 110 is connected to the common bit line BL.₁~ BL_nIt is connected to the.
[0010]
Each read word line RWL₁~ RWL_nAre connected to the row decoder 152 and each bit line BL₁~ BL_nAre connected to the column decoder 153.
[0011]
A row address and a column address designated from the outside are input to the address pin 154. The row address and column address are transferred from the address pin 154 to the address latch 155. Of the addresses latched by the address latch 155, the row address is transferred to the row decoder 152 via the address buffer 156, and the column address is transferred to the column decoder 153 via the address buffer 156.
[0012]
The row decoder 152 is connected to each read word line RWL.₁~ RWL_nAmong them, the read word line RWL corresponding to the row address latched by the address latch 155 is selected and each rewrite word line WWL is selected.₁~ WWL_nAmong them, the rewrite word line WWL corresponding to the row address latched by the address latch 155 is selected. In addition, the row decoder 152 generates a read word line RWL based on a signal from the voltage control circuit 157.₁~ RWL_nPotential and each rewrite word line WWL₁~ WWL_nTo control the potential.
[0013]
The column decoder 153 is connected to each bit line BL₁~ BL_nAmong them, the bit line corresponding to the column address latched by the address latch 155 is selected, and each bit line BL is selected based on the signal from the voltage control circuit 158.₁~ BL_nTo control the potential.
[0014]
Data designated from the outside is input to the data pin 159. The data is transferred from the data pin 159 to the column decoder 153 via the input buffer 160. The column decoder 153 uses each bit line BL₁~ BL_nIs controlled in accordance with the data.
[0015]
Data read from any memory cell 120 is stored in each bit line BL.₁~ BL_nTo the sense amplifier group 161 via the column decoder 153. The sense amplifier group 161 is a current sense amplifier. Data discriminated by the sense amplifier group 161 is output from the output buffer 162 to the outside via the data pin 159.
[0016]
The operation of each circuit (152 to 162) described above is controlled by the control core circuit 163.
[0017]
Next, a write (rewrite) operation and a read operation of the conventional MRAM 150 configured as described above will be described.
[0018]
(Write operation)
In this write operation, orthogonal currents are passed through the selected rewrite word line WWL and bit line BL. Thereby, only the TMR element 110 at the intersection of the bit line BL and the rewrite word line WWL can be rewritten. Specifically, each current flowing through the rewrite word line WWL and the bit line BL generates a magnetic field, and the sum of the two magnetic fields (synthetic magnetic field) acts on the TMR element 110. The direction of magnetization of the TMR element 110 is reversed by this combined magnetic field, and changes from “1” to “0”, for example.
[0019]
There are two types of TMR elements 110 other than the intersections, one in which no current flows and the other in which a current flows only in one direction. In the TMR element 110 in which no current flows, no magnetic field is generated, so the direction of magnetization does not change. In the TMR element 110 that flows only in one direction, a magnetic field is generated, but its magnitude is insufficient for reversal of magnetization. For this reason, in the TMR element 110 in which only current in one direction flows, the magnetization direction does not change.
[0020]
As described above, the TMR element located at the intersection of the selected bit line BL and the rewrite word line WWL by passing a current through the bit line BL corresponding to the selected address and the rewrite word line WWL. The magnetization direction of 110 can be written in the direction shown in FIG. As a result, data “0” or “1” can be written.
[0021]
(Read operation)
When reading the written data as described above, a voltage is applied to the read word line RWL to make the NMOS transistor 111 conductive. In this state, it is determined whether the current value flowing through the bit line BL is larger or smaller than the reference current value, thereby determining “1” or “0”.
[0022]
In this case, in the case of the data “0” shown in FIG. 18, the magnetization direction is parallel, so the resistance value (R₀) Is small. For this reason, the current value flowing through the bit line BL is larger than the reference current value. On the other hand, in the case of the data “1” shown in FIG. 19, since the magnetization direction is antiparallel, the resistance value (R₁) Is larger than that shown in FIG. For this reason, the current value flowing through the bit line BL is smaller than the reference current value.
[0023]
[Problems to be solved by the invention]
In the conventional MRAM 150 described above, when reading data, it is necessary to detect the current value by setting the potential of the bit line to a very small potential (0.4 V or less). This is because the TMR element 110 has a characteristic that a resistance change cannot be confirmed unless the potential difference applied to both ends of the TMR element 110 is small. For this reason, it is necessary to make the potential difference applied to both ends of the TMR element 110 very small (0.4 V or less), and as a result, the flowing current value becomes very small. Conventionally, in order to detect such a small current value, there is a disadvantage that the configuration of the sense amplifier (amplifier) becomes complicated. In addition, there is a problem that the reading speed becomes slow when trying to detect a minute current value.
[0024]
The present invention has been made to solve the above problems,
One object of the present invention is to provide a magnetic memory device in which the configuration of a sense amplifier (amplifier) is not complicated.
[0025]
Another object of the present invention is to provide a magnetic memory device capable of improving the reading speed as compared with the case where data is discriminated by detecting a minute current value.
[0026]
Still another object of the present invention is to facilitate replacement of a DRAM in the above magnetic memory device.
[0027]
[Means for Solving the Problems]
  The magnetic memory device according to claim 1 comprises:A first magnetic layer; and a second magnetic layer disposed opposite to the first magnetic layer with an insulating barrier layer interposed therebetween and less likely to reverse than the first magnetic layer.A memory cell comprising a first memory element and a second memory element exhibiting a ferromagnetic tunnel effect, and first and second transistors connected to the first and second memory elements, respectively; A word line connected to the control terminal, a bit line connected to the first memory element via the first transistor, and a bit line and bit line pair connected to the second memory element via the second transistor And an inverting bit line that connects to the bit line and the inverting bit line,The second magnetic layer of the first memory element and the second magnetic layer of the second memory element are connected to each other, and the second magnetic layer of the first memory element and the second magnetic layer An auxiliary word line for reducing the potential of the second memory element to the second magnetic layer to the ground potential;It has. AndAfter setting the bit line, the inverted bit line, and the auxiliary word line to a predetermined potential, the potential of the auxiliary word line is lowered in accordance with the rise timing of the signal to the word line, so that the second magnetic property of the first memory element is reduced. The potential of the layer and the second magnetic layer of the second memory element is lowered to the ground potential, and at that time, the bit line and the inverted bit line are caused by the difference in resistance value between the first memory element and the second memory element. A potential difference generated transiently is read out using an amplifier.
[0028]
According to the first aspect of the present invention, as described above, a memory cell is constituted by the two first and second memory elements exhibiting the ferromagnetic tunnel effect and the two first and second transistors, and the two first and second memory elements are formed. Data can be easily read by detecting the potential difference between the bit line connected to the memory element and the inverted bit line with an amplifier. This eliminates the need to detect a minute current value flowing through the bit line as in the case where a memory cell is constituted by one memory element and one transistor exhibiting a conventional ferromagnetic tunnel effect. As a result, the configuration of the amplifier is not complicated. In addition, unlike a conventional case where a minute current value flowing in a bit line is read out by reading out a potential difference generated between the bit line and the inverted bit line using an amplifier by inputting a signal to the word line, the memory element Even when the resistance is high, detection can be easily performed.
[0029]
According to the first aspect of the present invention, as described above, the potential difference between the bit line and the inverted bit line is detected by the amplifier, so that it is as simple as the amplifier (sense amplifier) used in the conventional DRAM. The amplifier can be used to read data stored in the magnetic memory device. As a result, it is not necessary to use a sense amplifier having a complicated configuration as in the case where a memory cell is composed of one memory element and one transistor exhibiting the conventional ferromagnetic tunnel effect, and high-speed reading is possible. Become. Further, since the configuration and circuit configuration of the sense amplifier and the operation method are similar to those of the conventional DRAM, the DRAM technology can be used as it is. As a result, replacement from DRAM is easy.
[0031]
  Claim1Then, ComplementThe auxiliary word line can easily lower the potential of the second magnetic layer of the first memory element and the second magnetic layer of the second memory element in the direction of the ground potential. As a result, when the potential between the second magnetic layer of the first memory element and the second magnetic layer of the second memory element is lowered to the ground potential, it is caused by the difference in resistance between the first memory element and the second memory element. Thus, a potential difference can be generated between the bit line and the inverted bit line. The stored data can be easily detected by detecting the potential difference with an amplifier.
[0032]
  Claim2The magnetic memory device in claim1'sIn the configuration, the signal fall timing to the word line is performed before the potential of the second magnetic layer of the first memory element and the potential of the second magnetic layer of the second memory element become the ground potential. Claim2Thus, with this configuration, it is possible to prevent the potential difference between the bit line and the inverted bit line from disappearing. That is, the potential difference between the bit line and the inverted bit line occurs only in the transient state. Therefore, when the potential of the second magnetic layer of the first and second memory elements becomes the ground potential, the bit line and the inverted bit line connected to the first magnetic layer also become the ground potential. As a result, the potential difference between the bit line and the inverted bit line disappears. Claim2Then, by lowering the signal to the word line before the potential of the second magnetic layer of the first and second memory elements becomes the ground potential, the potential difference is reduced before the potential difference between the bit line and the inverted bit line disappears. It can be detected by an amplifier.
[0033]
  Claim3The magnetic memory device according to claim 1.Or 2In the configuration, an amplifier and a separation transistor for separating the bit line and the inverted bit line are further provided in accordance with the fall timing of the signal to the word line. Claim3With this configuration, the amplifier is separated from the bit line and the inverted bit line by the isolation transistor before the potential of the second magnetic layer of the first and second storage elements becomes the ground potential. Thus, the potential difference between the bit line and the inverted bit line can be read out by the amplifier.
[0034]
  Claim4In the magnetic memory device according to claim 1,3In any of the configurations, the first storage element and the second storage element store data opposite to each other. Claim4With this configuration, data can be easily read using the resistance difference between the first memory element and the second memory element.
[0035]
  Claim5In the magnetic memory device in claim1'sThe configuration further includes a dummy bit line connected to the first memory element via the first transistor, and a detection circuit for detecting the falling timing of the dummy bit line. Claim5With this configuration, the falling timing of the bit line can be detected using the dummy bit line and the detection circuit. Thus, if the potential difference between the bit line and the inverted bit line is detected by the amplifier at the detected timing, the stored data can be easily read out.
[0036]
  Claim6In the magnetic memory device in claim5The configuration further comprises an amplifier and a separation transistor for separating the bit line and the inverted bit line according to the falling timing of the dummy bit line detected by the detection circuit, and the amplifier is detected by the detection circuit. The dummy bit line is activated according to the fall timing. Claim6Thus, with this configuration, the potential difference between the bit line and the inverted bit line can be easily detected by the amplifier.
[0037]
  Claim7In the magnetic memory device in claim5Or6In the configuration, the detection circuit includes a first transistor to which the input voltage is applied to the gate and a second transistor to which the reference voltage is applied to the gate, and a current flowing through the first transistor is determined from a current flowing through the second transistor. Also, when the input voltage is equal to the reference voltage, the L level is output. Claim7Thus, with this configuration, it is possible to effectively prevent the output from becoming unstable when the input voltage is the same as the reference voltage.
[0038]
  Claim8The magnetic memory device in FIG. 1 includes a first magnetic layer, a second magnetic layer having one surface opposed to the surface of the first magnetic layer via a first insulating barrier layer, and the other surface of the second magnetic layer. Includes a third magnetic layer disposed opposite to the second insulating barrier layer.Thus, the second magnetic layer is more difficult to reverse than the first magnetic layer and the third magnetic layer.A memory cell comprising one storage element exhibiting a ferromagnetic tunnel effect, first and second transistors connected to the first magnetic layer and the third magnetic layer of the storage element, respectively, and control of the first and second transistors A word line connected to the terminal, a bit line connected to the first magnetic layer via a first transistor, and a bit line and bit line pair connected to the third magnetic layer via a second transistor And an inverting bit line that connects to the bit line and the inverting bit line,,
An auxiliary word line for lowering the potential of the second magnetic layer of the storage element to the ground potential in accordance with the rise timing of the signal to the word line;It has. AndAfter setting the bit line, the inverted bit line, and the auxiliary word line to a predetermined potential, the potential of the auxiliary word line is lowered to the ground potential in accordance with the rising timing of the signal to the word line, so that The potential of the magnetic layer is lowered to the ground potential, and at that time, transiently occurs between the bit line and the inverted bit line due to the difference in resistance between the first magnetic layer and the third magnetic layer of the memory element. The potential difference is read out using an amplifier.
[0039]
  Claim8Then, as described above, a memory cell is composed of one memory element that exhibits the ferromagnetic tunnel effect including the first, second, and third magnetic layers, and two first and second transistors, and the first The data can be easily read by detecting the potential difference between the bit line connected to the third magnetic layer and the inverted bit line by the amplifier. This eliminates the need to detect a minute current value flowing through the bit line as in the case where a memory cell is constituted by one memory element and one transistor exhibiting a conventional ferromagnetic tunnel effect. As a result, the configuration of the amplifier is not complicated. In addition, unlike a conventional case where a minute current value flowing in a bit line is read out by reading out a potential difference generated between the bit line and the inverted bit line using an amplifier by inputting a signal to the word line, the memory element Even when the resistance is high, detection can be easily performed.
[0040]
  Claims8Then, by forming a memory cell by one memory element that exhibits the ferromagnetic tunnel effect including the first, second, and third magnetic layers and two first and second transistors, two memory elements and 2 The area of the memory cell can be reduced as compared with the case where the memory cell is constituted by one transistor.
[0041]
  Claims8Then, as described above, by using a simple amplifier similar to the amplifier (sense amplifier) used in the conventional DRAM by configuring the amplifier to detect the potential difference between the bit line and the inverted bit line, Data stored in the magnetic memory device can be read. As a result, it is not necessary to use a sense amplifier having a complicated configuration as in the case where a memory cell is composed of one memory element and one transistor exhibiting the conventional ferromagnetic tunnel effect, and high-speed reading is possible. Become. Further, since the configuration and circuit configuration of the sense amplifier and the operation method are similar to those of the conventional DRAM, the DRAM technology can be used as it is. As a result, replacement from DRAM is easy.According to the eighth aspect of the present invention, the potential of the second magnetic layer of the memory element can be easily lowered in the direction of the ground potential by the auxiliary word line. Thereby, when the potential of the second magnetic layer of the memory element is lowered to the ground potential, a potential difference can be generated between the bit line and the inverted bit line due to the difference in resistance value of the memory element. The stored data can be easily detected by detecting the potential difference with an amplifier.
[0042]
  Claim9In the magnetic memory device in claim8In the configuration, the first magnetic layer includes a sidewall-shaped first magnetic layer formed on one side surface of the second magnetic layer via the first insulating barrier layer, and the third magnetic layer includes the second magnetic layer. A sidewall-shaped third magnetic layer is formed on the other side surface of the layer via a second insulating barrier layer. Claim9Thus, with this configuration, it is possible to easily form one memory element including the first magnetic layer, the second magnetic layer, and the third magnetic layer.
[0046]
  Claim10In the magnetic memory device in claim8 or 9In this configuration, the timing of the signal fall to the word line is performed before the potential of the second magnetic layer of the memory element becomes the ground potential. Claim10Thus, with this configuration, it is possible to prevent the potential difference between the bit line and the inverted bit line from disappearing. That is, the potential difference between the bit line and the inverted bit line occurs only in the transient state. Therefore, when the potential of the second magnetic layer of the memory element becomes the ground potential, the bit line and the inverted bit line connected to the first magnetic layer and the third magnetic layer also become the ground potential. As a result, the potential difference between the bit line and the inverted bit line disappears. Claim10Then, the potential difference between the bit line and the inverted bit line is detected by an amplifier by dropping the signal to the word line before the potential of the second magnetic layer of the storage element becomes the ground potential. Can do.
[0047]
  Claim11In the magnetic memory device in claim8~10In any of the configurations, an amplifier and an isolation transistor for isolating the bit line and the inverted bit line are further provided in accordance with the fall timing of the signal to the word line. Claim11With this configuration, before the potential of the second magnetic layer of the storage element becomes the ground potential, the amplifier is separated from the bit line and the inverted bit line by the isolation transistor, thereby the bit line. And the potential difference between the inverted bit line can be read out by an amplifier.
[0048]
  Claim12In the magnetic memory device in claim8~11In any of the configurations, data opposite to each other is stored in the first magnetic layer and the third magnetic layer. Claim12With this configuration, data can be easily read using the resistance difference between the resistance of the first magnetic layer and the second magnetic layer and the resistance of the third magnetic layer and the second magnetic layer. Can do.
[0051]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below with reference to the drawings.
[0052]
(First embodiment)
FIG. 1 is a block diagram showing the overall configuration of the MRAM according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing a memory cell portion and a sense amplifier portion of the MRAM according to the first embodiment shown in FIG. FIG. 3 is an operation waveform diagram for explaining the read operation of the MRAM shown in FIGS.
[0053]
First, the overall configuration of the MRAM according to the first embodiment will be described with reference to FIGS. 1 and 2. The MRAM of the first embodiment has the same configuration as that of a conventional DRAM except for the memory cell array. This will be specifically described below. The MRAM according to the first embodiment is configured around a matrix memory cell array 51. The memory cell array 51 includes memory cells 52 arranged in the row direction and the column direction. The memory cell 52 stores 1-bit data which is the minimum unit of storage.
[0054]
In the MRAM of the first embodiment, one memory cell 52 includes two TMR elements 4a and 4b and two NMOS transistors 5a and 5b. As shown in FIG. 2, the TMR element 4a includes a ferromagnetic layer 3a, an insulating barrier layer 2a, and a ferromagnetic layer 1a that is more difficult to reverse than the ferromagnetic layer 3a. The TMR element 4b includes a ferromagnetic layer 3b, an insulating barrier layer 2b, and a ferromagnetic layer 1b that is more difficult to reverse than the ferromagnetic layer 3b. A word line WL is connected to the gates of the two NMOS transistors 5a and 5b.
[0055]
The TMR element 4a is an example of the “first memory element exhibiting a ferromagnetic tunnel effect” according to the present invention, and the TMR element 4b is an example of the “second memory element exhibiting a ferromagnetic tunnel effect” according to the present invention. is there. The ferromagnetic layers 3a and 3b are examples of the “first magnetic layer” in the present invention, and the ferromagnetic layers 1a and 1b are examples of the “second magnetic layer” in the present invention. The NMOS transistors 5a and 5b are examples of the “first transistor” and the “second transistor” in the present invention, respectively. The gates of the two NMOS transistors 5a and 5b are an example of the “control terminal” in the present invention.
[0056]
In the memory cell array 51, each memory cell 52 arranged in the row direction (vertical direction in FIG. 1) is connected to the word line WL and the auxiliary word line SWL. The memory cells 52 arranged in the column direction (horizontal direction in FIG. 1) are connected to the bit line BL and the inverted bit line / BL. The inverted bit line / BL constitutes one set of bit line pairs with the bit line BL in a corresponding relationship.
[0057]
Further, each bit line pair BL, / BL is connected to each sense amplifier (SA) 53 of a cross couple latch type. In each bit line pair BL, / BL, the signal levels of the bit line BL and the inverted bit line / BL change complementarily. Also, an NMOS transistor for separating each bit line pair BL, / BL and each sense amplifier (SA) 53 between each bit line pair BL, / BL and each sense amplifier (SA) 53. 8a and 8b are provided. A signal line Φ3 is connected to the gates of the NMOS transistors 8a and 8b. The NMOS transistors 8a and 8b are examples of the “separation transistor” in the present invention. The sense amplifier 53 is an example of the “amplifier” in the present invention.
[0058]
Each word line WL is connected to the row decoder 54. When a row address RA is designated from the outside, the row address RA is given from the row address buffer 55 to the row decoder 54. Thereby, the row decoder 54 selects the word line WL corresponding to the row address RA.
[0059]
Each word line WL is connected to one end of an auxiliary word line SWL via an inverter circuit including an NMOS transistor 6 and a PMOS transistor 7. Vcc is connected to the other end of the auxiliary word line SWL via a PMOS transistor 9. A signal line Φ 4 is connected to the gate of the PMOS transistor 9.
[0060]
The word line WL is connected to one input terminal of the AND circuit 11 and also connected to the output terminal of the AND circuit 11. The other input terminal of the AND circuit 11 is connected to a signal line Φ6 that is always 0 (L level) during writing.
[0061]
Also, NMOS transistors 10a and 10b are connected to the bit line BL and the inverted bit line / BL, respectively. A signal line Φ5 is connected to the gates of the NMOS transistors 10a and 10b. One ends of the NMOS transistors 10a and 10b are connected to each other. A precharge circuit 67 is connected to the NMOS transistors 10a and 10b connected to each other.
[0062]
Each sense amplifier 53 is connected to an input / output line I / O and an inverted input / output line / I / O through each transfer gate 56. The input / output line I / O and the inverted input / output line / I / O constitute an input / output line pair I / O, / I / O. The input / output line pair I / O, / I / O is connected to the read amplifier 57. The read amplifier 57 is connected to a data output circuit 58 via a data bus DB and an inverted data bus / DB. The data bus DB and the inverted data bus / DB constitute a data bus line pair DB, / DB. A precharge circuit 59 is connected to the input / output line pair I / O, / I / O.
[0063]
The levels of the input / output line I / O and the inverted input / output line / I / O change complementarily. Further, the levels of the data bus DB and the inverted data bus / DB change complementarily. Data is output from the output circuit 58 to the outside.
[0064]
Each transfer gate 56 is connected to a column decoder 60 via a column selection line CSL. Each transfer gate 56 includes a pair of NMOS transistors connected between the input / output line pair I / O, / I / O and the sense amplifier 53. The gates of the pair of NMOS transistors are connected to the column decoder 60 via one column selection line CSL. Therefore, when the column selection line CSL becomes H level, the pair of NMOS transistors is turned on, and the transfer gate 56 is turned on.
[0065]
When a column address CA is designated from the outside, the column address CA is supplied from the column address buffer 61 to a column decoder 60 and an address transition detection circuit (ATD: Address Transition Detector) 62.
[0066]
The ATD 62 detects a change in the column address CA, detects that the column address CA is designated from the outside, and generates a one-pulse pulse signal ATD1. That is, every time the column address CA changes, the pulse signal ATD1 is generated. The pulse signal ATD1 is output to the column decoder control circuit 63, the precharge control circuit 64, and the read amplifier control circuit 65.
[0067]
The precharge control circuit 64 generates a 1-pulse precharge circuit activation signal PC that is set to the H level for a preset time based on the fall of the pulse signal ATD1 from the H level to the L level. The activation signal PC is output to the precharge circuit 59.
[0068]
When activated, precharge circuit 59 sets input / output line pair I / O and / I / O to the same potential, and at the same time, precharge circuit 59 is set to a predetermined potential (for example, 1/2 Vcc: Vcc is a drive voltage of MRAM). It is designed to charge.
[0069]
When the activation signal PC is input, the precharge circuit 59 is deactivated (activated standby state) and stops precharging the input / output line pair I / O and / I / O. The column decoder control circuit 63 generates a one-column column decoder activation signal YS that is at a preset time H level based on the fall of the pulse signal ATD1 from the H level to the L level. The activation signal YS is output to the column decoder 60.
[0070]
The column decoder 60 is activated when the activation signal YS is input, and selects a column (one bit line pair BL, / BL) of the memory cell array 51 corresponding to the column address CA designated from the outside. That is, the column decoder 60 is activated when the activation signal YS is input. When activated, the column decoder 60 selects the column selection line CSL corresponding to the column address CA designated from the outside, and sets the column selection line CSL to the H level. As a result, the transfer gate 56 connected to the column selection line CSL is turned on. Therefore, the column of the memory cell array 51 corresponding to the column address CA designated from the outside is selected via the sense amplifier 53 corresponding to the transfer gate 56.
[0071]
The read amplifier control circuit 65 generates a one-pulse read amplifier activation signal READ obtained by delaying the pulse signal ATD1 for a predetermined time based on the fall of the pulse signal ATD1 from the H level to the L level. The timing and pulse width of the activation signal READ are set in advance. The activation signal READ is output to the read amplifier 57.
[0072]
The delay time of the activation signal READ is a time until the potential difference between the input / output pair lines I / O and / I / O becomes a potential difference sufficient for reading data. That is, based on the data read from the memory cell 52, the potential changes from a potential at which the input / output line pair I / O, / I / O is precharged to a potential difference sufficient to prevent the read amplifier 57 from erroneously reading. The time to wait for is set.
[0073]
That is, each of the control circuits 63 to 65 includes a delay circuit and a pulse generator that generate the activation signals YS, PC, and READ at an appropriate timing and pulse width in response to the fall of the pulse signal ATD1 from the H level to the L level. Each circuit is provided.
[0074]
Further, a read detection circuit 66 that detects a potential difference between the data bus line pair DB, / DB and generates a read detection signal READ based on the detection result is provided. Thereby, when the potential of the data bus line pair DB, / DB becomes equal to or greater than a predetermined potential difference, the data read from the memory cell 52 is determined and output to the outside. Therefore, the data output (read operation) can be detected by detecting the potential difference between the data bus line pair DB, / DB. The read detection circuit 66 detects a read operation based on the potential difference between the data bus line pair DB, / DB, and generates an H level read detection signal READ based on the detection result. This detection signal READ is output to the column decoder control circuit, precharge control circuit 64 and read amplifier 65.
[0075]
FIG. 4 is a cross-sectional structure diagram showing the memory cell portion of the first embodiment shown in FIGS. A cross-sectional structure of the memory cell 52 of the first embodiment will be described below with reference to FIG. In the memory cell 52 of the first embodiment, an isolation region 72 is formed in a predetermined region on the surface of the substrate 71. In the element formation region surrounded by the isolation region 72, N-type source / drain regions 73 are formed at a predetermined interval. On the channel region located between adjacent N-type source / drain regions 73, gate electrodes constituting word lines WL1 and WL2 are formed. This gate electrode and a pair of N-type source / drain regions constitute an NMOS transistor 5a.
[0076]
Further, the ferromagnetic layer 3a of the TMR element 4a is connected to the N-type source / drain regions 73 located at both ends via conductive layers 74 and 75. The ferromagnetic layer 3a is easily inverted and changes its direction according to data as shown in FIG. On the other surface of the ferromagnetic layer 3a, a ferromagnetic layer 1a that is more difficult to reverse than the ferromagnetic layer 3a is formed via an insulating barrier layer 2a. The ferromagnetic layer 1a is fixed in one direction without being inverted according to data. Auxiliary word lines SWL1 and SWL2 are connected to the ferromagnetic layer 1a via a conductive layer 77. A bit line BL is connected to the central N-type source / drain region 73 through a conductive layer 76. An interlayer insulating film 78 is formed between the bit line BL and the substrate 71.
[0077]
If the memory cell having the cross-sectional structure as described above is used, the MRAM memory cell 52 of the first embodiment having the circuit configuration shown in FIGS. 1 and 2 can be easily realized.
[0078]
Next, write and read operations of the MRAM configured as described above will be described.
[0079]
(Write operation)
In this write operation, a case where data is written to the memory cell 52 connected to the word line WL1 will be described. In the MRAM of the first embodiment, when data is written, first, the signal line Φ6 is set to L level. As a result, an L level signal is input to the other input terminal of the AND circuit 11. In this case, since the word line WL1 input to one input terminal of the AND circuit 11 is the word line selected by the row decoder 54, it is at the H level. Therefore, the portion of the selected word line WL1 output from the AND circuit 11 is at L level. Thus, by setting the signal line Φ6 to the L level, the word line WL1 connected to the output of the AND circuit 11 is forcibly set to the L level.
[0080]
Thereby, NMOS transistors 5a and 5b connected to word line WL1 connected to the output terminal of AND circuit 11 are turned off. Then, the PMOS transistor 9 is turned on by lowering the signal line Φ4 to the L level. In this case, since the word line WL1 connected to SWL1 via the inverter is in the H level, the NMOS transistor 6 constituting the inverter is turned on. As a result, the lower portion of SWL1 becomes the ground potential. In the upper part of SWL1, since the PMOS transistor 9 is turned on by the fall of Φ4 and becomes the Vcc potential, a current flows through SWL1 from the top to the bottom.
[0081]
Further, the selected bit line BL and the inverted bit line / BL are set to the H level and the L level, respectively, using the input / output line pair I / O, / I / O. Furthermore, the NMOS transistors 10a and 10b are turned on by raising the signal line Φ5 to the H level. As a result, the bit line BL and the corresponding inverted bit line / BL are short-circuited, and current flows from the H level bit line BL to the L level inverted bit line / BL. That is, a current in the left direction flows through the bit line BL, and a current in the right direction flows through the inverted bit line / BL.
[0082]
When the current flowing through the bit line BL and the inverted bit line / BL is in the opposite direction, an L level signal is applied to the bit line BL and an H level signal is applied to the inverted bit line / BL. give.
[0083]
As described above, in the selected memory cell, a current in the downward direction is supplied to the auxiliary word line SWL1, and currents in the opposite directions are supplied to the bit line pair BL, / BL. Reverse data (for example, “1”, “0”) can be easily written in the ferromagnetic layer 3a of the cell TMR element 4a and the ferromagnetic layer 3b of the TMR element 4b.
[0084]
Note that when data opposite to the above (for example, “0”, “1”) is written in the ferromagnetic layer 3a of the TMR element 4a and the ferromagnetic layer 3b of the TMR element 4b, BL and / The direction of the current flowing to BL may be reversed.
[0085]
Further, since no current flows through the auxiliary word line SWL in the unselected memory cell, data is not rewritten.
[0086]
(Read operation)
As described above, in the data write operation, the ferromagnetic layer 3a of the TMR element 4a connected to the bit line BL and the ferromagnetic layer 3b of the TMR element 4b connected to the inverted bit line / BL are In each case, data that is a reverse magnetic field is written. Hereinafter, a read operation when the memory cell 52 connected to the word line WL1 is selected will be described with reference to FIG.
[0087]
First, before the word line WL1 rises, the word line WL1 is in an L level state. In this case, since the PMOS transistor 7 of the inverter circuit connected to the word line WL1 is turned on, the potential of the auxiliary word line SWL1 becomes Vcc. As a result, the potential at the node a also becomes Vcc. Since TMR elements 4a and 4b are conductors, the potentials of TMR elements 4a and 4b are also Vcc. In this state, Φ5 is raised to H level, and the precharge circuit 67 precharges the bit line BL and the inverted bit line / BL to Vcc. When the word line WL1 rises, the word line WL1 is set to the H level by the row decoder 54, so that the NMOS transistors 5a and 5b connected to the word line WL1 are turned on. As a result, bit line BL and inverted bit line / BL are electrically connected to TMR elements 4a and 4b. In this state, the potentials of bit line BL, inverted bit line / BL and node a are Vcc.
[0088]
Further, when the word line WL1 rises to the H level, Φ5 becomes the L level, the precharge circuit 67 is turned off, and the NMOS transistor 6 of the inverter circuit connected to the word line WL1 is turned on, so that the auxiliary word line The potential of SWL1 is gradually lowered toward the GND potential. As a result, the potential of the node a is gradually lowered to the GND potential. As a result, the potentials of the bit line BL and the inverted bit line / BL are also gradually lowered to the GND potential. Here, in the TMR element 4a connected to the bit line BL side, the direction of the magnetic field is reversed between the upper and lower ferromagnetic layers 3a and 1a, and therefore the TMR element 4b connected to the inverted bit line / BL. The resistance is slightly higher than
[0089]
Note that at the timing when the potential of the bit line BL and the inverted bit line / BL starts to be lowered toward the GND potential, the bit line BL and the inverted bit line / BL and the node a have a slight potential difference, and therefore the MR ratio. The (resistance change rate) becomes the largest state.
[0090]
As the potential of the node a decreases, the potentials of the bit line BL and the inverted bit line / BL also decrease. In this case, since the TMR element 4a on the bit line BL side has a slightly high resistance, the way of decreasing the potential is slower than that of the inverted bit line / BL. As a result, a potential difference is generated between the bit line BL and the inverted bit line / BL. At the timing when this potential difference occurs, the word line falls from the H level to the L level as shown in FIG.
[0091]
The falling timing of the word line WL1 is performed before the potential of the node a becomes the GND potential. This is due to the following reason. That is, the potential difference between the bit line BL and the inverted bit line / BL occurs only in the transient state. Therefore, when the potentials of the ferromagnetic layers 1a and 1b (the potential of the node a) of the TMR elements 4a and 4b become the GND potential, the bit line BL and the inverted bit line / BL connected to the ferromagnetic layers 3a and 3b are also GND. Become potential. In this case, the potential difference between the bit line BL and the inverted bit line / BL disappears, so that the potential difference cannot be detected.
[0092]
At the transient timing, a potential difference is generated between the bit line BL and the inverted bit line / BL. However, since the TMR elements 4a and 4b are conductors, the bit line BL and the inverted bit line / BL are finally at the same potential. become. For this reason, the signal line Φ3 is lowered according to the fall timing of the word line WL1. Thereby, NMOS transistors (separation transistors) 8a and 8b are turned off, so that bit line BL and inverted bit line / BL are separated from sense amplifier 53. Thereafter, the sense amplifier 53 is activated by raising Φ1 and Φ2 of the sense amplifier 52. As a result, the potential difference between the bit line BL on the sense amplifier 53 side and the inverted bit line / BL on the sense amplifier 53 side is amplified and divided into Vcc and GND, respectively. In this way, a data read operation is performed.
[0093]
Note that Φ5 is raised at the fall timing of the signal line Φ3, and the precharge circuit 67 is turned on to precharge the bit line BL and the inverted bit line / BL to Vcc.
[0094]
In the first embodiment, as described above, the two TMR elements 4a and 4b and the two NMOS transistors 5a and 5b constitute one memory cell 52 and are connected to the two TMR elements 4a and 4b. By detecting the potential difference between the bit line BL and the inverted bit line / BL using the sense amplifier 53, data can be easily read. As described above, since the potential difference is detected, it is not necessary to detect a minute current value flowing through the bit line as in the case where one memory cell is constituted by one conventional TMR element and one NMOS transistor. As a result, it is possible to prevent the inconvenience that the configuration of the sense amplifier becomes complicated in order to detect a minute current value.
[0095]
Further, in the first embodiment, as described above, the potential difference between the bit line BL and the inverted bit line / BL is detected by the sense amplifier 53, so that it is the same as the sense amplifier used in the conventional DRAM. The simple sense amplifier 53 can be used to read data stored in the MRAM. In this way, data can be read out using a simple sense amplifier 53, so that high-speed reading is possible as compared with a conventional configuration using a sense amplifier having a complicated configuration.
[0096]
In the MRAM according to the first embodiment, the configuration of the sense amplifier 53 and the overall circuit configuration and operation method are similar to those of the conventional DRAM, so that the DRAM technology can be used as it is. As a result, replacement from DRAM becomes easy.
[0097]
(Second Embodiment)
FIG. 5 is a block diagram showing the overall configuration of the MRAM according to the second embodiment of the present invention. FIG. 6 is a circuit diagram showing a memory cell portion and a sense amplifier portion of the MRAM according to the second embodiment shown in FIG. FIG. 7 is a circuit diagram showing an internal configuration of the comparator unit of the MRAM according to the second embodiment shown in FIGS. 5 and 6.
[0098]
Referring to FIGS. 5 and 6, the MRAM according to the second embodiment is different from the MRAM according to the first embodiment shown in FIGS. 1 and 2 in that a dummy bit line (dummy BL) is provided and The comparator 201 for detecting the potential of the dummy bit line is provided. The comparator 201 is an example of the “detection circuit” in the present invention. Details will be described below.
[0099]
In the second embodiment, as shown in FIGS. 5 and 6, a dummy bit line (dummy BL) having the same configuration as the bit line BL is provided. That is, the TMR element 4a is connected to the dummy bit line via the transistor 5a. All the TMR elements 4a connected to the dummy bit line are set so that the magnetization directions of the ferromagnetic layers 1a and 3a are the same (parallel). The dummy bit line is connected to one input terminal of the comparator 201. Vcc (reference voltage) is connected to the other input terminal of the comparator 201. An inverter 202 is connected to the output of the comparator 201, and an inverter 203 is connected to the output of the inverter 202. The output of the inverter 202 is used as the signal Φ1, and the output of the inverter 203 is used as the signal Φ2. The signals Φ1 and Φ2 are used as activation signals for the sense amplifier 53.
[0100]
As shown in FIG. 7, the comparator 201 has a pair of PMOS transistors 213 and 214, an NMOS transistor 211 to which an input voltage (dummy bit line voltage) Vin is applied to its gate, and Vcc to its gate. And an NMOS transistor 212. The NMOS transistor 211 is an example of the “first transistor” in the present invention, and the NMOS transistor 212 is an example of the “second transistor” in the present invention. A constant current source 215 is connected to one terminals of the NMOS transistors 211 and 212. Further, Vcc is connected to one terminals of the PMOS transistors 213 and 214. An output voltage Vout is output from a connection point between the other terminal of the PMOS transistor 213 and the other terminal of the NMOS transistor 211.
[0101]
Here, the comparator 201 of the second embodiment shown in FIG. 7 is configured such that the amount of current flowing through the NMOS transistor 211 to which Vin is applied is larger than the amount of current flowing through the NMOS transistor 212 to which Vcc is applied. is doing. Specifically, by making the gate width of the NMOS transistor 211 slightly larger than the gate width of the NMOS transistor 212, the amount of current flowing through the NMOS transistor 211 is made larger than the amount of current flowing through the NMOS transistor 212. Note that the amount of current flowing through the NMOS transistor 211 can be made larger than the amount of current flowing through the NMOS transistor 212 by making the gate length of the NMOS transistor 211 slightly smaller than the gate length of the NMOS transistor 212 without changing the gate width. Is possible.
[0102]
Thus, by configuring the current amount of the NMOS transistor 211 to which Vin is applied to be larger than the current amount of the NMOS transistor 212 to which Vcc is applied, even when Vin is the same Vcc as the reference voltage Vcc. , An L level signal can be output as the output voltage Vout. This can prevent the output of the comparator 201 from becoming unstable when the input voltage Vin of the comparator 201 is Vcc. That is, in the comparator 201 of the second embodiment, when Vin is the same Vcc as the reference voltage Vcc, an L level signal is output, and when Vin becomes lower than the reference voltage Vcc, an H level signal is output. Is output.
[0103]
In the second embodiment, as shown in FIGS. 5 and 6, the signal Φ 7 and the output of the column decoder 60 are input to the AND circuit 205. The output of the AND circuit 205 is connected to the gate of the transistor 204 for connecting the bit line BL and the inverted bit line / BL. With this configuration, only the selected bit line BL and the corresponding inverted bit line / BL can be easily short-circuited.
[0104]
Next, a read operation and a write operation of the MRAM according to the second embodiment configured as described above will be described.
[0105]
(Read operation)
FIG. 8 is an operation waveform conceptual diagram for explaining a read operation of the MRAM according to the second embodiment of the present invention. 9 and 10 are operation waveform simulation diagrams for explaining the read operation of the MRAM according to the second embodiment. In the second embodiment, a read operation when the resistance of the TMR element 4a connected to the bit line BL is lower than the resistance of the TMR element 4b connected to the inverted bit line / BL will be described. That is, as in the memory cell 52 connected to the word line WL2 shown in FIG. 6, the reading is performed when the magnetization of the TMR element 4a is in the same direction (parallel) and the magnetization of the TMR element 4b is in the reverse direction (antiparallel). The operation will be described. Hereinafter, a read operation when the word line WL2 is selected will be described.
[0106]
First, referring to FIG. 6, in an initial state before word line WL2 rises, word line WL2 is in the L level. In this case, since the PMOS transistor 7 of the inverter circuit connected to the word line WL2 is turned on, the potential of the auxiliary word line SWL2 becomes Vcc. As a result, the potential at the node a also becomes Vcc. Since TMR elements 4a and 4b are conductors, the potentials of TMR elements 4a and 4b are also Vcc. In this state, Φ5 is raised to H level, and the precharge circuit 67 precharges the bit line BL, the inverted bit line / BL, and the dummy bit line to Vcc.
[0107]
When word line WL2 rises to H level, NMOS transistors 5a and 5b connected to word line WL2 are turned on. As a result, bit line BL and inverted bit line / BL are electrically connected to TMR elements 4a and 4b. In this state, the potentials of bit line BL, inverted bit line / BL, dummy bit line (dummy BL), node a, node b, and node c are Vcc.
[0108]
Further, before the word line WL2 rises to the H level, Φ5 becomes the L level, the precharge circuit 67 is turned off, and the NMOS transistor 6 of the inverter circuit connected to the word line WL2 is turned on. The potential of the line SWL2 is gradually lowered toward the GND potential. As a result, the potential of the node a is gradually lowered to the GND potential. For this reason, the potentials of the bit line BL and the inverted bit line / BL are also gradually lowered to the GND potential.
[0109]
FIG. 8 shows waveforms when the word line WL is raised and the auxiliary word line SWL is gradually lowered. As shown in FIG. 8, when the word line WL rises and the auxiliary word line SWL gradually falls, the node b and the node c (see FIG. 6) fall. At this time, since the TMR element 4a having the same magnetization (parallel) and the TMR element 4b having the opposite magnetization (antiparallel) have different resistance values, a potential difference is generated between the node b and the node c. Further, the bit line BL and the inverted bit line / BL on the cell side (memory cell 52 side) start to fall when the potentials of the node b and the node c become Vcc−Vt (threshold voltage) or less. In this case, the potential of the TMR element 4a having a low magnetization resistance parallel to the magnetization direction starts to drop earlier than the high resistance TMR element 4b having a magnetization direction antiparallel.
[0110]
Here, the on-resistances of the transistors 5a and 5b connected to the cell-side bit line BL and the inverted bit line / BL depend on the potential differences VgsB and VgsC (see FIG. 6) between the gates and the sources of the transistors 5a and 5b. In this case, since the potentials of the node b and the node c are different, VgsB of the transistor 5a and VgsC of the transistor 5b are different. For this reason, the transistor 5a connected to the TMR element 4a having the lower resistance (parallel) has a larger Vgs and a lower resistance. Therefore, the potential difference between the cell-side bit line BL and the inverted bit line / BL is larger than the potential difference between the node b and the node c. Similarly, the potential difference (Vsig) between the bit line BL on the sense amplifier side and the inverted bit line / BL further increases due to the influence of Vgs of the separating NMOS transistors 8a and 8b.
[0111]
However, the wiring capacity of the bit line BL and the inverted bit line / BL on the sense amplifier side is lighter than the wiring capacity of the bit line BL and the inverted bit line / BL on the cell side. The line BL and the inverted bit line / BL are at the same potential as the bit line BL and the inverted bit line / BL on the cell side. For this reason, there is a large potential difference between the two ends of the sense amplifier 53 when the sense amplifier side bit line and the inverted bit line start to drop from Vcc until the same potential as the cell side bit line and the inverted bit line. It is time to take.
[0112]
In the first embodiment described above, detection by the sense amplifier 53 is started at an arbitrary timing until the bit line BL and the inverted bit line / BL on the cell side become 0V. In this case, there is a possibility of missing a timing that is efficient for detection.
[0113]
Therefore, in the second embodiment, the dummy bit line (dummy BL) and the comparator 201 for detecting the potential of the dummy bit line are provided to detect the falling timing of the bit line BL on the sense amplifier side. . At that timing, the sense amplifier 53 is operated by separating the bit line and the inverted bit line on the cell side from the bit line and the inverted bit line on the sense amplifier side.
[0114]
Specifically, in the initial state, as described above, the potentials of the bit line BL and the inverted bit line / BL, the dummy bit line (dummy BL), and the auxiliary word line SWL2 are Vcc. Thereafter, the word line WL2 rises and the auxiliary word line SWL begins to gradually fall. As a result, a potential difference is generated between the bit line BL on the cell side and the inverted bit line / BL. Thereafter, when the potentials of the bit line BL and the inverted bit line / BL on the cell side become equal to or lower than Vcc−Vt, the potentials of the bit line BL and the inverted bit line / BL on the sense amplifier side are as shown in FIG. It starts to drop from Vcc. At this timing, the potential of the dummy bit line (comparator side) also starts to drop. In this case, since the TMR element 4a connected to the dummy bit line is set in a low resistance state in which the magnetization direction is parallel, the dummy bit line is the resistance of the bit line BL or the inverted bit line / BL. The potential starts to drop at the same timing as the lower one (bit line BL in the second embodiment).
[0115]
In the initial state, the input Vin of the comparator 201 to which the dummy bit line is connected is Vcc, which is the same as the reference voltage Vcc. In the second embodiment, as described above, when the input Vin of the comparator 201 is the same Vcc as the reference voltage Vcc, an L level signal is output as the output Vout. When the potential of the dummy bit line (comparator side) starts to drop from Vcc and the dummy bit line (comparator side) becomes a voltage lower than Vcc, the reference level of the comparator 201 is Vcc, so the comparator 201 outputs the H level. . In response to the signal, the signal Φ2 becomes H level and the signal Φ1 becomes L level. Thereby, the sense amplifier 53 is activated. At this timing, the signal Φ3 falls. As a result, isolation NMOS transistors 8a and 8b are turned off, so that the bit line and the inverted bit line on the cell side are separated from the bit line and the inverted bit line on the sense amplifier side.
[0116]
Thereafter, the potentials of the bit line and the inverted bit line on the sense amplifier side are amplified and read in the same manner as in the sensing of the DRAM. The cell-side bit line BL and the inverted bit line / BL return to the initial state by raising the signal Φ5 to the H level.
[0117]
Actual simulation waveforms are shown in FIG. 9 and FIG. FIG. 9 shows a waveform obtained by observing only the behavior of the bit line BL without starting sensing by the sense amplifier 53. FIG. 10 shows a waveform when the sense amplifier 53 is operated by operating the comparator 201.
[0118]
(Write operation)
Since the write operation of the second embodiment is basically the same as the write operation of the first embodiment described above, details thereof are omitted. However, in the second embodiment, as described above, the signal Φ7 and the column decoder output are input to the AND circuit 205, and the output of the AND circuit 205 is connected to the bit line BL and the inverted bit line / BL. Is connected to the gate of the transistor 204. This makes it possible to easily short-circuit only the selected bit line BL and the corresponding inverted bit line / BL during the write operation.
[0119]
In the second embodiment, as described above, the falling timing of the bit line BL on the sense amplifier side can be detected using the dummy bit line and the comparator 201. Then, at the falling timing of the dummy bit line detected by the comparator 201, the separation NMOS transistors 8a and 8b are turned off and the sense amplifier 53 is activated, whereby the bit line and the inverted bit line on the sense amplifier side are activated. And the sense amplifier 53 can easily detect the potential difference (Vsig).
[0120]
(Third embodiment)
FIG. 11 is a block diagram showing the overall configuration of the MRAM according to the third embodiment of the present invention. FIG. 12 is a circuit diagram showing a memory cell portion and a sense amplifier portion of the MRAM according to the third embodiment shown in FIG. Referring to FIGS. 11 and 12, the third embodiment is different from the first embodiment shown in FIGS. 1 and 2 only in the memory cell portion. That is, in the MRAM according to the third embodiment, one memory cell 82 includes one double junction TMR element 24 and two NMOS transistors 5a and 5b. The circuit configuration other than the memory cell portion of the third embodiment is the same as that of the first embodiment.
[0121]
As shown in FIG. 12, the double junction TMR element 24 of the third embodiment includes a ferromagnetic layer 23a, an insulating barrier layer 22a, a ferromagnetic layer 23b, an insulating barrier layer 22b, a ferromagnetic layer 23a, and And a ferromagnetic layer 21 that is more difficult to reverse than 23b. That is, the ferromagnetic layers 23a and 23b are formed on both surfaces of the ferromagnetic layer 21 that is difficult to reverse at the center via the insulating barrier layers 22a and 22b, respectively.
[0122]
Here, in the double junction TMR element 24 of the third embodiment, the ferromagnetic layer 1a of the TMR element 4a of the first embodiment shown in FIG. 2 and the ferromagnetic layer 1b of the TMR element 4b are shown in FIG. Shared by one ferromagnetic layer 21 shown in FIG. Accordingly, in the third embodiment, the single TJ element 24 can have the same function as the two TMR elements 4a and 4b of the first embodiment.
[0123]
The double junction TMR element 24 is an example of the “memory element exhibiting a ferromagnetic tunnel effect” in the present invention. The ferromagnetic layer 23a is an example of the “first magnetic layer” of the present invention, the ferromagnetic layer 21 is an example of the “second magnetic layer” of the present invention, and the ferromagnetic layer 23b is the present invention. This is an example of the “third magnetic layer”. The insulating barrier layer 22a is an example of the “first insulating barrier layer” in the present invention, and the insulating barrier layer 22b is an example of the “second insulating barrier layer” in the present invention.
[0124]
In the third embodiment, as described above, the two TMR elements 4a and 4b of the first embodiment are simply replaced with one double junction TMR element 24, and the other circuit configuration is the first. This is the same as the embodiment. Therefore, the write and read operations of the MRAM according to the third embodiment are the same as those in the first embodiment. Therefore, the details are omitted here.
[0125]
As described above, in the third embodiment, one double junction TMR element 24 including the ferromagnetic layers 21, 23a, and 23b, the insulating barrier layers 22a and 22b, and the two NMOS transistors 5a and 5b are 1 By configuring one memory cell 82, the area of the memory cell can be reduced as compared with the first embodiment in which one memory cell 52 is configured by two TMR elements 4a and 4b and two NMOS transistors 5a and 5b. can do.
[0126]
In the third embodiment, the same read operation as in the first embodiment described above is performed, so that the same effect as in the first embodiment can be obtained. That is, data is easily read by detecting the potential difference between the bit line BL connected to one double junction TMR element 24 and the inverted bit line / BL using the sense amplifier 53 (see FIG. 12). be able to. As described above, since the potential difference is detected, it is not necessary to detect a minute current value flowing through the bit line as in the conventional case in which one memory cell is constituted by one TMR element and one NMOS transistor. As a result, it is possible to prevent the inconvenience that the configuration of the sense amplifier becomes complicated in order to detect a minute current value.
[0127]
Further, in the third embodiment, similarly to the first embodiment described above, by configuring the potential difference between the bit line BL and the inverted bit line / BL to be detected by the sense amplifier 53 (see FIG. 12), Data stored in the MRAM can be read using a simple sense amplifier 53 similar to the sense amplifier used in the conventional DRAM. As described above, since data can be read out using the simple sense amplifier 53, high-speed reading can be performed as compared with the conventional configuration using the sense amplifier having a complicated configuration.
[0128]
Also, in the MRAM of the third embodiment, the configuration of the sense amplifier 53 and the overall circuit configuration and operation method are similar to those of the conventional DRAM, as in the first embodiment, and the DRAM technology is used as it is. be able to. As a result, replacement from DRAM becomes easy. Further, by inputting a pulse signal to the selected word line, the potential difference generated between the bit line and the inverted bit line is read out using the sense amplifier 53 (see FIG. 12), so that the conventional minute Unlike the case where the current value is read, data can be easily detected even when the resistance of the double junction TMR element 24 is high.
[0129]
13 is a plan layout view for realizing the circuit configuration of the MRAM according to the third embodiment shown in FIGS. 11 and 12. FIG. 14 is a cross-sectional view taken along line 100-100 shown in FIG. It is. The structure of the memory cell 82 of the MRAM according to the third embodiment will be described below with reference to FIGS. 13 and 14.
[0130]
First, in order to simplify the drawing, the plane layout diagram shown in FIG. 13 includes a bit line BL and an inverted bit line / BL, and ferromagnetic layers 21, 23a and 23b constituting the double junction TMR element 24. Only the bit line contact portion 94 is shown.
[0131]
As a cross-sectional structure of the memory cell 82 of the MRAM according to the third embodiment, an isolation region 92 is formed in a predetermined region on the surface of the substrate 91 as shown in FIG. N-type source / drain regions 93 are formed in the element formation region surrounded by the isolation region 92 at a predetermined interval. On the channel region located between adjacent N-type source / drain regions 93, gate electrodes constituting word lines WL1 and WL2 are formed.
[0132]
Sidewall-shaped ferromagnetic layers 23 a of the double junction TMR element 24 that are easily inverted are connected to N-type source / drain regions 93 located at both ends via a conductive layer 96. In this case, the conductive layer 96 and the ferromagnetic layer 23 a are connected via the contact hole 99. In order to prevent the conductive layer 96 and the ferromagnetic layer 23a from reacting, a barrier film (not shown) may be formed between the conductive layer 96 and the ferromagnetic layer 23a. On the side surface of the ferromagnetic layer 23a, a ferromagnetic layer 21 that is difficult to reverse is formed via an insulating barrier layer 22a. On the other side surface of the ferromagnetic layer 21, a sidewall-shaped ferromagnetic layer 23b that is easily inverted is formed via an insulating barrier layer 22b.
[0133]
Here, the ferromagnetic layers 23 a and 23 b of the double junction TMR element 24 are formed in a staggered manner with respect to the central ferromagnetic layer 21 as shown in FIG. 13.
[0134]
A bit line BL is connected to a bit line contact portion 94 located on the surface of the central N-type source / drain region 93 through a conductive layer 98. Interlayer insulating films 95 and 97 are formed so as to cover the entire surface.
[0135]
15 to 17 are a cross-sectional view and a perspective view for explaining a manufacturing process of the double junction TMR element portion shown in FIGS. 13 and 14. Next, a manufacturing process for the double junction TMR element 24 will be described with reference to FIGS.
[0136]
First, as shown in FIG. 15, the ferromagnetic layer 21 patterned in a predetermined shape is formed on the interlayer insulating film 95.
[0137]
After forming the alumina 22 as an insulating barrier material so as to cover the ferromagnetic layer 21 and the interlayer insulating film 95, a contact hole 99 is formed in a region located on the conductive layer 96 of the alumina 22. Thereafter, a ferromagnetic material layer 23 is formed on the entire surface. Then, the entire surface is anisotropically etched to form sidewall-shaped ferromagnetic layers 23a and 23b as shown in FIG. In this case, since the ferromagnetic layer 23a is also formed in the contact hole 99, the ferromagnetic layer 23a and the conductive layer 96 are electrically connected.
[0138]
In the third embodiment, as described above, the double junction TMR element 24 including the ferromagnetic layers 21, 23a, and 23b can be easily formed by using a process similar to the conventional sidewall formation process. .
[0139]
In addition, as a material of the ferromagnetic layers 21, 23a, and 23b of the third embodiment, for example, the ferromagnetic layers 23a and 23b that are easily inverted include Co₇₅-Fe_{twenty five}A multilayer film composed of a layer, a Py layer, and a Ta layer is used.₇₅-Fe_{twenty five}A multilayer film including a layer, an Ir—Mn layer, a Py layer, a Cu layer, a Py layer, and a Ta layer is used. The material of this ferromagnetic layer is disclosed on page 5 of the 116th meeting of the Japan Society of Applied Magnetics, “Current Status and Future Prospects of MRAM and Competing Technologies” (November 17, 2000).
[0140]
Thereafter, as shown in FIG. 17, the ferromagnetic layers 23a and 23b are patterned in a zigzag pattern. Thereby, the double junction TMR element 24 as shown in FIGS. 13 and 14 can be easily formed.
[0141]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.
[0142]
For example, in the above embodiment, the TMR element is used as the memory element constituting the memory cell. However, the present invention is not limited to this, and any memory element other than the TMR element may be used as long as the memory element exhibits a ferromagnetic tunnel effect. It is possible to use. Further, the same effect as that of the above embodiment can be obtained by using a memory element showing a magnetoresistive effect other than the memory element showing the ferromagnetic tunnel effect.
[0143]
In the second embodiment, the example in which the dummy bit line (dummy BL) and the comparator 201 are added to the configuration including the memory cell 52 of the first embodiment is shown. However, the present invention is not limited to this, The same effect can be obtained by adding a dummy bit line (dummy BL) and a comparator 201 to the configuration including the memory cell 82 of the third embodiment.
[0144]
【The invention's effect】
As described above, according to the present invention, the two first and second memory elements exhibiting the ferromagnetic tunnel effect and the two first and second transistors constitute a memory cell and two first and second transistors. In addition, when a potential difference between the bit line connected to the second memory element and the inverted bit line is detected by an amplifier, a memory cell is formed from one memory element and one transistor exhibiting a conventional ferromagnetic tunnel effect. Thus, since it is not necessary to use a sense amplifier having a complicated configuration, high-speed reading is possible. Further, since the configuration and circuit configuration of the sense amplifier and the operation method are similar to those of the conventional DRAM, the DRAM technology can be used as it is. As a result, replacement from DRAM becomes easy.
[0145]
In addition to the above effect, a memory cell is composed of one memory element that exhibits the ferromagnetic tunnel effect including the first, second, and third magnetic layers, and two first and second transistors. In addition, it is possible to obtain an effect that the area of the memory cell can be reduced as compared with the case where the memory cell is configured by two memory elements and two transistors.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of an MRAM according to a first embodiment of the present invention.
2 is a circuit diagram showing a configuration of a memory cell portion and a sense amplifier portion of the MRAM according to the first embodiment shown in FIG. 1;
FIG. 3 is an operation waveform diagram for explaining a read operation of the MRAM according to the first embodiment shown in FIGS. 1 and 2;
4 is a cross-sectional view showing a cross-sectional structure of a memory cell portion of the MRAM according to the first embodiment shown in FIGS. 1 and 2. FIG.
FIG. 5 is a block diagram showing an overall configuration of an MRAM according to a second embodiment of the present invention.
6 is a circuit diagram showing configurations of a memory cell unit and a sense amplifier unit of the MRAM according to the second embodiment shown in FIG. 5; FIG.
7 is a circuit diagram showing an internal configuration of the comparator shown in FIGS. 5 and 6. FIG.
FIG. 8 is an operation waveform conceptual diagram for explaining a read operation according to a second embodiment.
FIG. 9 is an operation waveform simulation diagram for explaining a read operation of the MRAM according to the second embodiment;
FIG. 10 is an operation waveform simulation diagram for explaining a read operation of the MRAM according to the second embodiment;
FIG. 11 is a block diagram showing an overall configuration of an MRAM according to a third embodiment of the present invention.
12 is a circuit diagram showing configurations of a memory cell portion and a sense amplifier portion of the MRAM according to the third embodiment shown in FIG. 11; FIG.
13 is a plan layout view of the memory cell portion of the MRAM according to the third embodiment shown in FIGS. 11 and 12. FIG.
14 is a cross-sectional view of the MRAM according to the third embodiment shown in FIG. 13 taken along the line 100-100.
15 is a cross-sectional view for explaining a manufacturing process of the double junction TMR element of the memory cell portion shown in FIG. 14;
16 is a cross-sectional view for explaining a manufacturing process of the double junction TMR element of the memory cell portion shown in FIG. 14;
17 is a perspective view for explaining a manufacturing process for the double-junction TMR element according to the third embodiment shown in FIG. 14; FIG.
FIG. 18 is a schematic diagram for explaining a configuration of a memory element of a conventional MRAM.
FIG. 19 is a schematic diagram for explaining a configuration of a memory element of a conventional MRAM.
FIG. 20 is a block diagram showing an overall configuration of a conventional MRAM.
[Explanation of symbols]
1a, 1b Ferromagnetic layer (second magnetic layer)
3a, 3b Ferromagnetic layer (first magnetic layer)
2a, 2b Insulating barrier layer
4a TMR element (first memory element)
4b TMR element (second memory element)
5a NMOS transistor (first transistor)
5b NMOS transistor (second transistor)
6 NMOS transistor
7 PMOS transistor
8a, 8b NMOS transistor (separation transistor)
9 PMOS transistor
10a, 10b NMOS transistor
21 Ferromagnetic layer (second magnetic layer)
22a Insulating barrier layer (first insulating barrier layer)
23a Ferromagnetic layer (first magnetic layer)
22b Insulating barrier layer (second insulating barrier layer)
23b Ferromagnetic layer (third magnetic layer)
24 Double junction TMR element (memory element)
51 Memory cell array
52, 82 memory cells
53 Sense amplifier
54 Row decoder
60 column decoder
67 Precharge circuit
201 Comparator (detection circuit)
211 NMOS transistor (first transistor)
212 NMOS transistor (second transistor)

Claims (12)

A first memory element exhibiting a ferromagnetic tunnel effect including a first magnetic layer and a second magnetic layer disposed opposite to the first magnetic layer via an insulating barrier layer and less likely to reverse than the first magnetic layer; A memory cell comprising a second memory element and first and second transistors respectively connected to the first and second memory elements;
A word line connected to the control terminals of the first and second transistors;
A bit line connected to the first memory element via the first transistor;
An inverted bit line connected to the second memory element via the second transistor and constituting a bit line pair with the bit line;
An amplifier connected to the bit line and the inverted bit line ;
The second magnetic layer of the first memory element and the second magnetic layer of the second memory element are connected to each other, and the second magnetic layer of the first memory element is activated in accordance with the rise timing of the signal to the word line. An auxiliary word line for lowering the potential of the layer and the second magnetic layer of the second storage element to the ground potential ,
After setting the bit line, the inverted bit line, and the auxiliary word line to a predetermined potential, the potential of the auxiliary word line is lowered according to the rising timing of a signal to the word line, thereby The potential of the second magnetic layer of the memory element and the second magnetic layer of the second memory element is lowered to the ground potential, and at this time, the difference is caused by the difference in resistance between the first memory element and the second memory element. A magnetic memory device that reads out a potential difference transiently generated between the bit line and the inverted bit line using the amplifier . Falling timing of the signal to the word line is carried out before the potential of the second magnetic layer of the first memory element, the potential of the second magnetic layer of the second memory element becomes the ground potential, according to claim 1 the magnetic memory device according to. 3. The magnetic memory device according to claim 1, further comprising an isolation transistor for isolating the amplifier from the bit line and the inverted bit line in accordance with a fall timing of a signal to the word line. . Wherein the first storage element and said second storage element, stored data opposite to each other, a magnetic memory device according to any one of claims 1-3. A dummy bit line connected to the first memory element via the first transistor;
The magnetic memory device according to claim 1, further comprising a detection circuit that detects a falling timing of the dummy bit line. In accordance with the falling timing of the dummy bit line detected by the detection circuit, the amplifier further comprises a separation transistor for separating the bit line and the inverted bit line,
6. The magnetic memory device according to claim 5 , wherein the amplifier is activated according to a falling timing of the dummy bit line detected by the detection circuit. The sensing circuit includes a first transistor having an input voltage applied to the gate and a second transistor having a reference voltage applied to the gate;
By larger than the current flowing in the current flowing through the first transistor to the second transistor, when the input voltage is equal to the reference voltage to output a L-level, the magnetic according to claim 5 or 6 Memory device. A first magnetic layer; a second magnetic layer having one surface opposed to the surface of the first magnetic layer via a first insulating barrier layer; and a second insulating layer on the other surface of the second magnetic layer. look including a third magnetic layer disposed opposite via a barrier layer, a second magnetic layer, the first magnetic layer and the third than the magnetic layer shows a single ferromagnetic tunneling hardly inverted storage element A memory cell comprising first and second transistors connected to the first magnetic layer and the third magnetic layer of the storage element, respectively.
A word line connected to the control terminals of the first and second transistors;
A bit line connected to the first magnetic layer via the first transistor;
An inverted bit line connected to the third magnetic layer via the second transistor and constituting a bit line pair with the bit line;
An amplifier connected to the bit line and the inverted bit line ;
An auxiliary word line for lowering the potential of the second magnetic layer of the storage element to the ground potential in accordance with the rise timing of the signal to the word line ;
After setting the bit line, the inverted bit line and the auxiliary word line to a predetermined potential, the potential of the auxiliary word line is lowered to the ground potential in accordance with the rising timing of the signal to the word line, The potential of the second magnetic layer of the storage element is lowered to the ground potential, and at that time, due to the difference in resistance value between the first magnetic layer and the third magnetic layer of the storage element, the bit line and the A magnetic memory device which reads out a potential difference generated transiently with an inverted bit line using the amplifier . The first magnetic layer includes a sidewall-shaped first magnetic layer formed on one side surface of the second magnetic layer via the first insulating barrier layer,
9. The magnetic memory device according to claim 8 , wherein the third magnetic layer includes a sidewall-shaped third magnetic layer formed on the other side surface of the second magnetic layer via the second insulating barrier layer. 10. The magnetic memory device according to claim 8 , wherein the signal fall timing to the word line is performed before the potential of the second magnetic layer of the storage element becomes the ground potential. Depending on the fall timing of the signal to the word line, and said amplifier further comprises a separation transistor for separating the bit lines and the inverted bit line, to any one of claims 8-10 The magnetic memory device described. Wherein the first magnetic layer and the third magnetic layer, is stored reverse data with each other, a magnetic memory device according to any one of claims 8-11.

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