JP3767127B2 - Liquid crystal display panel driving device, liquid crystal display device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention belongs to the technical field of liquid crystal display panel driving devices, liquid crystal display devices, and electronic equipment, and in particular, active using two-terminal nonlinear elements having bidirectional diode characteristics such as MIM (Metal Insulator Metal) driving elements. The present invention belongs to a technical field of a matrix driving type liquid crystal display panel driving device, a liquid crystal display device (liquid crystal display module) including the driving device, and an electronic device including the liquid crystal display device.
[0002]
[Prior art]
Conventionally, as an active matrix liquid crystal display panel, there is a liquid crystal display panel using a two-terminal type non-linear element having bidirectional diode characteristics such as an MIM driving element in addition to a TFT (thin film transistor) driving element. MIM driving elements and the like have steep thresholds, and are therefore advantageous in that there are fewer problems of crosstalk between pixels compared to the conventional simple matrix driving system. Compared to TFT driving elements, the element configuration and manufacturing process are advantageous. Is advantageous in that it is relatively simple.
[0003]
For gradation display in a liquid crystal display panel using this type of MIM drive element or the like, a binary driver circuit is used as a data side driver circuit, and for example, a period in which each drive element is selected, such as PWM (pulse width modulation). In general, it is performed by controlling a time ratio of taking a binary value (ON or OFF) of a data signal in one selection period (hereinafter referred to as 1H period) according to the gradation level. This gradation display will be described with reference to FIG.
[0004]
As shown in FIG. 26, the RES signal indicating the start timing of the 1H period is input to the data side driver circuit every 1H period. Here, the temporal ratio of the binary value during the 1H period described above and the transmittance of the liquid crystal display panel generally do not have a linear relationship. For example, in the case of 64 gradations, each gradation level 0 (for example, black), 1, 2,..., 63 (for example, white) obtained when the width for turning on during the 1H period is changed and the on width are as follows: The relationship shown in the graph of FIG. 27 is obtained depending on the characteristics of the liquid crystal and the characteristics of the liquid crystal display panel.
[0005]
For this reason, in the gradation display on the liquid crystal display panel using the MIM driving element, it is necessary to change the ON width of the data signal in accordance with the gradation level indicated by the input data based on such a relationship. More specifically, as apparent from FIG. 27, as the gradation level increases, that is, as the gradation level approaches from the gradation level 0 side to the gradation level 63 side, the on-width change rate decreases. Therefore, it is necessary to control a slight difference in the ON width.
[0006]
For this reason, conventionally, as shown in the second row from the top in FIG. 26, for example, “the number of gradations−2”, in which the interval differs according to the difference in the ON width of the data signal in accordance with the difference in gradation level. A GCP (gray scale control) signal including a train of pulses (for example, 62 in the case of 64 gradations) is generated. More specifically, under the relationship as shown in FIG. 27, the GCP signal gradually decreases in intervals as the gradation level increases, as shown in FIG. 28 for each pulse (each gradation level). It consists of a series of 62 pulses that narrow.
[0007]
Based on this GCP signal, the gradation level is controlled as follows. That is, in FIG. 26, when a GCP signal is generated corresponding to each 1H period, for example, 6-bit display data indicating the gradation level to be displayed in this 1H period indicates gradation level 2. In the corresponding 1H period, the data signal is turned on (for example, at a high voltage level) only during the period from the second pulse in the GCP signal to the end of the 1H period. Next, assuming that the display data indicates, for example, the gradation level 5, the data signal is turned on (for example, a low voltage) for a period from the fifth pulse in the GCP signal to the end of the 1H period in the corresponding 1H period. Level). If the next display data indicates, for example, gradation level 0, the data signal is turned off (for example, at a high voltage level) until the end of the corresponding 1H period. Note that the voltage level corresponding to ON is inverted every 1H period because the liquid crystal is driven by alternating current, and the on / off voltage of the scanning signal is also changed every 1H period (each row) as shown in FIG. Inverted.
[0008]
As a result, as shown at the bottom of FIG. 26, one pixel electrode (that is, one data line to which the display data shown in the figure is supplied) is connected between the scanning line (Nth row). The applied signal (= scanning signal−data signal) applied to the pixel electrode) exceeds the threshold value of the MIM driving element for a period corresponding to the ON width of the corresponding data signal, and the MIM driving element is turned on (low). Resistance state). As a result, an effective voltage corresponding to the ON width of the data signal is applied to the liquid crystal layer portion sandwiched between the pixel electrode and the data line or the scanning line. Thus, the ON width of the data signal substantially coincides with the data writing period to the pixel, and the ON width of the data signal determines the gradation level.
[0009]
As described above, according to the conventional gray scale display technology using the GCP signal, by using the N number of on-width data signals based on the GCP signal composed of a sequence of N−2 pulses, N kinds of gradation levels can be displayed.
[0010]
[Problems to be solved by the invention]
In an active matrix liquid crystal display panel, there is a general request to display a higher quality image by increasing the number of gradations, that is, by increasing the number of gradations.
[0011]
However, the conventional techniques described above have the following problems. That is, first, when the number of gradations is increased, the interval between the pulse trains constituting the GCP signal on the higher gradation level side is narrowed, so that the circuit for generating the GCP signal and the data side driver need to operate at high speed. It will occur. For this purpose, the period of the operation clock needs to be at least equal to or less than the minimum pulse interval in the GCP signal, which requires a high-performance clock and increases power consumption. Furthermore, when such high-speed operation is performed, slight changes in the delay time of the GCP signal and the pulse in the data signal due to external influences such as temperature changes and the operating environment cause the gradation level to be distorted. End up. In particular, in a liquid crystal display device (liquid crystal display module) having a liquid crystal display panel using an MIM driving element or the like that has an advantage of a simple configuration and a manufacturing method, the complexity of the driving device and the manufacturing cost associated therewith are increased. The rise of is a serious problem that asks the significance of its existence.
[0012]
The present invention has been made in view of the above-described problems, and uses a two-terminal nonlinear element having bidirectional diode characteristics, such as an MIM driving element, which enables high gradation using a relatively simple configuration. It is an object to provide a drive device for an active matrix liquid crystal display panel, a liquid crystal display device including the drive device, and an electronic device including the liquid crystal display device.
[0013]
[Means for Solving the Problems]
A driving device for a liquid crystal display panel according to the present invention is provided on a pair of substrates, a liquid crystal sandwiched between the pair of substrates, a plurality of data lines provided on one of the substrates, and the other substrate. A driving device for a liquid crystal display panel, comprising a plurality of scanning lines, and a plurality of pixels composed of switching elements connected in series between the data lines and the scanning lines and the liquid crystal, and counts a reference clock A first counter that counts, a second counter that counts a horizontal synchronization signal, a value of an operation result of an exclusive OR based on the LSB of each count value of the first counter and the second counter, and M (where M is a natural number) According to the result of the logical product with the LSB value of the plurality of bits of the original image data indicating the gradation level, the original image data excluding the LSB is left as it is and the plurality of bits An addition circuit that outputs 1 as the second image data by adding 1 to the original image data excluding the LSB and outputs the second image data of N bits corresponding to the gradation level in the horizontal scanning period. Where N is a natural number less than M), and the first image data output from the adder circuit in four pixels adjacent to each other in the row direction and the column direction are generated. The second image output from the adder circuit is supplied by supplying a data signal having the pulse width corresponding to the gradation level n indicated by, to each of the two pixels located diagonally of the four pixels and displaying the data signal. A driver circuit for supplying and displaying the data signal having the pulse width corresponding to the gradation level n + 1 indicated by the data to the remaining two pixels of the four pixels, respectively. And displaying the gradation level n + 0.5 by the data signal and the gradation level n + 1 of the data signal of the gradation level n.
In addition, the liquid crystal display panel driving device of the present invention includes a pair of substrates, a liquid crystal sandwiched between the pair of substrates, a plurality of data lines provided on one of the substrates, and the other substrate. A driving device for a liquid crystal display panel comprising a plurality of scanning lines, a switching element connected in series between the data lines and the scanning lines, and a plurality of pixels comprising the liquid crystal, Of the first counter, the second counter for counting the horizontal synchronization signal, the third counter for counting the vertical synchronization signal, the count value of each of the first counter, the second counter, and the third counter. The result of the logical product of the value of the result of the exclusive OR based on the LSB and the value of the LSB of the multi-bit original image data indicating M (where M is a natural number) gradation levels. Then, the original image data excluding the LSB is output as it is as the first image data of a plurality of bits, or the original image data excluding the LSB is added with 1 to add a plurality of bits of the second image data. An output circuit for generating a pulse having different pulse widths N (where N is a natural number less than M) corresponding to the gradation level in the horizontal scanning period, and a row direction and a column direction In four pixels adjacent to each other, in one frame or field, a data signal having the pulse width corresponding to the gradation level n indicated by the first image data output from the adder circuit is transferred to the pair of the four pixels. The data having the pulse width corresponding to the gradation level n + 1 indicated by the second image data output from the adder circuit is displayed by being supplied to two pixels located at the corners. A signal is supplied to the remaining two pixels of the four pixels for display, and in the next frame or field, a data signal having a pulse width corresponding to the gradation level n and a pulse width corresponding to the gradation level n + 1 A driver circuit that supplies the four pixels so as to alternate with the one frame or field to display the data signal, and has the gradation level n data signal and the gradation level n + 1. A gradation level n + 0.5 is displayed by a data signal.
Specifically, first, in order to solve the above problem, a pair of substrates, a liquid crystal sandwiched between the pair of substrates, a plurality of data lines provided on one substrate, and the other substrate A driving device for a liquid crystal display panel including a plurality of scanning lines provided in a plurality of pixels, the switching lines connected in series between the data lines and the scanning lines, and the liquid crystal, Image data indicating gradation levels of M (where M is a natural number) is input for each pixel and for each predetermined time unit, and a data signal consisting of N (where N is a natural number less than M) pulses having different widths. The first average value of the widths of the plurality of pulses forming the plurality of data signals over the plurality of predetermined time units for each pixel (that is, the plurality of pulse widths Wi (i within the plurality of L predetermined time units). = 1, ..., L) Average value for time Wi / L) and a second average value of widths of a plurality of pulses forming a plurality of data signals for a plurality of pixels respectively located in a predetermined region unit including each pixel (that is, a plurality of L forming a predetermined region unit) Generate at least one of the average values ΣWi / L) for the areas of a plurality of pulse widths Wi (i = 1,..., L) in the pixel corresponding to the gradation level of each pixel. The data signal driving means for supplying the data signal to the plurality of data lines in a time division manner and the scanning signal driving means for supplying the scanning signal to the plurality of scanning lines in a time division manner are provided.
[0014]
According to the driving device of the liquid crystal display panel, the data signal driving means includes, for example, 6-bit digital indicating one of gradation levels 0, 1, 2,. Image data indicating M gradation levels such as a signal is input for each pixel and for each predetermined time unit such as a field unit. Then, the data signal driving means generates a plurality of data signals over a plurality of predetermined time units for each pixel. The first average value of the widths of the plurality of pulses forming the above is generated so as to correspond to the gradation level of each pixel. Therefore, for example, with respect to a pixel for displaying gradation level 5, data signals of gradation level 4 and gradation level 6 are alternately generated for each field. In this case, as in “(4 + 6) / 2 = 5”, the first average value of the gradation levels for the generated signal data is the gradation level 5 to be displayed on the pixel. For example, for a pixel that should display gradation level 4, since the first average value corresponds to gradation level 4, a data signal of gradation level 4 is generated as it is. Alternatively, instead of or in addition to making the first average value correspond to the gradation level, the data signal driving means outputs a plurality of data signals for a plurality of pixels respectively located in a predetermined area unit including each pixel. The second average value of the widths of the plurality of pulses formed is generated so as to correspond to the gradation level of each pixel. Therefore, for example, if there are four adjacent pixels that should display gradation level 5, data signals of gradation level 4 and gradation level 6 are generated for the pixels at the diagonal positions, respectively. The In this case, as in “(4 × 2 + 6 × 2) / 4 = 5”, the second average value of the gradation levels for the generated signal data is the gradation level 5 to be displayed on the pixel. ing. For example, if there are four adjacent pixels that should display the gradation level 4, the second average value corresponds to the gradation level 4, so the data signal of the gradation level 4 is generated as it is. Is done. In this way, the data signal generated so that at least one of the first average value and the second average value corresponds to the gradation level is applied to the plurality of data lines at least for each column by the data signal driving means. Supplied in time division. On the other hand, the scanning signal driving means supplies the scanning signal to a plurality of scanning lines at least for each row in a time division manner. Accordingly, the two-terminal nonlinear element connected to the pixel electrode corresponding to the data line and the scanning line to which these signals are supplied has a voltage applied via the liquid crystal due to the voltage between the signal line and the scanning line. A predetermined threshold value is exceeded and turned on. As a result, a liquid crystal driving voltage is supplied to the corresponding pixel electrode. Here, when the first average value is made to correspond to the gradation level as described above, it corresponds to, for example, the gradation level 5 if a predetermined time unit such as a field unit is set sufficiently small for vision. A display similar to that driven by a pulse having a width corresponding to the gradation level 5 can be visually obtained without using a pulse having a width. In addition, when the second average value is made to correspond to the gradation level, if a predetermined area unit is set sufficiently small for vision, for example, a step having a width corresponding to the gradation level 5 is not used, and a step is used. A display similar to that driven by a pulse having a width corresponding to the tone level 5 is visually obtained.
[0015]
Further, in the above driving device, the data signal driving means includes a pulse width corresponding to a gradation level m (where m is an integer of 0 or more and less than M) forming at least one of the data signals, and at least one of the data. The data signal is generated so that at least one of a first average value and a second average value with a pulse width corresponding to the gradation level m + 2 forming the signal corresponds to the gradation level m + 1. And
[0016]
According to the liquid crystal display panel driving apparatus, the data signal driving means causes the pulse width corresponding to the gradation level m (for example, “4”) forming at least one data signal and the level forming at least one data signal. The data signal corresponding to the gradation level m + 1 (for example, “5”) is generated using the first average value with the pulse width corresponding to the gray level m + 2 (for example, “6”). Alternatively, instead of or in addition to the first average value corresponding to the gradation level, the data signal driving means causes the pulse width and gradation level corresponding to the gradation level m (for example, “4”). Using the second average value with the pulse width corresponding to m + 2 (for example, “6”), the data signal corresponding to the gradation level m + 1 (for example, “5”) is generated.
[0017]
The data signal driving means, for example, a pulse corresponding to the gradation level m forming three data signals (for example, “4”) and a pulse corresponding to the gradation level m + 4 forming one data signal (for example, If the first average value or the second average value with “8”) is used, two gradation levels are generated such that a data signal corresponding to the gradation level m + 1 (for example, “5”) is generated. Are averaged at various ratios to visually obtain various gradation levels between them.
[0018]
Further, in the above driving device, the data signal driving means may include a plurality of second average values for a plurality of pixels included in the predetermined area unit corresponding to the gradation level and included in the predetermined area unit. The data signal is generated so that the first average value for each of the pixels corresponds to the gradation level.
[0019]
According to the liquid crystal display panel driving apparatus, the data signal is generated as follows by the data signal driving means. That is, for example, the second average value for a plurality of pixels included in a predetermined region unit, such as two, four, six, eight, etc. adjacent pixels, becomes a gradation level in a certain predetermined time unit. Correspondingly, a data signal is generated. More specifically, for example, when the predetermined area unit is composed of two adjacent pixels, the left pixel corresponds to the gradation level “4”, and the right pixel corresponds to the gradation level “6” (the first level). The data signal is generated so that the average value of 2 is “5”. Then, next, the first average value of each of the plurality of pixels included in the predetermined area unit corresponds to the gradation level in the next time unit, that is, for example, the left pixel has gradation. The data signal is generated so as to correspond to the level “6” and the right pixel corresponds to the gradation level “4” (the second average value is “5”).
[0020]
Further, in the driving device, the data signal driving means and the scanning signal driving means invert the voltage polarities of the data signal and the scanning signal for each predetermined time unit with reference to an intermediate value of the data signal. The data signal and the scanning signal are generated, respectively, and the data signal driving means fixes a width of a pulse forming the data signal to a constant value for a time twice as long as the predetermined time unit.
[0021]
According to the driving device for the liquid crystal display panel, the data signal and the scanning signal are generated as follows by the data signal driving means and the scanning signal driving means. That is, for example, the voltage polarity of the data signal and the scanning signal is inverted with respect to the intermediate potential of the data signal every predetermined time unit such as one field unit. Therefore, it is possible to basically perform AC voltage driving on the liquid crystal. Here, in particular, since the width of the pulse forming the data signal is fixed to a constant value by a data signal driving means, for example, for two field units, a predetermined time unit is fixed to a constant value. Even if the widths of the pulses that make up the multiple data signals are not constant, the voltage due to the data signals is canceled every two times the predetermined time unit, effectively preventing the DC component from being applied to the liquid crystal Is done.
[0022]
Furthermore, a liquid crystal display device according to the present invention includes the above-described liquid crystal display panel driving device and the liquid crystal display panel.
[0023]
According to the liquid crystal display device (liquid crystal display module), the liquid crystal display panel includes a two-terminal type non-linear element in particular, but a data signal composed of pulses of N widths can be obtained by the driving device of the present invention described above. By using this, it is possible to realize more M gradation levels.
[0024]
Furthermore, in the liquid crystal display device, the two-terminal nonlinear element includes a MIM (Metal Insulator Metal) driving element.
[0025]
According to the above liquid crystal display device, the liquid crystal display panel is provided with the MIM drive element in particular, but the drive device of the present invention described above uses the data signal composed of pulses of N widths to increase the number of M. It is possible to achieve the same gradation level.
[0026]
Furthermore, an electronic apparatus according to the present invention includes the liquid crystal display device.
[0027]
According to the above electronic device, the electronic device includes the above-described liquid crystal display device of the present invention, and high gradation display is possible with a relatively simple configuration.
[0028]
Such an operation and other advantages of the present invention will become apparent from the embodiments described below.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0030]
(MIM drive element)
FIG. 1 is a plan view schematically showing an MIM driving element as an example of a two-terminal nonlinear element provided in a liquid crystal display panel constituting a liquid crystal display device according to an embodiment of the present invention, together with a pixel electrode. 2 is a cross-sectional view taken along the line AA in FIG. In FIG. 2, the scales of the layers and members are different for each layer and each member so that each layer and each member can be recognized on the drawing.
[0031]
1 and 2, the MIM driving element 20 is formed on an insulating film 31 formed on an MIM array substrate 30 constituting an example of the first substrate, and is formed on the insulating film 31 side. The first metal film 22, the insulating layer 24, and the second metal film 26 are sequentially formed to have an MIM structure (Metal Insulator Metal structure). The first metal film 22 of the two-terminal type MIM driving element 20 is connected to the scanning line 12 formed on the MIM array substrate 30 as one terminal, and the second metal film 26 is connected to the other terminal. Connected to the pixel electrode 34. Instead of the scanning lines 12, data lines (see FIG. 6) may be formed on the MIM array substrate 30 and connected to the pixel electrodes.
[0032]
The MIM array substrate 30 is made of an insulating and transparent substrate such as glass or plastic.
[0033]
The insulating film 31 that forms the base is made of, for example, tantalum oxide. However, the main purpose of the insulating film 31 is to prevent the first metal film 22 from being peeled off from the base and to prevent impurities from diffusing from the base into the first metal film 22 by heat treatment performed after the second metal film 26 is deposited. Is formed. Therefore, when the MIM array substrate 30 is made of a substrate having excellent heat resistance and purity, such as a quartz substrate, for example, if the separation or diffusion of impurities is not a problem, the insulating film 31 is omitted. can do.
[0034]
The first metal film 22 is made of a conductive metal thin film, for example, tantalum alone or a tantalum alloy. Alternatively, tantalum alone or a tantalum alloy as a main component, for example, an element belonging to Group 6, 7 or 8 in a periodic rate table such as tungsten, chromium, molybdenum, rhenium, yttrium, lanthanum, dysprolium, etc. It may be added. In this case, the element to be added is preferably tungsten, and the content ratio is preferably, for example, 0.1 to 6 atomic%.
[0035]
The insulating film 24 is made of, for example, an oxide film formed by anodic oxidation on the surface of the first metal film 22 in the chemical liquid.
[0036]
The second metal film 26 is made of a conductive metal thin film, for example, chromium alone or a chromium alloy.
[0037]
The pixel electrode 34 is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film.
[0038]
As shown in the cross-sectional view of FIG. 3, the second metal film and the pixel electrode described above may be composed of a transparent conductive film 36 made of the same ITO film or the like. The MIM driving element 20 ′ having such a configuration has an advantage that the second metal film and the pixel electrode can be formed by the same manufacturing process at the time of manufacturing. In FIG. 3, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted.
[0039]
Furthermore, as shown in the plan view of FIG. 4 and the BB cross-sectional view of FIG. 5, the MIM driving element 40 has a so-called back-to-back structure, that is, a first MIM driving element 40a. The second MIM driving element 40b may be configured to have a structure in which the polarity is reversed and connected in series. In FIG. 4 and FIG. 5, the same components as those in FIG. 1 and FIG.
[0040]
4 and 5, the first MIM driving element 40a includes a first metal film 42 made of tantalum or the like formed in order on an insulating film 31 formed on the MIM array substrate 30, and an anode. The insulating film 44 is made of an oxide film or the like, and the second metal film 46a is made of chromium or the like. On the other hand, the second MIM drive element 40b is based on the insulating film 31 formed on the MIM array substrate 30, and the first metal film 42, the insulating film 44, and the first metal film 46a are sequentially formed thereon. The second metal film 46b is spaced apart.
[0041]
The second metal film 46a of the first MIM driving element 40a is connected to the scanning line 48, and the second metal film 46b of the second MIM driving element 40b is connected to the pixel electrode 45 made of an ITO film or the like. . Accordingly, the scanning signal is supplied from the scanning line 48 to the pixel electrode 45 via the first and second MIM driving elements 40a and 40b. Instead of the scanning lines 48, data lines (see FIG. 6) may be formed on the MIM array substrate 30 and connected to the second metal film 46a of the first MIM driving element 40a.
[0042]
In the example shown in FIGS. 4 and 5, the insulating film 44 is smaller than the insulating film 24 in the example shown in FIGS. 1 and 2, and is set to, for example, about half the film thickness.
[0043]
As described above, several examples of the MIM driving element as the two-terminal type nonlinear element have been described. However, bidirectional diode characteristics such as a ZnO (zinc oxide) varistor, an MSI (Metal Semi-Insulator) driving element, and an RD (Ring Diode) are provided. The two-terminal nonlinear element having the above can be applied to the active matrix driving liquid crystal display panel of this embodiment.
[0044]
(LCD panel)
Next, an embodiment of an active matrix driving type liquid crystal display panel using the above-described MIM driving element 20 will be described with reference to FIGS. FIG. 6 is an equivalent circuit diagram showing the liquid crystal display panel according to the present embodiment together with the drive circuit, and FIG. 7 is a partially broken perspective view schematically showing the liquid crystal display panel according to the present embodiment.
[0045]
In FIG. 6, the liquid crystal display panel 10 has a plurality of scanning lines 12 arranged on the MIM array substrate 30 or its counter substrate connected to the scanning signal drive circuit 100, and is on the MIM array substrate 30 or its counter substrate. A plurality of arranged data lines 14 are connected to the data signal driving circuit 110. The scanning signal driving circuit 100 and the data signal driving circuit 110 may be formed on the MIM array substrate 30 shown in FIGS. 1 and 2 or the counter substrate thereof. In this case, the scanning signal driving circuit 100 and the data signal driving circuit 110 include the driving circuit. A liquid crystal display device (liquid crystal display module) is obtained. Alternatively, the scanning signal driving circuit 100 and the data signal driving circuit 110 may be configured by an IC independent of the liquid crystal display panel, and may be connected to the scanning lines 12 and the data lines 14 via predetermined wirings. The liquid crystal display device (liquid crystal display panel) does not include a driving circuit.
[0046]
In each pixel region 16, the scanning line 12 is connected to one terminal of the MIM driving element 20 (see FIG. 1), and the data line 14 is connected to the liquid crystal layer 18 and the pixel electrode 34 shown in FIG. The other terminal of the MIM driving element 20 is connected. Therefore, when a scanning signal is supplied to the scanning line 12 corresponding to each pixel region 16 and a data signal is supplied to the data line 14, the MIM driving element 20 in the pixel region is turned on, and the MIM driving element 20 is turned on. Thus, a driving voltage is applied to the liquid crystal layer 18 between the pixel electrode 34 and the data line 14.
[0047]
When the scanning signal driving circuit 100 and the data signal driving circuit 110 are provided on the MIM array substrate 30, a thin film forming process for the MIM driving element 20 and a thin film forming process for the scanning signal driving circuit 100 and the data signal driving circuit 110 are provided. There is an advantage that can be performed at the same time. However, for example, an LSI including the scanning signal driving circuit 100 and the data signal driving circuit 110 mounted by a TAB (tape automated bonding) method is connected to an LSI through an anisotropic conductive film provided in the peripheral portion of the MIM array substrate 30. If the configuration for connecting the scanning lines 12 and the data lines 14 is adopted, the liquid crystal display panel 10 can be manufactured more easily. Further, the scanning line 12 and the data line 14 are connected using a COG (chip on glass) system in which the above-described LSI is directly mounted on the MIM array substrate 30 and its opposite substrate via an anisotropic conductive film. You can also.
[0048]
In FIG. 7, the liquid crystal display panel 10 includes an MIM array substrate 30 and a counter substrate 32 that constitutes an example of a transparent second substrate disposed to face the MIM array substrate 30. The counter substrate 32 is made of, for example, a glass substrate. The MIM array substrate 30 is provided with a plurality of transparent pixel electrodes 34 in a matrix. The plurality of pixel electrodes 34 extend along a predetermined X direction, and are connected to the plurality of scanning lines 12 arranged in the Y direction orthogonal to the X direction. An alignment film made of an organic thin film such as a polyimide thin film and subjected to a predetermined alignment process such as a rubbing process is provided on the side facing the liquid crystal such as the pixel electrode 34, the MIM driving element 20, and the scanning line 12. .
[0049]
On the other hand, the counter substrate 32 is provided with a plurality of data lines 14 extending in the Y direction and arranged in a strip shape in the X direction. An alignment film made of an organic thin film such as a polyimide thin film and subjected to a predetermined alignment process such as a rubbing process is provided below the data line 14. In this case, the data line 14 is formed of a transparent conductive film such as an ITO film at least at a portion facing the pixel electrode 34. However, when the scanning line 12 is formed on the counter substrate 32 side instead of the data line 14, the scanning line 12 is formed of a transparent conductive film such as an ITO film.
[0050]
Depending on the application of the liquid crystal display panel 10, the counter substrate 32 may be provided with a color filter made of a color material film arranged in, for example, a stripe shape, a mosaic shape, or a triangle shape. A black matrix such as resin black in which carbon or titanium is dispersed in a photoresist may be provided. With such a color filter or black matrix, it is possible to display a color image on a single liquid crystal display panel, or to display a high-quality image by improving contrast or preventing color mixture of color materials.
[0051]
Between the MIM array substrate 30 and the counter substrate 32 configured as described above and arranged so that the pixel electrode 34 and the data line 14 face each other, a sealant disposed along the periphery of the counter substrate 32 is used. Liquid crystal is sealed in the enclosed space, and a liquid crystal layer 18 (see FIG. 6) is formed. The liquid crystal layer 18 adopts a predetermined alignment state by the alignment film described above in a state where the electric field from the pixel electrode 34 and the data line 14 is not applied. The liquid crystal layer 18 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing agent is an adhesive for bonding the substrates 30 and 32 around them, and a spacer for setting the distance between the substrates to a predetermined value is mixed therein.
[0052]
In FIG. 6, as the scanning signal driving circuit 100 sequentially sends scanning signals of a predetermined voltage to the MIM driving element 20 in a pulse manner, the data signal driving circuit 110 responds to the gradation level of the display signal as will be described later. A data signal having a pulse width is sequentially sent to the data line 14. In FIG. 7, when a voltage is applied to the pixel electrode 34 and the data line 14 in this way, the alignment state of the liquid crystal layer in the portion sandwiched between the pixel electrode 34 and the data line 14 is passed through the MIM driving element 20. In the normally white mode, the incident light cannot pass through the liquid crystal portion when the drive voltage is applied. In the normally black mode, the drive voltage is In the applied state, incident light can pass through the liquid crystal portion, and light having a contrast corresponding to a display signal is emitted from the liquid crystal display panel 10 as a whole.
[0053]
Although not shown in FIGS. 1 to 7, for example, a TN (twisted nematic) mode, respectively, is provided on the side on which the projection light of the counter substrate 32 is incident and on the side of the MIM array substrate 30 on which the projection light is emitted. Depending on the operation mode such as STN (super TN) mode, D-STN (double-STN) mode, and normally white mode / normally black mode, the polarizing film, retardation film, polarizing plate, etc. are in a predetermined direction. It is arranged with.
[0054]
(First Embodiment of Driving Circuit)
Next, the configuration and operation of the scanning signal driving circuit 100 and the data signal driving circuit 110 shown in FIG. 6 in the first embodiment will be described with reference to FIGS.
[0055]
First, the scanning signal driving circuit 100 that constitutes an example of the scanning signal driving unit generates a scanning signal having a predetermined peak value (voltage value) and a pulse width and having a constant period based on a reference clock for each pixel. The voltage applied to the electrodes is sequentially applied to the plurality of scanning lines 12 so that the voltage is inverted every frame with reference to the intermediate value of the data signal. Thus, the reason why the scanning signal is inverted (and the data signal is also inverted correspondingly) is to prevent the liquid crystal layer 18 from being deteriorated by AC driving the liquid crystal layer 18. Depending on the driving method, the scanning signal may be supplied to the scanning line 12 in a time-sharing manner for each row, or may be supplied in a time-sharing manner for each of a plurality of rows such as every three rows.
[0056]
As shown in the block diagram of FIG. 8, the data signal driving circuit 110a constituting an example of the data signal driving means includes a frame counter 200, an X counter 202, an AND gate 210, a 1 addition circuit 212, a GCP generation circuit 214, and an X driver. A circuit 216 is provided.
[0057]
In the data signal driving circuit 110a, for example, a 6-bit D0 to D5 (D0 is LSB) digital signal indicating one of 64 gradation levels (gradation levels 0 to 63) is received for each pixel. Further, a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, and a reference clock XCK for driving the X driver circuit 216 are input.
[0058]
The GCP generation circuit 214 includes 32 comparison circuits 214a and a logical sum circuit 214b that calculates a logical sum of the comparison results. The comparison circuit 214a resets the count value of the X counter 202 that is reset for each HSYNC and counted up for each reference clock XCK to 32 predetermined values based on the characteristics shown in FIG. Compare with Then, the logical sum circuit 214b computes the logical sum of the comparison results of these comparison circuits 214a, and the computation output has 32 gradation levels having the characteristics shown in FIG. A GCP signal composed of a sequence of 32 pulses per 1H period having a different interval in advance corresponding to the difference in the ON width of the MIM driving element 20 corresponding to the difference is generated. The GCP signal generated in this way (see the second stage from the top in FIG. 26) is supplied to the GCP input terminal of the X driver circuit 216.
[0059]
The frame counter 200 is counted up every VSYNC. A logical product of the LSB of the count value counted by the frame counter 200 and D0, which is the LSB of the input 6-bit digital signal, is calculated by the AND gate 210 and is supplied to the control signal terminal of the 1 adder circuit 212 as a control signal. Entered.
[0060]
When the level of the input control signal is “H”, the 1 adder circuit 212 adds +1 to the input 5-bit digital signal and outputs it, and the level of the input control signal is “L”. Sometimes, the input 5-bit digital signal is output as it is.
[0061]
When the 6-bit digital signals D0 ′ to D5 ′ (where D0 ′ is LSB) are input from the 1-adder circuit 212, the X driver circuit 216 receives the digital signals D0 ′ to D5 ′ based on the reference clock XCK. Are held in a predetermined internal register that has a one-to-one correspondence with the plurality of data lines 14. By sequentially generating the digital signals D0 ′ to D5 ′ corresponding to the digital signals D0 to D5 as described above and transferring them to the internal register of the X driver circuit 216, all the digital signals for one horizontal line are stored in this internal signal. It will be held in the register. From the internal register, using the LP signal as a trigger, according to the GCP signal consisting of a sequence of 32 pulses per 1H period input from the GCP generation circuit 214, it corresponds to the gradation level indicated by the 6-bit digital value in the internal register A data signal having the specified pulse width is output. As described above, data signals having 33 different widths are generated and supplied to the plurality of data lines 14 in response to the input of the 64-gradation digital signals D0 to D5.
[0062]
The above operation will be further described with reference to the timing chart of FIG.
[0063]
In FIG. 9, the vertical synchronization signal VSYNC is input for each frame, whereby the LSB of the frame counter 200 becomes 1 (H level) or 0 (L level). A plurality of horizontal synchronization signals HSYNC are input between the synchronization signals VSYNC.
[0064]
The GCP generation circuit 214 generates a GCP signal composed of a sequence of 32 pulses whose intervals gradually change corresponding to 33 different gradation levels in the 1H period.
[0065]
As a result, as shown in the lower part of FIG. 9, for example, a digital signal D0 to D5 having a gradation level of 5 is input to the pixel electrode of the specific address, and 1 (H level) or For each frame defined by a period in which the LSB of the frame counter 200 that is 0 (L level) is constant, digital signals D0 ′ to D5 ′ having gradation levels alternately 4 and 6 are output from the 1 addition circuit 212. Is output.
[0066]
As described above, for example, if a digital signal indicating the gradation level “5” is input over a plurality of frames for one pixel, the 1 addition circuit 212 outputs a digital signal indicating the gradation level “4”. The signal and the digital signal indicating the gradation level “6” are alternately output for each frame and input to the X driver circuit 216. That is, temporal averaging (first averaging) of a plurality of data signals over a plurality of frames is performed.
[0067]
As a result, the X driver circuit 216 outputs, for each frame, a data signal having a pulse width corresponding to the gradation level “4” and a data signal having a pulse width corresponding to the gradation level “6” for the pixel. Are alternately supplied via the data line 214.
[0068]
FIG. 10 schematically shows the principle of gradation display using the data signal generated as described above. In FIG. 9, the frame counter 200 is used to alternately output different gradation levels for each frame, but substantially the same effect can be obtained by alternately outputting different gradation levels for each field. Therefore, in the example shown in FIG. 10, a case where different gradation levels are output alternately for each field will be described. Here, the “frame” means, for example, a unit of one complete color screen after combining R, G and B monochromatic light screens to generate a color screen, or an NTSC interlace. One complete screen unit scanned by even and odd field scans. The “field” is, for example, a unit such as each monochromatic light field when a single color light screen of R, G, and B is synthesized to generate a color screen, or an even or odd field in an NTSC interlace. Refers to units.
[0069]
In FIG. 10, when a gradation level n is displayed in a certain pixel, a data signal having a pulse width corresponding to the gradation level n is generated and supplied to the data line 14 in the field 1 to field 4 ( Left column). Further, when displaying a gradation level n + 1 in a certain pixel, a data signal having a pulse width corresponding to the gradation level n + 1 is generated and supplied to the data line 14 in the field 1 to field 4 (right column). ). On the other hand, when a gradation level n + 0.5 is displayed in a certain pixel, a data signal having a pulse width corresponding to the gradation level n is generated in the field 1 and the field 3 and supplied to the data line 14. In the fields 2 and 4, a data signal having a pulse width corresponding to the gradation level n + 1 is generated and supplied to the data line 14 (center column).
[0070]
As described above, for example, when a 64-gradation digital signal is input for each pixel, for example, for each field unit, the data signal consisting of 33 different width pulses is generated by the data signal driving circuit 110a. An average value (first average value) of the widths of a plurality of pulses forming a plurality of data signals over a plurality of field units for each pixel is generated so as to correspond to the gradation level of each pixel. Thus, the data signal generated so that the first average value corresponds to the gradation level is supplied to the data line 14, and the scanning signal driving circuit 100 supplies the scanning signal to the scanning line 12. If a predetermined time unit such as a field unit or a frame unit is set sufficiently small for vision, for example, a pulse corresponding to an odd gradation level is not used, that is, a width corresponding to an even gradation level. Using only this pulse, a display similar to that obtained by supplying a pulse having a width corresponding to the odd gradation level can be visually obtained.
[0071]
As described above, according to the present embodiment, it is possible to realize 64 gradation levels, which is approximately twice as large, using a data signal composed of pulses having 33 widths, so that the pulse trains constituting the GCP signal can be realized. The number of gradations can be increased without reducing the interval. Therefore, in order to increase the number of gradations, it is not necessary to narrow the interval between the pulse trains constituting the GCP signal on the side where the gradation level is particularly high, and the GCP generation circuit 214 and the data signal driving circuit 110a need not be operated at high speed. Therefore, it is not necessary to shorten the cycle of the reference clock XCK on the X side in order to narrow the interval between the pulse trains constituting the GCP signal, and the increase in power consumption can be prevented. Furthermore, by performing a relatively low-speed operation in this way, the gradation level is distorted by a slight change in the delay time of the pulses constituting the GCP signal and data signal due to external influences such as temperature changes and the operating environment. The situation can be prevented in advance, and the stability of the operation is greatly increased.
[0072]
In particular, in the liquid crystal display panel 10 using the MIM driving element 20 which has an advantage of a simple configuration and manufacturing method, simplification and cost reduction associated with such driving device are very significant.
[0073]
In the embodiment shown in FIG. 8 to FIG. 10, the gradation level n and gradation level n + 1 are alternately displayed at a time ratio of 1: 1, so that the gradation level is expressed by the first average value. Although n + 1/2 is displayed, this time ratio is not limited to 1: 1. For example, the gradation level n + 2/3 can be displayed by alternately displaying these at a time ratio of 1: 2, and the gradation level can be displayed by alternately displaying them at a time ratio of 2: 1. n + 1/3 can be displayed, and by alternately displaying them at a time ratio of 1: 3, gradation levels n + 3/4 can be displayed, and these can be displayed alternately at a time ratio of 3: 1. Thus, the gradation level n + 1/4 can be displayed. More generally, using a temporal average value of a pulse width corresponding to the gradation level m forming at least one data signal and a pulse width corresponding to the gradation level m + 1 forming at least one data signal, A data signal corresponding to the key level m + α (0 <α <1) may be generated.
[0074]
(Second Embodiment of Driving Circuit)
Next, the configuration and operation of the scanning signal driving circuit 100 and the data signal driving circuit 110 in the second embodiment will be described with reference to FIGS.
[0075]
In the first embodiment of the drive circuit described above, the first average value is used to visually realize a gradation level that is not actually displayed. In the present embodiment, the second average value is used. That is, a gradation level that is not actually displayed is visually realized using an average value of gradation levels in an image display area composed of a plurality of adjacent pixels.
[0076]
The configuration and operation of the scanning signal driving circuit in the second embodiment are the same as in the case of the first embodiment.
[0077]
FIG. 11 shows a block diagram of a data signal driving circuit 110b constituting another example of the data signal driving means in the second embodiment. In FIG. 11, the same components as those in FIG. 8 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0078]
As shown in FIG. 11, the data signal driving circuit 110b includes an X counter 202, a Y counter 204, an EX. An OR gate 208, an AND gate 210, a 1 adder circuit 212, a GCP generation circuit 214, and an X driver circuit 216 are provided.
[0079]
The X counter 202 is reset every HSYNC and is counted up every reference clock XCK. The exclusive OR of the LSB of the count value counted by the X counter 202 and the LSB of the count value of the Y counter 204 reset every VSYNC and counted up every HSYNC is EX. The operation is performed by the OR gate 208. The logical product of the output exclusive OR and D0, which is the LSB of the input 6-bit digital signal, is calculated by the AND gate 210 and input to the control signal terminal of the 1 adder circuit 212 as a control signal. The
[0080]
The operation of the second embodiment configured as described above will be further described with reference to the timing chart of FIG.
[0081]
In FIG. 12, the GCP generation circuit 214 generates a GCP signal composed of a sequence of 32 pulses whose intervals gradually change corresponding to 33 different gradation levels in the 1H period.
[0082]
Then, as shown in the lower part of FIG. 12, for example, digital signals D0 to D5 indicating the gradation level “5” are input to a plurality of pixel electrodes adjacent in the row and column directions. Digital signals D0 ′ to D5 ′ indicating gradation levels “4” and “6” are alternately output for each period in which the LSB of the X counter 202 is constant based on the reference clock XCK. The digital signals D0 ′ to D5 ′ indicating the gradation levels “4” and “6” are alternately output and input to the X driver circuit 216 every 1H period in which the LSB is constant.
[0083]
As described above, for example, when a digital signal indicating the gradation level “5” is input to the plurality of pixel electrodes adjacent in the row and column directions, the gradation level “4” is displayed from the 1 addition circuit 212. A digital signal and a digital signal indicating a gradation level “6” are alternately output to these adjacent pixel electrodes and input to the X driver circuit 216. That is, area and space averaging (second averaging) is performed on a plurality of adjacent pixels.
[0084]
As a result, the X driver circuit 216 outputs a data signal having a pulse width corresponding to the gradation level “4” and a data signal having a pulse width corresponding to the gradation level “6” to these adjacent pixel electrodes. Are alternately supplied via the data line 214 for each row and column.
[0085]
FIG. 13 schematically shows the principle of gradation display using the data signal generated as described above.
[0086]
In FIG. 13, for example, when the gradation level n is displayed in four adjacent pixels, a data signal having a pulse width corresponding to the gradation level n is generated for each of the four pixels, and the data line 14 (left side of FIG. 13). When the gradation level n + 1 is displayed in the four adjacent pixels, a data signal having a pulse width corresponding to the gradation level n + 1 is generated and supplied to the data line 14 for each of the four pixels. (Right side of FIG. 13). On the other hand, when the gradation level n + 0.5 is displayed in the four adjacent pixels, for example, a pulse corresponding to the gradation level n is applied to each of the two pixels located diagonally out of the four pixels. A data signal having a width is generated and supplied to the data line 14, and a data signal having a pulse width corresponding to the gradation level n + 1 is generated and supplied to the data line 14 for each of the remaining two pixels. (Center of FIG. 13).
[0087]
As described above, for example, when a 64-gradation digital signal is input for each pixel, the data signal driving circuit generates a plurality of data signals composed of 33 different widths within a predetermined area unit. The second average value of the widths of the plurality of pulses forming the plurality of data signals for the pixel is generated so as to correspond to the gradation level. Thus, the data signal generated so that the second average value corresponds to the gradation level is supplied to the data line 14, and the scanning signal driving circuit 100 supplies the scanning signal to the scanning line 12. If a predetermined area unit is set sufficiently small for vision, for example, without using a pulse having a width corresponding to an odd gradation level, that is, using only a pulse having a width corresponding to an even gradation level. A display similar to that obtained by supplying a pulse having a width corresponding to an odd number of gradation levels is visually obtained.
[0088]
As described above, according to the second embodiment, it is possible to realize 64 gradation levels, which is approximately twice as large, by using a data signal composed of pulses having 33 widths. The same effect as the form can be obtained.
[0089]
Also in the case of the present embodiment, the gradation level n and the gradation level n + 1 are displayed at an area ratio of 1: 1, so that the gradation level n + 0.5 is displayed by the second average value. However, the area ratio is not limited to 1: 1. For example, the gradation level n + 2/3 can be displayed by displaying these at an area ratio of 1: 2, and the gradation level n + 1/3 can be displayed by displaying them at an area ratio of 2: 1. More generally, data signals corresponding to various gradation levels can be generated by employing various predetermined region units and area ratios.
[0090]
(Third embodiment of drive circuit)
Next, the configuration and operation of the scanning signal driving circuit 100 and the data signal driving circuit 110 in the third embodiment will be described with reference to FIGS.
[0091]
In the first embodiment of the drive circuit described above, a gradation level that is not actually displayed is visually realized by using the first average value. In the second embodiment, the second average is used. Although the gradation level that is not actually displayed using the value is visually realized, in the present embodiment, the gradation level is actually displayed using both the first average value and the second average value. Visually realize no gradation level.
[0092]
The configuration and operation of the scanning signal driving circuit in the third embodiment are the same as in the case of the first embodiment.
[0093]
FIG. 14 shows a block diagram of a data signal driving circuit 110c constituting another example of the data signal driving means in the third embodiment. In FIG. 14, the same components as those in FIG. 8 or FIG. 11 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0094]
As shown in FIG. 14, the data signal driving circuit 110b includes a frame counter 200, an X counter 202, a Y counter 204, an EX. An OR gate 206 and 208, an AND gate 210, a 1 addition circuit 212, a GCP generation circuit 214, and an X driver circuit 216 are configured.
[0095]
The frame counter 200 is counted up every VSYNC. The exclusive OR of the LSB of the count value counted by the frame counter 200 and the LSB of the count value counted by the X counter 202 is EX. The operation is performed by the OR gate 206. Further, the exclusive OR of the output exclusive OR and the LSB of the count value of the Y counter 204 is EX. The operation is performed by the OR gate 208. The logical product of the output exclusive OR and D0, which is the LSB of the input 6-bit digital signal, is calculated by the AND gate 210 and input to the control signal terminal of the 1 adder circuit 212 as a control signal. The
[0096]
The operation of the third embodiment configured as described above will be further described with reference to the timing chart of FIG.
[0097]
In FIG. 15, the GCP generation circuit 214 generates a GCP signal composed of a sequence of 32 pulses whose intervals gradually change corresponding to 33 different gradation levels in the 1H period.
[0098]
Then, as shown in the lower part of FIG. 15, for example, digital signals D0 to D5 indicating a gradation level “5” are input to a plurality of pixel electrodes adjacent in the row and column directions. Digital signals D0 ′ to D5 ′ indicating gradation levels “4” and “6” are alternately output for each period in which the LSB of the X counter 202 is constant based on the reference clock XCK. The digital signals D0 ′ to D5 ′ indicating the gradation levels “4” and “6” are alternately output and input to the X driver circuit 216 every 1H period in which the LSB is constant. When the above operation is performed for one frame, in the next frame, for example, digital signals D0 to D5 having a gradation level of 5 are input to the pixel electrode of a specific address, and based on the synchronization signal VSYNC. Digital signals D0 ′ to D5 ′ whose gradation levels are alternately 4 and 6 for each frame defined by a period in which the LSB of the frame counter 200 is 1 (H level) or 0 (L level). Is output from the 1-adder circuit 212.
[0099]
As described above, the first averaging is performed on a plurality of adjacent pixels as in the first embodiment described above, and the plurality of adjacent pixels is further processed as in the second embodiment described above. A second averaging at is also performed.
[0100]
FIG. 16 schematically shows the principle of gradation display using a data signal generated by the data signal driving circuit configured as described above. In FIG. 14, the frame counter 200 is used to alternately output different gradation levels for each frame. However, even if gradation values different for each field are output alternately, substantially the same effect can be obtained. Therefore, in the example shown in FIG. 16, a case where different gradation levels are output alternately for each field will be described.
[0101]
In FIG. 16, when displaying the gradation level n + 0.5 in the four adjacent pixels as shown in the center of FIG. 13, in the first field, two pixels located diagonally among these four pixels. For each, a data signal having a pulse width corresponding to the gradation level n is generated and supplied to the data line 14, and for each of the remaining two pixels, a pulse width corresponding to the gradation level n + 1 is set. A data signal is generated and supplied to the data line 14 (left side in FIG. 16). Further, for each of these four adjacent pixels, the second field corresponds to a different gradation level n (or n + 1) from the first field so that the gradation level n + 0.5 corresponds to the first average value. A data signal having a pulse width is generated and supplied to the data line 14 (center of FIG. 16). Similarly, for each of these four pixels, the gray level in the third field is the same as the first field, unlike the second field, so that the gray level n + 0.5 corresponds to the first average value. A data signal having a pulse width corresponding to the level n (or n + 1) is generated and supplied to the data line 14 (right side in FIG. 16).
[0102]
Furthermore, as shown in FIGS. 17 and 18, more complicated driving methods using temporal and area averaging are possible.
[0103]
That is, in FIG. 17, as shown in the upper part, gradation level 4 and gradation level 6 are displayed at a ratio of 3: 1 for each pixel, and as shown in the lower part, four adjacent levels are displayed. The pixels are driven so that the timing is shifted by one field. Then, with respect to these four adjacent pixels, gradation display in which the average value is the gradation level 4.5 in both time and area in four fields becomes possible.
[0104]
In FIG. 18, as shown in the upper part, gradation level 4 and gradation level 6 are displayed at a ratio of 6: 2 for each pixel, and as shown in the lower part, four adjacent pixels are displayed. The two pixels are driven so that the timing is shifted by one field. Then, with respect to these four adjacent pixels, gradation display in which the average value is the gradation level 4.5 in 8 fields in both time and area becomes possible.
[0105]
As described above, according to the third embodiment, the data signal is generated so that the second average value in the predetermined area unit corresponds to the gradation level, and further, for each of the plurality of pixels. Since the data signal is generated so that the first average value corresponds to the gradation level, for example, a data signal composed of pulses having two widths is used to correspond to a pulse having a width between those widths. The gradation level to be obtained is obtained as a gradation level that is uniform in terms of time and area visually. As a result, the interval between the pulse trains constituting the GCP signal can be made relatively large while making the flicker inconspicuous.
[0106]
(Fourth Embodiment of Drive Circuit)
In each of the embodiments described above, as in the case of normal liquid crystal driving, the liquid crystal layer 18 is applied between the pixel electrode 34 and the data line 14 for the purpose of preventing deterioration of the liquid crystal layer 18 and the like. The voltage to be driven is driven (AC drive) so that the polarity is inverted with reference to the intermediate value of the data signal for each field or frame. For this reason, for example, according to the driving method in the first embodiment shown in FIG. 10, as shown as driving method A in FIG. 19, the data signal (liquid crystal driving voltage) for each field is obtained for one pixel. The polarity is reversed. Here, for example, when gradation level 4 and gradation level 6 are alternately displayed for each field, a direct current component resulting from a difference in drive voltage between gradation level 4 and gradation level 6 is obtained. It is applied to the liquid crystal layer 18. This applied direct current component hardly poses a problem if the effective value of the change in the alignment state of the liquid crystal at these gradation levels (effective voltage value applied to the liquid crystal) is small. However, depending on the panel characteristics of the liquid crystal display panel 10 and the like, there may be a case where this effective value cannot be ignored (that is, when a DC voltage adversely affects the liquid crystal).
[0107]
Therefore, in the fourth embodiment of the drive circuit, as shown as drive method B in FIG. 19, every two fields or every two frames that coincide with the cycle in which the polarity inversion of the drive voltage is performed twice and returned to the original state. The gradation level is switched to. For example, gradation level 4 and gradation level 6 are alternately displayed every two fields. In this way, the polarity of the drive voltage is reversed twice during the two fields and returns to the original state, so that the gradation levels will be 4 and 6, but the gradation levels will be 3 and 7. However, the DC component applied to the liquid crystal every two fields can be made substantially zero. As described above, according to the present embodiment, it is possible to reduce the application of a DC voltage to the liquid crystal layer as compared with the driving method A.
[0108]
However, the driving method B shown in FIG. 19 is more disadvantageous than the driving method A from the viewpoint of flicker on the display screen. Thus, since the application of the DC voltage and the flicker are in a trade-off relationship, whether to select the driving method A or the driving method B depends on the panel characteristics, DC withstand voltage, It is preferable to determine the response speed and the like.
[0109]
When the driving method B in the present embodiment is adopted, as in the case of the third embodiment of the drive circuit described above (see FIG. 16), as shown in FIG. The gradation level between adjacent pixels is switched so that the second averaging is performed in addition to the averaging of 1. Thereby, flicker can be made inconspicuous.
[0110]
When the liquid crystal display panel 10 described above is applied to, for example, a color liquid crystal projector, the three liquid crystal display panels 10 are used as RGB light valves, and each panel has a dichroic mirror for RGB color separation. Therefore, it is not necessary to provide a color filter on the counter substrate 32 because the light of each color separated through the light is incident as incident light. On the other hand, when the liquid crystal display panel 10 is applied to, for example, a direct-view or reflective color liquid crystal television, an RGB color filter is formed on a counter substrate 32 together with its protective film in a predetermined region facing the pixel electrode 34. It may be formed.
[0111]
In the liquid crystal display panel 10, a planarizing film is applied to the entire surface of the pixel electrode 34, the MIM driving element 20, the scanning line 12, etc. by spin coating or the like in order to suppress alignment defects of liquid crystal molecules on the MIM array substrate 30 side. Alternatively, a CMP process may be performed.
[0112]
In the above embodiment, the first or second averaging is performed based on the so-called “four-value driving method”. However, according to the present invention, for example, Japanese Patent Laid-Open No. 2-125225, etc. Similarly, it is possible to perform averaging in terms of time or area based on the charge / discharge driving method disclosed in the above.
[0113]
Further, in the liquid crystal display panel 10, the liquid crystal layer 18 is made of nematic liquid crystal as an example. However, if polymer dispersed liquid crystal in which liquid crystal is dispersed as fine particles in a polymer is used, the alignment film and polarizing film described above are used. Further, there is no need for a polarizing plate or the like, and the advantages of high brightness and low power consumption of the liquid crystal display panel can be obtained by increasing the light utilization efficiency. Further, by forming the pixel electrode 34 from a metal film having a high reflectance such as Al, when the liquid crystal display panel 10 is applied to a reflection type liquid crystal display device, the liquid crystal molecules are substantially vertically aligned in the state where no voltage is applied. Also, SH (super homeotropic) type liquid crystal may be used. Furthermore, in the liquid crystal display panel 10, the data line 14 is provided on the counter substrate 32 side so as to apply an electric field (vertical electric field) perpendicular to the liquid crystal layer, but an electric field (lateral electric field) parallel to the liquid crystal layer is provided. ) Is applied to each pixel electrode 34 from a pair of electrodes for generating a horizontal electric field (that is, no electrode for generating a vertical electric field is provided on the counter substrate 32 side, and the MIM array substrate 30 side is not provided). It is also possible to provide an electrode for generating a transverse electric field. Using a horizontal electric field in this way is more advantageous in widening the viewing angle than using a vertical electric field. In addition, the present embodiment can be applied to various liquid crystal materials (liquid crystal phases), operation modes, liquid crystal alignments, driving methods, and the like.
[0114]
(Electronics)
Next, an embodiment of an electronic apparatus including the liquid crystal display panel 10, the scanning signal driving circuit 100, and the data signal driving circuit 110 described in detail above will be described with reference to FIGS.
[0115]
First, FIG. 21 shows a schematic configuration of an electronic apparatus including the liquid crystal display panel 10 and the like in this way.
[0116]
In FIG. 21, an electronic device includes a display information output source 1000, a display information processing circuit 1002, a driving circuit 1004 including the scanning signal driving circuit 100 and the data signal driving circuit 110, a liquid crystal display panel 10 and a clock generation circuit 1008. In addition, a power supply circuit 1010 is provided. The display information output source 1000 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit, and the like. Based on a clock from the clock generation circuit 1008, a video signal of a predetermined format, etc. The display information is output to the display information processing circuit 1002. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and display information input based on a clock. From the above, the 6-bit 64-gradation digital signal DATA (D0 to D5) is sequentially generated and output to the drive circuit 1004 together with the clock CLK. The driving circuit 1004 drives the liquid crystal display panel 10 by the scanning signal driving circuit 100 and the data signal driving circuit 110 by the driving method described above. The power supply circuit 1010 supplies predetermined power to the above-described circuits. Note that the drive circuit 1004 may be mounted on the MIM array substrate constituting the liquid crystal display panel 10, and in addition to this, the display information processing circuit 1002 may be mounted.
[0117]
Next, specific examples of the electronic apparatus configured as described above are shown in FIGS.
[0118]
In FIG. 22, a liquid crystal projector 1100 as an example of an electronic device prepares three liquid crystal display modules including the liquid crystal display panel 10 in which the above-described drive circuit 1004 is mounted on an MIM array substrate, and each of the RGB light valves 10R. It is configured as a projection type projector used as 10G and 10B. In the liquid crystal projector 1100, when projection light is emitted from the lamp unit 1102 of the white light source, light corresponding to the three primary colors of RGB is provided by the two dichroic mirrors 1108 through the plurality of mirrors 1106 inside the light guide 1104. Divided into components R, G, and B, they are led to light valves 10R, 10G, and 10B corresponding to the respective colors. The light components corresponding to the three primary colors modulated by the light valves 10R, 10G, and 10B are synthesized again by the dichroic prism 1112, and then projected as a color image on the screen or the like via the projection lens 1114.
[0119]
In FIG. 23, a laptop personal computer 1200, which is another example of an electronic device, includes the above-described liquid crystal display panel 10 in a top cover case, and further accommodates a CPU, a memory, a modem, and the like, and a keyboard 1202. Is incorporated in the main body 1204.
[0120]
In FIG. 24, a pager 1300 as another example of an electronic device includes a backlight 1306a in a liquid crystal display panel 10 in which the drive circuit 1004 described above is mounted on a MIM array substrate in a metal frame 1302 to form a liquid crystal display module. A light guide 1306, a circuit board 1308, first and second shield plates 1310 and 1312, two elastic conductors 1314 and 1316, and a film carrier tape 1318 are accommodated. In this example, the aforementioned display information processing circuit 1002 (see FIG. 21) may be mounted on the circuit board 1308 or on the MIM array substrate of the liquid crystal display panel 10. Further, the above-described drive circuit 1004 can be mounted on the circuit board 1308.
[0121]
Since the example shown in FIG. 24 is a pager, a circuit board 1308 and the like are provided. However, in the case of the liquid crystal display panel 10 in which the driving circuit 1004 and the display information processing circuit 1002 are mounted to form a liquid crystal display module, a liquid crystal display device in which the liquid crystal display panel 10 is fixed in a metal frame 1302 is used. In addition, a backlight type liquid crystal display device incorporating a light guide 1306 can be produced, sold, used, or the like.
[0122]
As shown in FIG. 25, in the case of the liquid crystal display panel 10 in which the driving circuit 1004 and the display information processing circuit 1002 are not mounted, an IC 1324 including the driving circuit 1004 and the display information processing circuit 1002 is mounted on the polyimide tape 1322. It is physically and electrically connected to a TCP (Tape Carrier Package) 1320 via an anisotropic conductive film provided on the periphery of the MIM array substrate 30 to produce, sell, use, etc. as a liquid crystal display device It is also possible.
[0123]
In addition to the electronic devices described above with reference to FIGS. 22 to 25, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic notebook, a calculator, a word processor, a workstation, a mobile phone A video phone, a POS terminal, a device provided with a touch panel, and the like are examples of the electronic device illustrated in FIG.
[0124]
As described above, according to the present embodiment, various electronic devices having a relatively simple configuration, capable of high gradation display, and equipped with a liquid crystal display device with high reliability in gradation display are realized. it can.
[0125]
【The invention's effect】
According to the present invention, it is possible to realize M (for example, M> N) gradation levels such as several times using a data signal including pulses having N widths. As a result, for example, when the data signal is generated by the data signal driving means based on the GCP signal, the number of gradations can be increased without reducing the interval between the pulse trains constituting the GCP signal. Therefore, in order to increase the number of gradations, it is not necessary to narrow the interval between the pulse trains constituting the GCP signal particularly on the higher gradation level side, and it is not necessary to operate the circuit for generating the GCP signal and the data signal driving means at high speed. . Therefore, it is not necessary to shorten the cycle of the operation clock in order to narrow the interval between the pulse trains constituting the GCP signal, a high-performance clock is unnecessary, and an increase in power consumption can be prevented. Further, by performing a relatively low-speed operation in this way, a situation in which the gradation level is distorted due to a slight change in the delay time of the GCP signal or data signal pulse due to an external influence such as a temperature change or an operating environment, etc. This can be prevented in advance, and the stability of the operation is greatly increased.
[0126]
In particular, in a liquid crystal display device including a liquid crystal display panel using a two-terminal nonlinear element such as MIM, which has an advantage of a simple configuration and a manufacturing method, simplification in such a driving device and associated cost reduction are as follows: Very meaningful.
[Brief description of the drawings]
FIG. 1 is a plan view showing an example of an MIM driving element provided in an embodiment of a liquid crystal display panel according to the present invention together with a pixel electrode.
FIG. 2 is a cross-sectional view taken along the line AA of FIG.
FIG. 3 is a cross-sectional view showing another example of the MIM driving element provided in the embodiment of the liquid crystal display panel.
FIG. 4 is a plan view showing still another example of the MIM driving element provided in the embodiment of the liquid crystal display panel together with the pixel electrode.
5 is a cross-sectional view taken along the line BB in FIG.
FIG. 6 is an equivalent circuit diagram showing a circuit constituting the embodiment of the liquid crystal display panel.
FIG. 7 is a partially broken perspective view schematically showing an embodiment of a liquid crystal display panel.
FIG. 8 is a block diagram showing a first embodiment of a data signal driving circuit according to the present invention.
FIG. 9 is a timing chart showing an operation of the data signal driving circuit according to the first embodiment;
FIG. 10 is a conceptual diagram showing the operation principle of the first embodiment of the data signal driving circuit.
FIG. 11 is a block diagram showing a second embodiment of a data signal driving circuit according to the present invention.
FIG. 12 is a timing chart showing the operation of the second embodiment of the data signal driving circuit;
FIG. 13 is a conceptual diagram showing the operation principle of the second embodiment of the data signal driving circuit.
FIG. 14 is a block diagram showing a third embodiment of a data signal driving circuit according to the present invention.
FIG. 15 is a timing chart showing the operation of the third embodiment of the data signal driving circuit;
FIG. 16 is a conceptual diagram (part 1) illustrating an operation principle of a data signal driving circuit according to a third embodiment;
FIG. 17 is a conceptual diagram (part 2) illustrating the operation principle of the third embodiment of the data signal driving circuit;
FIG. 18 is a conceptual diagram (part 3) illustrating the operation principle of the third embodiment of the data signal driving circuit;
FIG. 19 is a conceptual diagram (part 1) illustrating an operation principle of a data signal driving circuit according to a fourth embodiment;
FIG. 20 is a conceptual diagram (part 2) illustrating the operation principle of the data signal driving circuit according to the fourth embodiment;
FIG. 21 is a block diagram showing a schematic configuration of an embodiment of an electronic apparatus according to the present invention.
FIG. 22 is a cross-sectional view showing a liquid crystal projector as an example of an electronic apparatus.
FIG. 23 is a front view showing a personal computer as another example of an electronic apparatus.
FIG. 24 is an exploded perspective view showing a pager as an example of an electronic apparatus.
FIG. 25 is a perspective view showing a liquid crystal display device using TCP as an example of an electronic apparatus.
FIG. 26 is a timing chart when gradation display is performed using a conventional GCP signal.
FIG. 27 is a characteristic diagram showing a change in ON width of a pulse for driving a data signal during a 1H period with respect to a gradation level.
FIG. 28 is a characteristic diagram showing a change in pulse interval of each pulse constituting the GCP signal.
[Explanation of symbols]
10 ... Liquid crystal display panel
12, 48 ... scan lines
14 ... Data line
18 ... Liquid crystal layer
20, 20 ', 40a, 40b ... MIM drive element
30 ... MIM array substrate
32 ... Counter substrate
34, 45 ... Pixel electrodes
100: Scanning line driving circuit
110, 110a, 110b, 110c: Data line driving circuit
200: Frame counter
202 ... X counter
204 ... Y counter
212 ... 1 addition circuit
214 ... GCP generation circuit
216 ... X driver circuit
1100 ... Liquid crystal projector
1200 ... personal computer
1300 ... Pager

Claims (5)

A pair of substrates; a liquid crystal sandwiched between the pair of substrates; a plurality of data lines provided on one of the substrates; a plurality of scanning lines provided on the other substrate; A driving device for a liquid crystal display panel comprising a plurality of pixels comprising a switching element and a liquid crystal connected in series with a scanning line,
A first counter for counting a reference clock;
A second counter for counting the horizontal synchronization signal;
A value of an exclusive OR operation result based on the LSB of each count value of the first counter and the second counter, and a plurality of bits of original image data indicating M (where M is a natural number) gradation levels The original image data excluding the LSB is output as it is as the first image data having a plurality of bits, or the original image data excluding the LSB is output in accordance with the operation result of the logical product with the LSB value. An adding circuit that adds 1 to the output and outputs a plurality of bits of second image data;
A generation circuit that generates pulses having different pulse widths corresponding to gradation levels (where N is a natural number less than M) in a horizontal scanning period;
In four pixels adjacent to each other in the row direction and the column direction, a data signal having the pulse width corresponding to the gradation level n indicated by the first image data output from the adder circuit is paired with the four pixels. A data signal having the pulse width corresponding to the gradation level n + 1 indicated by the second image data output from the addition circuit is supplied to each of the two pixels located at the corners and displayed. A driver circuit that supplies and displays the remaining two pixels, respectively,
A driving device for a liquid crystal display panel, wherein the gray level n + 0.5 is displayed by the gray level n data signal and the gray level n + 1 data signal. A pair of substrates; a liquid crystal sandwiched between the pair of substrates; a plurality of data lines provided on one of the substrates; a plurality of scanning lines provided on the other substrate; A driving device for a liquid crystal display panel comprising a plurality of pixels comprising a switching element and a liquid crystal connected in series with a scanning line,
A first counter for counting a reference clock;
A second counter for counting the horizontal synchronization signal;
A third counter for counting the vertical synchronization signal;
A value of an exclusive OR operation result based on the LSB of each count value of the first counter, the second counter, and the third counter, and a plurality of M (where M is a natural number) gradation levels Depending on the operation result of the logical product with the LSB value in the original image data of bits, the original image data excluding the LSB is left as it is and output as the first image data of a plurality of bits, or the LSB is An adder circuit that adds 1 to the removed original image data and outputs it as second image data of a plurality of bits;
A generating circuit for generating pulses having different pulse widths in N (where N is a natural number less than M) corresponding to the gradation level in the horizontal scanning period;
In four pixels adjacent to each other in the row direction and the column direction, a data signal having the pulse width corresponding to the gradation level n indicated by the first image data output from the adder circuit in one frame or field. A data signal having the pulse width corresponding to the gradation level n + 1 indicated by the second image data output from the adder circuit is supplied to and displayed on two pixels located diagonally of the four pixels. The remaining two of the four pixels are supplied for display, and the next frame or field has a data signal having a pulse width corresponding to the gradation level n and a pulse width corresponding to the gradation level n + 1. A driver circuit for supplying a data signal to each of the four pixels so as to alternate with the one frame or field for display.
A driving device for a liquid crystal display panel, wherein the gray level n + 0.5 is displayed by the gray level n data signal and the gray level n + 1 data signal.   3. A liquid crystal display device comprising the liquid crystal display panel driving device according to claim 1 and the liquid crystal display panel.   The liquid crystal display device according to claim 3, wherein the switching element comprises a MIM (Metal Insulator Metal) driving element.   An electronic apparatus comprising the liquid crystal display device according to claim 3.

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