JP3750311B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device with reduced contact resistance in an electrode lead portion of a semiconductor device using silicon carbide (SiC) and a method for manufacturing the same, and is particularly suitable for application to a MOS transistor or the like.
[0002]
[Prior art]
Silicon carbide is an electrode having a large band gap and difficult to make ohmic contact. For this reason, conventionally, in order to obtain an ohmic contact with low contact resistance, the work function is adjusted, carbide or silicide is formed in the extraction portion (the surface of the semiconductor layer that contacts the extraction electrode), or the semiconductor layer is heavily doped. The method of performing etc. is used.
[0003]
[Problems to be solved by the invention]
However, when 4H or 6H cubic silicon carbide is used as the semiconductor substrate material, the impurity concentration of the semiconductor electrode layer is only about 1 × 10 ¹⁹ cm ⁻³ even if the doping level is very high. For this reason, when the extraction electrode is provided in the semiconductor electrode layer, if the extraction electrode is formed of nickel on the n-type semiconductor electrode layer, the extraction electrode is formed of 1 × 10 ⁻⁵ cm ⁻² and the p-type semiconductor electrode layer is formed of titanium. Is formed, contact resistance of only 1 × 10 ⁻⁴ cm ⁻² can be obtained.
[0004]
As a method for solving this problem, it is conceivable to further increase the doping level. However, when 4H or 6H cubic silicon carbide is used, the impurity concentration is set to 1 × 10 ¹⁹ cm ⁻³ in terms of material. However, it is difficult to increase the impurity concentration any more when these materials are used.
The present invention has been made in view of the above problems, and an object thereof is to reduce the contact resistance between a semiconductor layer made of hexagonal silicon carbide and an extraction electrode.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the following technical means are adopted.
In the invention according to claim 1, between the contact region (5) made of 4H or 6H hexagonal silicon carbide and the extraction electrode (12), it has the same conductivity type as the contact region (5), An intermediate layer (20) composed of 3C silicon carbide having a smaller band gap than the contact region (5) is provided.
[0006]
Thus, when the intermediate layer (20) composed of 3C silicon carbide having a small band gap is provided in the extraction portion, the energy barrier between the extraction electrode (12) and the intermediate layer (5) is small, The contact resistance between the extraction electrode (12) and the contact region (5) can be reduced as compared with the case where the layer (20) is not provided .
[0007]
Further, as shown in claim 2 , the intermediate layer (20) is composed of a plurality of layers, and the graded structure in which the band gap becomes smaller from the contact region (5) to the layer closer to the extraction electrode (12). In this case, since the energy barrier between the layers can be reduced, the contact resistance can be more effectively reduced. Specifically, co Ntakuto region (5) in the case constituted by silicon carbide. 4H, the layer closest to the electrode (12) is taken out of the intermediate layer (20) is constituted by a layer of 3C silicon carbide, A 6H silicon carbide layer may be formed between the silicon carbide layer and the contact region (5).
[0008]
As shown in the invention of claim 3 , the semiconductor substrate (1, 2, 3) constituted by the first semiconductor layer (3) of the second conductivity type made of hexagonal silicon carbide having a surface of 4H or 6H. A second semiconductor layer (20) made of 3C silicon carbide is formed thereon, and ion implantation is performed on the semiconductor substrate (1, 2, 3), so that the first semiconductor layer (3) and the second semiconductor layer ( If the first conductivity type contact region (5) is formed in the predetermined region 20), the lead-out portion of the contact region (5) can be formed of 3C silicon carbide. Thus, a silicon carbide semiconductor device having an effect similar to that of claim 1 can be formed.
[0009]
According to a fourth aspect of the present invention, after the first conductive type second semiconductor layer (20) made of 3C silicon carbide is formed on the main surface side of the semiconductor substrate (1, 2, 3), ion implantation is performed. Then, a first conductivity type contact region (5) is formed in a predetermined region of the second semiconductor layer (20) and the first semiconductor layer (3), and further ion implantation is performed, so that the second semiconductor layer (20) and it is also possible to form a second conductivity type semiconductor region (4) in the portion surrounding the contact region (5) of the first semiconductor layer (3).
[0010]
When the first conductive type second semiconductor layer (20) made of 3C silicon carbide is formed in this way and then the contact region (5) is formed by ion implantation, the contact region (5) can be taken out from the 3C. Therefore, the band gap can be reduced, and the same effect as in the first aspect can be obtained. Then, when the second semiconductor layer (20) is formed with the first conductivity type in this way, ion implantation is performed on a portion of the second semiconductor layer (20) around the contact region (5), If the semiconductor region (4) of the same second conductivity type as the high resistance layer (2) is used, the potential of the high resistance layer (2) can be fixed. In this case, since 3C silicon carbide is formed between the high resistance layer (2) and the extraction electrode (12), the contact resistance of the high resistance layer (2) can also be reduced.
[0011]
Further, as shown in claim 5 , the contact region (5) may be masked to remove the second semiconductor layer (20) around the contact region (5). That is, in between the electrode leading the high-resistance layer (2) (12), only has the purpose of potential fixing, for reducing the contact resistance is less important when the potential fixed contact as claimed in claim 4 Instead of changing the second semiconductor layer (20) around the region (5) to the second conductivity type, this portion is removed by etching so that the high resistance layer (2) and the extraction electrode (12) are in direct contact with each other. You can also
[0012]
Furthermore, as shown in claim 6 , if the second semiconductor layer (20) is previously formed of the second conductivity type, ion implantation or etching treatment is performed as in claims 4 and 5. Therefore, the number of steps can be simplified.
According to a seventh aspect of the invention, the ion implantation in the second step of the fourth to sixth aspects is performed so that the impurity concentration of the contact region (5) is 1 × 10 ¹⁹ cm ⁻³ or more. Yes.
[0013]
When the second semiconductor layer (20) made of 3C silicon carbide is formed on the surface of the first semiconductor layer (3), the doping level can be increased. Therefore, the contact region (5) can be formed with an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more, which has been difficult in the prior art, and the contact resistance can be more effectively reduced.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below.
(First embodiment)
FIG. 1 is a sectional view of an n-channel type vertical power MOSFET according to an embodiment of the present invention. Hereinafter, the structure of the vertical power MOSFET will be described with reference to FIG.
[0015]
Hexagonal (4H, 6H) to the n ⁺ -type silicon carbide semiconductor substrate 1 as a low-resistance semiconductor layer made of silicon carbide, n as a high-resistance semiconductor layer ^- type silicon carbide semiconductor layer 2 and the p ^- type silicon carbide semiconductor layer 3 and p ⁺ type silicon carbide semiconductor layer 4 are sequentially laminated. The p ⁺ type silicon carbide semiconductor region 4 is composed of 3C (cubic) silicon carbide at the top and hexagonal silicon carbide at the bottom.
[0016]
An n ⁺ type source region (contact region) 5 as a semiconductor region is formed in a predetermined region of the surface layer portion in p ⁻ type silicon carbide semiconductor layer 3. The n ⁺ -type source region 5 is composed of 3C silicon carbide at the top and hexagonal silicon carbide at the bottom.
A trench 7 is formed in a predetermined region of the n ⁺ type source region 5. This trench 7 penetrates through n ⁺ type source region 5 and p ⁻ type silicon carbide semiconductor layer 3 and reaches n ⁻ type silicon carbide semiconductor layer 2.
[0017]
A thermal oxide film 9 as a gate insulating film is formed on the entire upper surface of the wafer including the trench 7. A base electrode 10 made of polysilicon is formed on the channel forming portion in the groove 7, and an insulating film 11 is formed on the entire upper surface of the wafer including the gate electrode 10.
A source electrode 12 is formed on the insulating film 11, and the source electrode 12 is connected to the n ⁺ -type source region 5 and the p ⁺ -type silicon carbide semiconductor through a contact hole 13 formed in the thermal oxide film 9 and the insulating film 10. The region 4 is electrically connected.
[0018]
A drain electrode 14 is formed on the lower surface side of n ⁺ type silicon carbide semiconductor substrate 1.
When a predetermined driving voltage is applied to the gate electrode 10 in the vertical power MOSFET configured as described above, the p ⁻ type silicon carbide semiconductor layer 3 between the n ⁻ type silicon carbide semiconductor layer 2 and the n ⁺ type source region 5 is formed. It becomes a channel region and allows current to flow.
[0019]
At this time, as described above, since the upper part of the n ⁺ type source region 5 is made of 3C silicon carbide, the contact resistance between the source electrode 12 and the n ⁺ type source region 5 can be reduced. That is, as a method for reducing the contact resistance of the source electrode 12 and the n ⁺ -type source region 5, one can reduce the band gap of the n ⁺ -type source region 5 and one n ⁺ -type source region 5 It is conceivable to increase the doping level of 3C. However, since 3C silicon carbide can satisfy both of these, the contact resistance can be effectively reduced.
[0020]
FIG. 2 shows a band gap and the like at the contact portion between the source electrode 12 and the n ⁺ -type source region 5. However, in this figure, for reference, the lower portion of the n ⁺ -type source region 5 is shown in the case where both 6H silicon carbide and 4H silicon carbide are used. In the figure, Eg represents the band gap, and Ec and Ev represent the energy at the end of the conduction band and the end of the valence band, respectively.
[0021]
As shown in this figure, 3C silicon carbide has a smaller band gap than 6H silicon carbide or 4H silicon carbide, and when 4H or 6H silicon carbide is in direct contact with the metal constituting the extraction electrode. It can be seen that the energy barrier ΔEc at the extraction portion is lower when 3C silicon carbide is provided as an intermediate layer between them.
[0022]
For this reason, if the upper part of n ⁺ type source region 5 is made of 3C silicon carbide, the resistivity at the extraction portion is lower than when n ⁺ type source region 5 is formed only of 4H or 6H silicon carbide. You can see that you can.
As described above, since the doping level of 3C silicon carbide can be very high, the resistivity at the extraction portion can be further reduced.
[0023]
Further, as can be seen from this figure, the energy barrier ΔEc is smaller in 6H silicon carbide than in 4H silicon carbide. For this reason, when the n ⁻ type silicon carbide semiconductor layer 3 is formed of 4H silicon carbide, a 6H semiconductor layer is provided between the 4H n ⁻ type silicon carbide semiconductor layer 3 and the source region 5 of 3C, and energy By adopting a graded structure in which the barriers become smaller in order, the individual energy barriers can be made smaller, so that the contact resistance can be reduced more effectively.
[0024]
Next, a manufacturing method of the vertical power MOSFET having the above configuration will be described with reference to FIGS.
[Step shown in FIG. 3 (a)]
First, a low-resistance n ^{+ made} of hexagonal silicon carbide having a thickness of 400 μm and having a main surface with an off angle of 0 to 10 °, for example, an off angle of 8 °, with respect to the (0001−) carbon surface. A silicon carbide semiconductor substrate 1 is prepared. Then, n ⁻ type silicon carbide semiconductor layer 2 having a thickness of about 5.0 μm is epitaxially grown on the surface, and p ⁻ type silicon carbide semiconductor layer 3 having a thickness of about 2.5 μm is further formed on n ⁻ type silicon carbide semiconductor layer 2. Is epitaxially grown.
[0025]
At this time, since the main surface of n ⁺ type silicon carbide semiconductor substrate 1 has the above-described off angle, n ⁻ type silicon carbide semiconductor layer 2 and n ⁻ type silicon carbide semiconductor layer 3 have smooth surface shapes. Grows in state.
Next, crystal growth is performed while doping nitrogen ions in an atmosphere of SiH ₄ , C ₃ H ₈ , and H ₂ , and n made of 3C silicon carbide that is cubic on the p ⁻ -type silicon carbide semiconductor layer 3. ^- -type silicon carbide semiconductor layer 20. As growth conditions at this time, the SiC ratio and the temperature are determined based on the SiC ratio-temperature (° C.) characteristic diagram shown in FIG. In this characteristic diagram, the crystal structure of silicon carbide formed on the p ⁺ -type silicon carbide semiconductor layer 3 by changing the SiC ratio-temperature (° C.) condition under a pressure of 10.0 Torr was experimentally detected. In the figure, ◯ indicates that 3C silicon carbide, Δ indicates either 3C or hexagonal silicon carbide, and X indicates that hexagonal silicon carbide is formed.
[0026]
Further, as indicated by arrows in this figure, the crystal accuracy of 3C silicon carbide is better as the temperature is higher, and the surface shape is better as the SiC ratio is lower. Therefore, in consideration of these, it is desirable that n ⁺ -type silicon carbide semiconductor layer 20 be formed of 3C silicon carbide in a better crystalline state. Note that, under the condition where the SiC ratio is about 0.2 and the temperature is about 1400 ° C. (the portion indicated by Δ in the figure), either 3C or hexagonal crystal is formed. The structure is accurately determined because the gas amount and pressure are related in addition to the SiC ratio and temperature. Therefore, by changing these parameters, 3C silicon carbide can be surely formed. . For this reason, n ⁺ type silicon carbide semiconductor layer 20 can also be formed in a good crystalline state even under the above conditions.
[0027]
The n ⁻ -type silicon carbide semiconductor layer 20 made of 3C silicon carbide thus formed finally becomes the extraction portion, and the contact resistance of the extraction portion can be reduced by utilizing the characteristics of 3C silicon carbide. For reference, the portion made of 3C silicon carbide is also indicated by the same mark as in this figure in the subsequent drawings.
By the way, it is considered that the n ⁻ -type silicon carbide semiconductor layer 3 may be formed from 3C silicon carbide from the beginning if the contact resistance in the extraction portion is reduced. However, cubic silicon carbide cannot be formed with a desired thickness on n ⁺ type silicon carbide semiconductor substrate 1 made of hexagonal silicon carbide. Therefore, as in this embodiment, the n ⁻ -type silicon carbide semiconductor layer 20 made of 3C silicon carbide is formed only in the portion where the extraction electrode contacts.
[0028]
Thus, n ⁺ -type silicon carbide semiconductor substrate 1 on which is formed the n ^- -type silicon carbide semiconductor layer 3 Daburuepi on consisting of, consisting further 3C silicon carbide n ^{- -} type silicon carbide semiconductor layer 2 and the p type A wafer provided with silicon carbide semiconductor layer 20 is formed.
[Step shown in FIG. 3B]
A mask material 21 made of LTO laminated on the wafer is formed, and nitrogen (N ₂ ) ions are implanted at a dose of 8 × 10 ¹⁵ cm ⁻² at a temperature of 700 ° C. Thereby, n ⁺ type source region 5 is formed in a predetermined region of the surface layer portion of n ⁻ type silicon carbide semiconductor layer 20 and p ⁻ type silicon carbide semiconductor layer 3. Therefore, the upper part of n ⁺ type source region 5 is formed of 3C silicon carbide and the lower part is formed of hexagonal silicon carbide. Thereafter, annealing is performed at 1300 ° C. for 10 seconds.
[0029]
[Step shown in FIG. 3 (c)]
After removing the mask material 21, the surface of the n ⁺ -type source region 5 is again covered with the mask material 22, and aluminum ions are implanted at a dose of 2 × 10 ¹⁶ cm ⁻² at a temperature of 700 ° C. That is, as described above, since the surface layer when implanting aluminum ions is the n ⁺ type silicon carbide semiconductor layer 20 made of 3C silicon carbide, the dose of aluminum ions can be increased. In this case, the impurity concentration is reduced. It can be as high as 1 × 10 ²¹ cm ⁻³ . For this reason, the contact resistance in the extraction part can be reduced.
[0030]
In this manner, p ⁺ type silicon carbide semiconductor region 4 is formed in the surface layer portions of n ⁻ type silicon carbide semiconductor layer 20 and p ⁻ type silicon carbide semiconductor layer 3 around n ⁺ type source region 5. Therefore, as described above, the upper portion of p ⁺ type silicon carbide semiconductor region 4 is formed of 3C silicon carbide and the lower portion is formed of cubic silicon carbide. Thereafter, annealing is performed at 1300 ° C. for 10 seconds.
[0031]
[Step shown in FIG. 4 (a)]
After the Si ₃ N ₄ film 23 is formed on the entire wafer surface, a mask material 24 made of LTO is formed on the Si ₃ N ₄ film 23. In the Si ₃ N ₄ film 23 and the mask material 24, dry etching is performed by the RIE method using CF ₄ and O ₂ gas atmosphere with the central portion of the n ⁺ -type source region 5 being opened. As a result, a trench 7 that penetrates n ⁺ type source region 5 and p ⁻ type silicon carbide semiconductor layer 3 and reaches n ⁻ type silicon carbide semiconductor layer 2 is formed.
[0032]
[Step shown in FIG. 4B]
A sacrificial oxide film 25 is formed on the entire surface of the groove 7 by heat treatment at about 1080 ° C. for 4 hours. By forming the sacrificial oxide film 25, the surface shape of the groove 7 can be improved.
[Step shown in FIG. 4 (c)]
After removing the Si ₃ N ₄ film 23 and the mask material 24, heat treatment is performed at about 1080 ° C. for 4 hours to form an oxide film 25 on the entire wafer surface. The sacrificial oxide film and the oxide film 25 thus formed serve as the thermal oxide film 9 as the gate oxide film described above.
[0033]
[Step shown in FIG. 5A]
A polysilicon layer is stacked on the semiconductor substrate 100, and a gate electrode 10 is formed on the surface of the thermal oxide film 9 in the groove 7 by photo-etching. Since gate electrode 10 is used to form p ⁻ type silicon carbide semiconductor layer 3 between source region 5 and n ⁻ type silicon carbide semiconductor layer 2 as a channel region, at least p ⁻ type silicon carbide semiconductor layer 3 A gate electrode 10 is formed thereon.
[0034]
[Step shown in FIG. 5B]
An insulating film 11 made of LTO is formed on the upper surface of the gate electrode layer 10 by vapor deposition (for example, chemical vapor deposition).
[Step shown in FIG. 5 (c)]
Contact holes communicating with the n ⁺ -type source region 5 and the p ⁺ -type silicon carbide semiconductor region 4 are selectively formed in predetermined regions of the insulating film 11 and the thermal oxide film 9 by photo-etching. Thereafter, a source electrode 12 made of, for example, Ni is formed on the surfaces of the n ⁺ type source region 5 and the p ⁺ type silicon carbide semiconductor layer 4 including the insulating film 11. Further, a drain electrode 13 made of, for example, Ni is formed on the back side of the n ⁺ type silicon carbide semiconductor substrate 1. Thereby, the vertical power MOSFET having the configuration shown in FIG. 1 is completed.
[0035]
As described above, the vertical power MOSFET thus completed is made of n ⁺ silicon carbide, which has a band gap smaller than that of 6H silicon carbide or 4H silicon carbide and can increase the doping level. Since the intermediate layer is disposed between the type source region 5 and the hexagonal p ⁻ type silicon carbide semiconductor layer 3, the contact resistance at the extraction portion is very low.
[0036]
(Second Embodiment)
FIG. 7 shows a method for manufacturing the vertical power MOSFET in the second embodiment. In the present embodiment, only parts different from the manufacturing method of the vertical power MOSFET in the first embodiment will be described, and the same steps will be omitted.
In the present embodiment, the process of FIG. 7 is performed instead of the process of FIG. 3C of the first embodiment. In the first embodiment, in order to change the conductivity type of the n ⁻ type silicon carbide semiconductor layer 20 around the n ⁺ type source region 5 from N type to P type, ion implantation of aluminum ions is performed. In the embodiment, the n ⁻ type silicon carbide semiconductor layer 20 around the n ⁺ type source region 5 is removed by etching.
[0037]
Originally, the ion implantation is performed by changing the conductivity type of the n ⁻ -type silicon carbide semiconductor layer 20 around the n ⁺ -type source region 5 from N-type to P-type so that the p ⁻ -type silicon carbide semiconductor layer 3 becomes the source electrode 12. This is done in order to fix the potential by making contact. However, since it is not necessary to reduce the contact resistance in order to fix this potential, it is not necessary to intervene 3C silicon carbide as an intermediate layer in this portion. For this reason, n ⁻ type silicon carbide semiconductor layer 20 having N type conductivity is removed by etching, so that source electrode 12 and p ⁻ type silicon carbide semiconductor layer 3 are in direct contact with each other.
[0038]
As described above, the intermediate layer made of 3C silicon carbide may be formed only on the surface layer portion of the n ⁺ -type source region 5, and the above effect can be obtained even if the intermediate layer is not formed in other portions. Can do.
After this step, the vertical power MOSFET can be completed by performing the steps of FIGS. 4 and 5 as in the first embodiment. In this case, the vertical power MOSFET has no p ⁺ type silicon carbide region 4 as compared with FIG.
[0039]
(Third embodiment)
FIG. 8 shows a method of manufacturing the vertical power MOSFET in the second embodiment. In the present embodiment, only parts different from the manufacturing method of the vertical power MOSFET in the first embodiment will be described, and the same steps will be omitted.
In this embodiment, instead of the steps of FIGS. 3A and 3B of the first embodiment, the steps of FIGS. 8A and 8B are performed.
[0040]
[Step shown in FIG. 8 (a)]
First, as in the first embodiment, the n ⁻ type silicon carbide semiconductor layer 2 and the p ⁻ type silicon carbide semiconductor layer 3 are epitaxially grown in this order on the surface of the n ⁺ type silicon carbide semiconductor substrate 1. Thereafter, p ⁺ type silicon carbide semiconductor layer 20 ′ is formed on p ⁻ type silicon carbide semiconductor layer 3 instead of n ⁺ type silicon carbide semiconductor layer 20. Specifically, the atmosphere and temperature conditions are the same as in the first embodiment, and the ions to be implanted are changed to those in the first embodiment to form aluminum ions, thereby forming the p ⁺ type silicon carbide semiconductor layer 20 ′.
[0041]
[Step shown in FIG. 8B]
Next, nitrogen ions are implanted under the same temperature conditions as in the first embodiment. At this time, the dose of nitrogen ions is 8 × 10 ¹⁵ cm ⁻² plus the dose of aluminum ions implanted into the p-type silicon carbide semiconductor layer 20 ′. Thereafter, similarly to the first embodiment, the vertical power MOSFET is formed through the processes after FIG.
[0042]
In this way, by forming an intermediate layer made of 3C silicon carbide with a P-type conductor called p-type silicon carbide semiconductor layer 20 ', the n ⁺ -type is formed as in the first and second embodiments. The step of implanting aluminum ions into the portion around the source region 5 and the step of etching away 3C silicon carbide in this portion can be omitted. Thereby, the number of processes necessary for manufacturing the vertical power MOSFET can be simplified.
[0043]
At this time, since the main surface of n ⁺ type silicon carbide semiconductor substrate 1 has the above-described off angle, n ⁻ type silicon carbide semiconductor layer 2 and n ⁻ type silicon carbide semiconductor layer 3 have smooth surface shapes. Grows in state.
In the above embodiment, the source region 5 of the vertical power MOSFET has been described. However, the present invention can be applied not only to the source region 5 but also to a portion where the silicon carbide semiconductor region and the metal electrode are contacted.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a vertical power MOSFET according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining the size of a band gap when 3C silicon carbide is used.
3 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 1. FIG.
4 is a diagram showing manufacturing steps of the vertical power MOSFET subsequent to FIG. 3. FIG.
5 is a diagram showing the manufacturing process of the vertical power MOSFET subsequent to FIG. 4. FIG.
FIG. 6 is an explanatory diagram showing SiC ratio-temperature characteristics.
FIG. 7 is a diagram showing a manufacturing process of the vertical power MOSFET in the second embodiment.
FIG. 8 is a diagram showing a manufacturing process of the vertical power MOSFET in the third embodiment.
[Explanation of symbols]
1 ... n ⁺ type silicon carbide semiconductor substrate, 2 ... n ^- type silicon carbide semiconductor layer,
3 ... p ^- type silicon carbide semiconductor layer, 4 ... p ⁺ type semiconductor region, 5 ... source region,
7 ... groove, 9 ... thermal oxide film, 10 ... gate electrode, 11 ..., insulating film,
12 ... Source electrode, 13 ... Contact hole, 14 ... Drain electrode,
20... N ⁻ type silicon carbide semiconductor layer.

Claims (7)

Via a contact hole (13) having a contact region (5) made of 4H or 6H hexagonal silicon carbide and penetrating an insulating film (9, 11) formed on the upper surface of the contact region (5). In the silicon carbide semiconductor device formed by electrically connecting the extraction electrode (12) formed on the insulating film (9, 11) and the contact region (5),
3C silicon carbide having the same conductivity type as the contact region (5) and having a smaller band gap than the contact region (5) between the contact region (5) and the extraction electrode (12). A silicon carbide semiconductor device, characterized in that a configured intermediate layer (20) is provided. Via a contact hole (13) having a contact region (5) made of 4H or 6H hexagonal silicon carbide and penetrating an insulating film (9, 11) formed on the upper surface of the contact region (5). In the silicon carbide semiconductor device formed by electrically connecting the extraction electrode (12) formed on the insulating film (9, 11) and the contact region (5),
Between the contact region (5) and the extraction electrode (12), an intermediate layer (20) having the same conductivity type as the contact region (5) and having a smaller band gap than the contact region (5) The intermediate layer (20) is composed of a plurality of layers, and the band gap becomes smaller from the contact region (5) to the layer closer to the extraction electrode (12). ,
The contact region (5) is made of 4H silicon carbide;
Of the intermediate layer (20) formed of the plurality of layers, the layer closest to the extraction electrode (12) is composed of a 3C silicon carbide layer. The silicon carbide layer and the contact region (5) A silicon carbide semiconductor device comprising a 6H silicon carbide layer in between. On the semiconductor substrate (1, 2, 3) composed of the second conductivity type first semiconductor layer (3) made of silicon carbide having a surface of 4H or 6H, the second semiconductor layer (20 made of 3C silicon carbide) A first step of forming
A second step of forming a first conductivity type contact region (5) in a predetermined region of the first semiconductor layer (3) and the second semiconductor layer (20) by performing ion implantation;
A third step of forming an insulating film (9, 11) on the semiconductor substrate (1, 2, 3);
A fourth step of forming a contact hole (13) communicating with the contact region (5) in a predetermined region of the insulating film (9, 11);
And a fifth step of forming an extraction electrode (12) electrically connected to the contact region (5) through the contact hole (13) on the insulating film (9, 11). An apparatus for manufacturing a silicon carbide semiconductor device. On the first resistance type low resistance layer (1), a first resistance type high resistance layer (2) having a higher resistance than the low resistance layer (1) is formed, and on the high resistance layer (2). A semiconductor substrate (1, 2, 3) having a main surface of the first semiconductor layer (3), which is formed by forming a second semiconductor layer (3) of the second conductivity type made of 4H or 6H silicon carbide. A first step of forming a second semiconductor layer (20) of the first conductivity type made of 3C silicon carbide on the main surface side of
A second step of forming a first conductivity type contact region (5) in a predetermined region of the second semiconductor layer (20) and the first semiconductor layer (3) by performing ion implantation;
Ion implantation is performed to form a second conductivity type semiconductor region (4) in a portion of the second semiconductor layer (20) and the first semiconductor layer (3) around the contact region (5). 3 steps,
A fourth step of forming a groove (7) extending from the main surface through the contact region (5) and the first semiconductor layer (3) to reach the high resistance layer (2);
A fifth step of forming a first insulating film (9) on the surface of the second semiconductor layer (20) including the groove (7);
The first semiconductor layer (3) between the high resistance layer (2) and the contact region (5) is used as a channel region, and at least on the channel region, a gate electrode is interposed through the first insulating film (9). A sixth step of forming (10);
A seventh step of forming a second insulating film (11) on the semiconductor substrate (1, 2, 3) including the gate electrode (10);
An eighth step of forming a contact hole (13) communicating with the contact region (5) and the semiconductor region (4) in a predetermined region of the first and second insulating films (9, 11);
A ninth step of forming, on the first and second insulating films (9, 11), an extraction electrode (12) electrically connected to the contact region (5) through the contact hole (13); A method for manufacturing a silicon carbide semiconductor device, comprising: On the first resistance type low resistance layer (1), a first resistance type high resistance layer (2) having a higher resistance than the low resistance layer (1) is formed, and on the high resistance layer (2). A semiconductor substrate (1, 2, 3) having a main surface of the first semiconductor layer (3), which is formed by forming a second semiconductor layer (3) of the second conductivity type made of 4H or 6H silicon carbide. A first step of forming a second semiconductor layer (20) of the first conductivity type made of 3C silicon carbide on the main surface side of
A second step of forming a first conductivity type contact region (5) in a predetermined region of the second semiconductor layer (20) and the first semiconductor layer (3) by performing ion implantation;
A third step of exposing the first semiconductor layer (3) by removing the second semiconductor layer (20) around the contact region (5) while masking the contact region (5);
A fourth step of forming a groove (7) extending from the main surface through the contact region (5) and the first semiconductor layer (3) to reach the high resistance layer (2);
A fifth step of forming a first insulating film (9) on the surface of the second semiconductor layer (20) including the groove (7);
The first semiconductor layer (3) between the high resistance layer (2) and the contact region (5) is used as a channel region, and at least on the channel region, a gate electrode is interposed through the first insulating film (9). A sixth step of forming (10);
A seventh step of forming a second insulating film (11) on the semiconductor substrate (1, 2, 3) including the gate electrode (10);
An eighth step of forming a contact hole (13) communicating with the contact region (5) and the high resistance layer (2) in a predetermined region of the first and second insulating films (9, 11);
A ninth step of forming, on the first and second insulating films (9, 11), an extraction electrode (12) electrically connected to the contact region (5) through the contact hole (13); A method for manufacturing a silicon carbide semiconductor device, comprising: On the first resistance type low resistance layer (1), a first resistance type high resistance layer (2) having a higher resistance than the low resistance layer (1) is formed, and on the high resistance layer (2). A semiconductor substrate (1, 2, 3) having a main surface of the first semiconductor layer (3), which is formed by forming a second semiconductor layer (3) of the second conductivity type made of 4H or 6H silicon carbide. A first step of forming a second semiconductor layer (20) of the second conductivity type made of 3C silicon carbide on the main surface side of
A second step of forming a first conductivity type contact region (5) in a predetermined region of the second semiconductor layer (20) and the first semiconductor layer (3) by performing ion implantation;
A third step of forming a groove (7) extending from the main surface through the contact region (5) and the first semiconductor layer (3) to reach the high resistance layer (2);
A fourth step of forming a first insulating film (9) on the surface of the second semiconductor layer (20) including the groove (7);
The first semiconductor layer (3) between the high resistance layer (2) and the contact region (5) is used as a channel region, and at least on the channel region, a gate electrode is interposed through the first insulating film (9). A fifth step of forming (10);
A sixth step of forming a second insulating film (11) on the semiconductor substrate (1, 2, 3) including the gate electrode (10);
A seventh step of forming a contact hole (13) communicating with the contact region (5) in a predetermined region of the first and second insulating films (9, 11);
An eighth step of forming, on the first and second insulating films (9, 11), an extraction electrode (12) that is electrically connected to the contact region (5) through the contact hole (13); A method for manufacturing a silicon carbide semiconductor device, comprising: Wherein the ion implantation in the second step, according to any one of claims 3 to 6 impurity concentration of the contact region (5) and performs so as to 1 × 10 ¹⁹ cm ^-3 or more A method for manufacturing a silicon carbide semiconductor device.

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