JP3742075B2 - External storage subsystem - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an external storage subsystem, and more particularly to a technique effective when applied to improving the reliability of an external storage subsystem having a cache function.
[0002]
[Prior art]
For example, in a magnetic disk subsystem used as an external storage device in a general-purpose electronic computer system or the like, the rotation in the magnetic disk device can be performed by interposing a known cache memory such as a semiconductor memory in a part of the disk control device. A technique for avoiding a decrease in data transfer rate due to a mechanical factor such as waiting as much as possible is known.
[0003]
Regarding such a cache structure in the disk controller, A Multiport Page-memory Architecture and A Multiport Disc-Cache System (New Generation Computing 2 (1984) 241-260 OHMSHA.LTD. And Spring). As described above, a method for improving the access performance to the cache by dividing the memory bank into a plurality of memory banks has been studied. Furthermore, a switch network called Interconnection Network has been proposed as a method for coupling a plurality of memory banks and channels or disk control devices.
[0004]
[Problems to be solved by the invention]
The above prior art aims to improve the cache function by providing a plurality of memory banks and a switch network. Regarding the data bus structure inside the disk control device, a switch network system called Interconnection Network is considered. Has been. However, when implementing a data bus configuration that exchanges data by connecting multiple memory banks and multiple channel units or multiple control units, the switch network method is subject to hardware design constraints. There was a problem.
[0005]
Further, there is no mention of multiplexing of cache units constituted by memory banks.
[0006]
SUMMARY OF THE INVENTION An object of the present invention is to consider a constraint such as a data transfer rate on hardware and a data bus width, and a plurality of cache units and a plurality of channel units on the host device side, or a rotary storage device It is to realize a data bus structure that connects a plurality of control units on the side.
[0007]
Another object of the present invention is to provide an external storage subsystem having a cache function that has a high tolerance to failures and a high reliability.
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
[0010]
That is, the external storage subsystem of the present invention includes a rotary storage device that stores data accessed from a host device, and at least one of a permanent semiconductor memory and a non-endurance semiconductor memory as a storage medium, In an external storage subsystem including an external storage control device having a cache mechanism that responds to an access request to a rotary storage device from a host device by temporarily holding data exchanged with the host device A plurality of cache mechanisms independent from each other, and a plurality of independent access paths that enable independent access from the host device and the rotary storage device to each of the plurality of cache mechanisms. is there.
[0011]
The external storage subsystem according to the present invention is the external storage subsystem according to claim 1, wherein the external storage control device includes a plurality of channel units for controlling data exchange with a host device, and a rotary storage device. A plurality of control units that control data exchange with the device, and each of the channel unit and the control unit includes a plurality of first access paths to which a plurality of cache mechanisms are independently connected. It is what I did.
[0012]
The external storage subsystem according to the present invention is the external storage subsystem according to claim 1, wherein data is transferred between a plurality of channel units that control data exchange with a host device and a rotary storage device. A plurality of control units for controlling the exchange of data, and each of the plurality of cache mechanisms includes a plurality of second access paths to which each of the plurality of channel units and the control unit is connected. It is.
[0013]
The external storage subsystem according to the present invention is the external storage subsystem according to claim 1, wherein data is transferred between a plurality of channel units that control data exchange with a host device and a rotary storage device. And a plurality of control units that control the transfer of data, and a plurality of third access paths independent of the channel unit, the control unit, and the plurality of cache mechanisms are provided. A plurality of channel units, a control unit, and a plurality of cache mechanisms are individually connected.
[0014]
The external storage subsystem according to the present invention is the external storage subsystem according to claim 1, wherein data is transferred between a plurality of channel units that control data exchange with a host device and a rotary storage device. A plurality of control units for controlling the transfer of data, and a fourth access path for directly and independently connecting each of the individual channel units and controls and each of the plurality of cache mechanisms. It is.
[0015]
According to the external storage subsystem of the present invention described above, the cache units are multiplexed, and the access paths by the host device and the rotary storage device for each cache unit are independent, so that a plurality of cache units are provided. By combining this cache unit with a plurality of channel units or a plurality of control units, the data transfer rate, data bus width, etc. can be optimally configured.
[0016]
In addition, since the cache unit and the access path to the cache unit are multiplexed, there is a high probability that the cache function can be maintained even in the event of a failure, and the tolerance and reliability against failure of the external storage subsystem are ensured. To improve.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Example 1
Hereinafter, an example of an external storage subsystem according to an embodiment of the present invention will be described with reference to the drawings.
[0018]
As illustrated in FIG. 1, the computer system of this embodiment is composed of a central processing unit (CPU) 1 and a disk subsystem. The disk subsystem is composed of a disk control device 2 and a magnetic disk device 3.
[0019]
The CPU 1 and the disk control device 2 are connected via a plurality of channel interfaces 4, and the disk control device 2 and the magnetic disk device 3 are connected via a plurality of control interfaces 5.
[0020]
The CPU 1 issues an access command to the disk controller 2 via the channel interface 4, and the disk controller 2 controls the magnetic disk device 3 via the control interface 5 in accordance with a command from the CPU 1. Data read or write control is performed.
[0021]
In the disk controller 2, a plurality of channel units 60 and channel units 61 operating under the control of the channel control processor 110 and the channel control processor 111 are provided on the connection side of the channel interface 4. 5 is provided with a control unit 70 and a control unit 71 operating under the control unit control processor 120 and the control unit control processor 121.
[0022]
Instructions issued from the CPU 1 to the disk control device 2 are received by the channel units 60 and 61, decoded by the channel control processors 110 and 111, and control unit control necessary for controlling the magnetic disk device 3. The control unit control processors 120 and 121 control the magnetic disk device 3 via the control units 70 and 71.
[0023]
In the disk controller 2, two independent cache units 80 and 81, which temporarily store data using a semiconductor memory (not shown) as a storage medium, and two independent nonvolatile memory units that are also mutually independent 90 and a non-volatile memory unit 91 are provided. The non-volatile memory units 90 and 91 are rewritable memories and have the ability to hold data for a certain period of time regardless of the presence or absence of external power supply.
[0024]
The capacity of each of the cache units 80 and 81 is set to a value that enables a sufficient cache operation according to the storage capacity of the magnetic disk device 3, for example. Similarly, the capacity of each of the non-volatile memory units 90 and 91 is set to a value that enables a sufficient cache operation in accordance with the storage capacity of the magnetic disk device 3, for example.
[0025]
In this case, the channel unit 60 is provided with a plurality of mutually independent data buses 60A and 60B. On the data bus 60A side, a cache unit 80 is connected via an access line 80a, and a nonvolatile memory unit 91 is independently connected via an access line 91a. On the data bus 60B side, a cache unit 81 is connected via an access line 81a, and a nonvolatile memory unit 90 is connected via an access line 90a.
[0026]
Similarly, the channel unit 61 is provided with a plurality of mutually independent data buses 61A and data buses 61B. A cache unit 80 is connected to the data bus 61A via an access line 80c, and a nonvolatile memory unit 91 is connected to the data bus 61A via an access line 91c. On the data bus 61B side, a cache unit 81 is connected via an access line 81c, and a nonvolatile memory unit 90 is connected via an access line 90c.
[0027]
The control unit 70 is provided with a plurality of mutually independent data buses 70A and data buses 70B. A cache unit 80 is connected to the data bus 70A through an access line 80b, and a nonvolatile memory unit 91 is connected through an access line 91b. On the data bus 70B side, a cache unit 81 is connected via an access line 81b, and a nonvolatile memory unit 90 is connected via an access line 90b.
[0028]
Similarly, the control unit 71 is provided with a plurality of mutually independent data buses 71A and data buses 71B. A cache unit 80 is connected to the data bus 71A via an access line 80d, and a nonvolatile memory unit 91 is connected via an access line 91d. On the data bus 71B side, a cache unit 81 is connected via an access line 81d, and a nonvolatile memory unit 90 is connected via an access line 90d.
[0029]
That is, in the configuration of the present embodiment, both the channel units 60 and 61 and the control units 70 and 71 access the cache units 80 and 81 and the nonvolatile memory units 90 and 91 through paths independent of each other. Is possible.
[0030]
Hereinafter, an example of the operation of the external storage subsystem of this embodiment will be described.
[0031]
The write data sent from the CPU 1 to the disk controller 2 is temporarily stored in either the channel unit 60 or 61 and the data buses 60A, 60B, 61A, 61B according to the instruction of the channel control processor 110 or 111. Are stored in either one of the two cache units 80 or 81 and the nonvolatile memory unit 90 or 91. Thereafter, the data is read from either the cache unit 80 or 81 or the nonvolatile memory unit 90 or 91 according to the instruction of the control unit control processor 120 or 121, and the data buses 70A to 71B and the control unit 70 are read. Alternatively, write data is stored in the magnetic disk device 3 via 71.
[0032]
On the other hand, the channel control processor 110 or 111 that has received the data read request from the CPU 1 through the channel unit 60 or 61 examines the contents of the two cache units 80 or 81 and the nonvolatile memory unit 90 or 91. When there is data requested by the CPU 1, read data from the cache unit 80 or 81 or the nonvolatile memory unit 90 or 91 is sent to the CPU 1 via any one of the data buses 60 A to 61 B and the channel unit 60 or 61. send.
[0033]
When the data requested by the CPU 1 does not exist in the two cache units 80 or 81 and the nonvolatile memory unit 90 or 91, the channel control processor 110 or 111 reads the data from the magnetic disk device 3 as a control unit. Tell the control processor 120 or 121. The control unit control processor 120 or 121 having received the data read request from the channel control processor 110 or 111 sends the request data read from the magnetic disk device 3 to the control unit 70 or 71 and the data buses 70A to 71B. Through the cache unit 80 or 81.
[0034]
The channel control processor 110 or 111 receiving the read data storage completion report from the control unit control processor 120 or 121 to the cache unit 80 or 81 reports the data preparation completion to the CPU 1 and caches the read data according to the instruction of the CPU 1 Read data is sent from the unit 80 or 81 to the CPU 1 via the data buses 60A to 61B and the channel unit 60 or 61.
[0035]
FIG. 2 shows data buses 60A to 71B connecting between the channel units 60 and 61 or the control units 70 and 71 and the plurality of cache units 80 and 81 or the nonvolatile memory units 90 and 91 in the disk controller 2. Represents the signal configuration. In this embodiment, the channel units 60 and 61 or the control units 70 and 71 perform a master operation for the cache units 80 and 81 and the nonvolatile memory units 90 and 91. The cache units 80 and 81 or the nonvolatile memory units 90 and 91 perform a slave operation with respect to the channel units 60 and 61 or the control units 70 and 71.
[0036]
The channel units 60 and 61 or the control units 70 and 71 select the two cache units 80 and 81 or the nonvolatile memory units 90 and 91 by driving the SEL <0-1> signal line. The channel units 60 and 61 or the control units 70 and 71 are connected to the DTOUT / * DTIN signal line and the CMD / * DTIN signal line when the cache units 80 and 81 or the nonvolatile memory units 90 and 91 are selected. The state of the data buses 60A to 71B is designated by the combination of signals illustrated in FIG. According to the data bus protocol shown in FIG. 3, read data, write data, between the channel units 60 and 61 or the control units 70 and 71 and the cache units 80 and 81 or the nonvolatile memory units 90 and 91, Exchange commands and status.
[0037]
Thus, in the external storage subsystem of this embodiment, a plurality of cache units 80 and 81 and non-volatile memory units 90 and 91 are provided independently of each other, and the channel on the central processing unit 1 side Access to the plurality of cache units 80 and 81 and the non-volatile memory units 90 and 91 from the units 60 and 61 and the control units 70 and 71 side of the magnetic disk device 3 is performed by the plurality of data buses 60A to 71B. In addition, since the access lines 80a to 80d, the access lines 81a to 81d, the access lines 90a to 90d, and the access lines 91a to 91d can be performed independently, the data on each data bus or access line Benefits such as optimal transfer speed and data bus width There is.
[0038]
Also, one of the plurality of cache units 80 and 81 and the nonvolatile memory units 90 and 91, or a plurality of data buses 60A to 71B, access lines 80a to 80d, access lines 81a to 81d, and access lines Even if a failure occurs in any of 90a to 90d, access lines 91a to 91d, etc., the cache function can be maintained, and the tolerance to failure and the reliability of operation are reliably improved.
[0039]
(Example 2)
FIG. 5 is a block diagram showing an example of the configuration of an external storage subsystem according to another embodiment of the present invention.
[0040]
In the case of the second embodiment, each of the plurality of cache units 80 and 81 and the nonvolatile memory units 90 and 91 includes a plurality of data buses 80A, data bus 80B and data bus 81A, data. A bus 81B, a data bus 90A, a data bus 90B, a data bus 91A, and a data bus 91B are provided. For each of these data buses, channel units 60 and 61 and control units 70 and 71 are provided. Access lines 60a to 60d, access lines 61a to 61d, access lines 70a to 70d, and access lines 71a to 71d are connected independently of each other.
[0041]
Also in this case, the same effect as in the first embodiment can be obtained.
[0042]
Example 3
FIG. 6 is a block diagram showing an example of the configuration of an external storage subsystem according to still another embodiment of the present invention.
[0043]
In the case of the third embodiment, two common data buses 200A and 200B are provided. For each of them, the channel unit 60 is connected via an access line 60e and an access line 60f, and the channel unit 61 is connected via an access line 61e and an access line 61f. Are connected via access line 70e and access line 70f, control unit 71 is connected via access line 71e and access line 71f, and cache unit 80 is connected via access line 80e and access line 80f. The cache unit 81 is connected via an access line 81e and an access line 81f, the nonvolatile memory unit 90 is connected via an access line 90e and an access line 90f, and the nonvolatile memory unit 91 is connected to an access line 91e and access line 91f, respectively Is obtained so as to be connected to the stand.
[0044]
Also in this case, the same effects as those of the above embodiments can be obtained.
[0045]
(Example 4)
FIG. 7 is a block diagram showing an example of the configuration of an external storage subsystem according to still another embodiment of the present invention.
[0046]
In the case of the fourth embodiment, a cache unit group 800 including a plurality of cache units, a cache unit group 801, and a nonvolatile memory unit group 900 each including a plurality of nonvolatile memory units. , And the cache unit groups 800 and 801 and the nonvolatile memory unit groups 900 and 901 are grouped into data buses 60g to 60j, data buses 61g to 61j, and data bus 70g. ˜70j, connected to the channel unit 60, the channel unit 61, the control unit 70, and the control unit 71 via the data buses 71g˜71j.
[0047]
Also in this case, the same effects as those of the above embodiments can be obtained.
[0048]
The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor.
[0049]
【The invention's effect】
Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0050]
According to the external storage subsystem of the present invention, a plurality of cache units, a plurality of channel units on the host device side, and a plurality on the rotary storage device side in the external storage subsystem including the rotary storage device are provided. A simple structure can be connected to each control unit. Therefore, there is an effect of improving the cache function / performance in the disk controller.
[0051]
In addition, according to the external storage subsystem of the present invention, since both the cache unit and the access path to the cache unit are multiplexed, a fault tolerance is good and a highly reliable cache function is realized. The effect that it can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of the configuration of an external storage subsystem according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram illustrating an example of a signal configuration of a data bus connecting a channel unit or control unit and a plurality of cache units or nonvolatile memory units in the disk control device.
FIG. 3 shows an example of a data bus protocol for exchanging read data, write data, commands, and status between a channel unit or control unit and a cache unit or a nonvolatile memory unit. It is a conceptual diagram.
FIG. 4 is an explanatory diagram showing an example of a data bus mode for designating a data bus state;
FIG. 5 is a block diagram showing an example of the configuration of an external storage subsystem according to another embodiment of the present invention.
FIG. 6 is a block diagram showing an example of the configuration of an external storage subsystem according to still another embodiment of the present invention.
FIG. 7 is a block diagram showing an example of the configuration of an external storage subsystem according to still another embodiment of the present invention.
[Explanation of symbols]
1 Central processing unit (CPU) (host device)
2 Disk controller (external storage controller)
3 Magnetic disk unit (rotary storage device)
4 Channel interface 5 Control interface 60 Channel units 60a-60d Access lines 60e, 60f Access lines 60g-60j Data bus (fourth access path)
60A, 60B data bus (first access route)
61 Channel units 61a to 61d Access lines 61e and 61f Access lines 61g to 61h Data bus (fourth access path)
61A, 61B Data bus (first access route)
70 Control units 70a to 70d Access lines 70e and 70f Access lines 70g to 70j Data bus (fourth access path)
70A, 70B Data bus (first access path)
71 Control units 71a to 71d Access lines 71e and 71f Access lines 71g to 71j Data bus (fourth access path)
71A, 71B Data bus (first access path)
80 cash units (cache mechanism)
80a to 80d Access lines 80e and 80f Access lines 80A and 80B Data bus (second access path)
81 Cache unit (cache mechanism)
81a to 81d Access lines 81e and 81f Access lines 81A and 81B Data bus (second access path)
90 Nonvolatile memory unit (cache mechanism)
90a to 90d Access lines 90e and 90f Access lines 90A and 90B Data bus (second access path)
91 Nonvolatile memory unit (cache mechanism)
91a to 91d Access lines 91e and 91f Access lines 91A and 91B Data bus (second access path)
110, 111 Channel control processor 120, 121 Control unit control processor 200A, 200B Common data bus (third access path)
800, 801 Cache unit group 900, 901 Nonvolatile memory unit group

Claims (12)

A rotary storage device for storing data accessed from the host device;
A channel mechanism for transferring data transmitted from the host device and transferring the data to the host device; and at least one of a permanent semiconductor memory and a non-endurance semiconductor memory as the storage medium, the rotary storage device and the A cache mechanism that responds to an access request to the rotary storage device from the host device by temporarily holding the data exchanged with the host device, and is connected to the cache mechanism, and the cache mechanism An external storage control device having a control mechanism for transferring data to and receiving data sent from the host device from the cache mechanism ;
An external storage subsystem comprising:
A plurality of cache mechanisms independent of each other, and a plurality of independent access paths that allow independent access from each of the plurality of cache mechanisms from a single channel mechanism and a single control mechanism ;
When the data requested to be read from the host device exists in any one of the plurality of cache mechanisms, the data requested to be read is read from any one of the cache mechanisms, and the channel mechanism Is transferred to the host device via
When the data requested to be read from the higher-level device does not exist in the plurality of cache mechanisms, the data requested to be read is read from the rotary storage device, and from the control mechanism to the cache mechanisms. An external storage subsystem, wherein the external storage subsystem is transferred to any one of the cache mechanisms and transferred to the host device via the channel mechanism . The external storage control device includes a plurality of channel mechanisms that control the exchange of data with the host device, and a plurality of control mechanisms that control the exchange of data with the rotary storage device. 2. The external storage subsystem according to claim 1, wherein each of the channel mechanism and the control mechanism includes a plurality of first access paths to which the plurality of cache mechanisms are independently connected. The external storage control device includes a plurality of channel mechanisms that control the exchange of data with the host device, and a plurality of control mechanisms that control the exchange of data with the rotary storage device. 2. The external storage subsystem according to claim 1, wherein each of the plurality of cache mechanisms includes a plurality of second access paths to which the plurality of channel mechanisms and control mechanisms are connected. The external storage control device includes a plurality of channel mechanisms that control the exchange of data with the host device, and a plurality of control mechanisms that control the exchange of data with the rotary storage device. , the channel mechanism, a plurality of third access path independent provided for the control mechanism and a plurality of caching mechanism, with respect to the third access path, a plurality of the channel mechanism, the control mechanism and a plurality of said cache 2. The external storage subsystem according to claim 1, wherein the mechanisms are individually connected. The external storage control device includes a plurality of channel mechanisms that control the exchange of data with the host device, and a plurality of control mechanisms that control the exchange of data with the rotary storage device. 2. The external storage subsystem according to claim 1, further comprising a fourth access path for directly and independently connecting each of the individual channel mechanism and the control mechanism and each of the plurality of cache mechanisms. A rotary storage device that stores data sent from a host device and sends data to the host device in response to a request from the host device;
A plurality of channel mechanisms connected to the host device, for controlling the transfer of data sent from the host device, and for controlling the transfer of data sent to the host device;
Connected to said rotating storage to control the transfer of data sent from said rotating storage, a plurality of control Organization for controlling the transfer of data to be sent to said rotating storage,
A plurality of cache mechanisms for storing data transferred between the host device and the rotary storage device;
Each of the plurality of channel mechanisms and the plurality of control mechanisms is connected to an access path connected to any one of the plurality of cache mechanisms and to another cache mechanism of the one of the cache mechanisms. an access path that is one having at least,
When the data requested to be read from the host device exists in the plurality of cache mechanisms, the data requested to be read is read from any one of the plurality of cache mechanisms, and the plurality of channels Is transferred to the host device via any channel mechanism of the mechanism,
When the data requested to be read from the higher-level device does not exist in the plurality of cache mechanisms, the data requested to be read is read from the rotary storage device and controlled by any of the plurality of control mechanisms. Transferred from the mechanism to any one of the plurality of cache mechanisms, and transferred to the host device via any one of the plurality of channel mechanisms.
The plurality of access paths transfer data transmitted from the host device to any one of the plurality of channel mechanisms or data transmitted from any channel mechanism of the plurality of channel mechanisms to the host device. External storage subsystem, characterized in that the access path is an access path . A rotary storage device that stores data sent from a host device and sends data to the host device in response to a request from the host device;
A plurality of channel mechanisms connected to the host device, for controlling the transfer of data sent from the host device, and for controlling the transfer of data sent to the host device;
A plurality of control mechanisms connected to the rotary storage device to control transfer of data sent from the rotary storage device and to control transfer of data sent to the rotary storage device;
A plurality of cache mechanisms for storing data transferred between the host device and the rotary storage device;
Each of the plurality of channel mechanisms and the plurality of control mechanisms has two access paths;
Approximately half of the plurality of cache mechanisms have a plurality of access paths connected to one of the two access paths, and the other approximately half of the plurality of cache mechanisms is the A plurality of access paths connected to the other of the two access paths ,
When the data requested to be read from the host device is present in the plurality of cache mechanisms, the data requested to be read is read from any one of the plurality of cache mechanisms, Transferred to the host device via a channel mechanism,
When the data requested to be read from the higher-level device does not exist in the plurality of cache mechanisms, the data requested to be read is read from the rotary storage device and controlled by any of the plurality of control mechanisms. Transferred from the mechanism to any one of the plurality of cache mechanisms, and transferred to the host device via any one of the plurality of channel mechanisms.
The access path transfers data transmitted from the host device to any one of the plurality of channel mechanisms or data transmitted from any channel mechanism of the plurality of channel mechanisms to the host device. An external storage subsystem characterized by an access path . A rotary storage device that stores data sent from a host device and sends data to the host device in response to a request from the host device;
A plurality of channel mechanisms connected to the host device, for controlling the transfer of data sent from the host device, and for controlling the transfer of data sent to the host device;
A plurality of control mechanisms connected to the rotary storage device to control transfer of data sent from the rotary storage device and to control transfer of data sent to the rotary storage device;
A plurality of cache mechanisms for storing data transferred between the host device and the rotary storage device;
Each of the cache mechanisms has two access paths;
The plurality of channel mechanisms have a plurality of access paths connected to one of the two access paths;
The plurality of control mechanisms have a plurality of access paths connected to the other of the two access paths ,
When the data requested to be read from the host device exists in the plurality of cache mechanisms, the data requested to be read is read from any one of the plurality of cache mechanisms, and the plurality of channels Is transferred to the host device via any channel mechanism of the mechanism,
When the data requested to be read from the higher-level device does not exist in the plurality of cache mechanisms, the data requested to be read is read from the rotary storage device and controlled by any of the plurality of control mechanisms. Transferred from the mechanism to any one of the cache mechanisms, and transferred to the host device via any one of the plurality of channel mechanisms.
The plurality of access paths transfer data transmitted from the host device to any one of the plurality of channel mechanisms or data transmitted from any channel mechanism of the plurality of channel mechanisms to the host device. External storage subsystem, characterized in that the access path is an access path . The external storage subsystem according to claim 1-8 .
The external storage subsystem, wherein the cache mechanism has at least one nonvolatile memory and at least one volatile memory. The external storage subsystem according to claim 1-8 .
The external storage subsystem, wherein the cache mechanism has at least one volatile memory. The external storage subsystem according to claim 1-8 .
The external storage subsystem characterized in that the cache mechanism has at least one nonvolatile memory. The external storage subsystem of claim 7,
Almost half of the plurality of cache mechanisms have a plurality of access paths connected to one of the two access paths, and are connected to the other of the two access paths. It has no access route,
The other half of the plurality of cache mechanisms has a plurality of access paths connected to the other of the two access paths, and is connected to the one of the two access paths. An external storage subsystem characterized by having no access path to be used.

Images