JP3638737B2 - Active matrix liquid crystal display device and driving method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix liquid crystal display device, and is intended to reduce power consumption by suppressing fluctuations in the potential of a signal (data).
In particular, the present invention relates to an active matrix liquid crystal display device using an in-plane switching mode (also referred to as IPS) as a display method.
[0002]
[Prior art]
In the liquid crystal display device, it is necessary to invert the voltage applied to the liquid crystal element. This is performed to prevent display deterioration such as an afterimage phenomenon because deterioration of materials such as liquid crystal and alignment film and parasitic charges due to impurities occur when an electric field having a single polarity is applied for a long time. This operation is called an AC operation, and it is necessary to invert once every frame (field) or every several frames. In that case, there were various methods.
[0003]
In one frame, the entire display screen has the same polarity (frame inversion) (FIG. 11A), the same row has the same polarity, but the adjacent rows have different polarities (FIG. 11 (B), (C) in FIG. 11 shows dot inversion (FIG. 11 (D)) in which all adjacent pixels have different polarities.
[0004]
Conventionally, in order to perform such inversion, a signal whose polarity is inverted is supplied to a pixel from a data driver (signal driver).
[0005]
FIG. 8 shows a unit pixel of a conventional active matrix type liquid crystal display device. The thin film transistor (T) has a scan line (scan line) (X_n), And the data line (signal line) (P_m) Is sent to the liquid crystal element (LC) and, if necessary, to the auxiliary capacitor (C) provided in parallel therewith, and charges are accumulated. (Fig. 8)
[0006]
A driving signal in a display device in which such unit pixels are arranged in a matrix of N rows is as shown in FIG. Here, CLK is a clock signal (synchronization signal) and indicates the minimum time of the display device. In response, a signal is formed. Scan line (X₁ , X₂ , X_Three ,. . . X_N-1 , X_N), Pulses are sequentially applied as shown in the figure. On the other hand, the data line (P₁ ) Is applied with data corresponding to the image signal of each row. Here, an example of field inversion (FIG. 11A) is shown. For comparison, the image information is always the same. That is, the data in the second field (2nd Field) is obtained by inverting the data in the first field (1st Field) with respect to the reference potential (ground level).
[0007]
The same applies to the second field (2nd field) and the third field (3rd field). Moreover, although the example of the data of line inversion (FIG.11 (C)) was shown in FIG. 10, when the data corresponding to each row are compared, the polarity is reverse in the 1st field and the 2nd field.
[0008]
Whereas a conventional liquid crystal display device performs display by applying a voltage perpendicular to the substrate between the substrates, the liquid crystal display device of the present invention applies a voltage parallel to the substrate surface within the substrate. Thus, the display is performed. Such a driving method is called an in-plane switching (IPS) method. This is already shown in Japanese Patent Publication No. 63-21907 in which the basic concept in the case of use in an active matrix type liquid crystal display device using a thin film transistor as a switching element is shown.
[0009]
In addition, JP-A-7-43744, JP-A-7-43716, JP-A-7-36058, JP-A-6-160878, JP-A-6-202073, JP-A-7-134301, and JP-A-6-214244 are applied to the invention. It is shown.
[0010]
Further, when used in a simple matrix type liquid crystal display device, it is disclosed in JP-A-7-72491, and when used in an active matrix type liquid crystal display device using a thin film diode as a switching element, it is disclosed in JP-A-7-120791. ing.
[0011]
The principle of the IPS system disclosed in these prior arts will be briefly described with reference to FIGS. FIG. 6 shows a unit pixel of an active matrix liquid crystal display device based on the IPS method. As in the case of a normal active matrix liquid crystal display device, the data lines 1 and the scan lines 2 are provided in a matrix, but in addition, a ground line 3 (a ground line or a counter electrode line) is provided.
[0012]
Conventionally, the ground wire 3 is unnecessary because there is an electrode on the counter substrate. However, in the IPS system, there is no electrode on the counter substrate, so it is necessary to provide wiring having the same function in the plane.
[0013]
Normally, the ground wire 3 is held at a constant potential. Further, since it is formed at the same time as the scan line 2, it does not intersect with the scan line 2, that is, has a parallel configuration. This is because a part of the ground line 3 is overlapped with a part of the pixel electrode 4 formed at the same time as the data line 1 to form an auxiliary capacitor (C). That is, the scan line 2 and the ground line 3 are formed simultaneously, and the data line 1 and the pixel electrode 4 are formed simultaneously. A TFT 5 is formed as shown in the figure using a part of the scan line 2 as a gate electrode. Its source is in contact with the data line 1 and its drain is in contact with the pixel electrode 4. (Fig. 6)
[0014]
Thus, the structure in which the ground wire 3 is arranged opposite to the pixel electrode 4 generates an electric field as shown by an arrow between the pixel electrode 4 and the ground wire 3 as shown in FIG. The liquid crystal molecules are initially aligned so as to form a certain angle, for example, 45 °, with respect to a predetermined electric field, as shown in FIG. Next, when an electric field is applied, the liquid crystal molecules try to be parallel to the electric field, as shown in FIG. By making good use of the inclination of the liquid crystal molecules, light and shade can be expressed. The above is the principle of the IPS system. (Fig. 7)
[0015]
[Problems to be solved by the invention]
As described above, in the conventional active matrix type liquid crystal display device, it is necessary for the driver to generate data having a variation amount twice as large as the signal variation required only from the image information. That is, a voltage of 5V may be effectively applied to the liquid crystal. However, since the inversion is necessary, a driving capability in a range of 10V from + 5V to -5V is required. This was the biggest obstacle in reducing the driving voltage of the driver and reducing the power consumption.
[0016]
Similarly, the breakdown of transistors and the deterioration of characteristics due to an excessive voltage applied to the active matrix circuit are also problems.
[0017]
The present invention has been made in view of such a problem, and provides a configuration of a liquid crystal display device and a driving method thereof for performing necessary inversion while minimizing data fluctuation.
[0018]
Further, the conventional IPS system has a feature that the viewing angle is wider than that of the conventional liquid crystal display device because the alignment of the liquid crystal is parallel to the substrate. However, in the above prior art, no particular consideration is given to reducing the burden on the data driver, and the data is the same as in the conventional case.
[0019]
An object of the present invention is to invert the electric field applied to the liquid crystal molecules without inverting the polarity in the data, taking advantage of the characteristics of the IPS system in which a voltage is applied mainly in the same plane.
[0020]
[Means for Solving the Problems]
  The first configuration of the active matrix type liquid crystal display device for solving the above problems is as follows:
  A pair of first and second electrodes sandwiching the liquid crystal;
  A data line to which a video writing signal having a single polarity with respect to a reference potential is applied;
  SaidConnected to the first and second electrodes and alternately to either the first or the second electrode at a predetermined cycleSaidSupply video write signal and the otherSaidIt has polarity control means consisting of a circuit that uses the reference potential.DoIt is characterized by that.
[0021]
In order to solve the above problem, the second configuration of the active matrix liquid crystal display device according to the present invention is as follows.
A first scan line and a second scan line that do not intersect each other;
A data line intersecting the first and second scan lines;
A ground wire that intersects the first and second scan lines and does not intersect the data line;
A pair of first and second electrodes disposed in a region surrounded by the first and second scan lines, the data line, and the ground line, and sandwiching a liquid crystal;
First to fourth switching circuits;
Active matrix type liquid crystal display device having the same on the same plate,
The first to fourth switching circuits are circuits in which at least one transistor is connected in series,
In the transistors connected in series of the first switching circuit, the source of the first transistor is connected to the data line, and the gates of all the transistors are connected to the first scan line,
In the transistors connected in series in the second switching circuit, the source of the first transistor is connected to the ground line, and the gates of all the transistors are connected to the second scan line,
In the first and second switching circuits, the drain of the final transistor is connected to the first electrode,
In the transistors connected in series in the third switching circuit, the source of the first transistor is connected to the data line, and the gates of all the transistors are connected to the second scan line,
In the transistor connected in series of the fourth switching circuit, the source of the first transistor is connected to the ground line, and the gates of all the transistors are connected to the first scan line,
In the third and fourth switching circuits, the drain of the final transistor is connected to the second electrode, respectively, and an in-plane switching active matrix liquid crystal display device.
[0022]
  In addition, the configuration of the driving method of the active matrix liquid crystal display device for solving the above problems is as follows:
  A driving method of an in-plane switching type active matrix liquid crystal display device having the above second configuration,
  Said1And the second2These scan lines are characterized in that no pulse is applied simultaneously.
[0023]
Further, another configuration of the driving method of the active matrix liquid crystal display device is as follows:
A driving method of an in-plane switching type active matrix liquid crystal display device having the above second configuration,
The potential level of the signal input to the data line is always single polarity.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIG.
A circuit configuration of a unit pixel (nth row and mth column) in the liquid crystal display device of the present invention is shown in FIG. In the configuration shown in FIG. 1, the first to fourth switching circuits (SW₁ ~ SW_Four ) A single transistor (T₁ ~ T_Four ).
[0025]
As in the case of the conventional IPS system, the data line (P_m) And ground wire (Z_mHowever, unlike the conventional case, the ground line does not cross the data line. This is because in the present invention, the ground wire needs to be connected to the drain of another transistor.
[0026]
In the present invention, the source and drain of a transistor can be defined arbitrarily. Therefore, one can be appropriately defined as a source (or drain), and in that case, the other is defined as a drain (source). The As is usually used, there is no distinction according to the level of the potential.
[0027]
In the present invention, unlike the conventional IPS system, two scan lines are provided in each row. Transistor (T₁ ) And (T_Three ) Is a data line (P_m). This data line (P_m) Connected to the transistor (T₁ ) And (T_Three ) Is referred to as an input transistor.
[0028]
Input transistor (T₁ ), (T_Three ) Are connected to different scan lines, and these transistors are controlled independently. That is, the transistor (T₁ ) Is the scan line (X_n) By a transistor (T_Three ) Is the scan line (Y_n).
[0029]
Furthermore, the transistor (T₂ ) And (T_Four ) Source is the same ground wire (Z_m). Transistor (T₂ ) And (T_Four ) Is called a discharge transistor.
[0030]
Transistor (T₁ ) And (T₂ ), Transistor (T_Three ) And (T_Four ) Are connected to each other, and an IPS liquid crystal element (LC) is provided between the drains. The liquid crystal element (LC) includes a pair of first electrodes sandwiching a liquid crystal therebetween, and includes a transistor (T₁ ) And (T₂ ) Is connected to one electrode of the liquid crystal element (LC), and the transistor (T_Three ) And (T_Four ) Is connected to the other electrode of the liquid crystal element (LC).
Note that an auxiliary capacitor (C) may be formed in parallel with the liquid crystal element (LC).
[0031]
Transistor (T₂ ) Is the scan line (Y_n) And transistor (T_Four ) Is the scan line (X_n), Respectively. Therefore, the transistor (T₂ ) Is the scan line (Y_n) And transistor (T_Four ) Is the scan line (X_n), Respectively. (Fig. 1 (A))
As a result of having the above configuration, the transistor (T₁ ) And (T_Four ) And transistor (T₂ ) And (T_Three ) Are simultaneously driven.
[0032]
A state of a matrix in which a large number of such unit elements are arranged is shown in FIG. X scan line 11 (X₁ , X₂ , X_Three ,. . . X_N-1 , X_N) And Y scan line 12 (Y₁ , Y₂ , Y_Three ,. . . Y_N-1 , Y_N) And data line 13 (P₁ , P₂ , P_Three ,. . . P_M-1 , P_M) Are respectively controlled by the X scan driver 14, the Y scan driver 15, and the data driver 16 (in the case of N rows and M columns matrix).
[0033]
Since no voltage is particularly applied to the ground wire 17, it may be a structure that is fixed at a constant potential, for example, may be fixed at a ground potential. In FIG. 1B, the X scan driver 14 and the Y scan driver 15 are written separately, but they may be integrated. (Fig. 1 (B))
[0034]
The operation of the unit pixel shown in FIG. 1 will be described with reference to FIG. For ease of explanation, the data line (P_m) Is maintained at a constant positive potential. Actually, the data line (P_m) Is applied with a signal corresponding to the image information. On the other hand, the ground wire (Z_m) Shall be kept at a constant negative potential. Scan line (X_n) Is applied with the pulse (Sp), the transistor (T₁ ) And (T_Four ) Is turned ON, and the other transistors remain OFF.
[0035]
Therefore, as shown in FIG. 2A, the potential of the liquid crystal element (LC) is the upper side (transistor (T₁ ) Is connected to the positive electrode and the lower electrode (transistor (T_Three ) The electrode on the side connected to) becomes negative. (Fig. 2 (A))
[0036]
Scan line (X_n) Pulse (Sp) is turned off, all transistors (T₁ ~ T₂ ) Is turned off, but the charge accumulated in the liquid crystal element (LC) is retained.
[0037]
Next, scan lines (Y_n) Is applied to the transistor (T₂ ) And (T_Three ) Is turned ON, and the other transistors remain OFF. Therefore, as shown in FIG. 2B, the potential of the liquid crystal element (LC) is the upper side of the figure (transistor (T₁ ) Electrode on the side connected to the negative side, the lower side (transistor (T₂ ) Electrode on the side connected to) is positive, that is, the polarity is reversed from the case of FIG. (Fig. 2 (B))
[0038]
  Thus, the data line (P_mIt is a feature of the present invention that the direction of the electric field applied to the liquid crystal element (LC) can be reversed even if the polarity of the video signal applied to the liquid crystal element (LC) is single. Therefore, the fluctuation of the data potential, which is a problem to be solved by the present invention, can be halved.
  In the present invention, pulses are simultaneously applied to the X scan line and the Y scan line.NeverTherefore, all the transistors are not turned on at the same time.
[0039]
  In the active matrix display device according to the present invention, when the first scan line and the second scan line are not selected, all the switching circuits are turned off, and the first and second electrodes are turned off. Since it is disconnected from the data line and the ground line, the leakage of the charge held between the first and second electrodes is suppressed.Canit can.
[0040]
  The effect is that the first to fourth switching circuits (SW₁~ SW_Four)TheEven if it is composed of a single transistor, it can be obtained sufficiently, but the first to fourth switching circuits (SW₁~ SW_Four) Is composed of a plurality of thin film transistors connected in series, the resistance is connected in series to the first or second electrode, so that the leakage of charge held between the first or second electrode is further reduced. Can be suppressed.
[0041]
FIGS. 5A to 5C show another embodiment of the present invention. In the unit pixel shown in FIG. 1, the switching circuit SW₁ ~ SW_Four Is composed of a single thin film transistor. FIGS. 5A to 5C show a switching circuit (SW).₁ ~ SW_Four ) Is composed of a plurality of thin film transistors connected in series.
[0042]
In this specification, a plurality of thin film transistors connected in series have a configuration in which all gates are connected to the same scan line and the sources and drains of adjacent transistors are connected.
[0043]
FIG. 5A shows the first and third switching circuits SW.₁ , SW_Three Are connected in series with three thin film transistors (T₁₁, T₁₂, T₁₃) And (T₁₅, T₁₆, T₁₇). Thin film transistor (T₁₄) And (T₁₈) Is the second and fourth switching circuit (SW)₂ , SW_Four ).
[0044]
FIG. 5B shows the second and fourth switching circuits (SW₂ , SW_Four ) Are connected in series, and three thin film transistor groups (T_{twenty two}, T_{twenty three}, T_{twenty four}) And thin film transistor group (T₂₆, T₂₇, T₂₈). Thin film transistors (T_{twenty one}) And (T_{twenty five}) Is the first and third switching circuit (SW)₁ , SW_Three ).
[0045]
FIG. 5C shows the first and third switching circuits (SW₁ , SW_Three ) Are connected in series, and three thin film transistor groups (T₃₁, T₃₂, T₃₃), (T₃₇, T₃₈, T₃₉), And the second and fourth switching circuits SW₂ , SW_Four Three thin film transistor groups (T₃₄, T₃₅, T₃₆), (T₄₀, T₄₁, T₄₂).
[0046]
【Example】
Embodiment 1 In this embodiment, a driving method of the liquid crystal display device shown in FIGS. 1A and 1B will be described based on FIG. FIG. 3 shows signals supplied to the signal lines of the liquid crystal display device of this embodiment. In this embodiment, an example in which field inversion is performed in an N-row matrix liquid crystal display device is shown.
[0047]
As shown in FIG. 3, in the first field, the X scan line (X₁ , X₂ , X_Three ,. . . X_N-1 , X_N) Are sequentially applied with pulses. However, the Y scan line (Y₁ , Y₂ , Y_Three ,. . . Y_N-1 , Y_NNo pulse is applied to). On the other hand, the data line (here, P₁ However, a signal having a potential equal to or higher than the ground level (the potential of the ground line) is applied to the other data lines as well. In this case, the state of FIG.
[0048]
On the other hand, in the second field, contrary to the first field, the Y scan line (Y₁ , Y₂ , Y_Three ,. . . Y_N-1 , Y_N) Are sequentially applied with pulses. However, the X scan line (X₁ , X₂ , X_Three ,. . . X_N-1 , X_NNo pulse is applied to). Data on the data line is the same as in the first field.
[0049]
  In this case, FIG.B) State is realized. That is, the direction of the electric field applied to the liquid crystal element (LC) is reversed in the first field and the second field. The same applies between the second field and the third field. In this embodiment, in all rows, either state shown in FIG. 2A or FIG. 2B is realized, so that field inversion is performed. (Figure 3)
[0050]
  Example 2 In this example, a driving method of the liquid crystal display device shown in FIGS. 1A and 1B will be described with reference to FIG. FIG. 4 shows signals supplied to the signal lines of the liquid crystal display device of this embodiment. In this embodiment, an N-row matrix liquid crystal display device,lineAn example of inversion is shown.
[0051]
As shown in FIG. 4, in the first field, (X₁ ), (X_Three ),. . . (X_N) Only for odd-numbered rows and Y scan lines (Y₂ ), (Y_Four ) (Not shown),. . . (Y_N-1 ), A pulse is applied only to even-numbered rows, and no pulse is applied to other scan lines. On the other hand, the data line (here, P₁ However, a signal having a potential equal to or higher than the ground level (the potential of the ground line) is applied to the other data lines as well.
[0052]
In this case, the odd-numbered rows (first row, third row,..., N-th row) realize the state of FIG. 2A, and even rows (second row, fourth row,. (Line (N-1)) realizes the state of FIG.
[0053]
  On the other hand, in the second field, contrary to the first field, (Y₁), (Y_Three),. . . (Y _N ) Only for odd rows, and X scan lines (X₂), (X_Four) (Not shown),. . . (X _N-1 ), A pulse is applied only to even-numbered rows, and no pulse is applied to other scan lines. Data on the data line is the same as in the first field.
[0054]
In this case, the odd-numbered rows (first row, third row,... Nth row) are realized in the state of FIG. 2B, and even rows (second row, fourth row,. (Line (N-1)) realizes the state shown in FIG. That is, when attention is paid to a specific row, the direction of the electric field applied to the liquid crystal element (LC) is reversed in the first field and the second field. Further, in this embodiment, since the directions of the electric fields applied to the liquid crystal elements (LC) are opposite between the even rows and the odd rows, the lines are reversed. (Fig. 4)
[0055]
Example 3 In the unit pixel shown in FIG. 1, a switching circuit (SW₁ ~ SW_Four ) Is a single thin film transistor (T₁ ~ T_Four ). In this embodiment, the switching circuit (SW₁ ~ SW_Four ) Is composed of a plurality of thin film transistors connected in series. 5A to 5C are circuit configuration diagrams of the unit pixel of this embodiment. 5A to 5C, the same reference numerals as those in FIG. 1 denote the same members.
[0056]
FIG. 5A shows the first and third switching circuits (SW₁ , SW_Three ) Three thin film transistors (T) connected in series₁₁, T₁₂, T₁₃) And thin film transistor (T)₁₅, T₁₆, T₁₇). Thin film transistors (T₁₄) And (T₁₈) Is the second and fourth switching circuit (SW)₂ , SW_Four ).
[0057]
  Three thin film transistors (T₁₁, T₁₂, T₁₃), (T₁₅, T₁₆, T₁₇) Are the same scan line (X_n, Y_nAll thin film transistor groups (T₁₁, T₁₂, T₁₃)When(T ₁₅ ,T ₁₆ ,T ₁₇ ) Are simultaneously turned ON and OFF, the driving timing of the switching circuit of FIG. 5A is the same as that of the circuit of FIG.
[0058]
  Thin film transistor group (T₁₁, T₁₂, T₁₃), (T₁₅, T₁₆,T ₁₇ ) Is the same scan line X_n, Y_n1 is connected to the input transistor (T in FIG.₁),(T_Three)WhenThe same.
[0059]
In FIG. 5A, the data line (P_m) Connected to the thin film transistor group (T₁₁, T₁₂, T₁₃), (T₁₅, T₁₆, T₁₇) Is composed of the same number of thin film transistors, that is, a switching circuit having the same function is composed of the same number of thin film transistors. It can be carried out.
[0060]
FIG. 5B shows the second and fourth switching circuits (SW₂ , SW_Four ) Are connected in series, and three thin film transistor groups (T_{twenty two}, T_{twenty three}, T_{twenty four}) And thin film transistor group (T₂₆, T₂₇, T₂₈). Thin film transistors (T_{twenty one}) And (T_{twenty five}) Is the first and third switching circuit (SW)₁ , SW_Three ).
[0061]
Thin film transistor group (T_{twenty two}, T_{twenty three}, T_{twenty four}), (T₂₆, T₂₇, T₂₈) Are the same scan line (X_n, Y_n1 is connected to the discharge transistor (T in FIG. 1).₂ ) And (T_Four ) Same.
[0062]
In FIG. 5B, the ground wire (Z_m) Connected to the thin film transistor group (T_{twenty two}, T_{twenty three}, T_{twenty four}), (T₂₆, T₂₇, T₂₈) Is configured with the same number of thin film transistors, that is, a switching circuit having the same function is configured with the same number of thin film transistors. be able to.
[0063]
FIG. 5C shows the first and third switching circuits (SW₁ , SW_Three ) Of three thin film transistors (T₃₁, T₃₂, T₃₃), (T₃₇, T₃₈, T₃₉), And the second and fourth switching circuits (SW₂ , SW_Four ) Are connected in series, and three thin film transistor groups (T₃₄, T₃₅, T₃₆), (T₄₀, T₄₁, T₄₂).
[0064]
In FIG. 5C, all the switching circuits are formed of the same number of thin film transistors. Therefore, the characteristics of the switching circuit to which the liquid crystal element (LC) is connected can be made more uniform.
[0065]
[Effect of the present invention]
As described above, the present invention can reverse the direction of the electric field applied to the liquid crystal element without reversing the polarity of data. As a result, the driving voltage of the data driver can be reduced to half that of the conventional one, which is effective in reducing power consumption. Furthermore, the effect of adopting the present invention also appears in a transistor used for a scan driver drive circuit or an active matrix.
[0066]
For example, in an active matrix circuit (see FIG. 8) that employs a conventional driving method, the potential of the electrode on the counter substrate of the pixel is made constant. Assuming that the data is in the range of 5V, the potential of the data output from the data driver fluctuated with a potential difference of 10V from + 5V to -5V. That is, the maximum potential difference between the source and drain of the transistor was 10V.
[0067]
Then, in order to stably turn off the transistor at the time of non-selection, the potential of the gate electrode of the transistor is −5V or less (hereinafter, only described in the case of NMOS, + 5V or more in the case of PMOS), preferably −7V Usually, it was required to be set to about -8V.
[0068]
In order to ensure that the transistor is turned on when selected, the potential of the gate electrode is + 5V plus the threshold voltage Vth of the transistor, + (Vth + 5) V or higher, preferably + (Vth + 7) V or higher. In general, it was required to keep about + 8V. For this reason, the maximum potential difference between the source and drain of the transistor is 10 V, and the maximum potential difference between the gate and source (gate to drain) is 13 V, which is an abnormally high stress compared to the voltage required for the transistor from the image information. It can be seen that is applied. For this reason, the transistor used for the active matrix is required to be a high voltage transistor.
[0069]
Also, the potential output from the scan driver is ± 8 V, that is, the potential difference is 16 V, and an abnormally high voltage is required. The output voltage of the data driver is also 10V.
[0070]
However, when the present invention is used, the potential of data is 0V to + 5V, that is, the potential difference is 5V even when the same display is performed using the same transistor. Therefore, in such a case, in order to stably turn off the transistor when it is not selected, the potential of the gate electrode of the transistor should be 0 V or less, preferably -2 V or less, and usually about -3 V. In order to ensure that the transistor is turned on when selected, the potential of the gate electrode is + 5V plus the threshold voltage Vth of the transistor, + (Vth + 5) V or higher, preferably + (Vth + 7) V or higher. Usually, it is better to keep it at about + 8V.
[0071]
That is, in the transistor of the active matrix circuit using the present invention, the maximum potential difference between the source and the drain is 5 V, and the maximum potential difference between the gate and the source (gate to drain) is 8 V, which is reduced from the potential difference of 13 V in the conventional example. it can. It may seem that a decrease in potential difference of 5 V is not very effective.
[0072]
However, the reduction of the potential difference can sufficiently reduce the burden on the transistor. That is, it has a remarkable effect in improving the yield of the transistor. According to the experience of the present inventors, when silicon oxide having a thickness of 1200 mm is used as the gate insulating film, there are very few elements that are destroyed when the gate-source voltage is up to 10V. Every time increases, it increases exponentially. Accordingly, the fact that the gate-source voltage is 10 V or less is very significant industrially.
[0073]
Further, the potential difference of the data output from the scan driver is 11V, which is lower than the conventional 16V, and therefore the burden on the scan driver can be reduced. Thus, according to the present invention, power consumption not only in the data driver but also in the scan driver can be reduced, and the burden on the transistors used in the active matrix circuit can be reduced. In particular, in other words, the latter can be operated sufficiently even with a slightly poor quality transistor.
[0074]
Moreover, the fact that the output voltage of the scan driver and data driver can be reduced means that the burden on the transistors used in those circuits can be reduced, and this is particularly the same substrate as the active matrix circuit. In addition, this is effective in a so-called monolithic active matrix circuit in which a scan driver and a data driver are integrated. This is because, in a circuit generally used for a monolithic active matrix circuit, a thin film transistor is used in the same manner as the active matrix circuit, which is difficult in terms of pressure resistance.
[0075]
In the embodiments, the N-type transistor (NMOS) is described as an example, but it goes without saying that the transistor can be driven in the same manner even if it is a P-type transistor (PMOS). It can also be configured in a conventional mode such as TN. As described above, the present invention has various effects in an active matrix liquid crystal display device and is industrially useful.
[Brief description of the drawings]
FIG. 1 is a diagram showing a basic configuration of the present invention, FIG. 1A is a circuit configuration diagram of a unit pixel, and FIG. 1B is a block configuration diagram of a liquid crystal display device.
FIG. 2 is an explanatory diagram of an operation principle of a unit pixel shown in FIG.
3 is a diagram illustrating signals during operation of Embodiment 1. FIG. (Field inversion mode)
4 is a diagram illustrating signals during operation of Embodiment 2. FIG. (Line inversion mode)
FIG. 5 is a configuration diagram of a unit pixel according to the third embodiment.
FIG. 6 is a diagram illustrating a conventional IPS unit pixel.
FIG. 7 is a diagram showing an operation principle of a conventional IPS system.
FIG. 8 is a configuration diagram of a unit pixel of a conventional active matrix liquid crystal display device.
FIG. 9 shows an operation of a conventional active matrix liquid crystal display device. (Field inversion mode)
FIG. 10 is a diagram showing an operation of a conventional active matrix liquid crystal display device. (Line inversion mode)
FIG. 11 is a diagram showing the concept of field inversion (frame inversion), line inversion, and dot inversion.
[Explanation of symbols]
SW₁ , SW₂ , SW_Three , SW_Four ... Switching circuits
T₁ , T₂ , T_Three , T_Four ... Transistors
P_m                  ... Data lines
Z_m                  ···ground wire
X_n, Y_n            ... Scan lines
LC ... Liquid crystal element

Claims (10)

A pair of first and second electrodes sandwiching the liquid crystal;
A data line to which a video writing signal having a single polarity with respect to a reference potential is applied;
Connected to said first and second electrodes, and supplies the video writing signal to one of said first or said second electrode are alternately at a predetermined cycle, one from the circuit to the reference potential active matrix liquid crystal display device, characterized in that have a polarity control means made. A first scan line and a second scan line that do not intersect each other;
A data line intersecting the first and second scan lines;
A counter electrode line that intersects the first and second scan lines and does not intersect the data line;
A pair of first and second electrodes disposed in a region surrounded by the first and second scan lines, the data line, and the counter electrode line ;
And first to fourth switching circuits a Akti blanking matrix type liquid crystal display device of in-plane switching type having on the same substrate,
The first to fourth switching circuits are circuits in which at least one transistor is connected in series,
In the transistors connected in series of the first switching circuit, the source of the first transistor is connected to the data line, and the gates of all the transistors are connected to the first scan line,
In the transistors connected in series in the second switching circuit, the source of the first transistor is connected to the counter electrode line, and the gates of all the transistors are connected to the second scan line,
In the first and second switching circuits, the drain of the final transistor is connected to the first electrode,
In the transistors connected in series in the third switching circuit, the source of the first transistor is connected to the data line, and the gates of all the transistors are connected to the second scan line,
In the transistors connected in series of the fourth switching circuit, the source of the first transistor is connected to the counter electrode line, and the gates of all the transistors are connected to the first scan line,
In the third and fourth switching circuits, the drain of the last transistor is connected to the second electrode, respectively.   3. The active matrix liquid crystal display device according to claim 2, wherein the first switching circuit and the third switching circuit are configured by the same number of transistors.   3. The active matrix liquid crystal display device according to claim 2, wherein the second switching circuit and the fourth switching circuit are configured by the same number of transistors.   3. The active matrix liquid crystal display device according to claim 2, wherein each of the first to fourth switching circuits includes the same number of transistors. A first scan line and a second scan line that do not intersect each other;
A data line intersecting the first and second scan lines;
A counter electrode line that intersects the first and second scan lines and does not intersect the data line;
A pair of first and second electrodes sandwiching a liquid crystal, disposed in a region surrounded by the first and second scan lines, the data line, and the counter electrode line ;
Having the first to fourth switching circuits on the same substrate;
The first to fourth switching circuits are circuits in which at least one transistor is connected in series,
In the transistors connected in series of the first switching circuit, the source of the first transistor is connected to the data line, and the gates of all the transistors are connected to the first scan line,
In the transistors connected in series in the second switching circuit, the source of the first transistor is connected to the counter electrode line, and the gates of all the transistors are connected to the second scan line,
In the first and second switching circuits, the drain of the final transistor is connected to the first electrode,
In the transistors connected in series in the third switching circuit, the source of the first transistor is connected to the data line, and the gates of all the transistors are connected to the second scan line,
In the transistors connected in series of the fourth switching circuit, the source of the first transistor is connected to the counter electrode line, and the gates of all the transistors are connected to the first scan line,
In the third and fourth switching circuits, the drain of the final transistor is a driving method of an in-plane switching type active matrix liquid crystal display device connected to the second electrode, respectively.
A driving method of an active matrix liquid crystal display device, wherein no pulse is applied to the first and second scan lines simultaneously.   7. The field according to claim 6, wherein no pulse is applied to the second scan line in a field where a pulse is applied to the first scan line, and the first scan line is applied to a field next to the field. A driving method of an active matrix liquid crystal display device, wherein no pulse is applied and a pulse is applied to the second scan line. A first scan line and a second scan line that do not intersect each other;
A data line intersecting the first and second scan lines;
A counter electrode line that intersects the first and second scan lines and does not intersect the data line;
A pair of first and second electrodes sandwiching a liquid crystal, disposed in a region surrounded by the first and second scan lines, the data line, and the counter electrode line ;
Having the first to fourth switching circuits on the same substrate;
The first to fourth switching circuits are circuits in which at least one transistor is connected in series,
In the transistors connected in series of the first switching circuit, the source of the first transistor is connected to the data line, and the gates of all the transistors are connected to the first scan line,
In the transistors connected in series in the second switching circuit, the source of the first transistor is connected to the counter electrode line, and the gates of all the transistors are connected to the second scan line,
In the first and second switching circuits, the drain of the final transistor is connected to the first electrode,
In the transistors connected in series in the third switching circuit, the source of the first transistor is connected to the data line, and the gates of all the transistors are connected to the second scan line,
In the transistors connected in series of the fourth switching circuit, the source of the first transistor is connected to the counter electrode line, and the gates of all the transistors are connected to the first scan line,
In the third and fourth switching circuits, the drain of the last transistor is a driving method of an in-plane switching type active matrix liquid crystal display device connected to the second electrode of the liquid crystal element, respectively.
A driving method of an active matrix liquid crystal display device, wherein a potential level of a signal input to the data line is always single polarity. In any one of claims 6 to 8, in the field pulse is applied to at least one of the first scan line, rather than a pulse is applied to all the second scan line, the field In the next field, an active matrix liquid crystal display characterized in that a pulse is applied to at least one second scan line and no pulse is applied to all the first scan lines. Device driving method. In any one of Claims 6 thru | or 8 , in the field where the pulse was applied to the 1st scan line of arbitrary rows, a pulse is not applied to the 2nd scan line of the said row, and the said A pulse is not applied to any first scan line in two rows adjacent to the row, and a pulse is applied to any second scan line in two rows adjacent to the row. A driving method of an active matrix liquid crystal display device.

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