JP3628492B2 - Semiconductor device and test method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a circuit for performing a test in an analog / digital mixed semiconductor device having a digital / analog converter (hereinafter referred to as DAC), and a test method thereof.
[0002]
[Prior art]
FIG. 6 is a diagram showing a conventional semiconductor device. In the figure, 1 is a semiconductor device such as an analog / digital mixed LSI incorporating an N-bit DAC, for example, 2 is a digital circuit such as a logic circuit or a RAM circuit, 3 Is a clock / timing generator for generating an internal clock of the semiconductor device 1, and 4 is an N-bit DAC. The semiconductor device 1 has a large number of digital input / output terminals and a small number of analog output terminals.
[0003]
Next, the operation will be described.
First, the test apparatus T1 is connected to the semiconductor device 1 which is a device under test, a predetermined test pattern or signal is created and input to the semiconductor device 1, and for example, the output value from the semiconductor device 1 is compared with an expected value. Then, the quality of the function of the semiconductor device 1 is determined.
Here, the test apparatus T1 takes in the analog signal output from the DAC 4 together with the digital signal output from the digital circuit 2 of the semiconductor device 1 and performs a test.
[0004]
[Problems to be solved by the invention]
Since the conventional semiconductor device is configured as described above, it is necessary to use an expensive test device for a multi-pin analog / digital mixed semiconductor device when testing this semiconductor device. There were issues such as high costs.
[0005]
The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device and a test method thereof that can be tested at a low cost even in a mixed analog / digital semiconductor device. .
[0006]
[Means for Solving the Problems]
The semiconductor device according to the present invention comprises a number of digital signal input / output terminals, a digital circuit for inputting / outputting digital signals via the digital signal input / output terminals, and a predetermined digital signal output from the digital circuit. A semiconductor device comprising: a digital / analog converter for converting a signal into an analog signal; an output terminal of the digital / analog converter; and a clock generating means for supplying a clock to the digital circuit and the digital / analog converter. A comparison means is provided for comparing the analog signal output from the digital-analog converter with the test reference signal and outputting the comparison result to the test apparatus.
[0007]
The semiconductor device according to the present invention is the semiconductor device according to claim 1, wherein the digital-analog converter side and the output terminal side are connected during normal operation, and the output terminal side of the comparison means and the output terminal side during testing. Mode switching means for connecting the two is added.
[0008]
The semiconductor device according to the present invention is the semiconductor device according to claim 1 or 2, and includes a reference signal generating means for generating a test reference signal.
[0009]
The semiconductor device according to the present invention is the semiconductor device according to claim 3 , wherein the reference signal generating means is connected to a power source and a resistance circuit formed by combining a plurality of resistors, and an output terminal of the reference signal generating means And a plurality of switches for connecting or disconnecting between the side and a predetermined node of the resistor circuit, and a shift register for outputting a switching control signal for switching each switch at a predetermined timing.
[0010]
According to the semiconductor device test method of the present invention, a predetermined digital signal is input to a digital circuit from a digital signal input / output terminal, and the digital signal output from the digital circuit is converted into an analog signal by a digital / analog converter. The analog signal is compared with the test reference signal, the comparison result is output to the test device, and the test device determines the quality of the semiconductor device based on the taken comparison result. is there.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below.
Embodiment 1 FIG.
1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 1 is a semiconductor device, 2 is a digital circuit such as a logic circuit or a RAM circuit, and 3 is an internal clock of the semiconductor device 1. clock / timing generator for generating a (clock generating means), 4 is N-bit DAC (digital-to-analog converter), 5 DAC4 output voltage V _O and the reference voltage of the N-bit (reference signal for testing) A comparator (comparison means) for comparing V _ref , 6 is a switch (mode switching means) for connecting the DAC 4 and the output terminal 1b of the semiconductor device 1 during normal operation, and for connecting the comparator 5 and the output terminal 1b during testing. 1a, 1a,... Are digital signal input / output terminals, 1b is a DAC4 output terminal, 1c is a reference voltage terminal, 1d is a switch 6 Switch control terminal for trawl, 11 N input data signal line, 12 is a clock signal line to the digital circuit 2, 13 is the sampling clock signal line DAC4 of N bits.
[0012]
When testing the semiconductor device 1, a test device T 2 such as a logic tester is connected to the semiconductor device 1. A predetermined digital signal is input to the digital circuit 2, for example, from the test apparatus T2 via the digital signal input / output terminals 1a, 1a,..., And an analog output signal from the DAC 4 is output from the output terminal 1b during normal operation. Is output, and the digital output signal of the comparator 5 is taken into the test device T2 during the test. Further, the reference voltage V _ref created by the test apparatus T 2 is input to the comparator 5 from the reference voltage terminal 1 c. A control signal for switching the switch 6 is input to the switch 6 via the switch control terminal 1d.
The switch 6 has a DAC 4 side terminal 6a and a comparator 5 side terminal 6b. During normal operation, the switch 6 receives an “H” level control signal and connects the DAC side terminal 6a and the output terminal 1b. The "L" level control signal is received and the comparator side terminal 6b and the output terminal 1b are connected.
[0013]
Next, the operation will be described.
First, the test apparatus T2 is connected to the semiconductor device 1 through the terminals 1a, 1b,. An “L” level control signal is input from the switch control terminal 1d, and the terminal 6b of the switch 6 and the output terminal 1b are connected. Further, predetermined digital signals are inputted from predetermined digital signal input / output terminals 1a, 1a,.
The comparator 5 compares the analog output voltage V _O output from the DAC 4 with the reference voltage V _ref created in the test apparatus T2, and transmits a digital signal corresponding to the comparison result to the output terminal 1b. This digital signal is input to the test apparatus T2 and compared with an expected value to determine a non-defective product / defective product.
[0014]
Here, when the output voltage V _O from the DAC 4 is tested with an accuracy of 0.5 LSB (Least Significant Bit), the accuracy required for the voltage source of the test apparatus T2 is that the full-scale voltage of the DAC 4 is V _fs . Sometimes V _fs / ((2 ^N −1) /0.5).
Further, during normal operation, an “H” level control signal is input via the switch control terminal 1d, and the terminal 6a of the switch 6 and the output terminal 1b are connected. At this time, the analog output from the DAC 4 is directly transmitted to the output terminal 1b.
[0015]
As described above, according to the first embodiment, the comparator 5 that outputs the digital signal by comparing the output voltage V _{O of the} DAC 4 and the reference voltage V _{ref in} the semiconductor device, the normal operation, and the test The built-in switch 6 that eliminates the need for an expensive multi-pin analog / digital mixed semiconductor device testing device eliminates the need for a test device such as an inexpensive logic tester. As a result, the test cost can be reduced.
[0016]
In the first embodiment, the normal operation is performed when the “H” level control signal is input via the switch control terminal 1d. For example, when the high impedance state is set, You may comprise so that normal operation may be performed.
[0017]
Embodiment 2. FIG.
In the first embodiment, the reference voltage V _ref is created in the external test apparatus T2. In the second embodiment, the reference voltage V _ref is created in the semiconductor apparatus 1.
FIG. 2 is a block diagram showing a configuration of a semiconductor device according to the second embodiment of the present invention. In FIG. 2, 7 is a reference voltage generator (reference signal generating means) for generating a reference voltage V _ref , and 14 is serial data. An input signal line 15 is a shift clock signal line. 7a is a data input terminal of the reference voltage generator 7, 7b is a clock input terminal, and 7c is a reference voltage output terminal. Note that the same or corresponding parts as in FIG.
[0018]
FIG. 3 is a block diagram showing the configuration of the reference voltage generator of the semiconductor device according to the second embodiment of the present invention. In FIG. 3, reference numeral 71 is a combination of a plurality of resistors, and one end is connected to the power supply V _dd. A ladder resistor circuit (resistor circuit) having another end connected to the ground, 72 is a plurality of switches 72 a to 72 provided between a predetermined node of the ladder resistor circuit 71 and the reference voltage output terminal 7 c of the reference voltage generator 7. consists 72e, switches for connecting / disconnecting between each node and the reference voltage output terminal 7c in accordance with the switching control signal, 73 based on the shift clock signal CLK and the data input signal D _in, the switch groups 72 shift register for outputting a switching control signal for switching the switch, 7a is a data input terminal to which the data input signal D _in is input, 7b shift clock A clock input terminal to which No. CLK is input, 7c is the reference voltage output terminal reference voltage V _ref corresponding to the on-off states of the switches of the switch group 72 is outputted.
[0019]
The ladder resistor circuit 71 includes resistors R ₁ , R ₂ , R ₃ , R ₄ , and R ₅ connected in series, and is connected to a power source on one end (top voltage end) side and grounded on the other end (bottom voltage terminal) side. Connected to. Further, each of the nodes _{V 1, V 2, V 3} , V 4, V 5 between the resistors, switches 72a, 72b, 72c, 72d, one end of the 72e is connected. Further, the other ends of the switches 72a to 72e are connected to the reference voltage output terminal 7c.
FIG. 4 is a circuit diagram showing a structure of a shift register of the reference voltage generator according to the second embodiment of the present invention. In the figure, reference numerals 731, 731,... Are JK flip-flops, 732 are inverters, and 73a to 73e are switch control terminals. Shift register 73, as shown in FIG. 4, JK flip-flop 731,731, ... are connected to the five stages, based on the shift clock signal CLK and the data input signal _{D in,} switch from the switch control terminal 73a~73e Control signals A _{1 to} A ₅ are output.
In the case where, although the five shift registers of the ladder resistors and five stages for convenience of explanation, actually to test the output voltage V _O of DAC4 of N bits 0.5LSB of accuracy, (2 ^N- 1) /0.5 ladder resistors and ( ^2N- 1) /0.5 stage shift registers are required. The number of stages of the shift register can be arbitrarily set according to the required accuracy.
[0020]
Next, the operation will be described.
FIG. 5 is a timing chart for explaining the operation of the shift register according to the second embodiment of the present invention.
The operation during the test will be described. Data is input to the DAC 4 so that the DAC 4 outputs a ramp waveform. In FIG. 4, first, when the “H” level is input from the switch control terminal 1 d from the test device T 3, all the switching signals A _{1 to} A ₅ output from the switch control terminals 73 a to 73 e of the shift register 73 are “ Reset to “L” level.
Next, when the serial data “LHLLLLL...” Output from the digital circuit 2 is input to the shift register 73 and simultaneously the “L” level is applied from the switch control terminal 1d from the test device T3, as shown in FIG. The switching signals A _{1 to} A ₅ from the switch control terminals 73 a to 73 e of the shift register 73 are sequentially shifted in “H” level by the shift clock CLK.
[0021]
As shown in FIG. 3, the switching signals A _{1 to} A ₅ output from the switch control terminals 73 a to 73 e of the shift register 73 control the switch group 72, and turn on / off sequentially. As a result, the voltage from the ladder resistor circuit 71 is sequentially transmitted to the reference voltage terminal 7c. The reference voltage V _ref is a waveform in which a waveform that changes stepwise is periodically repeated.
Next, the analog output V _O of the ramp waveform from the DAC 4 is compared with the reference voltage V _ref by the comparator 5, and the digital signal transmitted to the output terminal 1 b is compared with the expected value in the test device T 3 to determine whether the product is good / defective. Determine. Here, for example, the linearity of the DAC 4 is measured by comparing the analog output V _O with the reference voltage V _ref . In the test apparatus T3, the digital circuit 2 is also examined based on digital signals output from predetermined digital signal input / output terminals 1a, 1a,.
The operation during normal operation is the same as that in the first embodiment, and a description thereof will be omitted.
[0022]
As described above, according to the second embodiment, in addition to the effects described in the first embodiment, since the reference voltage generator is provided in the semiconductor device, a high-precision reference signal source is not required for the test apparatus. The effect of becoming. Further, for example, by changing the number of resistors of the ladder resistor circuit, the number of stages of the shift register, etc., a desired accuracy can be freely set, and a predetermined reference voltage waveform can be created to test the semiconductor device. The effect that it can be obtained. Further, there is an effect that it is not necessary to have the reference voltage terminal 1c as an external pin.
[0023]
In the second embodiment, the ramp waveform is output from the comparator 5 and the linearity of the DAC is tested. However, the signal output from the comparator 5 is not limited to the ramp waveform, for example, a sine waveform. In addition, DAC test items that can be implemented are not limited to linearity.
[0024]
【The invention's effect】
As described above, according to the present invention, an expensive test device for a multi-pin analog / digital mixed semiconductor device is not required, and the test of the semiconductor device can be performed only with an inexpensive test device. There is an effect that can be reduced.
[0025]
According to the present invention, by providing the reference signal generating means inside the semiconductor device, there is an effect that a high-accuracy reference signal source is not required in the test apparatus.
[0026]
According to the present invention, for example, the desired accuracy can be freely set by changing the number of resistors in the resistor circuit, the number of stages of the shift register, etc., and a predetermined reference signal waveform can be created to test the semiconductor device. There is an effect that can be performed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a reference voltage generator according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram showing a configuration of a shift register of a reference voltage generator according to a second embodiment of the present invention.
FIG. 5 is a timing chart for explaining the operation of the shift register according to the second embodiment of the present invention;
FIG. 6 is a block diagram showing a configuration of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device, 1a, 1a, ... Digital signal input / output terminal, 1b Output terminal, 2 Digital circuit, 3 Clock / timing generator (clock generation means), 4 DAC (digital / analog converter), 5 Comparator (comparison) Means), 6 switches (mode switching means), 7 reference voltage generator (reference signal creation means), 71 ladder resistance circuit (resistance circuit), 72a to 72e switch, 73 shift register, 7c reference voltage output terminal (reference signal creation) output _means), R 1 _{~R 5 resistance,} V 1 ~V ₅ nodes, T2, T3 test device.

Claims (5)

A number of digital signal input / output terminals, a digital circuit for inputting / outputting digital signals via the digital signal input / output terminals, and a digital circuit for converting a predetermined digital signal output from the digital circuit into an analog signal In a semiconductor device comprising an analog converter, an output terminal of the digital / analog converter, and a clock generation means for supplying a clock to the digital circuit and the digital / analog converter,
A semiconductor device comprising comparison means for comparing an analog signal output from the digital-analog converter with a test reference signal and outputting the comparison result to a test device. The mode switching means for connecting the digital-analog converter side and the output terminal side during normal operation and for connecting the output terminal side of the comparison means and the output terminal side during testing is added. 1. The semiconductor device according to 1. 3. The semiconductor device according to claim 1, further comprising reference signal generating means for generating a test reference signal. The reference signal generating means is connected to a power source, and is connected to or disconnected from a resistance circuit formed by combining a plurality of resistors and an output terminal side of the reference signal generating means and a predetermined node of the resistance circuit. switch and, claim 3 Symbol mounting semiconductor device you; and a shift register for outputting a switching control signal for switching each switch at a predetermined timing. A predetermined digital signal is input to the digital circuit from the digital signal input / output terminal, the digital signal output from the digital circuit is converted into an analog signal by a digital / analog converter, and the analog signal and the test reference signal are converted. A method for testing a semiconductor device, wherein the comparison result is output to the test device, and the test device determines the quality of the semiconductor device based on the taken comparison result.

Images