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JP3620923B2 - Group 3 nitride semiconductor light emitting device - Google Patents

Group 3 nitride semiconductor light emitting device Download PDF

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Publication number
JP3620923B2
JP3620923B2 JP15027196A JP15027196A JP3620923B2 JP 3620923 B2 JP3620923 B2 JP 3620923B2 JP 15027196 A JP15027196 A JP 15027196A JP 15027196 A JP15027196 A JP 15027196A JP 3620923 B2 JP3620923 B2 JP 3620923B2
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Japan
Prior art keywords
layer
light emitting
semiconductor
substrate
emitting device
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JP15027196A
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Japanese (ja)
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JPH09312418A (en
Inventor
史郎 山崎
誠二 永井
隆弘 小澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Toyoda Gosei Co Ltd
Toyota Central R&D Labs Inc
National Institute of Japan Science and Technology Agency
Original Assignee
Japan Science and Technology Agency
Toyoda Gosei Co Ltd
Toyota Central R&D Labs Inc
National Institute of Japan Science and Technology Agency
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Description

【0001】
【発明の属する技術分野】
本発明は3族窒化物半導体を用いた半導体素子に関する。特に、素子特性や信頼性に優れた半導体素子に関する。
【0002】
【従来の技術】
従来、青色や短波長領域の発光素子の材料としてAlGaInN 系の化合物半導体を用いたものが知られている。その化合物半導体は直接遷移型であることから発光効率が高いこと、光の3原色の1つである青色及び緑色を発光色とすること等から注目されている。
【0003】
最近、AlGaInN 系半導体においても、Mgをドープして電子線を照射したり、熱処理によりp型化できることが明らかになった。この結果、従来のn層と半絶縁層(i層)とを接合させたMIS 型構造に換えて、AlGaN のp層と、ZnドープのInGaN の発光層と、AlGaN のn層とを用いたダブルヘテロ構造あるいは単一量子井戸構造の半導体素子が提案されている。
【0004】
上記構造を有する半導体素子のAlGaInN 系半導体は、有機金属化合物気相成長法あるいは分子線成長法等によるエピタキシャル成長により、半導体または絶縁体基板上に形成されている。
【0005】
理想的には、基板として、格子定数および熱膨張係数がAlGaInN 系半導体とほぼ一致し、且つ、エピタキシャル成長時の高温化でも安定した材料が適当である。その観点からは基板に、素子層と同一材料のAlGaInN 系半導体を用いるのが最適である。しかし実際には、基板として利用できる程大面積のAlGaInN 系半導体の単結晶を得ることは、構成元素の窒素の平衡蒸気圧が極めて高いため困難である。しかもその他の材料においても、格子定数および熱膨張係数がAlGaInN 系半導体と近く、且つ、エピタキシャル成長時の高温化でも安定したものは見つからない。
そこで従来の発光ダイオード20は、図5に示すように、AlGaInN 系半導体と格子定数および熱膨張係数が異なるサファイア21あるいは炭化珪素などを基板上に、順次、バッファ層22、GaN のn層23、GaN のn層24、InGaN の活性層25、AlGaN のp層26、GaN のコンタクト層27、電極層28、29を形成したものである。
【0006】
【発明が解決しようとする課題】
ところが上記の素子では製作時に、高温でのAlGaInN 系半導体のエピタキシャル成長終了後、室温まで温度を下げる過程において、基板とAlGaInN 系半導体との熱膨張係数の違いにより、熱応力が発生する。この熱応力により、基板あるいはAlGaInN 系半導体には結晶欠陥やクラック、又反りが発生しやくすなり問題が生じる。
【0007】
このような結晶欠陥やクラックの発生は、素子の電気的特性を悪化させ、歩留りを大きく減じる原因となる。更には、素子の劣化を引き起こし素子寿命を短くしてしまう。
【0008】
また反りの発生は、素子作製時のエッチングや電極形成などの微細加工の精度を低下させて素子特性を悪くしたり、素子の電極や保護膜が剥がれやすくなり信頼性を低下させる要因となる。更に、発光素子がレーザの場合には、発光層の両端面を鏡面として光共振器を構成して、誘導放出により光増幅を行っているが、発光層での反りの発生は光の損失を大きくし、光の増幅利得が低下することにもなる。
【0009】
そこで本発明の目的は、結晶欠陥やクラックが発生せず且つ反りがなく、結果として素子特性や信頼性に優れた3族窒化物半導体素子を提供することである。
【0010】
【課題を解決するための手段】
第1の発明の特徴は、半導体または絶縁体からなる基板と、その上に形成された3族窒化物半導体(AlxGaYIn1-X-YN;0≦X≦1, 0≦Y≦1, 0≦X+Y≦1) から成る多重層から成る発光素子層と、発光素子層に設けられた正及び負電極と、基板において発光素子層が形成されている面と反対側の面にに順に形成された半導体層及び SiO 2 から成る絶縁体層からなる裏面層を有することを特徴とする
【0011】
第2の発明の特徴は、裏面層を形成する半導体層が3族窒化物半導体(AlxGaYIn1-X-YN;0≦X ≦1,0≦Y ≦1, 0≦X+Y ≦1) から成る層であることである。
第3の発明の特徴は、基板がサファイアもしくは炭化珪素であることである。
第4の発明の特徴は、基板の厚さが30〜300μmであることである。
【0012】
【発明の作用及び効果】
上記の発光素子で、正及び負電極が設けられた発光素子層が形成されている面と反対側の基板面に半導体層及び SiO 2 から成る絶縁体層から成る裏面層を形成し、この裏面層の膜厚や層構造、成膜温度等を調整することで、発光素子層にかかる熱応力を低減し、且つ発光素子の反りをなくすことができる。その結果、半導体発光素子の基板や発光素子層における結晶欠陥やクラックの発生が抑えられ、発光素子層の電気的特性が向上し、歩留りを良くすることができる。また発光素子の劣化が殆どなくなり寿命が長くなる。更に、熱応力により発生する反りがなくなるため、発光素子作製時の微細加工の不具合や電極や保護膜のはがれ等がなく、発光素子特性や信頼性に優れる。更に、発光素子の発光層の反りがないために、両端面の鏡面の平行度が高くなると共に光の損失が少なくる。従って、発光層の端面を鏡面とした共振器構造を作製することが容易となり、誘導放出による光の増幅利得を大きくでき、高密度の光出力が得られる。
【0013】
【発明の実施の形態】
以下、本発明を具体的な実施例に基づいて説明する。なお本発明は下記実施例に限定されるものではない。
第1実施例
図1において、発光ダイオード10は、サファイア基板1を有しており、そのサファイア基板1上に0.05μmのAlN バッファ層2が形成されている。そのバッファ層2の上には、順に、膜厚約2.5 μm、電子濃度2 ×1018/cmのシリコン(Si)ドープGaN から成る高キャリア濃度n層3、膜厚約0.5 μm、電子濃度 5×1017/cmのシリコン(Si)ドープの(Alx1Ga1−x1y1In1−y1N から成る高キャリア濃度n層4、膜厚約0.05μm、(Alx2Ga1−x2y2In1−y2N から成り、シリコン(Si)と亜鉛(Zn)が、それぞれ、1 ×1018/cmに添加された活性層5,膜厚約1.0 μm、ホール濃度5 ×1017/cmのマグネシウム(Mg) ドープの(Alx3Ga1−x3y3In1−y3N から成るp層6,膜厚約0.2 μm、ホール濃度7 ×1017/cmのマグネシウム(Mg) ドープのGaN から成るコンタクト層7が形成されている。更に、コンタクト層7に接続する金属電極8とn層3に接続する金属電極9が形成されている。そしてサファイア基板の裏面には、基板に近い方から順に、0.05μmのAlN の裏面バッファ層12、膜厚約4.3 μmのGaN からなる裏面GaN 層13と膜厚約0.15μmのSiO層14が形成されている。
【0014】
尚、素子層はバッファ層2、n層3、n層4、活性層5、p層6、コンタクト層7で構成されており、裏面層は裏面バッファ層12および裏面GaN 層13およびSiO層14で構成されている。
【0015】
次に、この構造の半導体素子の製造方法について説明する。
上記発光ダイオード10は、有機金属気相成長法(以下MOVPE)による気相成長により製造された。
用いられたガスは、アンモニア(NH) 、キャリアガス(H)、トリメチルガリウム(Ga(CH)(以下「TMG 」と記す) 、トリメチルアルミニウム(Al(CH)(以下「TMA 」と記す) 、トリメチルインジウム(In(CH)(以下「TMI 」と記す) 、シラン(SiH)、ジエチル亜鉛(Zn(C)(以下、「DEZ 」と記す) とシクロペンタジエニルマグネシウム(Mg(C)(以下「CPMg 」と記す)である。
【0016】
まず、有機洗浄及び熱処理により洗浄したa面を主面とし、表裏両面が鏡面仕上げされた厚さ30〜300μmの単結晶のサファイア基板1をM0VPE 装置の反応室に載置されたサセプタに、裏面を上にして装着する。次に、常圧でHを流速2 liter/分で約30分間反応室に流しながら温度1100℃でサファイア基板1をベーキングした。
【0017】
次に、温度を 400℃まで低下させて、Hを20 liter/分、NH を10 liter/分、TMA を 1.8×10−5モル/分で約90秒間供給してAlN の裏面バッファ層12を約0.05μmの厚さに形成した。次に、サファイア基板1の温度を1150℃に保持し、Hを20 liter/分、NH を10 liter/分、TMG を 1.7×10−4モル/分で約7 分間導入し、膜厚約4.3 μmの裏面GaN 層13を形成した。次に裏面GaN 層13の上にプラズマCVD法によりSiO層14を0.15μmの厚さに形成し、図2に示すような構造を得た。
【0018】
次に、上記試料を再度M0VPE 装置の反応室に載置されたサセプタに、今度は表面を上にして装着した。続いて、常圧でHを流速2 liter/分で約30分間反応室に流しながら温度1100℃でサファイア基板1をベーキングした。
次に、温度を400 °C まで低下させて、Hを20 liter/分、NH を10 liter/分、TMA を 1.8×10−5モル/分で約90秒間供給してAlN のバッファ層2が約0.05μmの厚さに形成された。次に、サファイア基板1の温度を1150℃に保持し、Hを20 liter/分、NH を10 liter/分、TMG を 1.7×10−4モル/分、Hガスにより0.86ppm に希釈されたシランを20×10−8モル/分で40分導入し、膜厚約2.5 μm、電子濃度2 ×1018/cmのシリコン(Si)ドープGaN から成る高キャリア濃度n層3を形成した。
【0019】
上記の高キャリア濃度n層3を形成した後、続いて温度を1150°C に保持し、N又はHを10 liter/分、NH を10 liter/分、TMG を1.12×10−4モル/分、Hガスのより0.86ppm に希釈されたシランを 1×10−8モル/分で 7分導入し、膜厚約0.5 μm、濃度5 ×1017/cmのシリコンドープのGaN から成るn層4を形成した。
【0020】
続いて、温度を850 ℃に保持し、N又はHを20 liter/分、NH を10 liter/分、TMG を1.53×10−4モル/分、TMI を0.02×10−4モル/分、Hで0.86ppm に希釈されたシランを10×10−8モル/ 分、DEZ を2 ×10−4モル/分で 7分間導入し、膜厚約0.05μmのIn0.08Ga0.92N から成る活性層5を形成した。この活性層5のSi、Zn濃度は1 ×1018/cmであり、キャリ濃度は1 ×1018/cmである。
【0021】
続いて、温度を1100℃に保持し、N又はHを20 liter/分、NH を10 liter/分、TMG を1.12×10−4モル/分、TMA を0.47×10−4モル/分、及び、CPMg を2 ×10−4モル/分で60分間導入し、膜厚約1.0 μmのマグネシウム(Mg)ドープのAl0.08Ga0.92N から成るp層6を形成した。p層6のマグネシウム濃度は1 ×1020/cmである。この状態では、p層6は、まだ、抵抗率10 Ωcm以上の絶縁体である。次に、温度を1100℃に保持し、N又はHを20 liter/分、NH を10 liter/分、TMG を1.12×10−4モル/分、及び、CPMg を2 ×10−4モル/分で 4分間導入し、膜厚約0.2 μmのマグネシウム(Mg)ドープのGaN から成るコンタクト層7を形成した。コンタクト層7のマグネシウム濃度は2 ×1020/cmである。この状態では、コンタクト層7は、まだ、抵抗率10Ωcm以上の絶縁体である。
【0022】
次に、電子線照射装置を用いて、コンタクト層7及びp層6に一様に電子線を照射した。電子線の照射条件は、加速電圧約10KV、資料電流1μA、ビームの移動速度0.2mm/sec 、ビーム径60μmφ、真空度5.0 ×10−5Torrである。この電子線の照射により、コンタクト層7及びp層6は、それぞれ、ホール濃度 7×1017/cm,5×1017/cm、抵抗率 2Ωcm, 0.8 Ωcmのp伝導型半導体となった。このようにして、図3に示すような多層構造のウエハが得られた。
【0023】
続いて図4に示すように、電極9の形成のために、その部分に該当するコンタクト層7、p層6、活性層5、n層4の一部分を、エッチングにより除去した。次に、試料の上全面に、一様にニッケル(Ni)を蒸着し、フォトレジストの塗布、フォトリソグラフィー工程、エッチング工程を経て、コンタクト層7及びn層3の電極8,9をそれぞれ形成した。その後、上記のごとく処理されたウエハは、各素子毎に切断され、図1に示す構造の発光ダイオードを得た。この発光ダイオード10は駆動電流20mAで発光ピーク波長430 nm、発光強度1000mcd であった。
【0024】
次に裏面層を形成した場合と形成しない場合の、試料の反りの測定結果について説明する。図6は裏面層を形成しない場合、図7は裏面層を形成した場合の試料の反りを示している。裏面層を形成しない場合は試料が大きく反っていることが分かる。このような反りは熱応力、特に素子層と基板との界面での応力を増大させ、結晶欠陥やクラックが発生しやすく、素子特性に悪影響を及ぼす。図7に示すように、裏面層を形成することでこのような反りはほとんどなくなり、結晶欠陥やクラックの発生を抑えることができる。
【0025】
尚、本実施例では、活性層5には単層を用いたが、代わりに単一量子井戸構造あるいは多重量子井戸構造を用いても良い。また裏面層にはGaN を用いたが、AlGaInN 、GaAsやSi、ZnO 等の半導体、更に、SiOやSi等の絶縁体を用いても良い。
【0026】
更に、基板としてはサファイアや炭化珪素を好ましく用いることができるが、ZnO やMgAl も用いることができる。
また、基板の厚さは30〜300μmが望ましい。300μmより厚いと各素子の切断がしにくく、30μmより薄いと機械的強度が小さく取扱が困難である。
上記実施例は発光ダイオードについて説明したが、レーザダイオード、光電気変換素子、FETやその他の半導体素子にも応用できる。
【図面の簡単な説明】
【図1】本発明の具体的な実施例に係る発光ダイオードの構成を示した構成図。
【図2】同実施例の発光ダイオードの製造工程を示した断面図。
【図3】同実施例の発光ダイオードの製造工程を示した断面図。
【図4】同実施例の発光ダイオードの製造工程を示した断面図。
【図5】従来の発光ダイオードの構成を示した構成図。
【図6】裏面層を形成しない場合の試料の反りを測定した測定図。
【図7】裏面層を形成した場合の試料の反りを測定した測定図。
【符号の説明】
10…発光ダイオード
1…サファイア基板
2…バッファ層
3…高キャリア濃度nGaN層
4…GaN層
5…活性層
6…p層
7…コンタクト層
8,9…金属電極
12…裏面バッファ層
13…裏面GaN層
14…SiO
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device using a group 3 nitride semiconductor. In particular, the present invention relates to a semiconductor element having excellent element characteristics and reliability.
[0002]
[Prior art]
Conventionally, a material using an AlGaInN based compound semiconductor is known as a material for a light emitting element in a blue or short wavelength region. Since the compound semiconductor is a direct transition type, it has attracted attention because of its high emission efficiency and the use of blue and green as one of the three primary colors of light.
[0003]
Recently, it has become clear that AlGaInN based semiconductors can also be made p-type by doping Mg and irradiating an electron beam or by heat treatment. As a result, an AlGaN p layer, a Zn-doped InGaN light emitting layer, and an AlGaN n layer were used instead of the conventional MIS type structure in which an n layer and a semi-insulating layer (i layer) were joined. A semiconductor device having a double hetero structure or a single quantum well structure has been proposed.
[0004]
The AlGaInN 2 -based semiconductor of the semiconductor element having the above structure is formed on a semiconductor or insulator substrate by epitaxial growth using an organic metal compound vapor phase growth method or a molecular beam growth method.
[0005]
Ideally, a material whose lattice constant and thermal expansion coefficient substantially coincide with those of an AlGaInN-based semiconductor and that is stable even at high temperatures during epitaxial growth is suitable for the substrate. From this point of view, it is optimal to use an AlGaInN semiconductor of the same material as the element layer for the substrate. However, in practice, it is difficult to obtain an AlGaInN semiconductor single crystal having a large area that can be used as a substrate because the equilibrium vapor pressure of nitrogen, which is a constituent element, is extremely high. Moreover, in other materials, a lattice constant and a thermal expansion coefficient are close to those of an AlGaInN-based semiconductor, and stable materials are not found even at high temperatures during epitaxial growth.
Therefore, as shown in FIG. 5, in the conventional light emitting diode 20, sapphire 21 or silicon carbide having a lattice constant and a thermal expansion coefficient different from those of an AlGaInN semiconductor are sequentially formed on a substrate, a buffer layer 22, and a GaN n + layer 23. GaN n layer 24, InGaN active layer 25, AlGaN p layer 26, GaN contact layer 27, and electrode layers 28 and 29 are formed.
[0006]
[Problems to be solved by the invention]
However, in the above element, thermal stress is generated due to the difference in thermal expansion coefficient between the substrate and the AlGaInN semiconductor in the process of lowering the temperature to room temperature after the epitaxial growth of the AlGaInN semiconductor at a high temperature is completed. Due to this thermal stress, crystal defects, cracks, and warpage are likely to occur in the substrate or the AlGaInN semiconductor, resulting in a problem.
[0007]
The occurrence of such crystal defects and cracks deteriorates the electrical characteristics of the device and greatly reduces the yield. Furthermore, it causes deterioration of the device and shortens the device life.
[0008]
In addition, the occurrence of warpage is a factor that deteriorates the accuracy of microfabrication such as etching and electrode formation at the time of device fabrication to deteriorate device characteristics, or causes device electrodes and protective films to be easily peeled off, thereby reducing reliability. Further, when the light emitting element is a laser, an optical resonator is configured with both end faces of the light emitting layer as mirror surfaces and light amplification is performed by stimulated emission. However, warping in the light emitting layer causes loss of light. As a result, the amplification gain of light is lowered.
[0009]
Accordingly, an object of the present invention is to provide a group III nitride semiconductor device that is free from crystal defects and cracks and has no warping, and as a result has excellent device characteristics and reliability.
[0010]
[Means for Solving the Problems]
A feature of the first invention is that a substrate made of a semiconductor or an insulator, and a group III nitride semiconductor (Al x Ga Y In 1-XY N; 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1) formed thereon. , 0 ≦ X + Y ≦ 1), a positive and negative electrode provided on the light emitting device layer, and a surface of the substrate opposite to the surface on which the light emitting device layer is formed. wherein the order is formed of semiconductor layers and SiO 2 having a back surface layer composed of an insulator layer.
[0011]
A feature of the second invention is that the semiconductor layer forming the back layer is a group III nitride semiconductor (Al x Ga Y In 1-XY N; 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ X + Y ≦ 1) It is a layer which consists of.
A feature of the third invention is that the substrate is sapphire or silicon carbide.
A feature of the fourth invention is that the thickness of the substrate is 30 to 300 μm.
[0012]
[Action and effect of the invention]
In the above light emitting device, a back surface layer composed of a semiconductor layer and an insulating layer made of SiO 2 is formed on the substrate surface opposite to the surface on which the light emitting device layer provided with the positive and negative electrodes is formed. By adjusting the film thickness, layer structure, film formation temperature, and the like of the layers, thermal stress applied to the light-emitting element layer can be reduced and warpage of the light-emitting element can be eliminated. As a result, the occurrence of crystal defects and cracks in the substrate and the light emitting element layer of the semiconductor light emitting element can be suppressed, the electrical characteristics of the light emitting element layer can be improved, and the yield can be improved. Further, the light emitting element is hardly deteriorated and the life is extended. Further, since warpage caused by thermal stress is eliminated, there are no problems in microfabrication at the time of manufacturing a light emitting element, peeling of an electrode or a protective film, and the light emitting element characteristics and reliability are excellent. Further, since there is no warp of the light emitting layer of the light emitting element, the parallelism of the mirror surfaces at both end faces is increased and the loss of light is reduced. Therefore, it becomes easy to produce a resonator structure with the end face of the light emitting layer as a mirror surface, the amplification gain of light by stimulated emission can be increased, and a high-density optical output can be obtained.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on specific examples. The present invention is not limited to the following examples.
First embodiment In Fig. 1, a light emitting diode 10 has a sapphire substrate 1, and an AlN buffer layer 2 having a thickness of 0.05 m is formed on the sapphire substrate 1. On the buffer layer 2, in turn, a film thickness of about 2.5 [mu] m, an electron concentration 2 × 10 18 / cm 3 of silicon (Si) of doped GaN high carrier concentration n + layer 3, a thickness of about 0. High carrier concentration n layer 4 made of silicon (Si) -doped (Al x1 Ga 1-x1 ) y1 In 1-y1 N with an electron concentration of 5 × 10 17 / cm 3 , a film thickness of about 0.05 μm, Al x2 Ga 1-x2 ) y2 In 1-y2 N, silicon (Si) and zinc (Zn) added to 1 × 10 18 / cm 3 , respectively, active layer 5, film thickness of about 1.0 μm, p-layer composed of magnesium (Mg) -doped (Al x3 Ga 1-x3 ) y3 In 1-y3 N with a hole concentration of 5 × 10 17 / cm 3 , film thickness of about 0.2 μm, hole concentration of 7 × 10 of 17 / cm 3 magnesium Contact layer 7 made of GaN of beam (Mg) doped is formed. Furthermore, a metal electrode 8 connected to the contact layer 7 and a metal electrode 9 connected to the n + layer 3 are formed. On the back surface of the sapphire substrate, in order from the side closer to the substrate, a back buffer layer 12 of 0.05 μm AlN, a back surface GaN layer 13 made of GaN having a film thickness of about 4.3 μm, and SiO film having a film thickness of about 0.15 μm. Two layers 14 are formed.
[0014]
The element layer is composed of a buffer layer 2, an n + layer 3, an n layer 4, an active layer 5, a p layer 6, and a contact layer 7. The back layer is a back buffer layer 12, a back GaN layer 13, and SiO 2. It is composed of layer 14.
[0015]
Next, a method for manufacturing the semiconductor element having this structure will be described.
The light emitting diode 10 was manufactured by vapor phase growth by metal organic chemical vapor deposition (hereinafter referred to as MOVPE).
The gases used were ammonia (NH 3 ), carrier gas (H 2 ), trimethyl gallium (Ga (CH 3 ) 3 ) (hereinafter referred to as “TMG”), trimethyl aluminum (Al (CH 3 ) 3 ) (hereinafter referred to as “TMG”). referred to as "TMA"), trimethylindium (In (CH 3) 3) ( hereinafter referred to as "TMI"), silane (SiH 4), diethylzinc (Zn (C 2 H 5) 2) ( hereinafter, "DEZ" And cyclopentadienylmagnesium (Mg (C 5 H 5 ) 2 ) (hereinafter referred to as “CP 2 Mg”).
[0016]
First, a single crystal sapphire substrate 1 having a thickness of 30 to 300 μm with the a-side cleaned by organic cleaning and heat treatment as the main surface and mirror-finished on both front and back surfaces is placed on the back surface of the susceptor mounted in the reaction chamber of the M0VPE apparatus. Wear with the face up. Next, the sapphire substrate 1 was baked at a temperature of 1100 ° C. while flowing H 2 at normal pressure and a flow rate of 2 liters / minute into the reaction chamber for about 30 minutes.
[0017]
Next, the temperature was lowered to 400 ° C., H 2 was supplied at 20 liter / min, NH 3 was supplied at 10 liter / min, and TMA was supplied at 1.8 × 10 −5 mol / min for about 90 seconds to make the back side of AlN The buffer layer 12 was formed to a thickness of about 0.05 μm. Next, the temperature of the sapphire substrate 1 is maintained at 1150 ° C., H 2 is introduced at 20 liter / min, NH 3 is introduced at 10 liter / min, and TMG is introduced at 1.7 × 10 −4 mol / min for about 7 minutes, A back GaN layer 13 having a thickness of about 4.3 μm was formed. Next, a SiO 2 layer 14 having a thickness of 0.15 μm was formed on the back GaN layer 13 by plasma CVD to obtain a structure as shown in FIG.
[0018]
Next, the sample was again mounted on the susceptor placed in the reaction chamber of the M0VPE apparatus with the surface facing up. Subsequently, the sapphire substrate 1 was baked at a temperature of 1100 ° C. while flowing H 2 at normal pressure and a flow rate of 2 liters / minute into the reaction chamber for about 30 minutes.
Next, the temperature was lowered to 400 ° C., and H 2 was supplied at 20 liters / minute, NH 3 at 10 liters / minute, and TMA at 1.8 × 10 −5 moles / minute for about 90 seconds to supply AlN 3. The buffer layer 2 was formed to a thickness of about 0.05 μm. Next, the temperature of the sapphire substrate 1 is maintained at 1150 ° C., H 2 is 20 liters / minute, NH 3 is 10 liters / minute, TMG is 1.7 × 10 −4 mol / minute, and H 2 gas is reduced to 0. Silane diluted to 86 ppm is introduced at 20 × 10 −8 mol / min for 40 minutes, and a high carrier concentration of silicon (Si) -doped GaN having a film thickness of about 2.5 μm and an electron concentration of 2 × 10 18 / cm 3. An n + layer 3 was formed.
[0019]
After the high carrier concentration n + layer 3 is formed, the temperature is subsequently maintained at 1150 ° C., N 2 or H 2 is 10 liters / minute, NH 3 is 10 liters / minute, and TMG is 1.12 × Silane diluted to 10 −4 mol / min and 0.86 ppm from H 2 gas was introduced at 1 × 10 −8 mol / min for 7 minutes, and the film thickness was about 0.5 μm and the concentration was 5 × 10 17 / cm. An n layer 4 made of 3 silicon-doped GaN was formed.
[0020]
Subsequently, the temperature is maintained at 850 ° C., N 2 or H 2 is 20 liters / minute, NH 3 is 10 liters / minute, TMG is 1.53 × 10 −4 mol / minute, and TMI is 0.02 × 10. -4 mol / min, silane diluted to 0.86 ppm with H 2 was introduced at 10 × 10 −8 mol / min and DEZ at 2 × 10 −4 mol / min for 7 minutes, and the film thickness was about 0.05 μm. An active layer 5 made of In 0.08 Ga 0.92 N was formed. The active layer 5 has a Si and Zn concentration of 1 × 10 18 / cm 3 and a carry concentration of 1 × 10 18 / cm 3 .
[0021]
Subsequently, the temperature is maintained at 1100 ° C., N 2 or H 2 is 20 liter / min, NH 3 is 10 liter / min, TMG is 1.12 × 10 −4 mol / min, and TMA is 0.47 × 10. -4 mol / min and CP 2 Mg were introduced at 2 × 10 −4 mol / min for 60 minutes, and from about 0.0 μm magnesium (Mg) -doped Al 0.08 Ga 0.92 N A p-layer 6 was formed. The magnesium concentration of the p layer 6 is 1 × 10 20 / cm 3 . In this state, the p layer 6 is still an insulator having a resistivity of 10 8 Ωcm or more. Next, the temperature is maintained at 1100 ° C., N 2 or H 2 is 20 liter / min, NH 3 is 10 liter / min, TMG is 1.12 × 10 −4 mol / min, and CP 2 Mg is 2 A contact layer 7 made of GaN doped with magnesium (Mg) having a film thickness of about 0.2 μm was formed by introducing it at 4 × 4 −4 mol / min for 4 minutes. The magnesium concentration of the contact layer 7 is 2 × 10 20 / cm 3 . In this state, the contact layer 7 is still an insulator having a resistivity of 10 8 Ωcm or more.
[0022]
Next, the electron beam was uniformly irradiated to the contact layer 7 and the p layer 6 using the electron beam irradiation apparatus. The electron beam irradiation conditions are an acceleration voltage of about 10 KV, a data current of 1 μA, a beam moving speed of 0.2 mm / sec, a beam diameter of 60 μmφ, and a degree of vacuum of 5.0 × 10 −5 Torr. By this electron beam irradiation, the contact layer 7 and the p layer 6 are formed into p-conductivity type semiconductors having a hole concentration of 7 × 10 17 / cm 3 , 5 × 10 17 / cm 3 , and resistivity of 2 Ωcm and 0.8 Ωcm, respectively. became. In this way, a wafer having a multilayer structure as shown in FIG. 3 was obtained.
[0023]
Subsequently, as shown in FIG. 4, in order to form the electrode 9, a part of the contact layer 7, p layer 6, active layer 5, and n layer 4 corresponding to that portion was removed by etching. Next, nickel (Ni) is uniformly deposited on the entire upper surface of the sample, and the electrodes 8 and 9 of the contact layer 7 and the n + layer 3 are formed through a photoresist coating, a photolithography process, and an etching process, respectively. did. Thereafter, the wafer processed as described above was cut for each element to obtain a light emitting diode having the structure shown in FIG. The light emitting diode 10 had a driving current of 20 mA, an emission peak wavelength of 430 nm, and an emission intensity of 1000 mcd.
[0024]
Next, the measurement result of the curvature of the sample when the back layer is formed and when it is not formed will be described. 6 shows the warpage of the sample when the back layer is not formed, and FIG. 7 shows the warp of the sample when the back layer is formed. When the back layer is not formed, it can be seen that the sample is greatly warped. Such warpage increases thermal stress, particularly stress at the interface between the element layer and the substrate, and crystal defects and cracks are liable to occur, adversely affecting element characteristics. As shown in FIG. 7, by forming the back surface layer, such warpage is almost eliminated, and generation of crystal defects and cracks can be suppressed.
[0025]
In this embodiment, a single layer is used as the active layer 5, but a single quantum well structure or a multiple quantum well structure may be used instead. Further, although GaN is used for the back layer, a semiconductor such as AlGaInN, GaAs, Si, ZnO 2 , or an insulator such as SiO 2 or Si 3 N 4 may be used.
[0026]
Further, sapphire and silicon carbide can be preferably used as the substrate, but ZnO and MgAl 2 O 4 can also be used.
The thickness of the substrate is preferably 30 to 300 μm. If it is thicker than 300 μm, it is difficult to cut each element, and if it is thinner than 30 μm, mechanical strength is small and handling is difficult.
Although the above embodiment has been described with respect to a light emitting diode, it can also be applied to laser diodes, photoelectric conversion elements, FETs, and other semiconductor elements.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a configuration of a light emitting diode according to a specific embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a manufacturing process of the light-emitting diode of the same example.
FIG. 3 is a cross-sectional view showing a manufacturing process of the light-emitting diode of the example.
FIG. 4 is a cross-sectional view showing a manufacturing process of the light-emitting diode of the same example.
FIG. 5 is a configuration diagram showing a configuration of a conventional light emitting diode.
FIG. 6 is a measurement diagram in which the warpage of a sample when a back layer is not formed is measured.
FIG. 7 is a measurement diagram in which warpage of a sample when a back layer is formed is measured.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Light emitting diode 1 ... Sapphire substrate 2 ... Buffer layer 3 ... High carrier concentration n + GaN layer 4 ... GaN layer 5 ... Active layer 6 ... p layer 7 ... Contact layer 8, 9 ... Metal electrode 12 ... Back surface buffer layer 13 ... Back GaN layer 14 ... SiO 2 layer

Claims (4)

半導体または絶縁体からなる基板と、
その上に形成された3族窒化物半導体(AlxGaYIn1-X-YN;0≦X≦1, 0≦Y≦1, 0≦X+Y≦1) から成る多重層から成る発光素子層と、
当該発光素子層に設けられた正及び負電極と、
前記基板において前記発光素子層が形成されている面と反対側の面に順に形成された半導体層及び SiO 2 から成る絶縁体層からなる裏面層
を有することを特徴とする半導体発光素子。
A substrate made of a semiconductor or an insulator;
A light emitting device comprising a multi-layer formed of a group III nitride semiconductor (Al x Ga Y In 1-XY N; 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ X + Y ≦ 1) formed thereon Layers,
Positive and negative electrodes provided in the light emitting element layer;
A semiconductor light emitting device comprising: a semiconductor layer formed in order on a surface opposite to the surface on which the light emitting device layer is formed in the substrate ; and a back layer made of an insulating layer made of SiO 2 .
前記裏面層を形成する半導体層が3族窒化物半導体(AlxGaYIn1-X-YN;0≦X≦1,0≦Y≦1, 0≦X+Y≦1) から成る層であることを特徴とする請求項1に記載の半導体発光素子。 Semiconductor layer group III nitride semiconductor for forming the back surface layer; is a layer made of (Al x Ga Y In 1- XY N 0 ≦ X ≦ 1,0 ≦ Y ≦ 1, 0 ≦ X + Y ≦ 1) The semiconductor light emitting element according to claim 1. 前記基板がサファイアもしくは炭化珪素であることを特徴とする請求項1に記載の半導体発光素子。The semiconductor light-emitting element according to claim 1, wherein the substrate is sapphire or silicon carbide. 前記基板の厚さが30〜300μmであることを特徴とする請求項1に記載の半導体発光素子。The semiconductor light emitting element according to claim 1, wherein the substrate has a thickness of 30 to 300 μm.
JP15027196A 1996-05-21 1996-05-21 Group 3 nitride semiconductor light emitting device Expired - Fee Related JP3620923B2 (en)

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