JP3617337B2

JP3617337B2 - Pull-up differential bus driver and differential bus drive method

Info

Publication number: JP3617337B2
Application number: JP30995298A
Authority: JP
Inventors: 淳子前田; 直明仲
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1998-10-30
Filing date: 1998-10-30
Publication date: 2005-02-02
Anticipated expiration: 2018-10-30
Also published as: JP2000138577A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップ間において差動信号の伝送を行う場合などに使用して好適なプルアップ型差動バスドライバ及び差動バスドライブ方法に関する。
【０００２】
【従来の技術】
図６は従来のプルアップ型差動バスドライバの一例を含む信号伝送システムの一例の要部を示す回路図である。図６中、１はドライバをなす半導体装置、２はレシーバをなす半導体装置、３、４は半導体装置１、２間を接続する信号線、５、６は終端抵抗、７は終端電圧ＶＴ１を供給する終端電圧線、８は終端電圧ＶＴ２を供給する終端電圧線である。
【０００３】
また、半導体装置１において、９は従来のプルアップ型差動バスドライバ、ＳＩＮ、／ＳＩＮは内部回路（図示せず）からプルアップ型差動バスドライバ９に入力される差動入力信号、１０、１１はプルアップ型差動バスドライバ９から差動出力信号ＳＯＵＴ、／ＳＯＵＴが出力される信号出力端子である。
【０００４】
また、プルアップ型差動バスドライバ９において、１２は電源電圧Ｖ１を供給する電源線、１３は定電流源、１４は入力信号ＳＩＮによりオン、オフが制御されるスイッチング手段、１５は入力信号／ＳＩＮによりオン、オフが制御されるスイッチング手段である。
【０００５】
このように構成された信号伝送システムにおいては、入力信号ＳＩＮ＝Ｈレベル、入力信号／ＳＩＮ＝Ｌレベルとされた場合、スイッチング手段１４＝ＯＮ、スイッチング手段１５＝ＯＦＦとなり、信号線３は、定電流源１３から出力される電流によりプルアップされ、信号線３においては、Ｈレベル信号の伝送が行われると共に、信号線４は、終端抵抗６を介してプルダウンされ、信号線４においては、Ｌレベル信号の伝送が行われる。
【０００６】
これに対して、入力信号ＳＩＮ＝Ｌレベル、入力信号／ＳＩＮ＝Ｈレベルとされた場合には、スイッチング手段１４＝ＯＦＦ、スイッチング手段１５＝ＯＮとなり、信号線３は、終端抵抗５を介してプルダウンされ、信号線３においては、Ｌレベル信号の伝送が行われると共に、信号線４は、定電流源１３から出力される電流によりプルアップされ、信号線４においては、Ｈレベル信号の伝送が行われる。
【０００７】
【発明が解決しようとする課題】
図６に示す信号伝送システムにおいては、終端電圧ＶＴ１、ＶＴ２が電源電圧Ｖ１以下の場合には何ら問題は生じないが、何らかの要因により、終端電圧ＶＴ１又は終端電圧ＶＴ２が上昇して電源電圧Ｖ１よりも高くなり、もしくは、電源電圧Ｖ１が下降して終端電圧ＶＴ１又は終端電圧ＶＴ２が電源電圧Ｖ１よりも高くなることが考えられる。
【０００８】
このように、終端電圧ＶＴ１又は終端電圧ＶＴ２の電圧が電源電圧Ｖ１よりも高くなり、信号線３の電圧又は信号線４の電圧が電源電圧Ｖ１よりも高くなった場合には、半導体装置１においては、スイッチング手段１４又はスイッチング手段１５及び定電流源１３を介して電源線１２に電流が流れ込み、誤動作を誘発してしまうおそれがある。
【０００９】
本発明は、かかる点に鑑み、何らかの要因で信号線の電圧が電源電圧よりも高くなった時であっても、信号線側から電源線側に電流が流れ込まないようにし、プルアップ型差動バスドライバを搭載すべき半導体装置に搭載する場合には、信号線側から電源線側に電流が流れ込むことによる誤動作を回避し、信頼性の向上を図ることができるようにしたプルアップ型差動バスドライバを提供することを第１の目的とする。
【００１０】
また、本発明は、何らかの要因で信号線の電圧が電源電圧よりも高くなった時であっても、信号線側から電源線側に電流が流れ込まないようにし、プルアップ型差動バスドライバを搭載すべき半導体装置に適用する場合には、信号線側から電源線側に電流が流れ込むことによる誤動作を回避し、信頼性の向上を図ることができるようにした差動バスドライブ方法を提供することを第２の目的とする。
【００１１】
【課題を解決するための手段】
本発明のプルアップ型差動バスドライバは、上流端を電源電圧を供給する電源線に接続した定電流源と、一端を前記定電流源の下流端に接続し、他端を第１の信号線が接続される第１の信号出力端子に接続し、差動入力信号のうちの一方の信号によりオン、オフが制御される第１のスイッチング手段と、一端を前記定電流源の下流端に接続し、他端を第２の信号線が接続される第２の信号出力端子に接続し、差動入力信号のうちの他方の信号によりオン、オフが制御される第２のスイッチング手段とを備えるプルアップ型差動バスドライバにおいて、前記定電流源は、第１の信号線及び第２の信号線の一方又は両方の電圧が電源電圧よりも高くなった時、第１の信号線側及び第２の信号線側の一方又は両方から電源線側に電流が流れ込まないように制御する制御回路を含めて構成されているというものである。
【００１２】
本発明のプルアップ型差動バスドライバによれば、定電流源は、第１の信号線及び第２の信号線の一方又は両方の電圧が電源電圧よりも高くなった時、第１の信号線側及び第２の信号線側の一方又は両方から電源線側に電流が流れ込まないように制御する制御回路を含めて構成されているので、何らかの要因で、第１の信号線及び第２の信号線の一方又は両方の電圧が電源電圧よりも高くなった時であっても、第１の信号線側及び第２の信号線側の一方又は両方から電源線側に電流が流れ込まないようにすることができる。
【００１３】
本発明の差動バスドライブ方法は、上流端を電源電圧を供給する電源線に接続した定電流源と、一端を前記定電流源の下流端に接続し、他端を第１の信号線が接続される第１の信号出力端子に接続し、差動入力信号のうちの一方の信号によりオン、オフが制御される第１のスイッチング手段と、一端を前記定電流源の下流端に接続し、他端を第２の信号線が接続される第２の信号出力端子に接続し、差動入力信号のうちの他方の信号によりオン、オフが制御される第２のスイッチング手段とを備えるプルアップ型差動バスドライバを使用して第１の信号線及び第２の信号線をドライブする差動バスドライブ方法であって、第１の信号線及び第２の信号線の一方又は両方の電圧が電源電圧よりも高くなった時、第１の信号線側及び第２の信号線側の一方又は両方から電源線側に電流が流れ込まないように制御する工程を含むというものである。
【００１４】
本発明の差動バスドライブ方法によれば、定電流源は、第１の信号線及び第２の信号線の一方又は両方の電圧が電源電圧よりも高くなった時、第１の信号線側及び第２の信号線側の一方又は両方から電源線側に電流が流れ込まないように制御する工程を含んでいるので、何らかの要因で、第１の信号線及び第２の信号線の一方又は両方の電圧が電源電圧よりも高くなった時であっても、第１の信号線側及び第２の信号線側の一方又は両方から電源線側に電流が流れ込まないようにすることができる。
【００１５】
【発明の実施の形態】
以下、図１〜図５を参照して、本発明のプルアップ型差動バスドライバの第１実施形態〜第５実施形態について、本発明の差動バスドライブ方法の実施形態を含めて説明する。
【００１６】
第１実施形態・・図１
図１は本発明のプルアップ型差動バスドライバの第１実施形態を含む信号伝送システムの一例の要部を示す回路図である。図１中、２０はドライバをなす半導体装置、２１はレシーバをなす半導体装置、２２、２３は半導体装置２０、２１間を接続する信号線、２４、２５は終端抵抗、２６は終端電圧ＶＴ１を供給する終端電圧線、２７は終端電圧ＶＴ２を供給する終端電圧線である。
【００１７】
また、半導体装置２０において、２８は本発明のプルアップ型差動バスドライバの第１実施形態、ＳＩＮ、／ＳＩＮは内部回路（図示せず）から本発明のプルアップ型差動バスドライバの第１実施形態２８に入力される差動入力信号、２９、３０は本発明のプルアップ型差動バスドライバの第１実施形態２８から差動出力信号ＳＯＵＴ、／ＳＯＵＴが出力される信号出力端子である。
【００１８】
また、本発明のプルアップ型差動バスドライバの第１実施形態２８において、３１は電源電圧Ｖ１を供給する電源線、３２は定電流源、３３は入力信号ＳＩＮが入力される第１のスイッチング手段をなすＮチャネルＭＯＳトランジスタ（以下、ＮＭＯＳトランジスタという）、３４は入力信号／ＳＩＮによりオン、オフが制御される第２のスイッチング手段をなすＮＭＯＳトランジスタである。
【００１９】
ここに、定電流源３２は、上流端３２Ａを電源線３１に接続され、ＮＭＯＳトランジスタ３３は、ドレインを定電流源３２の下流端３２Ｂに接続され、ソースを信号出力端子２９に接続され、ＮＭＯＳトランジスタ３４は、ドレインを定電流源３２の下流端３２Ｂに接続され、ソースを信号出力端子３０に接続されている。
【００２０】
また、定電流源３２において、３５は定電流生成用のＰチャネルＭＯＳトランジスタ（以下、ＰＭＯＳトランジスタという）、３６は定電流生成のためにＰＭＯＳトランジスタ３５のゲートに供給すべきバイアス電圧を発生するバイアス回路、３７は第３の制御回路をなす制御回路、３８は第４の制御回路をなす制御回路である。
【００２１】
ここに、制御回路３７は、信号線２２の電圧又は信号線２３の電圧が電源電圧Ｖ１よりも低い時は、バイアス電圧をＰＭＯＳトランジスタ３５に供給し、信号線２２の電圧又は信号線２３の電圧が電源電圧Ｖ１よりも高い時は、信号線２２の電圧及び信号線２３の電圧のうちの高い方の電圧をＰＭＯＳトランジスタ３５のゲートに供給するものである。
【００２２】
制御回路３７において、３９は電源電圧Ｖ１を供給する電源線、４０はＮＭＯＳトランジスタであり、ＮＭＯＳトランジスタ４０は、ドレインをバイアス回路のバイアス電圧出力端に接続され、ゲートを電源線３９に接続され、ソースをＰＭＯＳトランジスタ３５のゲートに接続されている。
【００２３】
ＮＭＯＳトランジスタ４０は、後述するように、ＰＭＯＳトランジスタ３５のゲートに信号線２２の電圧又は信号線２３の電圧を供給してＰＭＯＳトランジスタ３５をオフとする場合に、バイアス回路３６側に電流が流れ込まないようにするためのものである。
【００２４】
また、４１は電源電圧Ｖ１を供給する電源線、４２、４３はＰＭＯＳトランジスタ、４４は第５の制御回路をなす制御回路、４５は第６の制御回路をなす制御回路である。
【００２５】
ＰＭＯＳトランジスタ４２は、信号線２２の電圧が電源電圧Ｖ１よりも高い時は、信号線２２の電圧をＰＭＯＳトランジスタ３５のゲートに供給してＰＭＯＳトランジスタ３５をオフとするものであり、ソースをＰＭＯＳトランジスタ３５のゲートに接続され、ゲートを電源線４１に接続され、ドレインを信号出力端子２９に接続されている。
【００２６】
また、ＰＭＯＳトランジスタ４３は、信号線２３の電圧が電源電圧Ｖ１よりも高い時は、信号線２３の電圧をＰＭＯＳトランジスタ３５のゲートに供給してＰＭＯＳトランジスタ３５をオフとするものであり、ソースをＰＭＯＳトランジスタ３５のゲートに接続され、ゲートを電源線４１に接続され、ドレインを信号出力端子３０に接続されている。
【００２７】
また、制御回路４４は、信号線２２が電源電圧Ｖ１よりも低い時は、ＰＭＯＳトランジスタ４２のウエルに電源電圧Ｖ１を供給し、信号線２２が電源電圧Ｖ１よりも高い時は、ＰＭＯＳトランジスタ４２のウエルに信号線２２の電圧を供給し、ＰＭＯＳトランジスタ４２のドレイン・ウエル間を逆バイアス状態に維持するものである。
【００２８】
制御回路４４において、４６、４７は電源電圧Ｖ１を供給する電源線、４８、４９はＰＭＯＳトランジスタであり、ＰＭＯＳトランジスタ４８は、ソースを電源線４６に接続され、ゲートを信号出力端子２９に接続され、ドレイン及びウエルをＰＭＯＳトランジスタ４２のウエルに接続され、ＰＭＯＳトランジスタ４９は、ソース及びウエルをＰＭＯＳトランジスタ４２のウエルに接続され、ゲートを電源線４７に接続され、ドレインを信号出力端子２９に接続されている。
【００２９】
また、制御回路４５は、信号線２３が電源電圧Ｖ１よりも低い時は、ＰＭＯＳトランジスタ４３のウエルに電源電圧Ｖ１を供給し、信号線２３が電源電圧Ｖ１よりも高い時は、ＰＭＯＳトランジスタ４３のウエルに信号線２３の電圧を供給し、ＰＭＯＳトランジスタ４３のドレイン・ウエル間を逆バイアス状態に維持するものである。
【００３０】
制御回路４５において、５０、５１が電源電圧Ｖ１を供給する電源線、５２、５３はＰＭＯＳトランジスタであり、ＰＭＯＳトランジスタ５２は、ソースを電源線５０に接続され、ゲートを信号出力端子３０に接続され、ドレイン及びウエルをＰＭＯＳトランジスタ４３のウエルに接続され、ＰＭＯＳトランジスタ５３は、ソース及びウエルをＰＭＯＳトランジスタ４３のウエルに接続され、ゲートを電源線５１に接続され、ドレインを信号出力端子３０に接続されている。
【００３１】
また、制御回路３８は、ＰＭＯＳトランジスタ３５のドレインの電圧が電源電圧Ｖ１よりも低い時は、ＰＭＯＳトランジスタ３５のウエルに電源電圧Ｖ１を供給し、ＰＭＯＳトランジスタ３５のドレインの電圧が電源電圧Ｖ１よりも高い時は、ＰＭＯＳトランジスタ３５のウエルにＰＭＯＳトランジスタ３５のドレインの電圧を供給し、ＰＭＯＳトランジスタ３５のドレイン・ウエル間を逆バイアス状態に維持するものである。
【００３２】
制御回路３８において、５４、５５は電源電圧Ｖ１を供給する電源線、５６、５７はＰＭＯＳトランジスタであり、ＰＭＯＳトランジスタ５６は、ソースを電源線５４に接続され、ゲートをＰＭＯＳトランジスタ３５のドレインに接続され、ドレイン及びウエルをＰＭＯＳトランジスタ３５のウエルに接続され、ＰＭＯＳトランジスタ５７は、ソース及びウエルをＰＭＯＳトランジスタ３５のウエルに接続され、ゲートを電源線５５に接続され、ドレインをＰＭＯＳトランジスタ３５のドレインに接続されている。
【００３３】
このように構成された信号伝送システムにおいては、信号線２２の電圧及び信号線２３の電圧が電源電圧Ｖ１よりも低い時は、制御回路３７においては、ＰＭＯＳトランジスタ４２＝ＯＦＦ、ＰＭＯＳトランジスタ４３＝ＯＦＦとなり、ＰＭＯＳトランジスタ３５のゲートにはバイアス回路３６から出力されるバイアス電圧がＮＭＯＳトランジスタ４０を介して供給され、ＰＭＯＳトランジスタ３５により定電流が生成される。
【００３４】
また、この場合、制御回路４４においては、ＰＭＯＳトランジスタ４８＝ＯＮ、ＰＭＯＳトランジスタ４９＝ＯＦＦとなり、ＰＭＯＳトランジスタ４２のウエルには電源電圧Ｖ１が供給され、ＰＭＯＳトランジスタ４２のドレイン・ウエル間は逆バイアス状態に維持される。
【００３５】
また、制御回路４５においては、ＰＭＯＳトランジスタ５２＝ＯＮ、ＰＭＯＳトランジスタ５３＝ＯＦＦとなり、ＰＭＯＳトランジスタ４３のウエルには電源電圧Ｖ１が供給され、ＰＭＯＳトランジスタ４３のドレイン・ウエル間は逆バイアス状態に維持される。
【００３６】
また、制御回路３８においては、ＰＭＯＳトランジスタ５６＝ＯＮ、ＰＭＯＳトランジスタ５７＝ＯＦＦとなり、ＰＭＯＳトランジスタ３５のウエルには電源電圧Ｖ１が供給され、ＰＭＯＳトランジスタ３５のドレイン・ウエル間は逆バイアス状態に維持される。
【００３７】
ここに、ＮＭＯＳトランジスタ３３のオン時に、何らかの要因で、信号線２２の電圧が電源電圧Ｖ１よりも高くなった場合、制御回路３７においては、ＰＭＯＳトランジスタ４２＝ＯＮとなり、ＰＭＯＳトランジスタ３５のゲートには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ３５＝ＯＦＦとされると共に、ＮＭＯＳトランジスタ４０＝ＯＦＦとなり、バイアス回路３６に電流が流れ込むことが防止される。
【００３８】
また、制御回路４４においては、ＰＭＯＳトランジスタ４８＝ＯＦＦ、ＰＭＯＳトランジスタ４９＝ＯＮとなり、ＰＭＯＳトランジスタ４２のウエルには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ４２のドレイン・ウエル間は逆バイアス状態に維持される。
【００３９】
また、制御回路３８においては、ＰＭＯＳトランジスタ５６＝ＯＦＦ、ＰＭＯＳトランジスタ５７＝ＯＮとなり、ＰＭＯＳトランジスタ３５のウエルには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ３５のドレイン・ウエル間は逆バイアス状態に維持される。
【００４０】
また、ＮＭＯＳトランジスタ３４のオン時に、何らかの要因で、信号線２３の電圧が電源電圧Ｖ１よりも高くなった場合、制御回路３７においては、ＰＭＯＳトランジスタ４３＝ＯＮとなり、ＰＭＯＳトランジスタ３５のゲートには信号線２３の電圧が供給され、ＰＭＯＳトランジスタ３５＝ＯＦＦとされると共に、ＮＭＯＳトランジスタ４０＝ＯＦＦとなり、バイアス回路３６に電流が流れ込むことが防止される。
【００４１】
また、制御回路４５においては、ＰＭＯＳトランジスタ５２＝ＯＦＦ、ＰＭＯＳトランジスタ５３＝ＯＮとなり、ＰＭＯＳトランジスタ４３のウエルには信号線２３の電圧が供給され、ＰＭＯＳトランジスタ４３のドレイン・ウエル間は逆バイアス状態に維持される。
【００４２】
また、制御回路３８においては、ＰＭＯＳトランジスタ５６＝ＯＦＦ、ＰＭＯＳトランジスタ５７＝ＯＮとなり、ＰＭＯＳトランジスタ３５のウエルには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ３５のドレイン・ウエル間は逆バイアス状態に維持される。
【００４３】
したがって、本発明のプルアップ型差動バスドライバの第１実施形態２８によれば、何らかの要因で、信号線２２及び信号線２３の一方又は両方の電圧が電源電圧Ｖ１よりも高くなった時であっても、信号線２２側及び信号線２３側の一方又は両方から電源線３１側に電流が流れ込まないようにすることができるので、信号線２２側及び信号線２３側の一方又は両方から電源線３１側に電流が流れ込むことによる半導体装置２０の誤動作を回避し、半導体装置２０の信頼性の向上を図ることができる。
【００４４】
第２実施形態・・図２
図２は本発明のプルアップ型差動バスドライバの第２実施形態を含む信号伝送システムの一例の要部を示す回路図である。図２に示す信号伝送システムは、図１に示す半導体装置２０と回路構成の異なる半導体装置５９を使用し、その他については、図１に示す信号伝送システムと同様に構成したものである。
【００４５】
半導体装置５９は、図１に示す本発明のプルアップ型差動バスドライバの第１実施形態２８の代わりに、本発明のプルアップ型差動バスドライバの第２実施形態６０を設け、その他については、図１に示す半導体装置２０と同様に構成したものである。
【００４６】
本発明のプルアップ型差動バスドライバの第２実施形態６０は、第１、第２のスイッチング手段として、図１に示すＮＭＯＳトランジスタ３３、３４の代わりに、ＰＭＯＳトランジスタ６１、６２を使用すると共に、ＰＭＯＳトランジスタ６１、６２のウエルの電圧を制御する第１、第２の制御回路をなす制御回路６３、６４を設け、その他については、図１に示す本発明のプルアップ型差動バスドライバの第１実施形態２８と同様に構成したものである。
【００４７】
制御回路６３は、信号線２２の電圧が電源電圧Ｖ１よりも低い時は、ＰＭＯＳトランジスタ６１のウエルに電源電圧Ｖ１を供給し、信号線２２の電圧が電源電圧Ｖ１よりも高い時は、ＰＭＯＳトランジスタ６１のウエルに信号線２２の電圧を供給し、ＰＭＯＳトランジスタ６１のドレイン・ウエル間を逆バイアス状態に維持するものである。
【００４８】
制御回路６３において、６５、６６は電源電圧Ｖ１を供給する電源線、６７、６８はＰＭＯＳトランジスタであり、ＰＭＯＳトランジスタ６７は、ソースを電源線６５に接続され、ゲートを信号出力端子２９に接続され、ドレイン及びウエルをＰＭＯＳトランジスタ６１のウエルに接続され、ＰＭＯＳトランジスタ６８は、ソース及びウエルをＰＭＯＳトランジスタ６１のウエルに接続され、ゲートを電源線６６に接続され、ドレインを信号出力端子２９に接続されている。
【００４９】
また、制御回路６４は、信号線２３の電圧が電源電圧Ｖ１よりも低い時は、ＰＭＯＳトランジスタ６２のウエルに電源電圧Ｖ１を供給し、信号線２３の電圧が電源電圧Ｖ１よりも高い時は、ＰＭＯＳトランジスタ６２のウエルに信号線２３の電圧を供給し、ＰＭＯＳトランジスタ６２のドレイン・ウエル間を逆バイアス状態に維持するものである。
【００５０】
制御回路６４において、６９、７０は電源電圧Ｖ１を供給する電源線、７１、７２はＰＭＯＳトランジスタであり、ＰＭＯＳトランジスタ７１は、ソースを電源線６９に接続され、ゲートを信号出力端子３０に接続され、ドレイン及びウエルをＰＭＯＳトランジスタ６２のウエルに接続され、ＰＭＯＳトランジスタ７２は、ソース及びウエルをＰＭＯＳトランジスタ６２のウエルに接続され、ゲートを電源線７０に接続され、ドレインを信号出力端子３０に接続されている。
【００５１】
このように構成された信号伝送システムにおいては、信号線２２の電圧及び信号線２３の電圧が電源電圧Ｖ１よりも低い時は、制御回路６３においては、ＰＭＯＳトランジスタ６７＝ＯＮ、ＰＭＯＳトランジスタ６８＝ＯＦＦとなり、ＰＭＯＳトランジスタ６１のウエルには電源電圧Ｖ１が供給され、ＰＭＯＳトランジスタ６１のドレイン・ウエル間は逆バイアス状態に維持される。
【００５２】
また、制御回路６４においては、ＰＭＯＳトランジスタ７１＝ＯＮ、ＰＭＯＳトランジスタ７２＝ＯＦＦとなり、ＰＭＯＳトランジスタ６２のウエルには電源電圧Ｖ１が供給され、ＰＭＯＳトランジスタ６２のドレイン・ウエル間は逆バイアス状態に維持される。
【００５３】
ここに、ＰＭＯＳトランジスタ６１のオン時に、何らかの要因で、信号線２２の電圧が電源電圧Ｖ１よりも高くなった場合、制御回路６３においては、ＰＭＯＳトランジスタ６７＝ＯＦＦ、ＰＭＯＳトランジスタ６８＝ＯＮとなり、ＰＭＯＳトランジスタ６１のウエルには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ６１のドレイン・ウエル間は逆バイアス状態に維持される。
【００５４】
また、ＰＭＯＳトランジスタ６２のオン時に、何らかの要因で、信号線２３の電圧が電源電圧Ｖ１よりも高くなった場合、制御回路６４においては、ＰＭＯＳトランジスタ７１＝ＯＦＦ、ＰＭＯＳトランジスタ７２＝ＯＮとなり、ＰＭＯＳトランジスタ６２のウエルには信号線２３の電圧が供給され、ＰＭＯＳトランジスタ６２のドレイン・ウエル間は逆バイアス状態に維持される。
【００５５】
したがって、本発明のプルアップ型差動バスドライバの第２実施形態６０によれば、何らかの要因で、信号線２２及び信号線２３の一方又は両方の電圧が電源電圧Ｖ１よりも高くなった時であっても、信号線２２側及び信号線２３側の一方又は両方から電源線３１側に電流が流れ込まないようにすることができるので、信号線２２側及び信号線２３側の一方又は両方から電源線３１側に電流が流れ込むことによる半導体装置５９の誤動作を回避し、半導体装置５９の信頼性の向上を図ることができる。
【００５６】
第３実施形態・・図３
図３は本発明のプルアップ型差動バスドライバの第３実施形態を含む信号伝送システムの一例の要部を示す回路図である。図３に示す信号伝送システムは、図２に示す半導体装置５９と回路構成の異なる半導体装置７４を使用し、その他については、図２に示す信号伝送システムと同様に構成したものである。
【００５７】
半導体装置７４は、図２に示す本発明のプルアップ型差動バスドライバの第２実施形態６０の代わりに、本発明のプルアップ型差動バスドライバの第３実施形態７５を設け、その他については、図２に示す半導体装置５９と同様に構成したものである。
【００５８】
本発明のプルアップ型差動バスドライバの第３実施形態７５は、ＰＭＯＳトランジスタ４２、６１のウエル及びＰＭＯＳトランジスタ４３、６２のウエルをそれぞれ共通化すると共に、図２に示す制御回路６３、６４を設けないようにし、その他については、図２に示す本発明のプルアップ型差動バスドライバの第２実施形態６０と同様に構成したものである。
【００５９】
このように構成された本発明のプルアップ型差動バスドライバの第３実施形態７５においては、ＰＭＯＳトランジスタ６１のドレイン・ウエル間の逆バイアス状態は、制御回路４４により維持され、ＰＭＯＳトランジスタ６２のドレイン・ウエル間の逆バイアス状態は、制御回路４５により維持される。
【００６０】
したがって、本発明のプルアップ型差動バスドライバの第３実施形態７５によれば、何らかの要因で、信号線２２及び信号線２３の一方又は両方の電圧が電源電圧Ｖ１よりも高くなった時であっても、信号線２２側及び信号線２３側の一方又は両方から電源線３１側に電流が流れ込まないようにすることができるので、信号線２２側及び信号線２３側の一方又は両方から電源線３１側に電流が流れ込むことによる半導体装置７４の誤動作を回避し、半導体装置７４の信頼性の向上を図ることができる。
【００６１】
なお、ＰＭＯＳトランジスタ４２、６１のウエル及びＰＭＯＳトランジスタ４３、６２のウエルをそれぞれ共通化すると共に、制御回路４４、４５の代わりに、図３に示す制御回路６３、６４を設けるようにしても良い。
【００６２】
第４実施形態・・図４
図４は本発明のプルアップ型差動バスドライバの第４実施形態を含む信号伝送システムの一例の要部を示す回路図である。図４に示す信号伝送システムは、図３に示す半導体装置７４と回路構成の異なる半導体装置７７を使用し、その他については、図３に示す信号伝送システムと同様に構成したものである。
【００６３】
半導体装置７７は、図３に示す本発明のプルアップ型差動バスドライバの第３実施形態７５の代わりに、本発明のプルアップ型差動バスドライバの第４実施形態７８を搭載し、その他については、図３に示す半導体装置７４と同様に構成したものである。
【００６４】
本発明のプルアップ型差動バスドライバの第４実施形態７８は、図３に示す定電流源３２と回路構成の異なる定電流源７９を搭載すると共に、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のウエルを共通化し、その他については、図３に示す本発明のプルアップ型差動バスドライバの第３実施形態７５と同様に構成したものである。
【００６５】
定電流源７９は、第３の制御回路として制御回路８０を設けると共に、第４の制御回路として、制御回路８１を設け、その他については、図３に示す定電流源３２と同様に構成したものである。
【００６６】
制御回路８０は、図３に示す制御回路３７が備える制御回路４４、４５を設けないようにし、その他については、図３に示す制御回路３７と同様に構成したものである。
【００６７】
また、制御回路８１は、信号線２２の電圧及び信号線２３の電圧が電源電圧Ｖ１よりも低い時は、ＰＭＯＳトランジスタ３５のウエルに電源電圧Ｖ１を供給し、信号線２２の電圧又は信号線２３の電圧が電源電圧Ｖ１よりも高い時は、ＰＭＯＳトランジスタ３５のウエルに信号線２２の電圧及び信号線２３の電圧のうちの高い方の電圧を供給し、ＰＭＯＳトランジスタ３５のドレイン・ウエル間を逆バイアス状態に維持するものである。
【００６８】
制御回路８１において、８２〜８４は電源電圧Ｖ１を供給する電源線、８５〜８７はＰＭＯＳトランジスタ、８８は第７の制御回路をなす制御回路であり、８９、９０はＰＭＯＳトランジスタである。
【００６９】
ここに、ＰＭＯＳトランジスタ８５は、ソースを電源線８２に接続され、ドレイン及びウエルをＰＭＯＳトランジスタ３５のウエルに接続され、ＰＭＯＳトランジスタ８６は、ソース及びウエルをＰＭＯＳトランジスタ３５のウエルに接続され、ゲートを電源線８３に接続され、ドレインを信号出力端子２９に接続され、ＰＭＯＳトランジスタ８７は、ソース及びウエルをＰＭＯＳトランジスタ３５のウエルに接続され、ゲートを電源線８４に接続され、ドレインを信号出力端子３０に接続されている。
【００７０】
また、ＰＭＯＳトランジスタ８９は、ソースをＰＭＯＳトランジスタ８５のゲートに接続され、ゲートを信号出力端子３０に接続され、ドレインを信号出力端子２９に接続され、ウエルをＰＭＯＳトランジスタ３５のウエルに接続され、ＰＭＯＳトランジスタ９０は、ソースをＰＭＯＳトランジスタ８５のゲートに接続され、ゲートを信号出力端子２９に接続され、ドレインを信号出力端子３０に接続され、ウエルをＰＭＯＳトランジスタ３５のウエルに接続されている。
【００７１】
このように構成された信号伝送システムにおいては、信号線２２の電圧及び信号線２３の電圧が電源電圧Ｖ１よりも低い時は、ＰＭＯＳトランジスタ８６＝ＯＦＦ、ＰＭＯＳトランジスタ８７＝ＯＦＦとなる。
【００７２】
また、この時、信号線２２の電圧が信号線２３の電圧よりも低い時は、ＰＭＯＳトランジスタ８９＝ＯＦＦ、ＰＭＯＳトランジスタ９０＝ＯＮとなり、ＰＭＯＳトランジスタ８５のゲートには信号線２３の電圧が供給され、ＰＭＯＳトランジスタ８５＝ＯＮとなる。
【００７３】
これに対して、信号線２３の電圧が信号線２２の電圧よりも低い時は、ＰＭＯＳトランジスタ８９＝ＯＮ、ＰＭＯＳトランジスタ９０＝ＯＦＦとなり、ＰＭＯＳトランジスタ８５のゲートには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ８５＝ＯＮとなる。
【００７４】
この結果、信号線２２の電圧及び信号線２３の電圧が電源電圧Ｖ１よりも低い時は、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のウエルには電源電圧Ｖ１が供給され、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のドレイン・ソース間は逆バイアス状態に維持される。
【００７５】
また、ＰＭＯＳトランジスタ６１のオン時に、何らかの要因で、信号線２２の電圧が電源電圧Ｖ１よりも高くなった場合、制御回路８０においては、ＰＭＯＳトランジスタ４２＝ＯＮとなり、ＰＭＯＳトランジスタ３５のゲートには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ３５＝ＯＦＦとなる。
【００７６】
また、制御回路８１においては、ＰＭＯＳトランジスタ８９＝ＯＮとなり、ＰＭＯＳトランジスタ８５のゲートには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ８５＝ＯＦＦとなると共に、ＰＭＯＳトランジスタ８６＝ＯＮとなる。
【００７７】
この結果、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のウエルには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のドレイン・ウエル間は逆バイアス状態が維持される。
【００７８】
したがって、本発明のプルアップ型差動バスドライバの第４実施形態７８によれば、何らかの要因で、信号線２２の電圧又は信号線２３の電圧が電源電圧Ｖ１よりも高くなった時であっても、信号線２２又は信号線２３側から電源線３１側に電流が流れ込まないようにすることができるので、信号線２２側又は信号線２３側から電源線３１側に電流が流れ込むことによる半導体装置７７の誤動作を回避し、半導体装置７７の信頼性の向上を図ることができる。
【００７９】
第５実施形態・・図５
図５は本発明のプルアップ型差動バスドライバの第５実施形態を含む信号伝送システムの一例の要部を示す回路図である。図５中、９２はドライバをなす半導体装置、９３はレシーバをなす半導体装置、９４、９５は半導体装置９２、９３間を接続する信号線、９６は半導体装置９２側の終端抵抗、９７、９８は半導体装置９３側の終端抵抗、９９は終端電圧ＶＴを供給する終端電圧線である。
【００８０】
半導体装置９２は、図４に示す本発明のプルアップ型差動バスドライバの第４実施形態７８の代わりに、本発明のプルアップ型差動バスドライバの第５実施形態１００を搭載すると共に、制御用端子１０１を設け、その他については、図４に示す半導体装置７７と同様に構成したものである。なお、制御用端子１０１は、終端抵抗９６内の端子に接続されている。
【００８１】
本発明のプルアップ型差動バスドライバの第５実施形態１００は、図４に示す定電流源７９と回路構成の異なる定電流源１０２を設け、その他については、図４に示す本発明のプルアップ型差動バスドライバの第４実施形態７８と同様に構成したものである。
【００８２】
定電流源１０２は、第４の制御回路として制御回路１０３を設け、その他については、図４に示す制御回路８１と同様に構成したものであり、制御回路１０３は、図４に示す制御回路８１が設ける制御回路８８を設けないようにすると共に、ＰＭＯＳトランジスタ８５のゲートを制御用端子１０１に接続し、その他については、制御回路８１と同様に構成したものである。
【００８３】
このように構成された信号伝送システムにおいては、信号線２２の電圧及び信号線２３の電圧が電源電圧Ｖ１よりも低い時は、ＰＭＯＳトランジスタ８６＝ＯＦＦ、ＰＭＯＳトランジスタ８７＝ＯＦＦとなると共に、ＰＭＯＳトランジスタ８５＝ＯＮとなる。
【００８４】
この結果、信号線２２の電圧及び信号線２３の電圧が電源電圧Ｖ１よりも低い時は、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のウエルには電源電圧Ｖ１が供給され、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のドレイン・ウエル間は逆バイアス状態に維持される。
【００８５】
また、何らかの要因で、信号線２２の電圧の電圧が電源電圧Ｖ１よりも高くなった場合、制御回路８０においては、ＰＭＯＳトランジスタ４２＝ＯＮとなり、ＰＭＯＳトランジスタ３５のゲートには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ３５＝ＯＦＦとなる。
【００８６】
また、制御回路１０３においては、ＰＭＯＳトランジスタ８５のゲートには終端電圧ＶＴが供給され、ＰＭＯＳトランジスタ８５＝ＯＦＦとなると共に、ＰＭＯＳトランジスタ８６＝ＯＮとなる。
【００８７】
この結果、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のウエルには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のドレイン・ウエル間は逆バイアス状態が維持される。
【００８８】
また、何らかの要因で、信号線２３の電圧が電源電圧Ｖ１よりも高くなった場合、制御回路８０においては、ＰＭＯＳトランジスタ４３＝ＯＮとなり、ＰＭＯＳトランジスタ３５のゲートには信号線２３の電圧が供給され、ＰＭＯＳトランジスタ３５＝ＯＦＦとなる。
【００８９】
また、制御回路１０３においては、ＰＭＯＳトランジスタ８５のゲートには終端電圧ＶＴが供給され、ＰＭＯＳトランジスタ８５＝ＯＦＦとなると共に、ＰＭＯＳトランジスタ８７＝ＯＮとなる。
【００９０】
この結果、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のウエルには信号線２２の電圧が供給され、ＰＭＯＳトランジスタ３５、４２、４３、６１、６２のドレイン・ウエル間は逆バイアス状態が維持される。
【００９１】
したがって、本発明のプルアップ型差動バスドライバの第５実施形態１００によれば、何らかの要因で、信号線２２及び信号線２３の一方又は両方の電圧が電源電圧Ｖ１よりも高くなった時であっても、信号線２２側及び信号線２３側の一方又は両方から電源線３１側に電流が流れ込まないようにすることができるので、信号線２２側及び信号線２３側の一方又は両方から電源線３１側に電流が流れ込むことによる半導体装置９２の誤動作を回避し、半導体装置９２の信頼性の向上を図ることができる。
【００９２】
なお、本発明のプルアップ型差動バスドライバの第５実施形態１００においては、制御用端子１０１を終端抵抗９６内の端子に接続するようにしているが、制御用端子１０１を設けず、ＰＭＯＳトランジスタ８５のゲートを信号出力端子２９又は信号出力端子３０に接続するようにしても良い。
【００９３】
【発明の効果】
以上のように、本発明のプルアップ型差動バスドライバによれば、定電流源は、第１の信号線の電圧及び第２の信号線の一方又は両方の電圧が電源電圧よりも高くなった時、第１の信号線側又は第２の信号線側の一方又は両方から電源線側に電流が流れ込まないように制御する制御回路を含めて構成するとしたことにより、何らかの要因で、第１の信号線の電圧及び第２の信号線の一方又は両方の電圧が電源電圧よりも高くなった時であっても、第１の信号線側又は第２の信号線側の一方又は両方から電源線側に電流が流れ込まないようにすることができるので、プルアップ型差動バスドライバを搭載すべき半導体装置に搭載する場合には、信号線側から電源線側に電流が流れ込むことによる誤動作を回避し、信頼性の向上を図ることができる。
【００９４】
また、本発明の差動バスドライブ方法によれば、第１の信号線の電圧及び第２の信号線の一方又は両方の電圧が電源電圧よりも高くなった時、第１の信号線側又は第２の信号線側の一方又は両方から電源線側に電流が流れ込まないように制御する工程を含めるとしたことにより、何らかの要因で、第１の信号線の電圧及び第２の信号線の一方又は両方の電圧が電源電圧よりも高くなった時であっても、第１の信号線側又は第２の信号線側の一方又は両方から電源線側に電流が流れ込まないようにすることができるので、プルアップ型差動バスドライバを搭載すべき半導体装置に適用する場合には、信号線側から電源線側に電流が流れ込むことによる誤動作を回避し、信頼性の向上を図ることができる。
【図面の簡単な説明】
【図１】本発明のプルアップ型差動バスドライバの第１実施形態を含む信号伝送システムの一例の要部を示す回路図である。
【図２】本発明のプルアップ型差動バスドライバの第２実施形態を含む信号伝送システムの一例の要部を示す回路図である。
【図３】本発明のプルアップ型差動バスドライバの第３実施形態を含む信号伝送システムの一例の要部を示す回路図である。
【図４】本発明のプルアップ型差動バスドライバの第４実施形態を含む信号伝送システムの一例の要部を示す回路図である。
【図５】本発明のプルアップ型差動バスドライバの第５実施形態を含む信号伝送システムの一例の要部を示す回路図である。
【図６】従来のプルアップ型差動バスドライバの一例を含む信号伝送システムの一例の要部を示す回路図である。
【符号の説明】
Ｖ１電源電圧
ＶＴ１、ＶＴ２、ＶＴ終端電圧[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pull-up type differential bus driver and a differential bus drive method suitable for use in transmitting differential signals between semiconductor chips.
[0002]
[Prior art]
FIG. 6 is a circuit diagram showing a main part of an example of a signal transmission system including an example of a conventional pull-up type differential bus driver. In FIG. 6, 1 is a semiconductor device that forms a driver, 2 is a semiconductor device that forms a receiver, 3 and 4 are signal lines connecting the semiconductor devices 1 and 2, 5 and 6 are termination resistors, and 7 is a termination voltage VT1. The termination voltage line 8 is a termination voltage line for supplying the termination voltage VT2.
[0003]
In the semiconductor device 1, reference numeral 9 denotes a conventional pull-up differential bus driver, and SIN and / SIN denote differential input signals input from the internal circuit (not shown) to the pull-up differential bus driver 9. , 11 are signal output terminals to which differential output signals SOUT, / SOUT are output from the pull-up type differential bus driver 9.
[0004]
In the pull-up type differential bus driver 9, reference numeral 12 denotes a power supply line for supplying a power supply voltage V1, 13 a constant current source, 14 a switching means whose on / off is controlled by an input signal SIN, and 15 an input signal / This switching means is controlled to be turned on and off by SIN.
[0005]
In the signal transmission system configured as described above, when the input signal SIN = H level and the input signal / SIN = L level, the switching means 14 = ON and the switching means 15 = OFF, and the signal line 3 is fixed. Pulled up by the current output from the current source 13, the signal line 3 transmits an H level signal, the signal line 4 is pulled down via the termination resistor 6, and the signal line 4 has L A level signal is transmitted.
[0006]
On the other hand, when the input signal SIN = L level and the input signal / SIN = H level, the switching means 14 = OFF and the switching means 15 = ON, and the signal line 3 is connected via the termination resistor 5. The signal line 3 is pulled down to transmit the L level signal, and the signal line 4 is pulled up by the current output from the constant current source 13. The signal line 4 transmits the H level signal. Done.
[0007]
[Problems to be solved by the invention]
In the signal transmission system shown in FIG. 6, no problem occurs when the termination voltages VT1 and VT2 are equal to or lower than the power supply voltage V1, but the termination voltage VT1 or the termination voltage VT2 rises due to some factor and exceeds the power supply voltage V1. Or the termination voltage VT1 or the termination voltage VT2 becomes higher than the power supply voltage V1.
[0008]
As described above, when the voltage of the termination voltage VT1 or the termination voltage VT2 becomes higher than the power supply voltage V1, and the voltage of the signal line 3 or the voltage of the signal line 4 becomes higher than the power supply voltage V1, the semiconductor device 1 May cause a current to flow into the power supply line 12 via the switching means 14 or the switching means 15 and the constant current source 13 and induce a malfunction.
[0009]
In view of this point, the present invention prevents pull-up differentials from flowing from the signal line side to the power supply line side even when the voltage of the signal line becomes higher than the power supply voltage for some reason. When mounted on a semiconductor device that should be equipped with a bus driver, a pull-up differential that prevents malfunction caused by current flowing from the signal line side to the power supply line side and improves reliability A first object is to provide a bus driver.
[0010]
Further, the present invention prevents a current from flowing from the signal line side to the power supply line side even when the voltage of the signal line becomes higher than the power supply voltage for some reason. When applied to a semiconductor device to be mounted, there is provided a differential bus drive method capable of avoiding malfunction caused by current flowing from a signal line side to a power supply line side and improving reliability. This is the second purpose.
[0011]
[Means for Solving the Problems]
The pull-up type differential bus driver of the present invention has a constant current source having an upstream end connected to a power supply line for supplying a power supply voltage, one end connected to the downstream end of the constant current source, and the other end to a first signal. A first switching means connected to a first signal output terminal to which the line is connected and controlled to be turned on / off by one of the differential input signals; and one end at the downstream end of the constant current source And a second switching means whose other end is connected to a second signal output terminal to which the second signal line is connected, and which is controlled to be turned on / off by the other signal of the differential input signals. In the pull-up type differential bus driver provided, the constant current source includes the first signal line side when the voltage of one or both of the first signal line and the second signal line becomes higher than the power supply voltage. Current does not flow from one or both of the second signal line side to the power line side Is that is configured to include a control circuit for controlled so.
[0012]
According to the pull-up type differential bus driver of the present invention, the constant current source includes the first signal when the voltage of one or both of the first signal line and the second signal line becomes higher than the power supply voltage. Since the control circuit is configured to control so that current does not flow from one or both of the line side and the second signal line side to the power supply line side, the first signal line and the second signal line for some reason. Even when the voltage of one or both of the signal lines becomes higher than the power supply voltage, current does not flow from one or both of the first signal line side and the second signal line side to the power supply line side. can do.
[0013]
The differential bus drive method of the present invention includes a constant current source having an upstream end connected to a power supply line for supplying a power supply voltage, one end connected to the downstream end of the constant current source, and the other end connected to a first signal line. Connected to the first signal output terminal to be connected, connected to the first switching means whose on / off is controlled by one of the differential input signals, and one end connected to the downstream end of the constant current source. And a second switching means having the other end connected to the second signal output terminal to which the second signal line is connected, and being controlled to be turned on and off by the other signal of the differential input signals. A differential bus driving method for driving a first signal line and a second signal line using an up-type differential bus driver, the voltage of one or both of the first signal line and the second signal line When becomes higher than the power supply voltage, the first signal line side and the second signal line Current from one or both of the power supply line side is that it comprises a step of controlling so as not flowing.
[0014]
According to the differential bus driving method of the present invention, the constant current source is connected to the first signal line side when the voltage of one or both of the first signal line and the second signal line becomes higher than the power supply voltage. And a step of controlling so that current does not flow from one or both of the second signal line side to the power supply line side, and therefore, one or both of the first signal line and the second signal line for some reason. Even when the voltage becomes higher than the power supply voltage, current can be prevented from flowing into the power supply line from one or both of the first signal line side and the second signal line side.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
The first to fifth embodiments of the pull-up type differential bus driver of the present invention will be described below including the embodiments of the differential bus drive method of the present invention with reference to FIGS. .
[0016]
First Embodiment FIG. 1
FIG. 1 is a circuit diagram showing a main part of an example of a signal transmission system including the first embodiment of the pull-up type differential bus driver of the present invention. In FIG. 1, 20 is a semiconductor device that forms a driver, 21 is a semiconductor device that forms a receiver, 22 and 23 are signal lines connecting the semiconductor devices 20 and 21, 24 and 25 are termination resistors, and 26 is a termination voltage VT <b> 1. The terminating voltage line 27 is a terminating voltage line that supplies the terminating voltage VT2.
[0017]
In the semiconductor device 20, reference numeral 28 denotes the first embodiment of the pull-up differential bus driver of the present invention, and SIN and / SIN denote the first embodiment of the pull-up differential bus driver of the present invention from an internal circuit (not shown). Differential input signals 29 and 30 input to the first embodiment 28 are signal output terminals from which the differential output signals SOUT and / SOUT are output from the first embodiment 28 of the pull-up type differential bus driver of the present invention. is there.
[0018]
In the first embodiment 28 of the pull-up differential bus driver according to the present invention, reference numeral 31 denotes a power supply line for supplying a power supply voltage V1, 32 denotes a constant current source, and 33 denotes a first switching to which an input signal SIN is inputted. An N-channel MOS transistor (hereinafter referred to as an NMOS transistor) 34 serving as a means is an NMOS transistor serving as a second switching means whose on / off is controlled by an input signal / SIN.
[0019]
Here, the constant current source 32 has an upstream end 32A connected to the power supply line 31, and the NMOS transistor 33 has a drain connected to the downstream end 32B of the constant current source 32, a source connected to the signal output terminal 29, and an NMOS. The transistor 34 has a drain connected to the downstream end 32 </ b> B of the constant current source 32 and a source connected to the signal output terminal 30.
[0020]
In the constant current source 32, 35 is a P channel MOS transistor (hereinafter referred to as a PMOS transistor) for generating a constant current, and 36 is a bias for generating a bias voltage to be supplied to the gate of the PMOS transistor 35 for generating a constant current. The circuit 37 is a control circuit forming a third control circuit, and 38 is a control circuit forming a fourth control circuit.
[0021]
Here, the control circuit 37 supplies a bias voltage to the PMOS transistor 35 when the voltage of the signal line 22 or the voltage of the signal line 23 is lower than the power supply voltage V1, and the voltage of the signal line 22 or the voltage of the signal line 23 is supplied. Is higher than the power supply voltage V 1, the higher one of the voltage of the signal line 22 and the voltage of the signal line 23 is supplied to the gate of the PMOS transistor 35.
[0022]
In the control circuit 37, 39 is a power supply line for supplying the power supply voltage V1, 40 is an NMOS transistor, the NMOS transistor 40 has a drain connected to the bias voltage output terminal of the bias circuit, a gate connected to the power supply line 39, The source is connected to the gate of the PMOS transistor 35.
[0023]
As will be described later, when the NMOS transistor 40 supplies the voltage of the signal line 22 or the voltage of the signal line 23 to the gate of the PMOS transistor 35 to turn off the PMOS transistor 35, no current flows into the bias circuit 36 side. It is for doing so.
[0024]
Reference numeral 41 denotes a power supply line for supplying the power supply voltage V1, 42 and 43 are PMOS transistors, 44 is a control circuit forming a fifth control circuit, and 45 is a control circuit forming a sixth control circuit.
[0025]
When the voltage of the signal line 22 is higher than the power supply voltage V1, the PMOS transistor 42 supplies the voltage of the signal line 22 to the gate of the PMOS transistor 35 to turn off the PMOS transistor 35, and the source is the PMOS transistor. The gate is connected to the power supply line 41, and the drain is connected to the signal output terminal 29.
[0026]
The PMOS transistor 43 supplies the voltage of the signal line 23 to the gate of the PMOS transistor 35 to turn off the PMOS transistor 35 when the voltage of the signal line 23 is higher than the power supply voltage V1. The PMOS transistor 35 is connected to the gate, the gate is connected to the power supply line 41, and the drain is connected to the signal output terminal 30.
[0027]
The control circuit 44 supplies the power supply voltage V1 to the well of the PMOS transistor 42 when the signal line 22 is lower than the power supply voltage V1, and controls the PMOS transistor 42 when the signal line 22 is higher than the power supply voltage V1. The voltage of the signal line 22 is supplied to the well and the drain-well of the PMOS transistor 42 is maintained in a reverse bias state.
[0028]
In the control circuit 44, 46 and 47 are power supply lines for supplying the power supply voltage V 1, 48 and 49 are PMOS transistors, and the PMOS transistor 48 has a source connected to the power supply line 46 and a gate connected to the signal output terminal 29. The drain and well are connected to the well of the PMOS transistor 42, the PMOS transistor 49 has the source and well connected to the well of the PMOS transistor 42, the gate connected to the power supply line 47, and the drain connected to the signal output terminal 29. ing.
[0029]
The control circuit 45 supplies the power supply voltage V1 to the well of the PMOS transistor 43 when the signal line 23 is lower than the power supply voltage V1, and controls the PMOS transistor 43 when the signal line 23 is higher than the power supply voltage V1. The voltage of the signal line 23 is supplied to the well and the drain-well of the PMOS transistor 43 is maintained in a reverse bias state.
[0030]
In the control circuit 45, 50 and 51 are power supply lines for supplying the power supply voltage V 1, 52 and 53 are PMOS transistors, and the PMOS transistor 52 has a source connected to the power supply line 50 and a gate connected to the signal output terminal 30. The drain and well are connected to the well of the PMOS transistor 43. The PMOS transistor 53 has the source and well connected to the well of the PMOS transistor 43, the gate connected to the power supply line 51, and the drain connected to the signal output terminal 30. ing.
[0031]
When the drain voltage of the PMOS transistor 35 is lower than the power supply voltage V1, the control circuit 38 supplies the power supply voltage V1 to the well of the PMOS transistor 35, and the drain voltage of the PMOS transistor 35 is higher than the power supply voltage V1. When the voltage is high, the drain voltage of the PMOS transistor 35 is supplied to the well of the PMOS transistor 35, and the drain-well of the PMOS transistor 35 is maintained in a reverse bias state.
[0032]
In the control circuit 38, 54 and 55 are power supply lines for supplying the power supply voltage V 1, 56 and 57 are PMOS transistors, and the PMOS transistor 56 has a source connected to the power supply line 54 and a gate connected to the drain of the PMOS transistor 35. The drain and well are connected to the well of the PMOS transistor 35. The PMOS transistor 57 has the source and well connected to the well of the PMOS transistor 35, the gate connected to the power supply line 55, and the drain connected to the drain of the PMOS transistor 35. It is connected.
[0033]
In the signal transmission system configured as described above, when the voltage of the signal line 22 and the voltage of the signal line 23 are lower than the power supply voltage V1, the PMOS transistor 42 = OFF and the PMOS transistor 43 = OFF in the control circuit 37. Thus, the bias voltage output from the bias circuit 36 is supplied to the gate of the PMOS transistor 35 via the NMOS transistor 40, and a constant current is generated by the PMOS transistor 35.
[0034]
In this case, in the control circuit 44, the PMOS transistor 48 = ON and the PMOS transistor 49 = OFF, the power supply voltage V1 is supplied to the well of the PMOS transistor 42, and the drain-well of the PMOS transistor 42 is in a reverse bias state. Maintained.
[0035]
In the control circuit 45, the PMOS transistor 52 = ON and the PMOS transistor 53 = OFF, the power supply voltage V1 is supplied to the well of the PMOS transistor 43, and the drain-well of the PMOS transistor 43 is maintained in the reverse bias state. The
[0036]
In the control circuit 38, the PMOS transistor 56 = ON and the PMOS transistor 57 = OFF, the power supply voltage V1 is supplied to the well of the PMOS transistor 35, and the drain-well of the PMOS transistor 35 is maintained in the reverse bias state. The
[0037]
Here, when the voltage of the signal line 22 becomes higher than the power supply voltage V1 for some reason when the NMOS transistor 33 is turned on, the PMOS transistor 42 is turned ON in the control circuit 37, and the gate of the PMOS transistor 35 is connected. The voltage of the signal line 22 is supplied, the PMOS transistor 35 is turned off, and the NMOS transistor 40 is turned off, preventing current from flowing into the bias circuit 36.
[0038]
In the control circuit 44, the PMOS transistor 48 = OFF and the PMOS transistor 49 = ON, the voltage of the signal line 22 is supplied to the well of the PMOS transistor 42, and the drain and well of the PMOS transistor 42 are in a reverse bias state. Maintained.
[0039]
In the control circuit 38, the PMOS transistor 56 = OFF and the PMOS transistor 57 = ON, the voltage of the signal line 22 is supplied to the well of the PMOS transistor 35, and the drain and well of the PMOS transistor 35 are in a reverse bias state. Maintained.
[0040]
Further, when the voltage of the signal line 23 becomes higher than the power supply voltage V1 for some reason when the NMOS transistor 34 is turned on, in the control circuit 37, the PMOS transistor 43 = ON, and the gate of the PMOS transistor 35 has a signal. The voltage of the line 23 is supplied, the PMOS transistor 35 is turned off, and the NMOS transistor 40 is turned off, preventing current from flowing into the bias circuit 36.
[0041]
In the control circuit 45, the PMOS transistor 52 = OFF and the PMOS transistor 53 = ON, the voltage of the signal line 23 is supplied to the well of the PMOS transistor 43, and the drain-well of the PMOS transistor 43 is in a reverse bias state. Maintained.
[0042]
In the control circuit 38, the PMOS transistor 56 = OFF and the PMOS transistor 57 = ON, the voltage of the signal line 22 is supplied to the well of the PMOS transistor 35, and the drain and well of the PMOS transistor 35 are in a reverse bias state. Maintained.
[0043]
Therefore, according to the first embodiment 28 of the pull-up type differential bus driver of the present invention, when the voltage of one or both of the signal line 22 and the signal line 23 becomes higher than the power supply voltage V1 for some reason. Even in such a case, current can be prevented from flowing into the power supply line 31 from one or both of the signal line 22 side and the signal line 23 side, so that power is supplied from one or both of the signal line 22 side and the signal line 23 side. The malfunction of the semiconductor device 20 due to the current flowing into the line 31 can be avoided, and the reliability of the semiconductor device 20 can be improved.
[0044]
Second Embodiment FIG. 2
FIG. 2 is a circuit diagram showing a main part of an example of a signal transmission system including the second embodiment of the pull-up type differential bus driver of the present invention. The signal transmission system shown in FIG. 2 uses a semiconductor device 59 having a circuit configuration different from that of the semiconductor device 20 shown in FIG. 1, and is otherwise configured in the same manner as the signal transmission system shown in FIG.
[0045]
The semiconductor device 59 is provided with a second embodiment 60 of the pull-up differential bus driver of the present invention instead of the first embodiment 28 of the pull-up differential bus driver of the present invention shown in FIG. These are configured similarly to the semiconductor device 20 shown in FIG.
[0046]
The second embodiment 60 of the pull-up differential bus driver of the present invention uses PMOS transistors 61 and 62 instead of the NMOS transistors 33 and 34 shown in FIG. 1 as the first and second switching means. , Control circuits 63 and 64 forming first and second control circuits for controlling the voltages of the wells of the PMOS transistors 61 and 62 are provided, and the others are provided in the pull-up type differential bus driver of the present invention shown in FIG. The configuration is the same as in the first embodiment 28.
[0047]
The control circuit 63 supplies the power supply voltage V1 to the well of the PMOS transistor 61 when the voltage of the signal line 22 is lower than the power supply voltage V1, and the PMOS transistor when the voltage of the signal line 22 is higher than the power supply voltage V1. The voltage of the signal line 22 is supplied to the well 61 and the drain-well of the PMOS transistor 61 is maintained in a reverse bias state.
[0048]
In the control circuit 63, 65 and 66 are power supply lines for supplying the power supply voltage V 1, 67 and 68 are PMOS transistors, and the PMOS transistor 67 has a source connected to the power supply line 65 and a gate connected to the signal output terminal 29. The drain and well are connected to the well of the PMOS transistor 61. The PMOS transistor 68 has the source and well connected to the well of the PMOS transistor 61, the gate connected to the power supply line 66, and the drain connected to the signal output terminal 29. ing.
[0049]
The control circuit 64 supplies the power supply voltage V1 to the well of the PMOS transistor 62 when the voltage of the signal line 23 is lower than the power supply voltage V1, and when the voltage of the signal line 23 is higher than the power supply voltage V1, The voltage of the signal line 23 is supplied to the well of the PMOS transistor 62, and the drain-well of the PMOS transistor 62 is maintained in a reverse bias state.
[0050]
In the control circuit 64, 69 and 70 are power supply lines for supplying the power supply voltage V 1, 71 and 72 are PMOS transistors, and the PMOS transistor 71 has a source connected to the power supply line 69 and a gate connected to the signal output terminal 30. The drain and well are connected to the well of the PMOS transistor 62. The PMOS transistor 72 has the source and well connected to the well of the PMOS transistor 62, the gate connected to the power supply line 70, and the drain connected to the signal output terminal 30. ing.
[0051]
In the signal transmission system configured as described above, when the voltage of the signal line 22 and the voltage of the signal line 23 are lower than the power supply voltage V1, in the control circuit 63, the PMOS transistor 67 = ON and the PMOS transistor 68 = OFF. Thus, the power supply voltage V1 is supplied to the well of the PMOS transistor 61, and the drain and well of the PMOS transistor 61 are maintained in the reverse bias state.
[0052]
In the control circuit 64, the PMOS transistor 71 = ON and the PMOS transistor 72 = OFF, the power supply voltage V1 is supplied to the well of the PMOS transistor 62, and the drain-well of the PMOS transistor 62 is maintained in the reverse bias state. The
[0053]
Here, when the voltage of the signal line 22 becomes higher than the power supply voltage V1 for some reason when the PMOS transistor 61 is turned on, in the control circuit 63, the PMOS transistor 67 = OFF and the PMOS transistor 68 = ON. The voltage of the signal line 22 is supplied to the well of the transistor 61, and the drain and well of the PMOS transistor 61 are maintained in a reverse bias state.
[0054]
When the voltage of the signal line 23 becomes higher than the power supply voltage V1 for some reason when the PMOS transistor 62 is turned on, the PMOS transistor 71 = OFF and the PMOS transistor 72 = ON in the control circuit 64. The well of 62 is supplied with the voltage of the signal line 23, and the drain-well of the PMOS transistor 62 is maintained in a reverse bias state.
[0055]
Therefore, according to the second embodiment 60 of the pull-up type differential bus driver of the present invention, when the voltage of one or both of the signal line 22 and the signal line 23 becomes higher than the power supply voltage V1 for some reason. Even in such a case, current can be prevented from flowing into the power supply line 31 from one or both of the signal line 22 side and the signal line 23 side, so that power is supplied from one or both of the signal line 22 side and the signal line 23 side. The malfunction of the semiconductor device 59 due to the current flowing into the line 31 can be avoided, and the reliability of the semiconductor device 59 can be improved.
[0056]
Third Embodiment FIG. 3
FIG. 3 is a circuit diagram showing a main part of an example of a signal transmission system including the third embodiment of the pull-up type differential bus driver of the present invention. The signal transmission system shown in FIG. 3 uses a semiconductor device 74 having a circuit configuration different from that of the semiconductor device 59 shown in FIG. 2, and is otherwise configured in the same manner as the signal transmission system shown in FIG.
[0057]
The semiconductor device 74 is provided with a third embodiment 75 of the pull-up type differential bus driver of the present invention instead of the second embodiment 60 of the pull-up type differential bus driver of the present invention shown in FIG. Is configured similarly to the semiconductor device 59 shown in FIG.
[0058]
The third embodiment 75 of the pull-up type differential bus driver of the present invention shares the wells of the PMOS transistors 42 and 61 and the wells of the PMOS transistors 43 and 62, and includes the control circuits 63 and 64 shown in FIG. The other configurations are the same as those of the second embodiment 60 of the pull-up type differential bus driver of the present invention shown in FIG.
[0059]
In the third embodiment 75 of the pull-up type differential bus driver of the present invention thus configured, the reverse bias state between the drain and well of the PMOS transistor 61 is maintained by the control circuit 44, and the PMOS transistor 62 The reverse bias state between the drain and the well is maintained by the control circuit 45.
[0060]
Therefore, according to the third embodiment 75 of the pull-up type differential bus driver of the present invention, when the voltage of one or both of the signal line 22 and the signal line 23 becomes higher than the power supply voltage V1 for some reason. Even in such a case, current can be prevented from flowing into the power supply line 31 from one or both of the signal line 22 side and the signal line 23 side, so that power is supplied from one or both of the signal line 22 side and signal line 23 side. The malfunction of the semiconductor device 74 due to the current flowing into the line 31 can be avoided, and the reliability of the semiconductor device 74 can be improved.
[0061]
In addition, the wells of the PMOS transistors 42 and 61 and the wells of the PMOS transistors 43 and 62 may be made common, and the control circuits 63 and 64 shown in FIG.
[0062]
Fourth Embodiment FIG. 4
FIG. 4 is a circuit diagram showing a main part of an example of a signal transmission system including the fourth embodiment of the pull-up type differential bus driver of the present invention. The signal transmission system shown in FIG. 4 uses a semiconductor device 77 having a circuit configuration different from that of the semiconductor device 74 shown in FIG. 3, and is otherwise configured in the same manner as the signal transmission system shown in FIG.
[0063]
The semiconductor device 77 includes the fourth embodiment 78 of the pull-up differential bus driver of the present invention instead of the third embodiment 75 of the pull-up differential bus driver of the present invention shown in FIG. Is configured similarly to the semiconductor device 74 shown in FIG.
[0064]
The fourth embodiment 78 of the pull-up type differential bus driver of the present invention is equipped with a constant current source 79 having a circuit configuration different from that of the constant current source 32 shown in FIG. 3, and PMOS transistors 35, 42, 43, 61, 62 wells are shared, and the others are configured in the same manner as the third embodiment 75 of the pull-up differential bus driver of the present invention shown in FIG.
[0065]
The constant current source 79 is provided with a control circuit 80 as a third control circuit, a control circuit 81 as a fourth control circuit, and the others are configured similarly to the constant current source 32 shown in FIG. It is.
[0066]
The control circuit 80 is configured not to include the control circuits 44 and 45 included in the control circuit 37 shown in FIG. 3, and is otherwise configured in the same manner as the control circuit 37 shown in FIG.
[0067]
Further, when the voltage of the signal line 22 and the voltage of the signal line 23 are lower than the power supply voltage V1, the control circuit 81 supplies the power supply voltage V1 to the well of the PMOS transistor 35, and the voltage of the signal line 22 or the signal line 23 is supplied. Is higher than the power supply voltage V1, the higher of the voltage of the signal line 22 and the voltage of the signal line 23 is supplied to the well of the PMOS transistor 35, and the drain and well of the PMOS transistor 35 are reversed. The bias state is maintained.
[0068]
In the control circuit 81, 82 to 84 are power supply lines for supplying the power supply voltage V1, 85 to 87 are PMOS transistors, 88 is a control circuit constituting a seventh control circuit, and 89 and 90 are PMOS transistors.
[0069]
Here, the PMOS transistor 85 has a source connected to the power supply line 82, a drain and a well connected to the well of the PMOS transistor 35, and a PMOS transistor 86 has a source and well connected to the well of the PMOS transistor 35, and a gate connected to the well. The PMOS transistor 87 has a source and well connected to the well of the PMOS transistor 35, a gate connected to the power supply line 84, and a drain connected to the signal output terminal 30. It is connected to the.
[0070]
The PMOS transistor 89 has a source connected to the gate of the PMOS transistor 85, a gate connected to the signal output terminal 30, a drain connected to the signal output terminal 29, a well connected to the well of the PMOS transistor 35, and a PMOS. The transistor 90 has a source connected to the gate of the PMOS transistor 85, a gate connected to the signal output terminal 29, a drain connected to the signal output terminal 30, and a well connected to the well of the PMOS transistor 35.
[0071]
In the signal transmission system configured as described above, when the voltage of the signal line 22 and the voltage of the signal line 23 are lower than the power supply voltage V1, the PMOS transistor 86 = OFF and the PMOS transistor 87 = OFF.
[0072]
At this time, when the voltage of the signal line 22 is lower than the voltage of the signal line 23, the PMOS transistor 89 = OFF and the PMOS transistor 90 = ON, and the voltage of the signal line 23 is supplied to the gate of the PMOS transistor 85. The PMOS transistor 85 is turned ON.
[0073]
On the other hand, when the voltage of the signal line 23 is lower than the voltage of the signal line 22, the PMOS transistor 89 = ON and the PMOS transistor 90 = OFF, and the voltage of the signal line 22 is supplied to the gate of the PMOS transistor 85. PMOS transistor 85 = ON.
[0074]
As a result, when the voltage of the signal line 22 and the voltage of the signal line 23 are lower than the power supply voltage V1, the power supply voltage V1 is supplied to the wells of the PMOS transistors 35, 42, 43, 61, 62, and the PMOS transistors 35, The drain and source of 42, 43, 61 and 62 are maintained in a reverse bias state.
[0075]
Further, when the voltage of the signal line 22 becomes higher than the power supply voltage V1 for some reason when the PMOS transistor 61 is turned on, in the control circuit 80, the PMOS transistor 42 = ON, and the gate of the PMOS transistor 35 has a signal. The voltage of the line 22 is supplied, and the PMOS transistor 35 is turned OFF.
[0076]
In the control circuit 81, the PMOS transistor 89 is turned ON, the voltage of the signal line 22 is supplied to the gate of the PMOS transistor 85, the PMOS transistor 85 is turned OFF, and the PMOS transistor 86 is turned ON.
[0077]
As a result, the voltage of the signal line 22 is supplied to the wells of the PMOS transistors 35, 42, 43, 61, 62, and the reverse bias state is maintained between the drain and well of the PMOS transistors 35, 42, 43, 61, 62. The
[0078]
Therefore, according to the fourth embodiment 78 of the pull-up differential bus driver of the present invention, when the voltage of the signal line 22 or the voltage of the signal line 23 becomes higher than the power supply voltage V1 for some reason. In addition, since it is possible to prevent current from flowing from the signal line 22 or the signal line 23 side to the power supply line 31 side, a semiconductor device by which current flows from the signal line 22 side or the signal line 23 side to the power supply line 31 side. 77 can be avoided, and the reliability of the semiconductor device 77 can be improved.
[0079]
Fifth embodiment FIG. 5
FIG. 5 is a circuit diagram showing an essential part of an example of a signal transmission system including the fifth embodiment of the pull-up type differential bus driver of the present invention. In FIG. 5, 92 is a semiconductor device that constitutes a driver, 93 is a semiconductor device that constitutes a receiver, 94 and 95 are signal lines connecting between the semiconductor devices 92 and 93, 96 is a termination resistor on the semiconductor device 92 side, and 97 and 98 are A termination resistor 99 on the semiconductor device 93 side is a termination voltage line for supplying a termination voltage VT.
[0080]
The semiconductor device 92 includes the fifth embodiment 100 of the pull-up differential bus driver of the present invention instead of the fourth embodiment 78 of the pull-up differential bus driver of the present invention shown in FIG. The control terminal 101 is provided, and the others are configured similarly to the semiconductor device 77 shown in FIG. Note that the control terminal 101 is connected to a terminal in the termination resistor 96.
[0081]
The fifth embodiment 100 of the pull-up type differential bus driver of the present invention is provided with a constant current source 102 having a circuit configuration different from that of the constant current source 79 shown in FIG. The up-type differential bus driver is configured similarly to the fourth embodiment 78.
[0082]
The constant current source 102 is provided with a control circuit 103 as a fourth control circuit, and the others are configured similarly to the control circuit 81 shown in FIG. 4, and the control circuit 103 is configured by the control circuit 81 shown in FIG. The control circuit 88 provided is not provided, the gate of the PMOS transistor 85 is connected to the control terminal 101, and the rest is configured in the same manner as the control circuit 81.
[0083]
In the signal transmission system configured as described above, when the voltage of the signal line 22 and the voltage of the signal line 23 are lower than the power supply voltage V1, the PMOS transistor 86 = OFF and the PMOS transistor 87 = OFF, and the PMOS transistor 85 = ON.
[0084]
As a result, when the voltage of the signal line 22 and the voltage of the signal line 23 are lower than the power supply voltage V1, the power supply voltage V1 is supplied to the wells of the PMOS transistors 35, 42, 43, 61, 62, and the PMOS transistors 35, Between the drains and wells 42, 43, 61 and 62, the reverse bias state is maintained.
[0085]
Further, when the voltage of the signal line 22 becomes higher than the power supply voltage V1 for some reason, in the control circuit 80, the PMOS transistor 42 = ON, and the voltage of the signal line 22 is applied to the gate of the PMOS transistor 35. The PMOS transistor 35 is turned OFF.
[0086]
In the control circuit 103, the termination voltage VT is supplied to the gate of the PMOS transistor 85, the PMOS transistor 85 = OFF and the PMOS transistor 86 = ON.
[0087]
As a result, the voltage of the signal line 22 is supplied to the wells of the PMOS transistors 35, 42, 43, 61, 62, and the reverse bias state is maintained between the drain and well of the PMOS transistors 35, 42, 43, 61, 62. The
[0088]
When the voltage of the signal line 23 becomes higher than the power supply voltage V1 for some reason, the PMOS transistor 43 is turned ON in the control circuit 80, and the voltage of the signal line 23 is supplied to the gate of the PMOS transistor 35. PMOS transistor 35 = OFF.
[0089]
In the control circuit 103, the termination voltage VT is supplied to the gate of the PMOS transistor 85, the PMOS transistor 85 = OFF and the PMOS transistor 87 = ON.
[0090]
As a result, the voltage of the signal line 22 is supplied to the wells of the PMOS transistors 35, 42, 43, 61, 62, and the reverse bias state is maintained between the drain and well of the PMOS transistors 35, 42, 43, 61, 62. The
[0091]
Therefore, according to the fifth embodiment 100 of the pull-up type differential bus driver of the present invention, when the voltage of one or both of the signal line 22 and the signal line 23 becomes higher than the power supply voltage V1 for some reason. Even in such a case, current can be prevented from flowing into the power supply line 31 from one or both of the signal line 22 side and the signal line 23 side, so that power is supplied from one or both of the signal line 22 side and the signal line 23 side. The malfunction of the semiconductor device 92 due to the current flowing into the line 31 can be avoided, and the reliability of the semiconductor device 92 can be improved.
[0092]
In the fifth embodiment 100 of the pull-up type differential bus driver of the present invention, the control terminal 101 is connected to the terminal in the termination resistor 96, but the control terminal 101 is not provided and the PMOS is provided. The gate of the transistor 85 may be connected to the signal output terminal 29 or the signal output terminal 30.
[0093]
【The invention's effect】
As described above, according to the pull-up differential bus driver of the present invention, in the constant current source, the voltage of the first signal line and the voltage of one or both of the second signal lines are higher than the power supply voltage. When the first signal line side or the second signal line side is configured to include a control circuit that controls so that current does not flow from the one or both of the first signal line side or the second signal line side to the power source line side, Even when the voltage of one or both of the signal line and the second signal line is higher than the power supply voltage, the power is supplied from one or both of the first signal line side and the second signal line side. Since it is possible to prevent the current from flowing into the line side, when a pull-up type differential bus driver is mounted on a semiconductor device, malfunction caused by the current flowing from the signal line side to the power supply line side may occur. Avoidance and improve reliability .
[0094]
Further, according to the differential bus drive method of the present invention, when one or both of the voltage of the first signal line and the voltage of the second signal line becomes higher than the power supply voltage, the first signal line side or By including the step of controlling so that current does not flow from one or both of the second signal line side to the power supply line side, the voltage of the first signal line and one of the second signal lines for some reason Alternatively, even when both voltages are higher than the power supply voltage, current can be prevented from flowing into the power supply line side from one or both of the first signal line side and the second signal line side. Therefore, when applied to a semiconductor device in which a pull-up type differential bus driver is to be mounted, it is possible to avoid malfunction due to current flowing from the signal line side to the power supply line side and to improve reliability.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a main part of an example of a signal transmission system including a first embodiment of a pull-up type differential bus driver of the present invention.
FIG. 2 is a circuit diagram showing a main part of an example of a signal transmission system including a second embodiment of the pull-up type differential bus driver of the present invention.
FIG. 3 is a circuit diagram showing a main part of an example of a signal transmission system including a third embodiment of the pull-up type differential bus driver of the present invention.
FIG. 4 is a circuit diagram showing a main part of an example of a signal transmission system including a fourth embodiment of the pull-up type differential bus driver of the present invention.
FIG. 5 is a circuit diagram showing a main part of an example of a signal transmission system including a fifth embodiment of the pull-up type differential bus driver of the present invention.
FIG. 6 is a circuit diagram showing a main part of an example of a signal transmission system including an example of a conventional pull-up type differential bus driver.
[Explanation of symbols]
V1 power supply voltage
VT1, VT2, VT termination voltage

Claims

A constant current source having an upstream end connected to a power supply line for supplying a power supply voltage;
One end is connected to the downstream end of the constant current source, the other end is connected to the first signal output terminal to which the first signal line is connected, and is turned on / off by one of the differential input signals. Controlled first switching means;
One end is connected to the downstream end of the constant current source, the other end is connected to a second signal output terminal to which a second signal line is connected, and is turned on / off by the other signal of the differential input signals In a pull-up type differential bus driver comprising: a second switching means for controlling
The constant current source includes the first signal line side and the second signal line side when the voltage of one or both of the first signal line and the second signal line is higher than a power supply voltage. A pull-up type differential bus driver comprising a control circuit for controlling so that current does not flow from one or both of the power source lines to the power supply line side.

The first switching means has a drain connected to the downstream end of the constant current source, a source connected to the first signal output terminal, and a gate to which one of the differential input signals is input. A first N-channel MOS transistor,
The second switching means has a drain connected to the downstream end of the constant current source, a source connected to the second signal output terminal, and a gate to which the other signal of the differential input signals is input. 2. The pull-up differential bus driver according to claim 1, comprising a second N-channel MOS transistor.

The first switching means has a source connected to the downstream end of the constant current source, a drain connected to the first signal output terminal, a well connected to a first control circuit, and a gate connected to the differential. A first P-channel MOS transistor to which one of the input signals is input;
The second switching means has a source connected to the downstream end of the constant current source, a drain connected to the second signal output terminal, a well connected to a second control circuit, and a gate connected to the differential. A second P-channel MOS transistor to which the other input signal is input;
The first control circuit maintains a reverse bias state between the drain and well of the first P-channel MOS transistor,
2. The pull-up differential bus driver according to claim 1, wherein the second control circuit maintains a reverse bias state between the drain and well of the second P-channel MOS transistor.

The first control circuit includes third switching means for connecting the power supply line and a well of the first P-channel MOS transistor, the first signal output terminal, and the first P-channel MOS transistor. A fourth switching means for connecting the well,
The third switching means is turned on when the voltage of the first signal line is lower than the power supply voltage, and is turned off when the voltage of the first signal line is higher than the power supply voltage.
The fourth switching means is turned off when the voltage of the first signal line is lower than the power supply voltage, and turned on when the voltage of the first signal line is higher than the power supply voltage.
The second control circuit includes fifth switching means for connecting the power supply line and the well of the second P-channel MOS transistor, the second signal output terminal, and the second P-channel MOS transistor. A sixth switching means for connecting the well,
The fifth switching means is turned on when the voltage of the second signal line is lower than the power supply voltage, and turned off when the voltage of the second signal line is higher than the power supply voltage.
The sixth switching means is turned off when the voltage of the second signal line is lower than the power supply voltage, and turned on when the voltage of the second signal line is higher than the power supply voltage. The pull-up type differential bus driver according to claim 3.

The third switching means has a source connected to the power supply line, a gate connected to the first signal output terminal, and a drain and a well connected to the well of the first P-channel MOS transistor. P-channel MOS transistor
The fourth switching means has a source and well connected to the well of the first P-channel MOS transistor, a gate connected to the power supply line, and a drain connected to the first signal output terminal. It consists of a P-channel MOS transistor,
The fifth switching means has a source connected to the power supply line, a gate connected to the second signal output terminal, and a drain and a well connected to the well of the second P-channel MOS transistor. P-channel MOS transistor
The sixth switching means has a source and well connected to the well of the second P-channel MOS transistor, a gate connected to the power supply line, and a drain connected to the second signal output terminal. 5. The pull-up differential bus driver according to claim 4, comprising a P-channel MOS transistor.

The constant current source is:
A third P-channel MOS transistor for generating a constant current having a source connected to the upstream end of the constant current source and a drain connected to the downstream end of the constant current source;
A bias circuit for generating a bias voltage to be supplied to the gate of the third P-channel MOS transistor in order to generate a constant current;
When the voltage of the first signal line and the voltage of the second signal line are lower than the power supply voltage, the bias voltage is supplied to the gate of the third P-channel MOS transistor, and the first signal line When one or both voltages of the second signal line are higher than the power supply voltage, the higher one of the voltage of the first signal line and the voltage of the second signal line is set to the first voltage. A third control circuit for supplying the gates of the three P-channel MOS transistors;
6. The pull-up according to claim 1, further comprising a fourth control circuit that maintains a reverse bias state between the drain and well of the third P-channel MOS transistor. Type differential bus driver.

The third control circuit includes:
A seventh switching means for connecting the bias circuit and a gate of the third P-channel MOS transistor;
An eighth switching means for connecting the gate of the third P-channel MOS transistor and the first signal output terminal;
Ninth switching means for connecting the gate of the third P-channel MOS transistor and the second signal output terminal;
The seventh switching means is turned on when the gate voltage of the third P-channel MOS transistor is lower than the power supply voltage, and the gate voltage of the third P-channel MOS transistor is higher than the power supply voltage. Turn off when high,
The eighth switching means is turned off when the voltage of the first signal line is lower than the power supply voltage, and turned on when the voltage of the first signal line is higher than the power supply voltage,
The ninth switching means is turned off when the voltage of the second signal line is lower than the power supply voltage, and is turned on when the voltage of the second signal line is higher than the power supply voltage. The pull-up type differential bus driver according to claim 6.

The seventh switching means comprises a third N-channel MOS transistor having a drain connected to a bias circuit, a gate connected to the power supply line, and a source connected to the gate of a third P-channel MOS transistor,
The eighth switching means has a source connected to the gate of the third P-channel MOS transistor, a gate connected to the power supply line, a drain connected to the first signal output terminal, and a well connected to the fifth A seventh P-channel MOS transistor connected to the control circuit of
The ninth switching means has a source connected to the gate of the third P-channel MOS transistor, a gate connected to the power supply line, a drain connected to the second signal output terminal, and a well connected to the sixth Comprising an eighth P-channel MOS transistor connected to the control circuit of
The fifth control circuit maintains a reverse bias state between the drain and well of the seventh P-channel MOS transistor,
8. The pull-up differential bus driver according to claim 7, wherein the sixth control circuit maintains a reverse bias state between the drain and well of the eighth P-channel MOS transistor.

The fifth control circuit includes tenth switching means for connecting the power supply line and the well of the seventh P-channel MOS transistor, the first signal output terminal, and the seventh P-channel MOS transistor. Eleventh switching means for connecting the well,
The tenth switching means is turned on when the voltage of the first signal line is lower than the power supply voltage, and turned off when the voltage of the first signal line is higher than the power supply voltage,
The eleventh switching means is turned off when the voltage of the first signal line is lower than the power supply voltage, and turned on when the voltage of the first signal line is higher than the power supply voltage.
The sixth control circuit includes a twelfth switching means for connecting the power supply line and the well of the eighth P-channel MOS transistor, the second signal output terminal, and the eighth P-channel MOS transistor. A thirteenth switching means for connecting the well,
The twelfth switching means is turned on when the voltage of the second signal line is lower than the power supply voltage, and is turned on when the voltage of the second signal line is higher than the power supply voltage.
The thirteenth switching means is turned off when the voltage of the second signal line is lower than the power supply voltage, and turned on when the voltage of the second signal line is higher than the power supply voltage. The pull-up type differential bus driver according to claim 8.

The tenth switching means has a source connected to the power supply line, a gate connected to the first signal output terminal, and a drain and a well connected to the well of the seventh P-channel MOS transistor. It consists of a P-channel MOS transistor,
The eleventh switching means has a source and a well connected to the well of the seventh P-channel MOS transistor, a gate connected to the power supply line, and a drain connected to the first signal output terminal. It consists of a P-channel MOS transistor,
The twelfth switching means has a source connected to the power supply line, a gate connected to the second signal output terminal, and a drain and a well connected to the well of the eighth P-channel MOS transistor. It consists of a P-channel MOS transistor,
The thirteenth switching means has a source and well connected to the well of the eighth P-channel MOS transistor, a gate connected to the power supply line, and a drain connected to the second signal output terminal. 10. The pull-up differential bus driver according to claim 9, comprising a P-channel MOS transistor.

The fourth control circuit includes:
Fourteenth switching means for connecting the power supply line and the well of the third P channel MOS transistor, and the drain of the third P channel MOS transistor and the well of the third P channel MOS transistor are connected. Fifteenth switching means,
The fourteenth switching means is turned on when the drain voltage of the third P-channel MOS transistor is lower than the power supply voltage, and the drain voltage of the third P-channel MOS transistor is higher than the power supply voltage. When off,
The fifteenth switching means is turned off when the drain voltage of the third P-channel MOS transistor is lower than the power supply voltage, and the drain voltage of the third P-channel MOS transistor is lower than the power supply voltage. 11. The pull-up type differential bus driver according to claim 6, wherein the pull-up type differential bus driver is turned on when it is high.

In the fourteenth switching means, a source is connected to the power supply line, a gate is connected to a drain of the third P-channel MOS transistor, and a drain and a well are connected to a well of the third P-channel MOS transistor. A thirteenth P-channel MOS transistor;
The fifteenth switching means has a source and well connected to the well of the third P-channel MOS transistor, a gate connected to the power supply line, and a drain connected to the drain of the third P-channel MOS transistor. 12. The pull-up differential bus driver according to claim 11, comprising a 14th P-channel MOS transistor.

The fourth control circuit includes:
Sixteenth switching means for connecting the power supply line and the well of the third P-channel MOS transistor;
Seventeenth switching means for connecting the first signal output terminal and the well of the third P-channel MOS transistor;
An eighteenth switching means for connecting the second signal output terminal and the well of the third P-channel MOS transistor;
The sixteenth switching means is turned on when the voltage of the first signal line and the voltage of the second signal line are lower than the power supply voltage, and the voltage of the first signal line or the second signal line Is turned off when the voltage is higher than the power supply voltage,
The seventeenth switching means turns off when the voltage of the first signal line is lower than the power supply voltage, and turns on when the voltage of the first signal line is higher than the power supply voltage.
The eighteenth switching means is turned off when the voltage of the second signal line is lower than the power supply voltage, and turned on when the voltage of the second signal line is higher than the power supply voltage. The pull-up type differential bus driver according to any one of claims 6 to 10.

The sixteenth switching means has a fifteenth P-channel having a source connected to the power supply line, a gate connected to a seventh control circuit, and a drain and well connected to the well of the third P-channel MOS transistor. The seventeenth switching means comprises a MOS transistor, the source and well are connected to the well of the third P-channel MOS transistor, the gate is connected to the power supply line, and the drain is connected to the first signal output terminal. It consists of a connected 16th P-channel MOS transistor,
In the seventeenth switching means, a source and a well are connected to a well of the third P-channel MOS transistor, a gate is connected to the power supply line, and a drain is connected to the second signal output terminal. It consists of a P-channel MOS transistor,
The seventh control circuit supplies the higher one of the voltage of the first signal line and the voltage of the second signal line to the gate of the fifteenth P-channel MOS transistor. 14. The pull-up type differential bus driver according to claim 13, wherein:

The seventh control circuit includes nineteenth switching means for connecting the first signal output terminal and the gate of the fifteenth P-channel MOS transistor, the second signal output terminal, and the fifteenth P Twentieth switching means for connecting the gate of the channel MOS transistor,
The nineteenth switching means is turned off when the voltage of the first signal line is lower than the voltage of the second signal line, and the voltage of the first signal line is the voltage of the second signal line. Turn on when higher than
The twentieth switching means is turned off when the voltage of the second signal line is lower than the voltage of the first signal line, and the voltage of the second signal line is the voltage of the first signal line. 15. The pull-up type differential bus driver according to claim 14, wherein the pull-up type differential bus driver is turned on when it is higher.

The nineteenth switching means has a source connected to the gate of the fifteenth P-channel MOS transistor, a gate connected to the second signal output terminal, and a drain connected to the first signal output terminal, An eighteenth P-channel MOS transistor having a well connected to the well of the third P-channel MOS transistor;
The twentieth switching means has a source connected to the gate of the fifteenth P-channel MOS transistor, a gate connected to the first signal output terminal, and a drain connected to the second signal output terminal, 16. The pull-up type differential bus driver according to claim 15, comprising a nineteenth P-channel MOS transistor having a well connected to the well of the third P-channel MOS transistor.

The sixteenth switching means has a source connected to the power supply line and a gate connected to the first signal output terminal, or the second signal output terminal, or the first signal line and the second signal. A fifteenth P-channel MOS transistor connected to a terminal in the termination resistor when the line is terminated with a termination resistor;
In the seventeenth switching means, a source and a well are connected to a well of the third P-channel MOS transistor, a gate is connected to the power supply line, and a drain is connected to the first signal output terminal. It consists of a P-channel MOS transistor,
The eighteenth switching means has a source and well connected to the well of the third P-channel MOS transistor, a gate connected to the power supply line, and a drain connected to the second signal output terminal. 14. The differential bus driver according to claim 13, comprising a P-channel MOS transistor.

9. The wells of the first and seventh P-channel MOS transistors are shared, and either one of the first control circuit or the fifth control circuit is not provided. 17. The pull-up differential bus driver according to 17.

9. The well of the second and eighth P-channel MOS transistors is made common, and either the second control circuit or the sixth control circuit is not provided. 18. A pull-up differential bus driver according to -17.

The first, second, third, seventh, and eighth P-channel MOS transistors have a common well, and the first, second, fifth, and sixth control circuits are not provided. 18. The pull-up type differential bus driver according to claim 8-17.

A constant current source having an upstream end connected to a power supply line for supplying a power supply voltage;
One end is connected to the downstream end of the constant current source, the other end is connected to the first signal output terminal to which the first signal line is connected, and is turned on / off by one of the differential input signals. Controlled first switching means;
One end is connected to the downstream end of the constant current source, the other end is connected to a second signal output terminal to which a second signal line is connected, and is turned on / off by the other signal of the differential input signals A differential bus drive method for driving the first signal line and the second signal line using a pull-up differential bus driver comprising:
When the voltage of one or both of the first signal line and the second signal line becomes higher than the power supply voltage, the voltage is supplied from one or both of the first signal line side and the second signal line side. A differential bus drive method comprising a step of controlling so that current does not flow into a power supply line side.