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JP3698893B2 - 2 line switching semiconductor switch - Google Patents

2 line switching semiconductor switch Download PDF

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Publication number
JP3698893B2
JP3698893B2 JP17891298A JP17891298A JP3698893B2 JP 3698893 B2 JP3698893 B2 JP 3698893B2 JP 17891298 A JP17891298 A JP 17891298A JP 17891298 A JP17891298 A JP 17891298A JP 3698893 B2 JP3698893 B2 JP 3698893B2
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JP
Japan
Prior art keywords
semiconductor switch
line switching
switching semiconductor
parallel
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP17891298A
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Japanese (ja)
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JP2000014008A (en
Inventor
博 山本
清次 立花
正行 内藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Mitsubishi Electric Industrial Systems Corp
West Japan Railway Co
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Toshiba Mitsubishi Electric Industrial Systems Corp
West Japan Railway Co
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Description

【0001】
【発明の属する技術分野】
この発明は、電力系統を2回線受電し、受電した2回線中一方の回線にて負荷に電力を供給しておきこの回線に事故による停電あるいは電圧低下が発生した場合において、瞬時に他方の回線に切り替えて負荷側の無停電を図る2回線切替用半導体開閉器に関するものである。
【0002】
【従来の技術】
図11は例えば電気評論1997年11月号(P77−P81)に示された従来の2回線切替用半導体開閉器を示す回路図であり、図において、A、Bは電力系統のA系統とB系統、Lは負荷、MC11は2回線切替用半導体開閉器で、1a,1bはサイリスタ素子、2a,2bはスナバコンデンサ、3a,3bはスナバ抵抗器、4a,4b,4cは電圧検出用の電磁形計器用変成器、8a,8bは高速開極スイッチ、15a,15bは電磁形計器用変成器4a,4b,4cの検出結果に従ってサイリスタ素子1a,1bおよび高速開極スイッチ8a,8bの開閉制御を行う制御装置を示す。
【0003】
次に動作について説明する。サイリスタ素子1a及び高速開極スイッチ8aがオン状態、サイリスタ素子1b及び高速開極スイッチ8bがオフ状態にてA系統から負荷Lに給電している時、A系統に例えば3相短絡が発生すると電磁形計器用変成器4a,4cの電圧検出出力は低下する。これを制御装置15a,15bにて検出し瞬時にサイリスタ素子1a及び高速開極スイッチ8aをオフし、サイリスタ素子1b及び高速開極スイッチ8bをオンすることによってA系統からB系統に無瞬断で切替し負荷Lの無停電化を図っている。
【0004】
【発明が解決しようとする課題】
従来の2回線切替用半導体開閉器は以上のように構成されているので、A系統が短絡事故を伴わない停電時(上位の遮断器が開放された時等)において、B系統からスナバコンデンサを経由して負荷側及び電源側の電磁形計器用変成器が充電されるため、停電検出されずに2回線切替ができないので、スナバコンデンサの容量を最小限としインピーダンスを最大限とするとともに電磁形計器用変成器の2次側にダミー負荷(図示せず)を接続することによって、負荷が無負荷状態に於いても電圧低下検出可能とすることが必要であった。
【0005】
また、スナバコンデンサと電磁形計器用変成器の励磁インピーダンス及び負荷側の変圧器の励磁インピーダンスとの直列共振による過電圧により、サイリスタ素子が破壊するのでスナバ抵抗器によりダンピングを図らなければならないなどの問題点があった。
【0006】
この発明は上記のような課題を解決するためになされたものであり、スナバコンデンサ及びスナバ抵抗器は本来の目的である使用する半導体(サイリスタ素子)の動特性に合致した定数のものが使用できるとともに、電圧検出の手段、負荷の如何に関わらず適用可能で、さらに電源側及び負荷側からの対地間サージ電圧を抑制することが可能な2回線切替用半導体開閉器を得ることを目的とする。
【0007】
【課題を解決するための手段】
上記の目的に鑑み、この発明は、電源側及び負荷側の電圧検出手段からの検出結果に従って2つの電力系統を切り替えて接続し負荷側の無停電を図る2回線切替用半導体開閉器であって、開閉手段に並列に接続されたスナバコンデンサの少なくとも数十倍以上の容量を有する大容量コンデンサを半導体開閉器の電源側及び負荷側にそれぞれ並列接続し、上記大容量コンデンサを星形接続とし、該星形接続の中性点を直接接地したことを特徴とする2回線切替用半導体開閉器にある。
【0008】
またこの発明は、上記開閉手段をゲートターンオフサイリスタ素子を逆並列接続したもので構成したことを特徴とする2回線切替用半導体開閉器にある。
【0009】
またこの発明は、上記電圧検出手段を半導体開閉器の電源側及び負荷側にそれぞれコンデンサ形計器用変成器を並列接続したもので構成したことを特徴とする2回線切替用半導体開閉器にある。
【0011】
またこの発明は、上記開閉手段をサイリスタ素子を逆並列接続し、さらにこれに高速開極スイッチを並列接続したもので構成したことを特徴とする2回線切替用半導体開閉器にある。
【0012】
またこの発明は、逆並列接続された上記ゲートターンオフサイリスタ素子に、高速開極スイッチを並列接続したことを特徴とする2回線切替用半導体開閉器にある。
【0013】
【発明の実施の形態】
実施の形態1.
以下、この発明の実施の形態1を図に基づいて説明する。図1はこの発明の一実施の形態による2回線切替用半導体開閉器を示す回路図である。図1において、従来のものと同一もしくは相当部分は同一符号で示す。MC1は2回線切替用半導体開閉器、5a,5bは制御装置、6a,6b,6cは電源側及び負荷側に星形接続にて設置したスナバコンデンサの数十倍以上(例えば50倍以上)の容量を有する大容量コンデンサである。
【0014】
なお、電圧検出手段が電磁形計器用変成器4a,4b,4cで構成され、開閉手段がサイリスタ素子1a、1bで構成される。
【0015】
次に動作について説明する、電源側及び負荷側に該大容量コンデンサ6a,6b,6cを設置したことにより、A系統に短絡事故を伴わない停電が発生してもA系続の開閉器の負荷側及び電源側にはスナバコンデンサ2a,2bと大容量コンデンサ6a,6b,6cの容量に逆比例した電圧(電源電圧の1/50以下)が現れることになるので、電圧検出は可能となり所望の2回線切替が可能となる。
【0016】
なお、該大容量コンデンサを接続することにより電磁形計器用変成器及び負荷側変圧器の励磁インピーダンスとスナバコンデンサとの直列共振を防止することが可能である。
【0017】
実施の形態2.
図2はこの発明の別の実施の形態による2回線切替用半導体開閉器を示す回路図である。図2において、上記実施の形態のものと同一もしくは相当部分は同一符号で示す。MC2は2回線切替用半導体開閉器、11a,11bはゲートターンオフサイリスタ素子である。
【0018】
この実施の形態では半導体開閉器の開閉手段としてゲートターンオフサイリスタ素子11a,11bを使用するようにしたので、切り替え時間を1/2以下(1サイクル以下→1/2サイクル以下)にすることができる。
【0019】
実施の形態3.
図3はこの発明の別の実施の形態による2回線切替用半導体開閉器を示す回路図である。図3において、上記実施の形態のものと同一もしくは相当部分は同一符号で示す。MC3は2回線切替用半導体開閉器、7a,7b,7cはコンデンサ形計器用変成器である。
【0020】
この実施の形態では、電源側及び負荷側の電圧検出手段として電磁形計器用変成器の代わりにコンデンサ形計器用変成器7a,7b,7cを設けるようにしたので、電源側及び負荷側に設置する大容量コンデンサ6a,6b,6cの容量を軽減した経済的に優れた2回線切替用半導体開閉器を得ることができる。
【0021】
なお図4には実施の形態2のゲートターンオフサイリスタ素子11a,11bを使用したものにおいて本実施の形態を実施した2回線切替用半導体開閉器MC4の回路図を示す。これにおいても同様な効果が得られる。
【0022】
実施の形態4.
図5はこの発明の別の実施の形態による2回線切替用半導体開閉器を示す回路図である。図5において、上記実施の形態のものと同一もしくは相当部分は同一符号で示す。MC5は2回線切替用半導体開閉器である。
【0023】
上記実施の形態1では、電源側及び負荷側に星形接続にてスナバコンデンサの例えば50倍以上の容量を有する大容量コンデンサを設置する場合について述べたが、図5に示すように、該大容量コンデンサ6a,6b,6cの中性点を接地するようにしたので、電源側及び負荷側からの対地間サージ電圧を抑制することが可能となり、高い信頼性を有する2回線切替用半導体開閉器を得ることができる。
【0024】
なお図6には実施の形態2のゲートターンオフサイリスタ素子11a,11bを使用したものにおいて本実施の形態を実施した2回線切替用半導体開閉器MC6の回路図、図7には実施の形態3のコンデンサ形計器用変成器7a,7b,7cを使用したものにおいて本実施の形態を実施した2回線切替用半導体開閉器MC7の回路図、および図8には図4に示された実施の形態2のゲートターンオフサイリスタ素子11a,11bおよび実施の形態3のコンデンサ形計器用変成器7a,7b,7cを使用したものにおいて本実施の形態を実施した2回線切替用半導体開閉器MC8の回路図を示す。これたにおいても、同様な効果が得られる。
【0025】
実施の形態5.
図9はこの発明の別の実施の形態による2回線切替用半導体開閉器を示す回路図である。図9において、上記実施の形態のものと同一もしくは相当部分は同一符号で示す。MC9は2回線切替用半導体開閉器、8a,8bは高速開極スイッチ、15a,15bは制御装置である。
【0026】
なお、電圧検出手段が電磁形計器用変成器4a,4b,4cで構成され、開閉手段がサイリスタ素子1a、1bおよび高速開極スイッチ8a,8bで構成される。
【0027】
上記実施の形態1では、半導体開閉器の開閉素子としてサイリスタ素子を使用する場合について述べたが、図9に示すように、サイリスタ素子1a,1bに並列に高速開極スイッチ8a,8bを接続した構成とすることにより、サイリスタ素子1a,1bの通電期間を半導体開閉器のオン時3サイクル程度とオフ時1サイクル未満に限定し、この期間以外は高速開極スイッチ8a,8bにて通電することができるため、低損失でサイリスタ素子1a,1bの冷却手段(図示せず)が不要である、コンパクトな2回線切替用半導体開閉器MC9を得ることができる。
【0028】
なお図10には実施の形態2のゲートターンオフサイリスタ素子11a,11bを使用したものにおいて本実施の形態を実施した2回線切替用半導体開閉器MC10の回路図を示す。これたにおいても、同様な効果が得られる。
【0029】
さらに、この発明は上記の各実施の形態に限定されることなく、必要に応じて各実施の形態の所望の組み合わが可能であることは言うもでもない。
【0030】
【発明の効果】
上記のようにこの発明では、
電源側及び負荷側の電圧検出手段からの検出結果に従って2つの電力系統を切り替えて接続し負荷側の無停電を図る2回線切替用半導体開閉器であって、開閉手段に並列に接続されたスナバコンデンサの少なくとも数十倍以上の容量を有する大容量コンデンサを半導体開閉器の電源側及び負荷側にそれぞれ並列接続し、上記大容量コンデンサを星形接続とし、該星形接続の中性点を直接接地したことを特徴とする2回線切替用半導体開閉器としたので、スナバコンデンサ及びスナバ抵抗器は半導体開閉器のスナバ定数を使用する半導体の動特性に合致したものが使用できるとともに、電圧検出手段、負荷の如何に関わらず適用可能で、さらに電源側及び負荷側からの対地間サージ電圧を抑制することが可能な2回線切替用半導体開閉器が得られる効果がある。
【0031】
また、上記開閉手段をゲートターンオフサイリスタ素子を逆並列接続したもので構成したので、切り替え時間を1/2以下(1サイクル以下→1/2サイクル以下)とすることができ、早い切り替えが可能となる。
【0032】
また、上記電圧検出手段を半導体開閉器の電源側及び負荷側にそれぞれコンデンサ形計器用変成器を並列接続したもので構成したので、電源側及び負荷側に設置する大容量コンデンサの容量を軽減できる。
【0034】
また、上記開閉手段をサイリスタ素子あるいはゲートターンオフサイリスタ素子を逆並列接続し、さらにこれに高速開極スイッチを並列接続したもので構成したので、サイリスタ素子の通電期間を半導体開閉器のオン時3サイクル程度とオフ時1サイクル未満に限定し、この期間以外は高速開極スイッチにて通電することができるため、低損失でサイリスタ素子の冷却手段が不要であり、2回線切替用半導体開閉器をコンパクトにできる。
【図面の簡単な説明】
【図1】 この発明の実施の形態1による2回線切替用半導体開閉器を示す回路図である。
【図2】 この発明の実施の形態2による2回線切替用半導体開閉器を示す回路図である。
【図3】 この発明の実施の形態3による2回線切替用半導体開閉器を示す回路図である。
【図4】 この発明の実施の形態3による別の2回線切替用半導体開閉器を示す回路図である。
【図5】 この発明の実施の形態4による2回線切替用半導体開閉器を示す回路図である。
【図6】 この発明の実施の形態4による別の2回線切替用半導体開閉器を示す回路図である。
【図7】 この発明の実施の形態4によるさらに別の2回線切替用半導体開閉器を示す回路図である。
【図8】 この発明の実施の形態4によるさらに別の2回線切替用半導体開閉器を示す回路図である。
【図9】 この発明の実施の形態5による2回線切替用半導体開閉器を示す回路図である。
【図10】 この発明の実施の形態5による別の2回線切替用半導体開閉器を示す回路図である。
【図11】 従来の2回線切替用半導体開閉器を示す回路図である。
【符号の説明】
1a,1b サイリスタ素子、2a,2b スナバコンデンサ、3a,3b スナバ低抗器、4a,4b,4c 電磁形計器用変成器、5a,5b,15a,15b 制御装置、6a,6b,6c 大容量コンデンサ、7a,7b,7c コンデンサ形計器用変成器、8a,8b 高速開極スイツチ、11a,11b ゲートターンオフサイリスタ素子。
[0001]
BACKGROUND OF THE INVENTION
In the present invention, when two power lines are received by the power system and power is supplied to the load on one of the two received lines and a power failure or voltage drop occurs due to an accident on this line, the other line is instantaneously The present invention relates to a two-line switching semiconductor switch that switches to a non-interruption on the load side.
[0002]
[Prior art]
FIG. 11 is a circuit diagram showing a conventional two-line switching semiconductor switch disclosed in, for example, the November 1997 issue of Electric Review (P77-P81). In the figure, A and B are the A system and B of the power system. System, L is a load, MC11 is a two-line switching semiconductor switch, 1a and 1b are thyristor elements, 2a and 2b are snubber capacitors, 3a and 3b are snubber resistors, 4a, 4b and 4c are electromagnetic waves for voltage detection Transformers for shape instruments, 8a and 8b are high-speed open-circuit switches, 15a and 15b are open / close controls for thyristor elements 1a and 1b and high-speed open-circuit switches 8a and 8b in accordance with the detection results of electromagnetic-type instrument transformers 4a, 4b and 4c. The control apparatus which performs is shown.
[0003]
Next, the operation will be described. When the thyristor element 1a and the high-speed open switch 8a are on and the thyristor element 1b and the high-speed open switch 8b are off and the power is supplied from the A system to the load L, for example, a three-phase short circuit occurs in the A system. The voltage detection output of the shape transformers 4a and 4c decreases. This is detected by the control devices 15a and 15b, and the thyristor element 1a and the high-speed opening switch 8a are turned off instantaneously, and the thyristor element 1b and the high-speed opening switch 8b are turned on so that there is no instantaneous interruption from the A system to the B system. The load L is switched to achieve uninterruptible power.
[0004]
[Problems to be solved by the invention]
Since the conventional two-line switching semiconductor switch is configured as described above, a snubber capacitor is connected from the B system in the event of a power outage without a short circuit accident in the A system (such as when the upper circuit breaker is opened). Since the load-type and power-side electromagnetic instrument transformers are charged via the power line, two lines cannot be switched without detecting a power failure, so the snubber capacitor capacity is minimized and the impedance is maximized. By connecting a dummy load (not shown) to the secondary side of the instrument transformer, it was necessary to be able to detect a voltage drop even when the load was unloaded.
[0005]
In addition, the thyristor element is destroyed by overvoltage due to series resonance between the excitation impedance of the snubber capacitor and the electromagnetic transformer, and the excitation impedance of the transformer on the load side. There was a point.
[0006]
The present invention has been made to solve the above-described problems, and a snubber capacitor and a snubber resistor having constant values that match the dynamic characteristics of a semiconductor (thyristor element) to be used can be used. In addition , an object is to obtain a two-line switching semiconductor switch that can be applied regardless of voltage detection means and load, and can suppress a surge voltage to ground from the power supply side and the load side. .
[0007]
[Means for Solving the Problems]
In view of the above object, the present invention is a two-line switching semiconductor switch that switches between two power systems in accordance with detection results from voltage detection means on the power source side and load side to achieve uninterruptible power on the load side. A large-capacity capacitor having a capacity of at least several tens of times that of the snubber capacitor connected in parallel to the switching means is connected in parallel to the power supply side and the load side of the semiconductor switch, and the large-capacity capacitor is connected in a star shape. A two-line switching semiconductor switch is characterized in that the neutral point of the star connection is directly grounded .
[0008]
The present invention also provides a two-line switching semiconductor switch characterized in that the switching means is composed of gate turn-off thyristor elements connected in reverse parallel.
[0009]
The present invention also provides a two-line switching semiconductor switch in which the voltage detecting means is configured by connecting a capacitor-type instrument transformer in parallel to the power supply side and the load side of the semiconductor switch, respectively.
[0011]
According to the present invention, there is provided a two-line switching semiconductor switch characterized in that the switching means comprises a thyristor element connected in reverse parallel, and a high-speed opening switch connected in parallel thereto.
[0012]
The present invention also provides a two-line switching semiconductor switch in which a high-speed opening switch is connected in parallel to the gate turn-off thyristor element connected in reverse parallel.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a two-line switching semiconductor switch according to an embodiment of the present invention. In FIG. 1, the same or corresponding parts as those of the conventional one are indicated by the same reference numerals. MC1 is a two-line switching semiconductor switch, 5a and 5b are control devices, and 6a, 6b and 6c are tens of times (for example, 50 times or more) of a snubber capacitor installed in a star connection on the power supply side and load side. A large-capacity capacitor having a capacity.
[0014]
The voltage detecting means is composed of electromagnetic instrument transformers 4a, 4b, 4c, and the switching means is composed of thyristor elements 1a, 1b.
[0015]
Next, the operation will be described. By installing the large-capacity capacitors 6a, 6b, 6c on the power supply side and the load side, even if a power failure without a short-circuit accident occurs in the A system, the load on the A system switch Since the voltage (less than 1/50 of the power supply voltage) appears in proportion to the capacity of the snubber capacitors 2a, 2b and the large-capacitance capacitors 6a, 6b, 6c on the power supply side and the power supply side, the voltage can be detected and desired. Two lines can be switched.
[0016]
By connecting the large-capacity capacitor, it is possible to prevent series resonance between the excitation impedance of the electromagnetic type instrument transformer and the load side transformer and the snubber capacitor.
[0017]
Embodiment 2. FIG.
FIG. 2 is a circuit diagram showing a two-line switching semiconductor switch according to another embodiment of the present invention. In FIG. 2, the same or corresponding parts as those in the above embodiment are indicated by the same reference numerals. MC2 is a two-line switching semiconductor switch, and 11a and 11b are gate turn-off thyristor elements.
[0018]
In this embodiment, since the gate turn-off thyristor elements 11a and 11b are used as the switching means of the semiconductor switch, the switching time can be reduced to ½ or less (1 cycle or less → 1/2 cycle or less). .
[0019]
Embodiment 3 FIG.
FIG. 3 is a circuit diagram showing a two-line switching semiconductor switch according to another embodiment of the present invention. In FIG. 3, the same or corresponding parts as those in the above embodiment are indicated by the same reference numerals. MC3 is a two-line switching semiconductor switch, and 7a, 7b, and 7c are capacitor-type instrument transformers.
[0020]
In this embodiment, capacitor-type instrument transformers 7a, 7b, and 7c are provided as voltage detection means on the power source side and the load side instead of the electromagnetic instrument transformer, so that they are installed on the power source side and the load side. Thus, an economically excellent two-line switching semiconductor switch in which the capacity of the large-capacitance capacitors 6a, 6b, 6c is reduced can be obtained.
[0021]
FIG. 4 shows a circuit diagram of a two-line switching semiconductor switch MC4 in which the present embodiment is implemented using the gate turn-off thyristor elements 11a and 11b of the second embodiment. In this case, the same effect can be obtained.
[0022]
Embodiment 4 FIG.
FIG. 5 is a circuit diagram showing a two-line switching semiconductor switch according to another embodiment of the present invention. In FIG. 5, the same or corresponding parts as those in the above embodiment are indicated by the same reference numerals. MC5 is a two-line switching semiconductor switch.
[0023]
In the first embodiment, the case where a large-capacity capacitor having, for example, 50 times or more the capacity of a snubber capacitor is installed in a star connection on the power supply side and the load side has been described. However, as shown in FIG. Since the neutral points of the capacitive capacitors 6a, 6b, 6c are grounded, it is possible to suppress the surge voltage between the power supply side and the load side, and it is possible to suppress the surge voltage to the ground, and the highly reliable semiconductor switch for two-line switching Can be obtained.
[0024]
6 is a circuit diagram of a two-line switching semiconductor switch MC6 in which the present embodiment is implemented using the gate turn-off thyristor elements 11a and 11b of the second embodiment, and FIG. 7 is a circuit diagram of the third embodiment. FIG. 8 is a circuit diagram of a two-line switching semiconductor switch MC7 in which the present embodiment is implemented using capacitor-type instrument transformers 7a, 7b and 7c, and FIG. 8 shows the second embodiment shown in FIG. A circuit diagram of a two-line switching semiconductor switch MC8 embodying the present embodiment using the gate turn-off thyristor elements 11a, 11b and the capacitor-type instrument transformers 7a, 7b, 7c of the third embodiment is shown. . Even in this case, the same effect can be obtained.
[0025]
Embodiment 5 FIG.
FIG. 9 is a circuit diagram showing a two-line switching semiconductor switch according to another embodiment of the present invention. In FIG. 9, parts that are the same as or equivalent to those in the above embodiment are denoted by the same reference numerals. MC9 is a two-line switching semiconductor switch, 8a and 8b are high-speed opening switches, and 15a and 15b are control devices.
[0026]
The voltage detecting means is constituted by electromagnetic type instrument transformers 4a, 4b, 4c, and the opening / closing means is constituted by thyristor elements 1a, 1b and high-speed opening switches 8a, 8b.
[0027]
In the first embodiment, the case where a thyristor element is used as the switching element of the semiconductor switch has been described. However, as shown in FIG. 9, high-speed opening switches 8a and 8b are connected in parallel to the thyristor elements 1a and 1b. With this configuration, the energization period of the thyristor elements 1a and 1b is limited to about 3 cycles when the semiconductor switch is on and less than 1 cycle when the semiconductor switch is off, and the high-speed opening switches 8a and 8b are energized during other periods. Therefore, it is possible to obtain a compact two-line switching semiconductor switch MC9 that has low loss and does not require a cooling means (not shown) for the thyristor elements 1a and 1b.
[0028]
FIG. 10 shows a circuit diagram of a two-line switching semiconductor switch MC10 in which the present embodiment is implemented using the gate turn-off thyristor elements 11a and 11b of the second embodiment. Even in this case, the same effect can be obtained.
[0029]
Further, the present invention is not limited to the above-described embodiments, and it is needless to say that a desired combination of the embodiments is possible as necessary.
[0030]
【The invention's effect】
As described above, in the present invention,
A two-line switching semiconductor switch that switches between and connects two power systems in accordance with detection results from voltage detection means on the power supply side and load side to achieve uninterruptible power on the load side, and is a snubber connected in parallel to the switching means A large-capacity capacitor having a capacity at least several tens of times that of the capacitor is connected in parallel to the power supply side and load side of the semiconductor switch, and the large-capacity capacitor is used as a star connection, and the neutral point of the star connection is directly Since it is a two-line switching semiconductor switch characterized by being grounded , the snubber capacitor and snubber resistor can be used in accordance with the dynamic characteristics of the semiconductor using the snubber constant of the semiconductor switch, and the voltage detection means , applicable irrespective of the load, further power supply side and the ground between the surge voltage semiconductor switch for two-line switch that can suppress from the load side is obtained, et al. There is that effect.
[0031]
Further, since the opening / closing means is composed of gate turn-off thyristor elements connected in reverse parallel, the switching time can be reduced to ½ or less (1 cycle or less → 1/2 cycle or less), and quick switching is possible. Become.
[0032]
In addition, since the voltage detecting means is configured by connecting a capacitor-type instrument transformer in parallel to the power supply side and the load side of the semiconductor switch, respectively, the capacity of the large-capacitance capacitors installed on the power supply side and the load side can be reduced. .
[0034]
Further, since the switching means is constituted by connecting a thyristor element or a gate turn-off thyristor element in antiparallel and further connecting a high speed opening switch in parallel thereto, the energization period of the thyristor element is set to 3 cycles when the semiconductor switch is turned on. It is limited to less than 1 cycle when off, and it can be energized with a high-speed open-circuit switch during this period, so it has low loss and does not require a cooling means for thyristor elements, making the two-line switching semiconductor switch compact. Can be.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a two-line switching semiconductor switch according to Embodiment 1 of the present invention;
FIG. 2 is a circuit diagram showing a two-line switching semiconductor switch according to Embodiment 2 of the present invention;
FIG. 3 is a circuit diagram showing a two-line switching semiconductor switch according to Embodiment 3 of the present invention;
FIG. 4 is a circuit diagram showing another two-line switching semiconductor switch according to Embodiment 3 of the present invention;
FIG. 5 is a circuit diagram showing a two-line switching semiconductor switch according to Embodiment 4 of the present invention;
FIG. 6 is a circuit diagram showing another two-line switching semiconductor switch according to Embodiment 4 of the present invention;
FIG. 7 is a circuit diagram showing still another two-line switching semiconductor switch according to Embodiment 4 of the present invention;
FIG. 8 is a circuit diagram showing still another two-line switching semiconductor switch according to Embodiment 4 of the present invention;
FIG. 9 is a circuit diagram showing a two-line switching semiconductor switch according to Embodiment 5 of the present invention;
FIG. 10 is a circuit diagram showing another two-line switching semiconductor switch according to Embodiment 5 of the present invention;
FIG. 11 is a circuit diagram showing a conventional two-line switching semiconductor switch.
[Explanation of symbols]
1a, 1b Thyristor element, 2a, 2b Snubber capacitor, 3a, 3b Snubber resistor, 4a, 4b, 4c Electromagnetic transformer, 5a, 5b, 15a, 15b Controller, 6a, 6b, 6c Large capacity capacitor 7a, 7b, 7c Capacitor-type instrument transformer, 8a, 8b High-speed opening switch, 11a, 11b Gate turn-off thyristor element.

Claims (5)

電源側及び負荷側の電圧検出手段からの検出結果に従って2つの電力系統を切り替えて接続し負荷側の無停電を図る2回線切替用半導体開閉器であって、開閉手段に並列に接続されたスナバコンデンサの少なくとも数十倍以上の容量を有する大容量コンデンサを半導体開閉器の電源側及び負荷側にそれぞれ並列接続し、上記大容量コンデンサを星形接続とし、該星形接続の中性点を直接接地したことを特徴とする2回線切替用半導体開閉器。A two-line switching semiconductor switch that switches between and connects two power systems in accordance with detection results from voltage detection means on the power supply side and load side to achieve uninterruptible power on the load side, and is a snubber connected in parallel to the switching means A large-capacity capacitor having a capacity at least several tens of times that of the capacitor is connected in parallel to the power supply side and load side of the semiconductor switch, and the large-capacity capacitor is used as a star connection, and the neutral point of the star connection is directly A two-line switching semiconductor switch characterized by being grounded . 上記開閉手段をゲートターンオフサイリスタ素子を逆並列接続したもので構成したことを特徴とする請求項1に記載の2回線切替用半導体開閉器。  2. The two-line switching semiconductor switch according to claim 1, wherein the switching means is composed of gate turn-off thyristor elements connected in reverse parallel. 上記電圧検出手段を半導体開閉器の電源側及び負荷側にそれぞれコンデンサ形計器用変成器を並列接続したもので構成したことを特徴とする請求項1または2に記載の2回線切替用半導体開閉器。  3. A two-line switching semiconductor switch according to claim 1, wherein said voltage detecting means is constituted by a capacitor-type instrument transformer connected in parallel to each of a power source side and a load side of the semiconductor switch. . 上記開閉手段をサイリスタ素子を逆並列接続し、さらにこれに高速開極スイッチを並列接続したもので構成したことを特徴とする請求項1又は3に記載の2回線切替用半導体開閉器。 4. The two-line switching semiconductor switch according to claim 1 , wherein the switching means comprises a thyristor element connected in reverse parallel and a high-speed opening switch connected in parallel thereto. 逆並列接続された上記ゲートターンオフサイリスタ素子に、高速開極スイッチを並列接続したことを特徴とする請求項2に記載の2回線切替用半導体開閉器。  3. The two-line switching semiconductor switch according to claim 2, wherein a high-speed opening switch is connected in parallel to the gate turn-off thyristor element connected in reverse parallel.
JP17891298A 1998-06-25 1998-06-25 2 line switching semiconductor switch Expired - Lifetime JP3698893B2 (en)

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