JP3694599B2 - Liquid crystal display device - Google Patents

Description

【００４４】
図２、図３共にクロック信号線の結線を省略してあるが図２のクロックドインバータ６５、６６にはクロック信号線ＨＣＬＫ１、ＨＣＬＫ２が、図３のクロックドインバータ６５、６６には、クロック信号線ＶＣＬＫ１、ＶＣＬＫ２が接続されている。以下の説明では、任意のクロックΦ、Φバーを用いて説明する。
【００４５】
図４（ｃ）に示すラッチ回路６７は、クロックドインバータ６５の出力をインバータ６３ａの入力に接続し、このインバータ６３ａの出力をクロックドインバータ６６の入力に接続している。このためクロック信号ΦのＨレベル立ち上がり時にクロックドインバータ６５に入力された信号が反転しインバータ６３ａに入力される。次にクロック信号ΦバーがＨレベルとなると、クロックドインバータ６５はハイインピーダンスとなるがクロックドインバータ６６がインバータとして働き、クロックドインバータ６５の出力は、インバータ６３ａとクロックドインバータ６６でラッチされ、インバータ６３ａから反転信号が出力する。
【００４６】
またラッチ回路６８は、クロックドインバータ６６の出力がインバータ６３ａの入力に接続され、このインバータ６３ａの出力はクロックドインバータ６５の入力に接続されている。このためクロック信号ΦバーのＨレベルの立ち上がり時（すなわちクロック信号Φの立ち下がり時）にクロックドインバータ６６に入力された信号が反転しインバータ６３ａに入力される。次にクロック信号ΦがＨレベルとなると、クロックドインバータ６６はハイインピーダンスとなるがクロックドインバータ６５がインバータとして働き、クロックドインバータ６６の出力は、インバータ６３ａとクロックドインバータ６５でラッチされ、インバータ６３ａから反転信号が出力する。
【００４７】
図６に図４（ｃ）に示すラッチ回路６７、６８のタイミングチャートの１例を示す。図６では、クロック信号Φの立ち上がり▲１▼に対して、入力信号ＤＩの同期がとれてなく、クロック信号Φの立ち上がり▲１▼に遅れて入力信号ＤＩはＨレベルとなっている。また入力信号ＤＩはクロック信号Φの立ち上がり▲３▼に遅れてＬレベルとなっている。
【００４８】
このためラッチ回路６７はクロック信号ΦがＨレベルの場合、入力をそのまま出力し、クロック信号ΦがＬレベルとなった時、直前の状態を保持するので、出力ＯＵＴ１は入力信号ＤＩと同じタイミングで状態が変化する。対して２段目のラッチ回路６６では、クロック信号Φの立ち下がり▲２▼で出力ＯＵＴ１のＨレベルを出力し、クロック信号Φの立ち上り▲３▼で、その出力をラッチしそれをクロック信号Φの立ち下り▲４▼まで保持し、クロック信号Φの立ち下がり▲４▼で出力ＯＵＴ１のＬレベルを出力するため、出力ＯＵＴ２から以降は、クロック信号Φと同期がとれた出力となっている。
【００４９】
このように、双方向シフトレジスタＨＳＲ、ＶＳＲの１段目の出力は２段目以降の出力とは異なり、クロック信号と同期がとれないために、双方向シフトレジスタＨＳＲ１、ＨＳＲ５１３、ＶＳＲ１、ＶＳＲ３８６の初段部分はダミーのラッチ回路としており、その出力が映像信号供給回路２１および、垂直出力回路３２に接続されていない。
【００５０】
図２、図３に示すように、双方向シフトレジスタＨＳＲ、ＶＳＲは複数連続して設けられている。図４（ｃ）、図４（ｄ）では、前段のラッチ回路６７の出力をＯＵＴ１で示し、後段のラッチ回路６８の出力をＯＵＴ２で示したが、双方向シフトレジスタＨＳＲ、ＶＳＲは複数連続して設けられるので、ラッチ回路６８の次段には、ラッチ回路６７が接続される。図６に示すＯＵＴ３は、次段のラッチ回路６７の出力を示している。
【００５１】
出力ＯＵＴ２、ＯＵＴ３と映像信号との関係を図６を用いて説明する。ＯＵＴ２、ＯＵＴ３は前述したように、図４（ｃ）に示すようなラッチ回路６７、６８の出力である。図６に示すように、ラッチ回路６８がクロック信号Φの立ち下がり▲２▼で前段の出力をＯＵＴ２に出力し、クロック信号Φの立ち上り▲３▼でその出力をラッチし、クロック信号Φの立ち下がり▲４▼まで値を保持し、次に図４では図示されない次段のラッチ回路６７がクロック信号Φの立ち上がり▲３▼で前段の出力をＯＵＴ３に出力する。そのために、クロック信号Φの立ち上がり▲３▼では、ＯＵＴ２、ＯＵＴ３共に出力オン状態となる。このときに映像信号線が単数の場合では、双方向シフトレジスタＨＳＲの出力ＯＵＴ２、ＯＵＴ３に対応する画素に同じ映像信号が書き込まれるという問題点がある。すなわち，ＯＵＴ２からの出力で操作される映像信号供給回路と、ＯＵＴ３からの出力で操作される映像信号供給回路とが、同時に同じ映像信号線に接続されると、２つの画素に同じ映像信号が入力されることになる。ラッチ回路６７とラッチ回路６８の出力のどちらか一方のみを映像信号供給回路２１を操作する信号として用いれば、前述のような問題は生じないが、シフトレジスタを構成するラッチ回路の数は２倍になる。このため、本実施の形態では図２に示すように、映像信号２２もＶＩＤ１〜ＶＩＤ４のように複数に分割されて供給されており前記問題点も解決される。
【００５２】
また、本実施の形態では水平方向の画素数は１０２５画素で、垂直方向の画素数は７６９画素で奇数である。しかしながら、双方向シフトレジスタＨＳＲ、ＶＳＲは、ラッチ回路６７とラッチ回路６８とを一組とするように設けられており、ラッチ回路６７とラッチ回路６８の合計が偶数となるように構成されている。
【００５３】
このことは、走査方向が反転した場合もクロック信号Φの同じエッジ（立ち上がり又は、立ち下がり）で入力信号ＤＩを取り込むためである。すなわち、図４（ｃ）に示すラッチ回路６７と６８の場合、走査方向が反転するとラッチ回路６７と６８の順番も逆転し、図４（ｄ）に示すように、右からラッチ回路６８、６７の順番になる。しかしながら、このラッチ回路の順番を、信号の入力側を基準としてみると走査方向を反転してもラッチ回路６７と６８の順番は変化しない。ラッチ回路６７はクロック信号Φの立ち上がりで入力を出力しクロック信号Φの立ち上りでその出力を保持し、ラッチ回路６８はクロック信号Φの立ち下がりで入力を出力し、クロック信号Φの立ち上りでその出力を保持する。このためラッチ回路６７、６８の合計を奇数とすると、走査方向を切り換えたときの入力信号ＤＩを取り込むときのクロックΦのエッジが異なってしまう。
【００５４】
さらに、ラッチ回路６７、６８の合計が奇数の場合の問題点を図３を例に示すと、図３の走査方向が上から下の場合では、初段はラッチ回路６７となり、クロックΦの立ち上がりで走査が開始される。対して走査方向が下から上の場合では、ラッチ回路６８が初段となり、クロックΦの立ち下がりで走査か開始される。このため３板方式の液晶プロジェクタ等、同時に逆方向に走査する液晶パネルを表示する場合など、クロックΦと映像信号のタイミングを調整する必要等の問題が生じる。
【００５５】
上述したような問題点をも解決するため、図２、図３の水平シフトレジスタ部２０、垂直シフトレジスタ部３０では、双方向シフトレジスタＨＳＲ１、ＨＳＲ５１３、ＶＳＲ１、ＶＳＲ３８５の１段目をダミーのラッチ回路として、ラッチ回路６７、６８の合計を偶数としている。
【００５６】
なお、双方向シフトレジスタの説明を、入力側からラッチ回路６７、６８の順番に並ぶ場合を用いて説明したが、図４（ａ）のような、ラッチ回路の並ぶ順番がラッチ回路６８、６７となる場合でも同等の動作となる。またクロック信号Φは任意の信号として説明したが、水平方向走査に用いる双方向シフトレジスタＨＳＲに用いられるクロック信号と、垂直方向走査に用いる双方向シフトレジスタＶＳＲに用いられるクロック信号とでは、その周期、デューティ比等が異なってもかまわず、液晶パネルの画素数等に従ったクロック信号が用いられる。
【００５７】
次に双方向シフトレジスタのリセット回路について説明する。図２の水平シフトレジスタ部２０では、リセット用トランジスタ２８が設けられており、インバータ６１、６２の入力をＨレベルにすることで、クロック信号の状態にかかわらず、各双方向シフトレジスタＨＳＲの出力をＬレベルにでき、映像信号供給回路２１の出力を強制的に停止できるようになっている。このため電源投入時の双方向シフトレジスタＨＳＲの状態を一定に保つことができるので、双方向シフトレジスタＨＳＲの電源電流を過渡的にも小さくすることができる。このためシフトレジスタの電源ラインの線幅を狭くすることができる。また垂直シフトレジスタ部３０にも同じくリセット回路を設けてあり、各シフトレジスタの出力をＬレベルとすることができ、映像信号供給回路２１、出力回路３２及び画素領域のスイッチング素子をオフ状態にできるので、液晶に直流電圧が印加されることを防ぐことができる。
【００５８】
また液晶パネルの画素数よりも少ない画素数の規格の画像を出力する場合、例えば、ＸＧＡパネルにＶＧＡの映像を表示する場合、ＶＧＡの水平走査が終了した時点で水平シフトレジスタ部２０を、また垂直走査が終了した時点で垂直シフトレジスタ部３０をリセットすることで、残りの画素領域に２重に表示されることが防止できる。
【００５９】
なお、双方向シフトレジスタＨＳＲ、ＶＳＲの出力をＬレベルとするようにリセット用トランジスタ２８はＰ型トランジスタを用いたが、映像信号供給回路２１、３２をオフ状態とするために、リセット用トランジスタ２８にＮ型トランジスタを用いることも可能である。
【００６０】
次に、図７から図１３を用いて本実施の形態の水平シフトレジスタ部２０による水平信号供給回路２１の駆動方法を示す。まず図７から図９を用いて映像信号をあらかじめ外部でサンプリングして複数の系列に分割した場合の駆動方法について説明する。図１、図２に示すように映像信号は４本の映像信号入力線２２（ＶＩＤ１〜ＶＩＤ４）で供給されているが、これにより画素に映像信号を書き込む時間を長くすることが可能である。すなわち外部回路において映像信号をクロック信号Φの周期に合わせてサンプリングし、図７に示す映像信号Ｖ１乃至Ｖ４のように、映像信号に対応した電圧を一定期間、映像信号入力線に供給する。その際サンプリングする順番に従って、映像信号入力線ＶＩＤ１には映像信号Ｖ１が供給され、映像信号入力線ＶＩＤ２には映像信号Ｖ２が、以下、映像信号Ｖ３、映像信号Ｖ４とサンプリングした一定電圧の信号が供給される。このように映像信号入力線２２を複数設けることで映像信号の出力期間を重複させ、映像信号が供給されている期間を延ばすことが可能である。
【００６１】
上述したように、サンプリングした映像信号を複数の系列に分割し、映像信号の周波数を低減した場合、シフトレジスタは映像信号の出力期間に合わせて、オン状態の期間を長くするよう駆動される。
【００６２】
図７では図４（ａ）の双方向シフトレジスタＨＳＲの駆動方法を、映像信号がクロック信号Φの２周期分にあたる期間あたえられる場合の例を示しており、入力信号ＤＩがクロック信号Φの立ち上がりａ−１からａ−４までＨレベルとなるように入力されている、そのため出力ＯＵＴ１がクロック信号Φの立ち上がりａ−１からａ−４までＨレベルであることから、出力ＯＵＴ１の状態をクロック信号Φの立ち上がりで出力し保持する出力ＯＵＴ２は、クロック信号Φの２周期分にあたる立ち上がりａ−１からａ−５までＨレベルとなる。同じく出力ＯＵＴ３以降もクロック信号Φの２周期分の間Ｈレベルを出力する。
【００６３】
上記駆動方法とすることで、映像信号がクロック信号Φの複数周期分にあたる期間あたえられる場合でも、映像信号の期間に合わせてシフトレジスタの出力期間を長くすることが可能である。
【００６４】
図７では図が複雑となることを避けるために、映像信号Ｖ１と映像信号Ｖ２に対応する出力ＯＵＴ２、出力ＯＵＴ３についてのみ記載しているが、同様に映像信号を画素に書き込むために、双方向シフトレジスタＨＳＲから画素数に応じて駆動信号が出力される。また、画素数が増加する等により画素毎の書き込み時間が短くなった場合には、映像信号入力線の本数をさらに増加してもよい。
【００６５】
次に映像信号を分割した場合について、映像信号の位相が揃っている場合（図８）と、揃っていない場合（図９）について説明する。なお図８から図１０では、説明をわかりやすくするために、１行１３列の画素ｐ１〜ｐ１３にスイッチｓ１乃至ｓ１３を用いて、映像信号Ｖ１乃至Ｖ４を書き込む場合について記載してある。映像信号はサンプリングされ、４本の映像信号線にＶ１、Ｖ２、Ｖ３、Ｖ４の順番で分割されている。図中、映像信号Ｖ１乃至Ｖ４の信号波形に付された符号は書き込まれる画素との対応を示している。
【００６６】
図８では画素の書き込み時間はクロック信号４周期分まで延ばされており、さらに映像信号Ｖ１乃至Ｖ４の位相が揃うように再度サンプリングしている。この場合、スイッチｓ１乃至ｓ４を同時にオンとして画素ｐ１〜ｐ４に書き込んでも、映像信号Ｖ１乃至Ｖ４の位相が揃っているので、正常に書き込みが行われる。よって、スイッチｓ１からｓ４までを駆動する信号を出力するシフトレジスタは共通とすることができ、シフトレジスタの段数を少なくすることができる。またスイッチｓ５からｓ８を駆動する信号はスイッチｓ１からｓ４までを駆動する信号の立ち下がるのを受けて、立ち上ればよくクロック信号の１周期を映像信号の立ち上りから立ち下がりまでの間に合わせてシフトレジスタを駆動すればよく、図７を用いて前述したように、クロック信号の複数の周期分出力が可能なシフトレジスタを用いる必要はない。
【００６７】
次に図９に、映像信号Ｖ１乃至Ｖ４の位相が揃っていない場合を示す。この場合サンプリングが１度ですみ外部の回路は簡単で済むが、映像信号Ｖ１乃至Ｖ４の位相が揃っていないので、映像信号を画素に書き込むスイッチｓ１乃至ｓ１３を駆動する信号も画素数分必要である。このためシフトレジスタも画素数分段数が必要であり図８の場合に比べてシフトレジスタの段数が増加する。さらに、映像信号の出力期間に合わせて駆動するためには、図７に示すようにシフトレジスタの出力期間を延ばすことが必要である。
【００６８】
次に、走査方向を反転した場合の映像信号の並び替えについて説明する。図１０は図９の映像信号線の並びで、スイッチｓ１３から順にｓ１までをオン状態にして、画素ｐ１３からｐ１に映像信号を書き込んだ場合を示す。まず映像信号Ｖ１に１番目の映像信号が供給され、スイッチｓ１３がオンとなり図中左端の画素に１番目の映像信号が書き込まれる。次に、映像信号Ｖ２に２番目の映像信号が供給され、スイッチｓ１２がオン状態となるが、スイッチｓ１２は映像信号Ｖ４とつながっているため、映像信号は画素に書き込まれず、スイッチｓ１２がオン状態のままで、映像信号Ｖ４に４番目の映像信号が供給されて、左から２番目の画素ｐ１２には４番目の映像信号が書き込まれる。さらにｐ１１には３番目の映像信号が書き込まれ、ｐ１０には２番目と６番目の映像信号が書き込まれる。このように反転走査に対応して映像信号を並べ換えないと、映像信号の並びが元の画像の並びと異なってしまうといった問題点がある。
【００６９】
図１１に信号切替え回路の一例を示す。図１１に示す例では、4本の映像信号入力端子２４ａ、２４ｂ、２４ｃ、２４ｄにそれぞれ時系列に映像信号が入力される。信号切替え回路２３は、４本の映像信号入力端子のうち、左から２番目と４番目の端子２４ｂと、２４ｄに入力される映像信号を入れ替える作用をする。図に１１おいて、切替えの必要がない左から１番目と３番目の端子２４ａ、２４ｃについても、端子２４ｂ、２４ｄと同様の回路を設けているが、切替え動作は行わない。これは、２番目と４番目の端子２４ｂ、２４ｄに入力される映像信号に対して位相や振幅に差を生じさせないためである。
【００７０】
図１２に図２に示す水平シフトレジスタ部２０からの信号により、映像信号供給回路２１が映像信号線に映像信号を供給するようすを説明する概略回路図と図１３にタイミングチャートを示す。図１２では、図をわかりやすくするために、映像信号供給回路２１はスイッチで表示し、水平シフトレジスタ部２０の詳細は省略してあるが、図２で示す映像信号供給回路２１と水平シフトレジスタ部２０と同じものである。また、図１の画素領域１０中の１行分の画素Ｐ１乃至Ｐ１０２５を模式的に記載してあり、図１の映像信号線１１を各画素に対応するようＬ１乃至Ｌ１０２５で示している。
【００７１】
映像信号Ｖ１乃至Ｖ４は信号切替え回路２３で映像信号入力線２２（ＶＩＤ１〜ＶＩＤ４）が選ばれ、それぞれが図１３に示すようなタイミングで映像信号入力線に供給される。水平シフトレジスタ部２０からは図１２中左から右の順番に画素に映像信号が書き込まれる場合には（順方向走査）、出力Ｈ１乃至Ｈ１０２５が映像信号に対して図１３（ａ）に示すタイミングで出力される。図１３（ａ）では図をわかりやすくするため、出力Ｈ１乃至Ｈ５までしか記載していないが、同様に出力Ｈ１０２５まで出力は続き、１行分の画素の書き込みが行われる。なお図１３（ａ）は順方向走査を、図１３（ｂ）は逆方向走査の場合を示し、図中各映像信号Ｖ１乃至Ｖ４の信号波形に付されているＰ１乃至Ｐ１０２５の符号は、図１２に示す画素Ｐ１乃至Ｐ１０２５に書き込まれる映像信号であることを示す。
【００７２】
水平シフトレジスタ部２０から出力Ｈ１が出力されると、映像信号入力線ＶＩＤ１と映像信号線Ｌ１（１１）が電気的に接続され、映像信号入力線ＶＩＤ１に出力されていた映像信号Ｖ１が映像信号線Ｌ１を介して画素Ｐ１に供給される。以下同様に、映像信号入力線ＶＩＤ１に出力されていた映像信号Ｖ１が映像信号線Ｌ１０２５を介して画素Ｐ１０２５に書き込まれるまで続き、１行分の画素の書き込みが行われる。
【００７３】
図１３（ｂ）に示す逆方向走査では、まず映像信号入力線ＶＩＤ２に映像信号Ｖ４が出力され、映像信号入力線ＶＩＤ４に映像信号Ｖ２が出力されるように信号切替え回路２３を用いて映像信号の並びが切替えられている。
【００７４】
逆方向走査では、水平シフトレジスタ部２０から出力Ｈ１０２５が最初に出力されると、画素Ｐ１０２５に映像信号Ｖ１が書き込まれる。つぎに出力Ｈ１０２４が出力されると、映像信号入力線ＶＩＤ４に供給されている映像信号が画素Ｐ１０２４に供給されるが、この時信号切替え回路２３で映像信号入力線ＶＩＤ４には、映像信号Ｖ２が出力されるので、２番目にサンプリングされた映像信号が画素Ｐ１０２４に書き込まれることとなる。以下同様に順次１行分の画素に映像信号が書き込まれる。
【００７５】
以上説明したように水平シフトレジスタ部２０により映像信号供給回路２１が駆動され、画素に映像信号が書き込まれる。
【００７６】
次に図１４から図２０を用いて垂直シフトレジスタ３０により走査信号を駆動する方法を説明する。
【００７７】
図１４に図４（ｂ）の双方向シフトレジスタＶＳＲでクロック信号Φのデューティ比を変更した場合のタイミングチャートの１例を示す。図１４では、クロック信号Φの立ち下がりｂ−１に対応して、出力ＯＵＴ２がＨレベルとなっている。次にクロック信号Φの立ち上がりｂ−２に対応して出力ＯＵＴ３がＨレベルとなる。このときクロック信号Φのデューティ比はＨレベルの期間が長く、Ｌレベルの期間が短く設定されており、それに伴い出力ＯＵＴ２の立ち上がりから、出力ＯＵＴ３の立ち上がりまでの期間が短くなっている。
【００７８】
さらにクロック信号Φの立ち下がりｂ−３に対応して出力ＯＵＴ４がＨレベルとなり、クロック信号Φの立ち上がりｂ−４に対応して出力ＯＵＴ５がＨレベルとなる、このときクロック信号Φのデューティ比はＨレベルの期間が長く、Ｌレベルの期間が短いため、出力ＯＵＴ３の立ち上がりから、出力ＯＵＴ４の立ち上がりまでの期間が長く、出力ＯＵＴ３の立ち上がりから、出力ＯＵＴ５４立ち上がりまでの期間が長くなっている。
【００７９】
このようにクロック信号Φのデューティ比を変更することで、あたかも各出力ＯＵＴ１、出力ＯＵＴ２、… の位相がずれたように駆動することが可能である。
【００８０】
図１５、図１６は順次走査駆動する場合の駆動タイミングを示すタイミングチャートで、図１５は図３の上から下に向かって走査する順方向走査を示している。そのため、第１垂直方向設定線にはＨレベルが入力されている。映像信号はビデオ信号等の各画素毎に書き込まれる階調等の１ライン分の信号を表している、また１Ｈは１ライン分の水平走査期間を表している。図４に示すラッチ回路６７はクロックＶＣＬＫ１の立ち上がりエッジで入力信号を出力し保持する、ラッチ回路６８はクロックＶＣＬＫ１の立ち下がりで入力信号を出力し保持する。このため、クロックＶＣＬＫ１のデューティを変化させることで奇数ラインと偶数ラインの画素に対応するシフトレジスタからの出力の位相を変化させることが可能である。
【００８１】
クロックＶＣＬＫ１のデューティ比をＬレベルの期間が、映像信号のブランク期間以内程度となるように調節する。そのために、双方向シフトレジスタＶＳＲ１の出力ＧＳ１は入力信号（走査スタート信号）ＶＤＩを図１５のように入力すると、クロックＶＣＬＫ１の立ち下がりで入力を出力してＨレベルとなり次のクロックＶＣＬＫ１の立ち下がりまで値を保持する。ただし、図６を用いて前述したように、双方向シフトレジスタＶＳＲ１の初段にはダミーのラッチ回路が設けられている。双方向シフトレジスタＶＳＲ２の出力ＧＳ２はクロックＶＣＬＫ１の立ち上がりで、出力ＧＳ１のＨレベルを取り込み、次のクロックＶＣＬＫ１の立ち上がりまで値を保持する。
【００８２】
この出力ＧＳ１と出力ＧＳ２との位相差は、クロックＶＣＬＫ１のＬレベルの期間とほぼ等しい期間となる。このとき垂直走査制御端子ＣＮＴ１と、ＣＮＴ２とは図１５に示すように与えられており、出力ＧＳ１は垂直走査制御端子ＣＮＴ１と垂直走査制御部３３のＮＡＮＤ回路で演算され出力回路３２に出力され、出力回路３２の出力Ｇ１として出力され、出力ＧＳ２は垂直走査制御端子ＣＮＴ２と垂直走査制御部３３で演算され、出力回路３２の出力Ｇ２として出力される。
【００８３】
図１５に示す駆動方法では、垂直走査制御端子ＣＮＴ１とＣＮＴ２を用いる場合を説明したが、垂直走査制御端子ＣＮＴ１とＣＮＴ２にＨレベルを出力し、垂直クロック信号ＶＣＬＫのデューティ比を５０％で駆動しても同じ結果を得ることができる。
【００８４】
次に図１６に、図３の下から上に向かって走査する逆方向の順次走査のタイミングチャートを示す。逆方向ののため、第１垂直方向設定線はＬレベルが入力される。図１６の場合は、基本的な動作は図１５と同じであるが、出力Ｇ７６９から逆にＧ１に向かい順番に出力され、最後に走査終了信号ＶＤＯが端子３８に出力される。
【００８５】
図１７は走査信号線の２ｎ−１ラインと２ｎラインとの同時駆動の場合のタイミングチャートを示す。ただし、ここでｎは整数を示す。垂直走査制御端子ＣＮＴ１とＣＮＴ２とを同相で与えることで、出力回路３２からの出力Ｇ１とＧ２とを同時に出力することができる。
【００８６】
また図１８に走査信号線の２ラインと２ｎ＋１ラインとの同時駆動の場合のタイミングチャートを示す。クロックＶＣＬＫ１は反転しており、Ｈレベルの期間が映像信号のブランク期間とほぼ同等の期間となっている。双方向シフトレジスタＶＳＲ１はクロックＶＣＬＫ１の立ち下がりで、ダミーのラッチ回路の出力のＨレベルを取り込み、出力ＧＳ１にＨレベルを出力し次のクロックＶＣＬＫ１の立ち下がりまで値を保持する。双方向シフトレジスタＶＳＲ２の１段目のラッチ回路６７は出力ＧＳ１のＨレベルをクロックＶＣＬＫ１の立ち上がりで取り込み出力ＧＳ２に出力し次のクロックＶＣＬＫの立ち上がりまで保持する。次に、垂直シフトレジスタＶＳＲ２の２段目のラッチ回路６６は出力ＧＳ２のＨレベルをクロックＶＣＬＫ１の立ち下がりで取り込み出力ＧＳ２に出力し次のクロックＶＣＬＫ１の立ち上がりまで保持する。出力ＧＳ１とＧＳ２との位相差はクロックＶＣＬＫ１のＬレベルの期間とほぼ等しい期間となっており、ほぼクロックＶＣＬＫ１の１周期に近い期間となり、出力ＧＳ２とＧＳ３との位相差はクロックＶＣＬＫ１のＨレベルの期間とほぼ等しい期間となっている。そのため、出力ＧＳ２とＧＳ３との位相差は短くなっており、出力ＧＳ２とＧＳ３とは、ほぼ同相で出力される。さらに出力ＧＳ２とＧＳ３とが重なって出力される期間に、垂直走査制御端子ＣＮＴ１とＣＮＴ２から信号を同相で与えることで、出力回路３２からの出力Ｇ２とＧ３とを同時に駆動することができる。
【００８７】
図１９に走査信号線の２ｎ−１ラインと２ｎラインとを同時駆動し、２ｎライン目を間引き、その後２ｎラインと２ｎ＋１ラインとを同時駆動する駆動方法を示す。クロックＶＣＬＫ１を２ｎライン目の終わりで反転し、クロックＶＣＬＫ１の立ち上がりを１周期分遅らせることで、出力ＧＳ２ｎのＨレベルの期間が、クロックＶＣＬＫ１の２周期近くになり、垂直走査制御端子ＣＮＴ１とＣＮＴ２から信号を同相で与えて垂直走査制御部３３で演算させることで、出力Ｇ２ｎを２回出力させ、２本同時駆動している走査信号線の２ｎライン目を間引くことができる。
【００８８】
図２０に走査信号線の２ｎ−１ラインと２ｎ−２ラインとを同時駆動し、２ｎ−１ライン目を間引き、その後２ｎラインと２ｎ−１ラインとを同時駆動する駆動方法を示す。
【００８９】
図２１（ａ）は、図４（ｂ）に示すラッチ回路６７、６８に負荷駆動能力を向上させ、シフトレジスタの動作を高速にするためのバッファ用インバータを設けたものである。ラッチ回路６７、６８をクロックドインバータ６３〜６６で構成するとともに、バッファ用インバータ６０１を挿入している。バッファ用インバータ６０１はクロックドインバータとクロックドインバータとの間に挿入されているため、各クロックドインバータの負荷駆動能力不足を補い、高速駆動が可能なシフトレジスタを形成することが可能となる。
【００９０】
次に図２１（ｂ）を用いて図２１（ａ）の動作を説明する。図２１（ｂ）に示すラッチ回路６７は、クロックドインバータ６５の出力がインバータ６０１ａの入力に接続され、インバータ６０１ａの出力がインバータ６３ａの入力に接続され、このインバータ６３ａの出力をインバータ６０１ｂを介してクロックドインバータ６６の入力に接続している。
【００９１】
クロックドインバータ６５に入力された信号は３回反転され、インバータ６３ａから出力されるため、クロック信号ΦのＨレベル立ち上がり時にクロックドインバータ６５に入力された信号はインバータ６３ａから反転され出力される。次にクロック信号ΦバーがＨレベルとなると、クロックドインバータ６５はハイインピーダンスとなるがクロックドインバータ６６がインバータとして働き、インバータ６３ａの出力は２回反転してクロックドインバータ６６から出力される。ここで、クロック信号ΦバーがＨレベルとなる前のクロックドインバータ６５の出力と、クロック信号ΦバーがＨレベルとなった後のクロックドインバータ６６の出力が同じ値となるため、クロック信号ΦバーがＨレベルとなる前のクロックドインバータ６５の入力はラッチされ、インバータ６３ａから反転信号が出力する。
【００９２】
またラッチ回路６８でも同様な動作となり、入力の値がラッチされ、インバータ６３ａから反転信号が出力する。このようにバッファ用インバータ６０１を追加することで、双方向シフトレジスタＨＳＲ、ＶＳＲは負荷駆動能力不足が補われ、高速駆動が可能となる。
【００９３】
図２２は本発明の液晶表示装置を適用した液晶プロジェクタを説明する光学系の模式図であって、２２０は光源、２２１は放物面鏡、２２２はコンデンサレンズ、２２３は反射鏡、２２４は第１の絞り、２２５はレンズ、２２６はダイクロイックプリズム、２２７Ｒは赤色用反射型液晶表示装置、２２７Ｇは緑色用反射型液晶表示装置、２２７Ｂは青色用反射型液晶表示装置、２２８は第２の絞り、２２９は投射レンズ、２３０はスクリーンである。本実施の形態では、緑色用反射型液晶表示装置２２７Ｇを逆方向走査することとなる。
【００９４】
図２３は本発明による液晶表示装置を反射型液晶表示装置に適用した場合を説明する展開斜視図であって、７１４は液晶パネル、７０１は透明基板、７０２はシリコン基板で画素電極等と共に画素電極を駆動する駆動回路が設けられ、上述した水平シフトレジスタ部２０、垂直シフトレジスタ部３０が形成されている。透明基板７０１とシリコン基板７０２の間には図示しないが液晶層が設けられている。７０７はパッケージ、７０９は液晶パネル７１４に給電するためのフレキシブルプリント基板、７１３は遮光枠、７１２はフレキシブルプリント基板押さえ、７１０は液晶パネル７１４の熱を外部に逃がす放熱シート、７１１はパッケージ７０７の底部に設けられた放熱板である。
【００９５】
図２４は本発明を反射型液晶表示装置の一つであるポリマー分散型液晶（ＰＤＬＣ）に適用した場合の、液晶表示装置の液晶層を示す概略構成図である。液晶層は高分子マトリクス７０３中に液晶７３９を分散したポリマー分散型液晶（ＰＤＬＣ）で、印加電圧に応じて光を散乱する状態から透過する状態に変化する。図２３（ａ）に本液晶プロジェクタに用いられる液晶表示装置で光が散乱する様子を示し、図２４（ｂ）に反射する様子を示す。第２の基板７０２には反射画素電極７３８、第１の基板７０１には透明電極７３０が形成されている。
【００９６】
図２４（ａ）に示すように第２の基板７０２の反射画素電極７３８と第１の基板７０１の透明電極７３０との間に電圧を印加してない状態では、液晶７３９はそれぞれ不規則な方向に配列している。この状態では高分子マトリクス７０３と液晶分子とに屈折率の差が生じ、入射光７４１は散乱する、７４２は散乱光を示す。図２４（ｂ）に示すように第２の基板７０２の反射画素電極７３８と第１の基板７０１の透明電極７３０との間に電圧を印加した状態では、液晶７３９が一定方向に配向する。この液晶７３９が一定方向に配向したときの屈折率と高分子マトリクス７０３の屈折率を合わせておくと、入射光７４１は散乱せず反射画素電極７３８で正反射する、なお７４３は反射光を示す。
【００９７】
【発明の効果】
以上説明したように、本発明による液晶表示装置によれば、双方向に走査することが可能となり、画像を反転出力することが容易になり、反転出力する手段を別に設ける必要もなくコンパクトな液晶表示装置となる。
【図面の簡単な説明】
【図１】本発明による液晶表示装置を説明する概略ブロック図である。
【図２】本発明による液晶表示装置を説明する概略回路図である。
【図３】本発明による液晶表示装置を説明する概略回路図である。
【図４】本発明による液晶表示装置を説明する概略回路図である。
【図５】本発明による液晶表示装置に用いられるクロックドインバータを説明する概略回路図である。
【図６】本発明による液晶表示装置の動作を説明する概略タイミングチャートである。
【図７】本発明による液晶表示装置の動作を説明する概略タイミングチャートである。
【図８】本発明による液晶表示装置の動作を説明する概略回路図と概略タイミングチャートである。
【図９】本発明による液晶表示装置の動作を説明する概略回路図と概略タイミングチャートである。
【図１０】本発明による液晶表示装置の動作を説明する概略回路図と概略タイミングチャートである。
【図１１】本発明による液晶表示装置の信号切替え回路を説明する概略回路図である。
【図１２】本発明による液晶表示装置の映像信号供給回路を説明する概略回路図である。
【図１３】本発明による液晶表示装置の映像信号供給回路の動作を説明する概略タイミングチャートである。
【図１４】本発明による液晶表示装置の動作を説明する概略タイミングチャートである。
【図１５】本発明による液晶表示装置の動作を説明する概略タイミングチャートである。
【図１６】本発明による液晶表示装置の動作を説明する概略タイミングチャートである。
【図１７】本発明による液晶表示装置の動作を説明する概略タイミングチャートである。
【図１８】本発明による液晶表示装置の動作を説明する概略タイミングチャートである。
【図１９】本発明による液晶表示装置の動作を説明する概略タイミングチャートである。
【図２０】本発明による液晶表示装置の動作を説明する概略タイミングチャートである。
【図２１】本発明による液晶表示装置のラッチ回路を説明する概略回路図である。
【図２２】本発明の液晶表示装置を適用した液晶プロジェクタを説明する光学系の模式図である。
【図２３】本発明による液晶表示装置を反射型液晶表示装置に適用した場合を説明する展開斜視図である。
【図２４】本発明をＰＤＬＣに適用した場合の、液晶表示装置の液晶層を示す概略構成図である。
【図２５】３板方式の液晶プロジェクタ光学系を説明する概略構成図である。
【符号の説明】
１０…画素領域、１１…映像信号線、１２…走査信号線、１３…スイッチング素子、１４…画素電極、１５…対向電極、１６…保持容量、２０…水平シフトレジスタ部、２１…映像信号供給回路、２２…映像信号入力線、２３…映像信号切替回路、２４…映像信号入力端子、２５…水平走査リセット信号入力端子、２６…水平走査スタート信号入力端子、２７…水平走査終了信号出力端子、３０…垂直シフトレジスタ部、３２…垂直出力回路で、３３…垂直走査制御回路、３６…垂直走査リセット端子、３７…垂直走査スタート信号入力端子、３８…垂直走査終了信号出力端子、６１、６２、６３、６４、６５、６６…クロックドインバータ、６７、６８…ラッチ回路、７１、７２…Ｐ型トランジスタ、７３、７４…Ｎ型トランジスタ、ＨＳＲ、ＶＳＲ…双方向シフトレジスタ、ＨＣＬＫ１、ＨＣＬＫ２、ＶＣＬＫ１、ＶＣＬＫ２、Φ、Φバー…クロック信号線、ＲＬ…水平走査方向設定信号線、ＲＬ１…第１水平方向設定線、ＲＬ２…第２水平方向設定線、ＵＤ…垂直走査方向設定線、ＵＤ１…第１垂直方向設定線、ＵＤ２…第２垂直方向設定線、ＣＮＴ１、ＣＮＴ２…制御信号入力端子、ＤＩ…入力信号、ＯＵＴ…出力、２２０…光源、２２１…放物面鏡、２２２…コンデンサレンズ、２２３…反射鏡、２２４…第１の絞り、２２５…レンズ、２２６…ダイクロイックプリズム、２２７Ｒ…赤色用反射型液晶表示装置、２２７Ｇ…緑色用反射型液晶表示装置、２２７Ｂ…青色用反射型液晶表示装置、２２８…第２の絞り、２２９…投射レンズ、２３０…スクリーン、７１４…液晶パネル、７０１…透明基板、７０２…シリコン基板、７０７…パッケージ、７０９…フレキシブルプリント基板、７１３…遮光枠、７１２…フレキシブルプリント基板押さえ、７１０…放熱シート、７１１…放熱板。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device, and more particularly to a technique effective when used for a display substrate having an active matrix structure and a driving circuit thereof formed on a glass substrate or a silicon chip.
[0002]
[Prior art]
Liquid crystal panels are widely used as monitors for information devices such as television receivers and personal computers, and other display devices for various display devices.
[0003]
In this type of liquid crystal panel, a drive electrode that serves as a pixel selection power supply electrode or a switching element power supply electrode is formed on one substrate, a common electrode is formed on the other substrate, and both electrode sides are opposed to each other. The liquid crystal layer is sandwiched between the bonding gaps.
[0004]
In the system using an amorphous silicon thin film for the channel layer of the switching element, the transistor characteristics are limited, and the drive circuit characteristics are not sufficient, so that a peripheral drive circuit is externally provided.
[0005]
On the other hand, a thin film transistor (hereinafter referred to as TFT) is formed using a polysilicon film, and a drive circuit is also formed on the same glass substrate. As a TFT element using a polysilicon film, a product having a number of pixels of about 100,000 and a diagonal length of a display area of 0.7 inches is used as a color finder for a small video camera.
[0006]
Furthermore, in the TFT display device using this polysilicon film, the use as a light valve of a projector and the use as a panel for a head mount (glasses type) display oriented to virtual reality have been developed.
[0007]
In addition, a polymer-dispersed liquid crystal (hereinafter referred to as PDLC) in which a common electrode is formed on a transparent substrate, a drive electrode is formed on a silicon substrate, and a polymer-dispersed liquid crystal layer is sandwiched between the bonding gaps between the two, A reflective liquid crystal element has been developed in which an electrode having a purpose of reflecting light is formed on a silicon substrate, and a liquid crystal layer is sandwiched between the silicon substrate and a transparent substrate.
[0008]
As described above, in a method of using a TFT display device using a polysilicon film or a display device using a PDLC or a reflective liquid crystal element, a three-plate type liquid crystal using a display device that forms an image for each of red, green, and blue There is a projector optical system.
[0009]
FIG. 25 shows an outline of a three-plate liquid crystal projector optical system. For example, light from a light source 850 including a short arc metal halide lamp and a parabolic mirror reaches the dichroic mirror 851. Here, the dichroic mirror 851 has a function of reflecting or transmitting light in a specific wavelength range, and only blue light is reflected by changing its direction by 90 degrees, and other light is transmitted. The transmitted light is incident on the dichroic mirror 852, only the green light is reflected, and the transmitted light is red. In this way, each of the lights separated in the order of blue, green, and red is incident on dedicated liquid crystal panels 853, 854, and 855.
[0010]
Each panel 853, 854, and 855 reproduces an image corresponding to each color, and the incident light is synthesized after being modulated for each color.
[0011]
The dichroic mirror 856 reflects green light and combines it with the transmitted blue light, and the dichroic mirror 857 combines it with the red light. The synthesized light is projected onto the screen by the projection lens.
[0012]
[Problems to be solved by the invention]
In the optical system as described above, since the blue transmitted light is never reflected, the liquid crystal panel pattern is synthesized as it is and is incident on the projection lens. The red transmitted light undergoes a 90-degree change of direction twice by the reflecting mirror 858 and the dichroic mirror 857, so that the liquid crystal panel pattern is synthesized as it is and incident on the projection lens in the same manner as the blue transmitted light. Is done.
[0013]
Furthermore, since the green transmitted light is changed in direction by 90 degrees once by the dichroic mirror 856, the up and down or the left and right are inverted and incident on the projection lens. Therefore, in order to match the images, the green liquid crystal panel 854 displays an image that is reversed left and right or up and down. Reference numeral 859 denotes a reflection mirror.
[0014]
In general, in the green liquid crystal panel 854, an inversion drive circuit is separately provided to invert the image horizontally and vertically, or the green liquid crystal panel 854 is specially used for displaying an inverted image, and the red and blue liquid crystal panels 853 and 855 are provided. A method is used in which scanning is performed in the opposite direction, or image data is temporarily stored in a memory and read out so that the image is reversed.
[0015]
In other words, in the three primary color separation type liquid crystal projector, the number of inversions for one color is different from the odd number (or even number), and in the normal liquid crystal panel, an image that is reversed horizontally or vertically is output. Therefore, in general, a special configuration is added to output an inverted image.
[0016]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.
[0017]
A liquid crystal, a plurality of pixel electrodes for driving the liquid crystal, an output circuit for supplying a signal for driving the pixel electrode, and a scanning circuit for outputting a plurality of scanning signals for driving the output circuit are provided on the same substrate. The scanning circuit is capable of scanning in the first scanning direction and the second scanning direction, and the scanning circuit is an output in the first scanning direction and an input in the second scanning direction. 1 input / output unit, a second input / output unit that is an output in the case of the second scanning direction and an input in the case of the first scanning direction, and a first input / output in the case of the first scanning direction. The liquid crystal display device includes a reset circuit that turns off the display unit and turns off the second input / output unit in the second scanning direction.
[0018]
A liquid crystal; a pixel electrode for driving the liquid crystal; an output circuit for supplying a signal for driving the pixel electrode; and a scanning circuit for outputting a scanning signal for driving the output circuit on the same substrate. The liquid crystal display device can scan in the first scanning direction and the second scanning direction, and the output of the first stage of the scanning circuit is not connected to the output circuit.
[0019]
A liquid crystal; a plurality of pixel electrodes for driving the liquid crystal; an output circuit for supplying a signal for driving the pixel electrode; and a scanning circuit for outputting a scanning signal for driving the output circuit. A liquid crystal display device capable of scanning in one scanning direction and a second scanning direction and capable of changing the phase of adjacent scanning signals of the scanning circuit by changing the duty ratio of a clock signal input to the scanning circuit; To do.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0021]
FIG. 1 shows an embodiment of a liquid crystal display device according to the present invention. FIG. 1 shows a block for each function formed on the substrate, and 10 shows a pixel region. A plurality of video signal lines 11 extending in the vertical direction in FIG. 1 and arranged in parallel in the horizontal direction are provided in the pixel region 10. Parallel scanning signal lines 12 are provided. A switching element 13 is provided in the vicinity of the intersection of the video signal line 11 and the scanning signal line 12, and the video signal is written to the pixel electrode 14 by operating the switching element 13 by the scanning signal line 12 and the video signal line 11. A counter electrode 15 is provided to face the pixel electrode 14, and the liquid crystal is driven by a potential difference between the pixel electrode 14 and the counter electrode 15 to display an image. The pixel electrode 14 is provided with a holding capacitor 16 for the purpose of holding a video signal in the pixel electrode for a certain period. In FIG. 1, the pixel electrode 14, the counter electrode 15, and the storage capacitor 16 are shown in an equivalent circuit. Further, in order to simplify the drawing and make it easy to understand, the pixel portion is displayed only for one pixel, but a plurality of pixels are arranged in a matrix in the pixel region.
[0022]
In general, image writing starts from the upper left of FIG. 1, and video signals are sequentially written from the left to the right in the first row of pixels arranged in a matrix, and the first row is written. 1 shows an example of 1025 pixels in the horizontal direction and 769 pixels in the vertical direction, and when 1025 pixels in the first row are written, the video signal is again output in the right direction from the left side in the second row. 14 are sequentially written. Similarly, writing is performed up to the last 769 lines, and an image is displayed.
[0023]
In order to display a horizontally reversed image on such a liquid crystal display device, it is necessary to write a video signal from the right side to the left side of the pixels arranged in a matrix. Even in a system in which data for one row is temporarily stored in a latch circuit and the like, and then a video signal for one row is output according to the data, data is sequentially written in the latch circuit and the like from the left to the right.
[0024]
FIG. 2 shows a circuit configuration of the horizontal shift register unit 20. The HSR is a bidirectional shift register, and can shift a signal in both the left and right directions. From the left in the figure, HSR1, HSR2,. The bidirectional shift register HSR is composed of clocked inverters 61, 62, 65, 66. Details of the bidirectional shift register HSR will be described later. The video signal supply circuit 21 receives the output signal from the horizontal shift register unit 20 and outputs the video signal supplied from the video signal input lines 22 (VID1 to VID4) to the video signal line 11. Note that the video signal supply circuit 21 also performs level shift by converting the signal level of the output signal from the horizontal shift register unit 20 to a signal level for driving the video signal.
[0025]
The video signals supplied to the video signal input lines 22 (VID1 to VID4) are obtained by rearranging the order of the video signals input to the video signal input terminal 24 by the signal switching circuit 23 shown in FIG. It is. In the embodiment shown in FIGS. 1 and 2, video signals are supplied in parallel through four signal lines. For example, the first and second pixels horizontally arranged in order from the left of the video signal input terminal 24. Th ... the fourth corresponds to the order. Therefore, when the scanning direction is switched, it is necessary to change the order of the video signals. However, by changing the order of the video signals connected to the video signal input line 22 by the signal switching circuit 23, the order of the external video signals is changed. There is no need to replace it. Details of the signal switching circuit 23 will be described later.
[0026]
1 and 2, reference numeral 25 denotes a horizontal scanning reset signal input terminal. The bidirectional shift register HSR is reset by driving the reset transistor 28. Reference numeral 26 denotes a horizontal scanning start signal input terminal. When a start signal for scanning from the left to the right in FIG. 1 is supplied to the horizontal shift register unit 20 by the clocked inverter 61 and scanning is performed from right to left, A start signal is supplied to the horizontal shift register unit 20 by the clocked inverter 62. Reference numeral 27 denotes a horizontal scanning end signal output terminal.
[0027]
In FIG. 2, RL is a horizontal scanning direction setting signal line, RL1 is a first horizontal direction setting line, RL2 is a second horizontal direction setting line, and is a signal that defines the scanning direction of the bidirectional shift register. The first horizontal direction setting line RL1 takes out the signal inverted twice by the inverter from the horizontal scanning direction setting signal line RL, and the second horizontal direction setting line RL2 is inverted once by the inverter from the horizontal scanning direction setting signal line RL. Taking out the signal. Therefore, one of the first horizontal direction setting line RL1 and the second horizontal direction setting line RL2 is a signal obtained by inverting the other. HCLK is a horizontal clock signal line, HCLK1 is a first horizontal clock signal line, and HCLK2 is a second horizontal clock signal line.
[0028]
FIG. 3 shows a circuit configuration of the vertical shift register unit 30. Similarly to the horizontal shift register unit 20, the vertical shift register unit 30 can also shift signals in both directions, and when displaying an upside down image, a scanning signal is output upward from the lower side. . VSR is a bidirectional shift register, 32 is a vertical output circuit, and 33 is a vertical scanning control circuit. The vertical scanning control circuit 33 controls vertical scanning by control signals from the control signal input terminals CNT1 and CNT2. Reference numeral 36 denotes a vertical scanning reset terminal, 37 denotes a vertical scanning start signal input terminal, and 38 denotes a vertical scanning end signal output terminal. The bidirectional shift register VSR includes clocked inverters 63, 64, 65, and 66.
[0029]
UD is a vertical scanning direction setting line, UD1 is a first vertical direction setting line, and UD2 is a second vertical direction setting line. In FIG. 3, the first vertical direction setting line UD1 takes out a signal inverted twice by the inverter from the vertical scanning direction setting line UD, and the second vertical direction setting line UD2 takes one time from the vertical scanning direction setting line UD by the inverter. The inverted signal is taken out. Therefore, one of the first vertical direction setting line UD1 and the second vertical direction setting line UD2 is a signal obtained by inverting the other. VCLK is a vertical clock signal line, VCLK1 is a first vertical clock signal line, and VCLK2 is a second vertical clock signal line.
[0030]
FIG. 4 is a circuit configuration diagram illustrating the bidirectional shift registers HSR and VSR constituting the horizontal shift register unit 20 and the vertical shift register unit 30. FIG. 5 is a circuit diagram illustrating the clocked inverters 61, 62, 63, 64, 65, 66 used in the horizontal shift register unit 20 and the vertical shift register unit 30.
[0031]
First, the clocked inverters 61 and 62 used in the bidirectional shift register HSR shown in FIG. 4A will be described with reference to FIGS.
[0032]
The first horizontal direction setting line RL1 is at the H level when scanning from left to right in FIG. 2, and the second horizontal direction setting line RL2 is at the H level when scanning from right to left in FIG. In FIG. 1 and FIG. 2, the connection is omitted for the sake of clarity, but the first horizontal direction setting line RL1 and the second horizontal direction setting line RL2 are both clocked inverters 61 that constitute the bidirectional shift register HSR, 62.
[0033]
The clocked inverter 61 includes P-type transistors 71 and 72 and N-type transistors 73 and 74 as shown in FIG. The P-type transistor 71 is connected to the second horizontal direction setting line RL2, and the N-type transistor 74 is connected to the first horizontal direction setting line RL1. Therefore, when the first horizontal direction setting line RL1 is H level and the second horizontal direction setting line RL2 is L level, the clocked inverter 61 functions as an inverter, and the second horizontal direction setting line RL2 is H level and the first horizontal direction setting is performed. When the line RL1 is at the L level, the impedance is high.
[0034]
Conversely, in the clocked inverter 62, as shown in FIG. 5B, the P-type transistor 71 is connected to the first horizontal direction setting line RL1, and the N-type transistor 74 is connected to the second horizontal direction setting line RL2. ing. Therefore, when the second horizontal direction setting line RL2 is at H level, it functions as an inverter, and when the first horizontal direction setting line RL1 is at H level, it becomes high impedance. The operation of the bidirectional shift register HSR will be omitted by describing the operation of the bidirectional shift register VSR.
[0035]
Next, the clocked inverters 63 and 64 used in the bidirectional shift register VSR shown in FIGS. 4B, 4C and 4D will be described with reference to FIGS. The operation of the bidirectional shift register VSR in which the scanning direction is switched according to the value of the vertical scanning direction setting line UD that defines the above will be described.
[0036]
In FIG. 3, the first vertical direction setting line UD1 is at H level when scanning from top to bottom, and the second vertical direction setting line UD2 is at H level when scanning from bottom to top. In FIG. 1 and FIG. 3, the connection is omitted for the sake of clarity, but the first vertical direction setting line UD1 and the second vertical direction setting line UD2 are both clocked inverters 63 constituting the bidirectional shift register VSR, 64.
[0037]
The clocked inverter 63 includes P-type transistors 71 and 72 and N-type transistors 73 and 74 as shown in FIG.
[0038]
The first vertical direction setting line UD 1 is connected to the input of the N-type transistor 74, and the second vertical direction setting line UD 2 is connected to the input of the P-type transistor 71. 5D, the second vertical direction setting line UD2 is connected to the input of the N-type transistor 74 of the clocked inverter 64, and the first vertical direction setting line UD1 is connected to the input of the P-type transistor 71. Has been. Therefore, the clocked inverter 63 functions as an inverter when the first vertical direction setting line UD1 is H level and the second vertical direction setting line UD2 is L level, and the second vertical direction setting line UD2 is H level and the first vertical direction. When the setting line UD1 is at L level, the impedance becomes high impedance. The clocked inverter 64 operates opposite to the clocked inverter 63 with respect to the levels of the first and second vertical direction setting lines UD1, UD2.
[0039]
In the bidirectional shift register VSR shown in FIG. 4B, the first vertical direction setting line UD1 is at the H level, the clocked inverter 63 functions as the inverter 63a, and the clocked inverter 64 becomes high impedance. c), and when the second vertical direction setting UD2 is at the H level, the clocked inverter 64 functions as the inverter 64a and the clocked inverter 63 has a high impedance. Therefore, the equivalent circuit shown in FIG. It becomes a circuit. As described above, in the bidirectional shift register VSR, the scan direction of the shift register can be determined by the values of the first vertical direction setting line UD1 and the second vertical direction setting line UD2.
[0040]
Similarly, in the bidirectional shift register HSR, the scanning direction of the shift register can be determined by the values of the first horizontal direction setting line RL1 and the second horizontal direction setting RL2.
[0041]
Next, the operation of the shift register will be described with reference to FIG. The clocked inverter 65 has the circuit configuration shown in FIG. 5E. As shown in Table 1, when the clock Φ is H level and the clock Φ bar is L level, the input is inverted and the clock Φ is When the clock Φ bar is at the H level at the L level, the impedance becomes high.
[0042]
The clocked inverter 66 has the circuit configuration shown in FIG. 5 (f). When the clock Φ bar is at the H level and the clock Φ is at the L level, the input is inverted and the clock Φ bar is at the L level. When the clock Φ is at the H level, the impedance becomes high impedance.
[0043]
[Table 1]

[0044]
2 and 3, the clock signal lines are omitted, but the clocked inverters 65 and 66 in FIG. 2 have clock signal lines HCLK1 and HCLK2, and the clocked inverters 65 and 66 in FIG. Lines VCLK1 and VCLK2 are connected. In the following description, description will be made using arbitrary clocks Φ and Φ bars.
[0045]
In the latch circuit 67 shown in FIG. 4C, the output of the clocked inverter 65 is connected to the input of the inverter 63a, and the output of the inverter 63a is connected to the input of the clocked inverter 66. For this reason, when the clock signal Φ rises to the H level, the signal input to the clocked inverter 65 is inverted and input to the inverter 63a. Next, when the clock signal Φ bar becomes H level, the clocked inverter 65 becomes high impedance, but the clocked inverter 66 functions as an inverter, and the output of the clocked inverter 65 is latched by the inverter 63a and the clocked inverter 66, An inverted signal is output from the inverter 63a.
[0046]
In the latch circuit 68, the output of the clocked inverter 66 is connected to the input of the inverter 63a, and the output of the inverter 63a is connected to the input of the clocked inverter 65. Therefore, the signal input to the clocked inverter 66 is inverted and input to the inverter 63a when the clock signal Φbar rises to the H level (that is, when the clock signal Φ falls). Next, when the clock signal Φ becomes H level, the clocked inverter 66 becomes high impedance, but the clocked inverter 65 functions as an inverter, and the output of the clocked inverter 66 is latched by the inverter 63a and the clocked inverter 65. An inverted signal is output from 63a.
[0047]
FIG. 6 shows an example of a timing chart of the latch circuits 67 and 68 shown in FIG. In FIG. 6, the input signal DI is not synchronized with the rising edge (1) of the clock signal Φ, and the input signal DI is at the H level after the rising edge (1) of the clock signal Φ. The input signal DI is at the L level after the rising edge (3) of the clock signal Φ.
[0048]
Therefore, when the clock signal Φ is at the H level, the latch circuit 67 outputs the input as it is, and when the clock signal Φ is at the L level, the latch circuit 67 maintains the previous state, so that the output OUT1 has the same timing as the input signal DI. The state changes. On the other hand, the latch circuit 66 in the second stage outputs the H level of the output OUT1 at the falling edge {circle around (2)} of the clock signal Φ, latches the output at the rising edge {circle around (3)} of the clock signal Φ, and outputs it. Since the output OUT1 is output at the L level at the falling edge (4) of the clock signal Φ, the output from the output OUT2 is synchronized with the clock signal Φ.
[0049]
In this way, the output of the first stage of the bidirectional shift registers HSR and VSR is different from the output of the second and subsequent stages, and is not synchronized with the clock signal. Therefore, the bidirectional shift registers HSR1, HSR513, VSR1, and VSR386 The first stage portion is a dummy latch circuit, and its output is not connected to the video signal supply circuit 21 and the vertical output circuit 32.
[0050]
As shown in FIGS. 2 and 3, a plurality of bidirectional shift registers HSR and VSR are provided in succession. 4C and 4D, the output of the latch circuit 67 in the previous stage is indicated by OUT1, and the output of the latch circuit 68 in the subsequent stage is indicated by OUT2. However, a plurality of bidirectional shift registers HSR and VSR are consecutive. Therefore, the latch circuit 67 is connected to the next stage of the latch circuit 68. OUT3 shown in FIG. 6 indicates the output of the latch circuit 67 at the next stage.
[0051]
The relationship between the outputs OUT2 and OUT3 and the video signal will be described with reference to FIG. OUT2 and OUT3 are the outputs of the latch circuits 67 and 68 as shown in FIG. As shown in FIG. 6, the latch circuit 68 outputs the output of the previous stage to OUT2 at the falling edge (2) of the clock signal Φ, latches the output at the rising edge (3) of the clock signal Φ, and rises the clock signal Φ. The value is held until the fall {circle around (4)}, and then the next stage latch circuit 67 (not shown in FIG. 4) outputs the output of the previous stage to OUT3 at the rise {circle around (3)} of the clock signal Φ. Therefore, at the rising edge (3) of the clock signal Φ, both the outputs OUT2 and OUT3 are turned on. At this time, when there is a single video signal line, there is a problem that the same video signal is written to the pixels corresponding to the outputs OUT2 and OUT3 of the bidirectional shift register HSR. That is, when the video signal supply circuit operated by the output from OUT2 and the video signal supply circuit operated by the output from OUT3 are simultaneously connected to the same video signal line, the same video signal is supplied to the two pixels. Will be entered. If only one of the outputs of the latch circuit 67 and the latch circuit 68 is used as a signal for operating the video signal supply circuit 21, the above problem does not occur, but the number of latch circuits constituting the shift register is doubled. become. For this reason, in this embodiment, as shown in FIG. 2, the video signal 22 is also divided and supplied as VID1 to VID4, and the above problem is solved.
[0052]
In this embodiment, the number of pixels in the horizontal direction is 1025 pixels, and the number of pixels in the vertical direction is 769 pixels, which is an odd number. However, the bidirectional shift registers HSR and VSR are provided so that the latch circuit 67 and the latch circuit 68 are combined, and the sum of the latch circuit 67 and the latch circuit 68 is an even number. .
[0053]
This is because the input signal DI is captured at the same edge (rising or falling) of the clock signal Φ even when the scanning direction is reversed. That is, in the case of the latch circuits 67 and 68 shown in FIG. 4C, when the scanning direction is reversed, the order of the latch circuits 67 and 68 is also reversed. As shown in FIG. It becomes the order. However, when the order of the latch circuits is based on the signal input side, the order of the latch circuits 67 and 68 does not change even if the scanning direction is reversed. The latch circuit 67 outputs an input at the rising edge of the clock signal Φ and holds the output at the rising edge of the clock signal Φ. The latch circuit 68 outputs an input at the falling edge of the clock signal Φ, and outputs the input at the rising edge of the clock signal Φ. Hold. Therefore, if the sum of the latch circuits 67 and 68 is an odd number, the edge of the clock Φ when the input signal DI when the scanning direction is switched is different.
[0054]
Further, FIG. 3 shows an example of a problem when the total number of the latch circuits 67 and 68 is an odd number. When the scanning direction in FIG. 3 is from top to bottom, the first stage is the latch circuit 67 and the rising edge of the clock Φ. Scanning begins. On the other hand, when the scanning direction is from the bottom to the top, the latch circuit 68 is the first stage, and scanning is started at the falling edge of the clock Φ. For this reason, when displaying a liquid crystal panel that simultaneously scans in the opposite direction, such as a three-plate type liquid crystal projector, there arises a problem that the timing of the clock Φ and the video signal needs to be adjusted.
[0055]
In order to solve the above-described problems, in the horizontal shift register unit 20 and the vertical shift register unit 30 in FIGS. 2 and 3, the first stage of the bidirectional shift registers HSR1, HSR513, VSR1, and VSR385 is a dummy latch. As a circuit, the sum of the latch circuits 67 and 68 is an even number.
[0056]
The bidirectional shift register has been described using the case where the latch circuits 67 and 68 are arranged in the order from the input side. However, the order in which the latch circuits are arranged as shown in FIG. Even in this case, the same operation is performed. Although the clock signal Φ has been described as an arbitrary signal, the clock signal Φ has a period between the clock signal used for the bidirectional shift register HSR used for horizontal scanning and the clock signal used for the bidirectional shift register VSR used for vertical scanning. However, the duty ratio may be different, and a clock signal according to the number of pixels of the liquid crystal panel is used.
[0057]
Next, a bidirectional shift register reset circuit will be described. In the horizontal shift register unit 20 of FIG. 2, a reset transistor 28 is provided. By setting the inputs of the inverters 61 and 62 to the H level, the output of each bidirectional shift register HSR regardless of the state of the clock signal. Can be set to L level, and the output of the video signal supply circuit 21 can be forcibly stopped. For this reason, since the state of the bidirectional shift register HSR when the power is turned on can be kept constant, the power supply current of the bidirectional shift register HSR can be reduced transiently. For this reason, the line width of the power line of the shift register can be reduced. Similarly, the vertical shift register unit 30 is provided with a reset circuit, and the output of each shift register can be set to L level, and the video signal supply circuit 21, the output circuit 32, and the switching element in the pixel region can be turned off. Therefore, it is possible to prevent a DC voltage from being applied to the liquid crystal.
[0058]
Also, when outputting an image with a standard number of pixels smaller than the number of pixels of the liquid crystal panel, for example, when displaying a VGA image on an XGA panel, the horizontal shift register unit 20 is set when the horizontal scanning of the VGA ends. By resetting the vertical shift register unit 30 when the vertical scanning is completed, it is possible to prevent double display in the remaining pixel areas.
[0059]
Note that the reset transistor 28 is a P-type transistor so that the outputs of the bidirectional shift registers HSR and VSR are at the L level, but the reset transistor 28 is used to turn off the video signal supply circuits 21 and 32. It is also possible to use an N-type transistor.
[0060]
Next, a driving method of the horizontal signal supply circuit 21 by the horizontal shift register unit 20 of the present embodiment will be described with reference to FIGS. First, a driving method when a video signal is sampled externally in advance and divided into a plurality of sequences will be described with reference to FIGS. As shown in FIGS. 1 and 2, the video signal is supplied through four video signal input lines 22 (VID1 to VID4). This makes it possible to lengthen the time for writing the video signal to the pixel. That is, the video signal is sampled in the external circuit in accordance with the cycle of the clock signal Φ, and the voltage corresponding to the video signal is supplied to the video signal input line for a certain period, as in the video signals V1 to V4 shown in FIG. At this time, the video signal V1 is supplied to the video signal input line VID1 in accordance with the sampling order, the video signal V2 is supplied to the video signal input line VID2, and the video signal V3 and the video signal V4 are sampled at a constant voltage. Supplied. By providing a plurality of video signal input lines 22 in this way, it is possible to overlap the video signal output periods and extend the period in which the video signals are supplied.
[0061]
As described above, when the sampled video signal is divided into a plurality of series and the frequency of the video signal is reduced, the shift register is driven so as to extend the on-state period in accordance with the output period of the video signal.
[0062]
FIG. 7 shows an example in which the video signal is given a period corresponding to two cycles of the clock signal Φ, as an example of the driving method of the bidirectional shift register HSR in FIG. A-1 to a-4 are input so as to be at H level. Therefore, since the output OUT1 is at H level from the rising edge a-1 to a-4 of the clock signal Φ, the state of the output OUT1 is changed to the clock signal. The output OUT2 output and held at the rising edge of Φ is at the H level from the rising edges a-1 to a-5 corresponding to two cycles of the clock signal Φ. Similarly, after the output OUT3, the H level is output for two cycles of the clock signal Φ.
[0063]
With the above driving method, the output period of the shift register can be lengthened in accordance with the period of the video signal even when the video signal is given for a plurality of periods of the clock signal Φ.
[0064]
In FIG. 7, only the output OUT2 and the output OUT3 corresponding to the video signal V1 and the video signal V2 are shown in order to avoid the complexity of the diagram, but in order to write the video signal to the pixels in the same way, A drive signal is output from the shift register HSR according to the number of pixels. Further, when the writing time for each pixel becomes short due to an increase in the number of pixels, the number of video signal input lines may be further increased.
[0065]
Next, with respect to the case where the video signal is divided, the case where the phases of the video signal are aligned (FIG. 8) and the case where the phases are not aligned (FIG. 9) will be described. 8 to 10, in order to make the explanation easy to understand, the case where the video signals V1 to V4 are written to the pixels p1 to p13 in the first row and the 13th column using the switches s1 to s13 is described. The video signal is sampled and divided into four video signal lines in the order of V1, V2, V3, and V4. In the figure, the reference numerals attached to the signal waveforms of the video signals V1 to V4 indicate the correspondence with the pixels to be written.
[0066]
In FIG. 8, the pixel writing time is extended to 4 cycles of the clock signal, and sampling is performed again so that the phases of the video signals V1 to V4 are aligned. In this case, even if the switches s1 to s4 are simultaneously turned on and written to the pixels p1 to p4, the video signals V1 to V4 are in phase, so that the writing is performed normally. Therefore, the shift registers that output signals for driving the switches s1 to s4 can be shared, and the number of stages of the shift registers can be reduced. In addition, the signals for driving the switches s5 to s8 need only rise in response to the fall of the signals for driving the switches s1 to s4, so that one cycle of the clock signal is matched between the rise and fall of the video signal. The shift register may be driven, and it is not necessary to use a shift register that can output a plurality of cycles of the clock signal as described above with reference to FIG.
[0067]
Next, FIG. 9 shows a case where the phases of the video signals V1 to V4 are not aligned. In this case, only one sampling is required and the external circuit is simple. However, since the phases of the video signals V1 to V4 are not aligned, signals for driving the switches s1 to s13 for writing the video signals to the pixels are also required for the number of pixels. is there. For this reason, the shift register also requires the number of stages corresponding to the number of pixels, and the number of stages of the shift register increases as compared with the case of FIG. Further, in order to drive in accordance with the output period of the video signal, it is necessary to extend the output period of the shift register as shown in FIG.
[0068]
Next, rearrangement of video signals when the scanning direction is reversed will be described. FIG. 10 shows the case where the video signal lines are arranged in FIG. 9 and the video signals are written to the pixels p13 to p1 with the switches s13 to s1 sequentially turned on. First, the first video signal is supplied to the video signal V1, the switch s13 is turned on, and the first video signal is written to the leftmost pixel in the figure. Next, the second video signal is supplied to the video signal V2, and the switch s12 is turned on. However, since the switch s12 is connected to the video signal V4, the video signal is not written to the pixel, and the switch s12 is turned on. In this state, the fourth video signal is supplied to the video signal V4, and the fourth video signal is written in the second pixel p12 from the left. Further, the third video signal is written in p11, and the second and sixth video signals are written in p10. Thus, if the video signals are not rearranged in accordance with the reverse scanning, there is a problem that the video signal arrangement is different from the original image arrangement.
[0069]
FIG. 11 shows an example of the signal switching circuit. In the example shown in FIG. 11, video signals are input in time series to the four video signal input terminals 24a, 24b, 24c, and 24d, respectively. The signal switching circuit 23 operates to switch the video signals input to the second and fourth terminals 24b and 24d from the left among the four video signal input terminals. In FIG. 11, the first and third terminals 24a and 24c from the left that do not need to be switched are provided with the same circuit as the terminals 24b and 24d, but the switching operation is not performed. This is to prevent a difference in phase and amplitude with respect to the video signals input to the second and fourth terminals 24b and 24d.
[0070]
FIG. 12 is a schematic circuit diagram for explaining how the video signal supply circuit 21 supplies a video signal to the video signal line by a signal from the horizontal shift register unit 20 shown in FIG. 2, and FIG. 13 shows a timing chart. In FIG. 12, for the sake of clarity, the video signal supply circuit 21 is displayed as a switch, and details of the horizontal shift register unit 20 are omitted, but the video signal supply circuit 21 and the horizontal shift register shown in FIG. This is the same as the unit 20. Further, the pixels P1 to P1025 for one row in the pixel region 10 of FIG. 1 are schematically described, and the video signal line 11 of FIG. 1 is indicated by L1 to L1025 so as to correspond to each pixel.
[0071]
The video signal input lines 22 (VID1 to VID4) are selected by the signal switching circuit 23 and the video signals V1 to V4 are supplied to the video signal input lines at timings as shown in FIG. When video signals are written from the horizontal shift register unit 20 to the pixels in the order from left to right in FIG. 12 (forward scanning), the outputs H1 to H1025 correspond to the timing shown in FIG. Is output. In FIG. 13A, only the outputs H1 to H5 are shown for the sake of clarity, but the output continues to the output H1025, and pixels for one row are written. 13A shows the case of forward scanning, and FIG. 13B shows the case of backward scanning. In FIG. 13, the reference numerals P1 to P1025 attached to the signal waveforms of the video signals V1 to V4 are shown in FIG. 12 is a video signal written to the pixels P1 to P1025 shown in FIG.
[0072]
When the output H1 is output from the horizontal shift register unit 20, the video signal input line VID1 and the video signal line L1 (11) are electrically connected, and the video signal V1 output to the video signal input line VID1 is the video signal. It is supplied to the pixel P1 via the line L1. Similarly, the video signal V1 output to the video signal input line VID1 continues until the video signal line L1025 is written to the pixel P1025, and writing of pixels for one row is performed.
[0073]
In the reverse scanning shown in FIG. 13B, the video signal V4 is first output to the video signal input line VID2, and the video signal is output using the signal switching circuit 23 so that the video signal V2 is output to the video signal input line VID4. Has been switched.
[0074]
In reverse scanning, when the output H1025 is first output from the horizontal shift register unit 20, the video signal V1 is written to the pixel P1025. Next, when the output H1024 is output, the video signal supplied to the video signal input line VID4 is supplied to the pixel P1024. At this time, the video signal V2 is supplied to the video signal input line VID4 by the signal switching circuit 23. Therefore, the second sampled video signal is written to the pixel P1024. Similarly, video signals are sequentially written to pixels for one row.
[0075]
As described above, the video signal supply circuit 21 is driven by the horizontal shift register unit 20, and the video signal is written to the pixel.
[0076]
Next, a method of driving the scanning signal by the vertical shift register 30 will be described with reference to FIGS.
[0077]
FIG. 14 shows an example of a timing chart when the duty ratio of the clock signal Φ is changed by the bidirectional shift register VSR of FIG. In FIG. 14, the output OUT2 is at the H level corresponding to the falling b-1 of the clock signal Φ. Next, the output OUT3 becomes H level corresponding to the rising b-2 of the clock signal Φ. At this time, the duty ratio of the clock signal Φ is set such that the period of the H level is long and the period of the L level is short, and accordingly, the period from the rise of the output OUT2 to the rise of the output OUT3 is shortened.
[0078]
Further, the output OUT4 becomes H level corresponding to the falling b-3 of the clock signal Φ, and the output OUT5 becomes H level corresponding to the rising b-4 of the clock signal Φ. At this time, the duty ratio of the clock signal Φ is Since the H level period is long and the L level period is short, the period from the rise of the output OUT3 to the rise of the output OUT4 is long, and the period from the rise of the output OUT3 to the rise of the output OUT54 is long.
[0079]
In this way, by changing the duty ratio of the clock signal Φ, it is possible to drive as if the phases of the outputs OUT1, OUT2,.
[0080]
FIGS. 15 and 16 are timing charts showing driving timings in the case of sequential scanning driving, and FIG. 15 shows forward scanning in which scanning is performed from the top to the bottom of FIG. Therefore, the H level is input to the first vertical direction setting line. The video signal represents a signal for one line such as a gradation written for each pixel such as a video signal, and 1H represents a horizontal scanning period for one line. The latch circuit 67 shown in FIG. 4 outputs and holds the input signal at the rising edge of the clock VCLK1, and the latch circuit 68 outputs and holds the input signal at the falling edge of the clock VCLK1. For this reason, it is possible to change the phase of the output from the shift register corresponding to the pixels of the odd-numbered line and the even-numbered line by changing the duty of the clock VCLK1.
[0081]
The duty ratio of the clock VCLK1 is adjusted so that the L level period is within the blank period of the video signal. Therefore, when the input signal (scanning start signal) VDI is input as shown in FIG. 15, the output GS1 of the bidirectional shift register VSR1 becomes an H level at the falling edge of the clock VCLK1, and falls on the next clock VCLK1. Holds the value until. However, as described above with reference to FIG. 6, a dummy latch circuit is provided in the first stage of the bidirectional shift register VSR1. The output GS2 of the bidirectional shift register VSR2 takes in the H level of the output GS1 at the rise of the clock VCLK1, and holds the value until the next rise of the clock VCLK1.
[0082]
The phase difference between the output GS1 and the output GS2 is a period substantially equal to the L level period of the clock VCLK1. At this time, the vertical scanning control terminals CNT1 and CNT2 are given as shown in FIG. 15, and the output GS1 is calculated by the NAND circuit of the vertical scanning control terminal CNT1 and the vertical scanning control unit 33 and output to the output circuit 32. The output G1 is output as the output G1 of the output circuit 32, and the output GS2 is calculated by the vertical scanning control terminal CNT2 and the vertical scanning control unit 33 and output as the output G2 of the output circuit 32.
[0083]
In the driving method shown in FIG. 15, the case where the vertical scanning control terminals CNT1 and CNT2 are used has been described. However, H level is output to the vertical scanning control terminals CNT1 and CNT2, and the duty ratio of the vertical clock signal VCLK is driven at 50%. But you can get the same result.
[0084]
Next, FIG. 16 shows a timing chart of sequential scanning in the reverse direction for scanning from the bottom to the top of FIG. Since the direction is reverse, L level is input to the first vertical direction setting line. In the case of FIG. 16, the basic operation is the same as that of FIG. 15, but the output G769 is output in turn toward G1, and finally the scan end signal VDO is output to the terminal 38.
[0085]
FIG. 17 shows a timing chart in the case of simultaneous driving of 2n-1 lines and 2n lines of scanning signal lines. Here, n represents an integer. By giving the vertical scanning control terminals CNT1 and CNT2 in phase, the outputs G1 and G2 from the output circuit 32 can be output simultaneously.
[0086]
FIG. 18 shows a timing chart in the case of simultaneous driving of two scanning signal lines and 2n + 1 lines. The clock VCLK1 is inverted, and the H level period is substantially the same as the blank period of the video signal. The bidirectional shift register VSR1 takes in the H level of the output of the dummy latch circuit at the fall of the clock VCLK1, outputs the H level to the output GS1, and holds the value until the next fall of the clock VCLK1. The latch circuit 67 at the first stage of the bidirectional shift register VSR2 takes in the H level of the output GS1 at the rising edge of the clock VCLK1, outputs it to the output GS2, and holds it until the next rising edge of the clock VCLK. Next, the latch circuit 66 in the second stage of the vertical shift register VSR2 takes in the H level of the output GS2 at the falling edge of the clock VCLK1, outputs it to the output GS2, and holds it until the next rising edge of the clock VCLK1. The phase difference between the outputs GS1 and GS2 is substantially the same as the L level period of the clock VCLK1, and is almost a period of one cycle of the clock VCLK1, and the phase difference between the outputs GS2 and GS3 is the H level of the clock VCLK1. The period is almost equal to the period. For this reason, the phase difference between the outputs GS2 and GS3 is short, and the outputs GS2 and GS3 are output in substantially the same phase. Further, the signals G2 and G3 from the output circuit 32 can be driven simultaneously by applying signals from the vertical scanning control terminals CNT1 and CNT2 in the same phase during a period in which the outputs GS2 and GS3 are overlapped.
[0087]
FIG. 19 shows a driving method in which the 2n-1 line and 2n line of the scanning signal lines are simultaneously driven, the 2n line is thinned, and then the 2n line and 2n + 1 line are simultaneously driven. By inverting the clock VCLK1 at the end of the 2n line and delaying the rising edge of the clock VCLK1 by one cycle, the H level period of the output GS2n becomes close to two cycles of the clock VCLK1, and the vertical scan control terminals CNT1 and CNT2 By giving the signals in phase and calculating by the vertical scanning control unit 33, the output G2n is output twice, and the 2n lines of the scanning signal lines that are simultaneously driven can be thinned out.
[0088]
FIG. 20 shows a driving method in which the 2n-1 line and the 2n-2 line of the scanning signal lines are simultaneously driven, the 2n-1 line is thinned, and then the 2n line and 2n-1 line are simultaneously driven.
[0089]
In FIG. 21A, the latch circuits 67 and 68 shown in FIG. 4B are provided with buffer inverters for improving the load driving capability and speeding up the operation of the shift register. The latch circuits 67 and 68 are constituted by clocked inverters 63 to 66, and a buffer inverter 601 is inserted. Since the buffer inverter 601 is inserted between the clocked inverters, the lack of load driving capability of each clocked inverter can be compensated and a shift register capable of high-speed driving can be formed.
[0090]
Next, the operation of FIG. 21A will be described with reference to FIG. In the latch circuit 67 shown in FIG. 21B, the output of the clocked inverter 65 is connected to the input of the inverter 601a, the output of the inverter 601a is connected to the input of the inverter 63a, and the output of the inverter 63a is passed through the inverter 601b. To the input of the clocked inverter 66.
[0091]
Since the signal input to the clocked inverter 65 is inverted three times and output from the inverter 63a, the signal input to the clocked inverter 65 when the clock signal Φ rises to the H level is inverted and output from the inverter 63a. Next, when the clock signal Φ bar becomes H level, the clocked inverter 65 becomes high impedance, but the clocked inverter 66 functions as an inverter, and the output of the inverter 63a is inverted twice and output from the clocked inverter 66. Here, since the output of the clocked inverter 65 before the clock signal Φ bar becomes the H level and the output of the clocked inverter 66 after the clock signal Φ bar becomes the H level have the same value, the clock signal Φ The input of the clocked inverter 65 before the bar becomes H level is latched, and an inverted signal is output from the inverter 63a.
[0092]
The latch circuit 68 operates in the same manner, the input value is latched, and an inverted signal is output from the inverter 63a. By adding the buffer inverter 601 in this way, the bidirectional shift registers HSR and VSR can be compensated for insufficient load driving capability and can be driven at high speed.
[0093]
FIG. 22 is a schematic diagram of an optical system for explaining a liquid crystal projector to which the liquid crystal display device of the present invention is applied. 220 is a light source, 221 is a parabolic mirror, 222 is a condenser lens, 223 is a reflecting mirror, and 224 is a first mirror. 1 aperture, 225 a lens, 226 a dichroic prism, 227R a red reflective liquid crystal display device, 227G a green reflective liquid crystal display device, 227B a blue reflective liquid crystal display device, 228 a second aperture stop, 229 is a projection lens, and 230 is a screen. In the present embodiment, the green reflective liquid crystal display device 227G is scanned in the reverse direction.
[0094]
FIG. 23 is a developed perspective view for explaining a case where the liquid crystal display device according to the present invention is applied to a reflective liquid crystal display device. 714 is a liquid crystal panel, 701 is a transparent substrate, 702 is a silicon substrate, and pixel electrodes together with pixel electrodes and the like. The horizontal shift register unit 20 and the vertical shift register unit 30 described above are formed. Although not shown, a liquid crystal layer is provided between the transparent substrate 701 and the silicon substrate 702. 707 is a package, 709 is a flexible printed circuit board for supplying power to the liquid crystal panel 714, 713 is a light shielding frame, 712 is a flexible printed circuit board retainer, 710 is a heat dissipation sheet for releasing the heat of the liquid crystal panel 714 to the outside, and 711 is a bottom portion of the package 707 It is the heat sink provided in.
[0095]
FIG. 24 is a schematic configuration diagram showing a liquid crystal layer of a liquid crystal display device when the present invention is applied to a polymer dispersed liquid crystal (PDLC) which is one of reflection type liquid crystal display devices. The liquid crystal layer is a polymer-dispersed liquid crystal (PDLC) in which a liquid crystal 739 is dispersed in a polymer matrix 703, and changes from a light scattering state to a transmission state according to an applied voltage. FIG. 23A shows how light is scattered by the liquid crystal display device used in the present liquid crystal projector, and FIG. 24B shows how it is reflected. A reflective pixel electrode 738 is formed on the second substrate 702, and a transparent electrode 730 is formed on the first substrate 701.
[0096]
As shown in FIG. 24A, in the state where no voltage is applied between the reflective pixel electrode 738 of the second substrate 702 and the transparent electrode 730 of the first substrate 701, the liquid crystal 739 has irregular directions. Are arranged. In this state, a difference in refractive index occurs between the polymer matrix 703 and the liquid crystal molecules, the incident light 741 is scattered, and 742 indicates scattered light. As shown in FIG. 24B, in a state where a voltage is applied between the reflective pixel electrode 738 of the second substrate 702 and the transparent electrode 730 of the first substrate 701, the liquid crystal 739 is aligned in a certain direction. If the refractive index when the liquid crystal 739 is aligned in a certain direction and the refractive index of the polymer matrix 703 are matched, the incident light 741 is not scattered but is regularly reflected by the reflective pixel electrode 738, and 743 indicates reflected light. .
[0097]
【The invention's effect】
As described above, according to the liquid crystal display device of the present invention, it is possible to scan in both directions, and it becomes easy to invert and output an image, and it is not necessary to provide a means for inversion and output a compact liquid crystal. It becomes a display device.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram illustrating a liquid crystal display device according to the present invention.
FIG. 2 is a schematic circuit diagram illustrating a liquid crystal display device according to the present invention.
FIG. 3 is a schematic circuit diagram illustrating a liquid crystal display device according to the present invention.
FIG. 4 is a schematic circuit diagram illustrating a liquid crystal display device according to the present invention.
FIG. 5 is a schematic circuit diagram illustrating a clocked inverter used in the liquid crystal display device according to the present invention.
FIG. 6 is a schematic timing chart illustrating the operation of the liquid crystal display device according to the present invention.
FIG. 7 is a schematic timing chart illustrating the operation of the liquid crystal display device according to the present invention.
FIG. 8 is a schematic circuit diagram and a schematic timing chart for explaining the operation of the liquid crystal display device according to the present invention.
FIG. 9 is a schematic circuit diagram and a schematic timing chart for explaining the operation of the liquid crystal display device according to the present invention.
FIG. 10 is a schematic circuit diagram and a schematic timing chart for explaining the operation of the liquid crystal display device according to the present invention.
FIG. 11 is a schematic circuit diagram illustrating a signal switching circuit of the liquid crystal display device according to the present invention.
FIG. 12 is a schematic circuit diagram illustrating a video signal supply circuit of a liquid crystal display device according to the present invention.
FIG. 13 is a schematic timing chart for explaining the operation of the video signal supply circuit of the liquid crystal display device according to the present invention.
FIG. 14 is a schematic timing chart illustrating the operation of the liquid crystal display device according to the present invention.
FIG. 15 is a schematic timing chart illustrating the operation of the liquid crystal display device according to the present invention.
FIG. 16 is a schematic timing chart illustrating the operation of the liquid crystal display device according to the present invention.
FIG. 17 is a schematic timing chart illustrating the operation of the liquid crystal display device according to the present invention.
FIG. 18 is a schematic timing chart illustrating the operation of the liquid crystal display device according to the present invention.
FIG. 19 is a schematic timing chart illustrating the operation of the liquid crystal display device according to the present invention.
FIG. 20 is a schematic timing chart illustrating the operation of the liquid crystal display device according to the present invention.
FIG. 21 is a schematic circuit diagram illustrating a latch circuit of a liquid crystal display device according to the present invention.
FIG. 22 is a schematic diagram of an optical system for explaining a liquid crystal projector to which the liquid crystal display device of the present invention is applied.
FIG. 23 is a developed perspective view illustrating a case where the liquid crystal display device according to the present invention is applied to a reflective liquid crystal display device.
FIG. 24 is a schematic configuration diagram showing a liquid crystal layer of a liquid crystal display device when the present invention is applied to PDLC.
FIG. 25 is a schematic configuration diagram illustrating a three-plate liquid crystal projector optical system.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Pixel region, 11 ... Video signal line, 12 ... Scanning signal line, 13 ... Switching element, 14 ... Pixel electrode, 15 ... Counter electrode, 16 ... Retention capacity, 20 ... Horizontal shift register part, 21 ... Video signal supply circuit , 22 ... Video signal input line, 23 ... Video signal switching circuit, 24 ... Video signal input terminal, 25 ... Horizontal scanning reset signal input terminal, 26 ... Horizontal scanning start signal input terminal, 27 ... Horizontal scanning end signal output terminal, 30 ... vertical shift register section, 32 ... vertical output circuit, 33 ... vertical scanning control circuit, 36 ... vertical scanning reset terminal, 37 ... vertical scanning start signal input terminal, 38 ... vertical scanning end signal output terminal, 61, 62, 63 64, 65, 66 ... clocked inverter, 67, 68 ... latch circuit, 71, 72 ... P-type transistor, 73, 74 ... N-type transistor, HS , VSR: Bidirectional shift register, HCLK1, HCLK2, VCLK1, VCLK2, Φ, Φ bar ... Clock signal line, RL ... Horizontal scanning direction setting signal line, RL1 ... First horizontal direction setting line, RL2 ... Second horizontal direction setting UD ... vertical scanning direction setting line, UD1 ... first vertical direction setting line, UD2 ... second vertical direction setting line, CNT1, CNT2 ... control signal input terminal, DI ... input signal, OUT ... output, 220 ... light source, 221 ... Parabolic mirror, 222 ... Condenser lens, 223 ... Reflector, 224 ... First stop, 225 ... Lens, 226 ... Dichroic prism, 227R ... Red reflective liquid crystal display device, 227G ... Green reflective liquid crystal Display device, 227B ... Blue reflective liquid crystal display device, 228 ... Second aperture, 229 ... Projection lens, 230 ... Screen, 714 ... Liquid crystal Nell, 701 ... transparent substrate, 702 ... silicon substrate, 707 ... package 709 ... flexible printed circuit board, 713 ... light shielding frame, 712 ... pressing the flexible printed circuit board, 710 ... heat-radiating sheet, 711 ... heat radiating plate.

Claims (4)

A liquid crystal, a plurality of pixel electrodes for driving the liquid crystal, a switching element connected to the pixel electrode, an output circuit for supplying a signal to the switching element, and a plurality of scanning signals for driving the output circuit are output. Having a scanning circuit on the same substrate,
The scanning circuit includes a series connection of a plurality of bidirectional shift register stages capable of scanning in a first scanning direction and a second scanning direction,
The bidirectional shift register stage includes:
A connecting portion for connecting the first latch circuit, the second latch circuit, the first latch circuit, and the second latch circuit;
A reset circuit,
The first latch circuit and the second latch circuit are:
A first clocked inverter that operates as an inverter when the scanning direction is the first scanning direction and a second clocked inverter that operates as an inverter when the scanning direction is the second scanning direction;
The first latch circuit includes a first input / output terminal that is an output when scanning in the first scanning direction and an input when scanning in the second scanning direction;
The second latch circuit includes a second input / output terminal that is an output when scanning in the second scanning direction and an input when scanning in the first scanning direction,
The first input / output terminal and the second input / output terminal are connected via the connection portion,
The scanning signal is output from the connection unit to the output circuit,
The reset circuit is
In the case of the first scanning direction, the first clocked inverter outputs a signal for turning off the output circuit from the first input / output terminal,
The liquid crystal display device, wherein the second clocked inverter operates so as to output a signal for turning off the output circuit from a second input / output terminal in the second scanning direction. A liquid crystal, a pixel electrode that drives the liquid crystal, a switching element connected to the pixel electrode, an output circuit that supplies a signal to the switching element, and a scanning circuit that outputs a scanning signal that drives the output circuit are the same On the substrate,
The scanning circuit includes a first latch circuit and a second latch circuit, and is capable of scanning in a first scanning direction and a second scanning direction,
The first latch circuit and the second latch circuit are:
A first clocked inverter that operates as an inverter when the scanning direction is the first scanning direction;
A second clocked inverter that operates as an inverter when the scanning direction is the second scanning direction;
The first latch circuit includes a first input / output terminal that is an output when scanning in the first scanning direction and an input when scanning in the second scanning direction;
The second latch circuit includes a second input / output terminal that is an output when scanning in the second scanning direction and an input when scanning in the first scanning direction,
An output terminal for outputting the scanning signal is provided at a connection portion between the first input / output terminal and the second input / output terminal,
The first stage output terminal of the scanning circuit is not connected to the output circuit,
In the case of the first scanning direction, the first clocked inverter outputs a signal for turning off the output circuit from the first input / output terminal,
In the second scanning direction, the second clocked inverter operates so as to output a signal for turning off the output circuit from a second input / output terminal.
A liquid crystal display device comprising a reset circuit. The first latch circuit having the output terminal of the first stage of the scanning circuit is an input when scanning in the first scanning direction and a third input serving as an output when scanning in the second scanning direction. 3. The liquid crystal display device according to claim 2, further comprising an output terminal, wherein the third input / output terminal is connected to a scan start signal input terminal and a scan end signal output terminal. The first latch circuit having the output terminal of the first stage of the scanning circuit is an input when scanning in the first scanning direction and a third input serving as an output when scanning in the second scanning direction. The third input / output terminal has an output terminal and is connected to the scan start signal input terminal via a clocked inverter that operates as an inverter when scanning in the first scanning direction, and in the second scanning direction. 3. The liquid crystal display device according to claim 2, wherein the liquid crystal display device is connected to a scanning end signal output terminal via a clocked inverter that operates as an inverter when scanning.

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