JP3693453B2 - Decoder circuit - Google Patents

Description

【００３１】
書き込み／消去時電圧供給回路１０３のドライバ回路２０７は直列に接続された３つのトランジスタ５２１、５２２、５２３より構成される。Ｐchトランジスタ５２１はソースを電圧切換回路５１５の出力に接続し、ドレインをＰchトランジスタ５２２のソースに接続し、ゲートをレベルシフト回路２０８の出力に接続し、バルクを電圧切換回路５１８の出力に接続している。また、Ｐchトランジスタ５２２は上記のようにソースをＰchトランジスタ５２１のドレインに接続し、ゲートを電圧切換回路５１６の出力に接続し、ドレインをＮchトランジスタ５２３のドレインに接続し、更にバルクを電圧切換回路５１８に接続している。更にＮchトランジスタ５２３は、ソースを電圧切換回路５１７の出力に接続し、ドレインを上記のようにＰchトランジスタ５２２のドレインに接続し、ゲートを上記Ｎchトランジスタ５２３のゲートと共通にしてレベルシフト回路２０８の出力に接続し、バルクを負高電圧昇圧回路５１９の出力に接続する。
【００３２】
このようにドライバ回路２０７を構成するとともに、消去時の選択ワード線に対応して、電圧切換回路５１５の出力を高正電圧Ｖppとし電圧切換回路５１６の出力を電源電圧Ｖdd（Ｖpp＞Ｖdd）とし、電圧切換回路５１７の出力を電源電圧Ｖddとすることによって（このときのレベルシフト回路２０８の出力は表１より電源電圧Ｖdd）、Ｐchトランジスタ５２１をオン、Ｐchトランジスタ５２２をオン、Ｎchトランジスタ５２３をオフにし、ワード線に高正電圧Ｖppを印加することになる。
【００３３】
一方、消去時の非選択ワード線１０４に対応して、電圧切換回路５１５の出力を高正電圧Ｖppとし、電圧切換回路５１６の出力を高正電圧Ｖppとし、電圧切換回路５１７の出力を電源電圧Ｖddとすることによって（このときのレベルシフト回路２０８の出力は０ｖ）、Ｐchトランジスタ５２１をオン、Ｐchトランジスタ５２２をオフ、Ｎchトランジスタ５２３もオフにし、ワード線に０ｖを印加することになり、これによって選択消去が可能となる。
【００３４】
上記消去時において、Ｐchトランジスタ５２１、５２２のバルクに接続された電圧切換回路５１８の出力は正高電圧Ｖppであり、ソースあるいはドレインに印加された電圧と同電位（非選択時のＰchトランジスタ５２２のドレイン電圧のみ０ｖ、従ってバルクドレイン間は逆バイアス）であるので、電流リークはないことになる。また、Ｎchトランジスタ５２３のバルクに接続された負高電圧昇圧５１９の出力は０ｖであり、ソースあるいはドレインとバルクとの間は逆バイアス（非選択時のドレイン電圧のみ０ｖ、従ってバルクドレイン間は同電位）であるので、電流リークはないことになる。
【００３５】
書き込み時は選択ワード線に対応して、電圧切換回路５１５の出力を０ｖとし電圧切換回路５１６の出力を負高電圧Ｖbbとし、電圧切換回路５１７の出力も負高電圧Ｖbbとする。このとき、上記レベルシフト回路２０８の出力は電源電圧Ｖddであるので、Ｐchトランジスタ５２１をオン、Ｐchトランジスタ５２２をオフ、Ｎchトランジスタ５２３をオンにし、ワード線に負高電圧Ｖbbを印加することになる。
【００３６】
一方、書き込み時の非選択ワード線に対応して、電圧切換回路５１５、電圧切換回路５１６、電圧切換回路５１７の出力のそれぞれを上記選択時と同様にする。このとき、上記レベルシフト回路２０８の出力は負高電圧Ｖbbであるので、Ｐchトランジスタ５２１はオフ、Ｐchトランジスタ５２２もオフ、Ｎchトランジスタ５２３もオフになって、ワード線に電圧切換回路５１５の出力０ｖを印加することになる。
【００３７】
上記書き込み時において、Ｐchトランジスタ５２１のバルクに接続された電圧切換回路５１８の出力は電源電圧Ｖddであり、ソースあるいはドレインに印加される電圧は０ｖであるので逆バイアスとなる。また、Ｐchトランジスタ５２２のバルクへの印加電圧は上記電源電圧Ｖddであり、ソースに印加される電圧は０ｖ、ドレインに印加される電圧は選択時負高電圧Ｖbb、非選択時０ｖであるので、いずれの場合も逆バイアスとなる。更に、上記書き込み時において、Ｎchトランジスタ５２３のバルクに接続された負高電圧昇圧回路５１９の出力は負高電圧Ｖbbであり、ソースあるいはドレインに印加される電圧も選択時負高電圧Ｖbbまたは非選択時０ｖであるので同電位あるいは逆バイアスとなる。従って、電流リークはないことになる。
【００３８】
更に、読み出し時は選択ワード線に対応して、電圧切換回路５１５の出力を０ｖとし電圧切換回路５１６の出力を読み出し電圧Ｖprとし、電圧切換回路５１７の出力も読み出し電圧Ｖprとする。このとき、上記レベルシフト回路２０８の出力は電源電圧Ｖddであるので、Ｐchトランジスタ５２１をオフ、Ｐchトランジスタ５２２もオフ、Ｎchトランジスタ５２３もオフにする。また、読み出し時の非選択ワード線に対応して、電圧切換回路５１５、電圧切換回路５１６、電圧切換回路５１７の出力のそれぞれを上記選択時と同様にする。このとき、上記レベルシフト回路２０８の出力は０ｖであるので、Ｐchトランジスタ５２１はオフ、Ｐchトランジスタ５２２はオフ、更にＮchトランジスタ５２３もオフになる。
【００３９】
またこのときに各Ｐchトランジスタ５２１、５２２およびＮchトランジスタ５２３のバルクには電圧切換回路５１８、５１７より読み出し電圧Ｖprが印加されており、該各トランジスタ５２１、５２２、５２３のソースあるいはドレインに印加された電圧と同電位あるいは逆バイアスの関係にあるので、電流リークは発生しない。
【００４０】
尚、以上の記述を表としてまとめると下記の２表のごとくになる。図５及び表２において読み出し電圧Ｖprとの関係はＶpr＞Ｖddである。
【００４１】
【表２】

【００４２】
次に読み出し時のワード線への電圧制御はレベルシフト回路２０６と読み出し時ドライバ回路２０５で行うようになっている。レベルシフト回路２０６は入力を選択、非選択に応じて電源電圧Ｖddと０ｖのいずれかの位をとる上記アドレス信号５１３、又はその反転信号とし、該アドレス信号に基づいて正昇圧回路５０９と、接地電圧を選択するようになっている。ここで、正昇圧回路５０９の出力を消去／書き込み／読み出しに応じて、電源電圧Ｖdd／電源電圧Ｖdd／読み出し電圧Ｖprとする。これによって、レベルシフト回路２０６の出力は、選択、非選択に対応して、下記表３のごとくになる。尚、レベルシフト回路２０６自体の構成は公知であるので説明を省略する。
【００４３】
【表３】

【００４４】
次段のドライバ回路２０５は、高耐圧のＰchトランジスタとＮchトランジスタのドレインを相互に接続するとともに、Ｐchトランジスタのソースとバルクに正昇圧回路５０９の出力を接続し、Ｎchトランジスタのソースを接地し、更に両トランジスタのゲート上に上記レベルシフト回路２０６の出力が接続される構成となっている。
【００４５】
上記構成において基本的には、消去、書込み時の選択時には上記レベルシフト回路２０６よりＰchトランジスタ、およびＮchトランジスタのゲートに０ｖを与えて当該Ｐchトランジスタをオン、Ｎchトランジスタをオフにするが、このとき以下に説明するように、ワード線に接続されたＮchトランジスタ１０７がオフとなっているので、該ワード線に印加されている正または負の高圧が当該ドライバ回路２０５に印加されることはない。また、読み出し時の選択時にも上記同様、レベルシフト回路２０６よりＰchトランジスタ、およびＮchトランジスタのゲートに０ｖを与えて当該Ｐchトランジスタをオン、Ｎchトランジスタをオフにする。このときはワード線に接続されたＮchトランジスタ１０７がオンとなっているので、読出し電圧Ｖprがワード線に印加されることになる。
【００４６】
尚、消去、書込み、読み出しの各場合における非選択の場合には、上記レベルシフト回路２０５の出力は正昇圧回路５０９の各場合の出力と同じになるので、ドライバ回路２０５のＰchトランジスタはオフ、およびＮchトランジスタはオンになって、ワード線は接地される。以上をまとめると以下の表４のようになる。
【００４７】
【表４】

【００４８】
ここで、電圧切換回路１０８よりＮchトランジスタ１０７のゲートに対して、消去時に電源電圧Ｖdd（ソース電圧Ｖddと同じ電位であって、ワード線１０４に印加される高正電圧Ｖppより低い電圧）が印加されるので、該Ｎchトランジスタ１０７はオフとなる。また書き込み時には負高電圧Ｖbb（ソース電圧Ｖddより低い電圧であって、ワード線１０４に印加される高正電圧Ｖbbと同じ電位）が印加されるので、該Ｎchトランジスタ１０７は上記消去時と同様オフとなる。
【００４９】
また、上記実施の態様１と同様に、書き込みと消去時のワード線への印加電圧が逆（書き込み時にワード線に正高電圧、消去時にワード線に負高電圧を印加）となるＣＨＥ書き込み／ＦＮ消去方式の場合は、書き込みと消去の上記動作を置き換えることにより本回路の適用が可能である。
【００５０】
（実施の形態４）
図５は本発明の実施の形態４におけるデコーダ回路の回路図を示すものである。メモリセルアレイ１０１と正高圧読み出し／消去時電圧供給回路６０２はＮchトランジスタ６０７を介して接続され、該Ｎchトランジスタ６０７はドレインをワード線１０４に、ソースとバルクは正高圧読み出し／消去時電圧供給回路６０２の出力６０５に接続される。負高耐圧書き込み時電圧供給回路６０３の出力６０６は、前記メモリセルアレイ１０１のワード線１０４、すなわち前記Ｎchトランジスタ６０７のドレインに接続されている。
【００５１】
更に、上記Ｎchトランジスタ６０７のゲートは、電圧切換回路６０８の出力に接続され、該Ｎchトランジスタ６０７と電圧切換回路６０８で、上記正高圧読み出し／消去時電圧供給回路６０２と負高耐圧書き込み時電圧供給回路６０３との間を遮断するスイッチング回路２００を構成する。
【００５２】
また、入力アドレス信号６０９は正高圧読み出し／消去時電圧供給回路６０２と負高耐圧書き込み時電圧供給回路６０３に同時に入力され、各動作時（読み出し／消去／書き込み）のアドレス信号に応じて、上記正高圧読み出し／消去時電圧供給回路６０２と負高耐圧書き込み時電圧供給回路６０３が必要な電圧をワード線１０４に出力するようになっている。上記電圧切換回路６０８は、読み出し／消去時には正高電圧（Ｖｐｐ）をＮchトランジスタ６０７のゲートに印加し該Ｎchトランジスタ６０７をオンさせる。書き込み時には、Ｎchトランジスタ６０７のゲートにワード線と上記読み出し／消去時電圧供給回路を遮断する電圧を印加することによって当該Ｎchトランジスタ６０７をオフさせ、これによって、正高圧読み出し／消去時電圧供給回路６０２と負高耐圧書き込み時電圧供給回路６０３を遮断して、正高圧読み出し／消去時電圧供給回路６０２への電流リークパスをカットする。
【００５３】
また、正高耐圧読み出し／消去時電圧供給回路６０２において、消去時にワード線に印加される電圧Ｖppが５ｖ程度であれば、該正高耐圧読み出し／消去時電圧供給回路６０２には高耐圧（十数ボルト程度の耐圧）トランジスタを不要とし、５ｖ程度の耐圧の電流供給能力の比較的高いトランジスタで構成することが可能となり、読み出し時の高速アクセスが可能となる。
【００５４】
上記はＦＮ書き込み／ＦＮ読み出し（書き込み時負高電圧、消去時正高電圧）を用いているが、実施の形態１と同様に、書き込みと消去時のワード線への印加電圧が逆（書き込み時正高電圧、消去時負高電圧を印加）となるＣＨＥ書き込み／ＦＮ消去方式の場合は、書き込みと消去の上記動作を置き換えることにより適用可能である。すなわち、書込み時（電子注入時）にはさほど高い正電圧を必要としない（５ｖ程度）ので上記と同様の効果を得ることができる。
【００５５】
さらに図５においては分離トランジスタとしてＮchトランジスタ６０７の構成例を示しているが、実施の形態２と同様にＰchトランジスタでも構成可能である。
【００５６】
（実施の形態５）
図６は本発明の実施の形態５におけるデコーダ回路の回路図を示すものであり、以下その構成を作用とともに説明する。尚、レベルシフト回路７０７、７０８自体の構成は公知であるので、ここでは説明を省略する。
【００５７】
図６において、レベルシフト回路７０８には選択と非選択に応じて電源電圧Ｖｄｄと０ｖの組合せよりなるアドレス信号７０９またはその反転信号を入力する（アドレス信号７０９は選択、非選択の各電圧が消去Ｅ、書込みＰ、読み出しＲにおいて変化している点に注意）。これによって、表５に示すように、レベルシフト回路７０８の出力は消去／書き込み／読み出しに応じて電源電圧Ｖｄｄかあるいは、負高電圧昇圧回路７１０の出力（消去時０ｖ、書き込み時Ｖbb、読み出し時０ｖ）を選択することになる。
【００５８】
【表５】

【００５９】
上記、レベルシフト回路７０８の出力あるいはその反転信号を受けて、レベルシフト回路７０７の出力は、消去／書き込み／読み出しに応じて正昇圧回路７０６（消去時Ｖpp、書き込み時Ｖdd、読み出し時Ｖpr）と負高電圧昇圧回路７１０のいずれかの電圧を下記表６に示すように出力する。
【００６０】
【表６】

【００６１】
上記のレベルシフト回路７０７の出力を受けて、ドライバ回路７０５は正昇圧回路７０６の出力か負高電圧昇圧回路７１０の出力かのいずれかを選択することになる。
【００６２】
ドライバ回路７０５は、高耐圧のＰchトランジスタとＮchトランジスタのドレインを相互に接続しするとともに、Ｐchトランジスタのソースとバルクに正昇圧回路７０６の出力を接続し、Ｎchトランジスタのソースとバルクに負電圧切換回路７１０の出力を接続する構成となっている。
【００６３】
上記の構成により、消去時の選択ワード線に対応して、ドライバ回路７０５の出力が０ｖであるので、Ｐchトランジスタがオン、Ｎchトランジスタがオフとなって正昇圧回路７０６の出力すなわち正高電圧Ｖppがワード線１０４に出力される。逆に消去時の選択ワード線に対応して、ドライバ回路７０５の出力が正高電圧Ｖppであるので、Ｐchトランジスタがオフ、Ｎchトランジスタがオンとなって負電圧切換回路７１０の出力すなわち０ｖがワード線１０４に出力される。
【００６４】
また、書込み時の選択ワード線に対応して、ドライバ回路７０５の出力が０ｖであるが、このときの正昇圧回路７０６の出力が０ｖでありまた負電圧切換回路７１０の出力が負高電圧Ｖbbであるので、Ｐchトランジスタがオフ、Ｎchトランジスタがオンとなって負電圧切換回路７１０の出力すなわち負高電圧Ｖbbがワード線１０４に出力される。逆に書込みの選択ワード線に対応して、ドライバ回路７０５の出力が負高電圧Ｖbbであるので、Ｐchトランジスタがオン、Ｎchトランジスタがオフとなって正昇圧回路７０６の出力すなわち０ｖがワード線１０４に出力される。
【００６５】
更に、読み出し時の選択ワード線に対応して、ドライバ回路７０５の出力が０ｖであるので、Ｐchトランジスタがオン、Ｎchトランジスタが オフとなって正昇圧回路７０６の出力すなわち読み出し電圧Ｖprがワード線１０４に出力される。逆に消去時の選択ワード線に対応して、ドライバ回路７０５の出力が正高電圧Ｖppであるので、Ｐchトランジスタがオフ、Ｎchトランジスタがオンとなって負電圧切換回路７１０の出力すなわち０ｖがワード線１０４に出力される。
【００６６】
以上の記述をまとめると下記の表７に示すようになる。
【００６７】
【表７】

【００６８】
上記したように、この回路構成によって、消去時のドライバ回路７０５の出力を選択／非選択に対応して０ｖ／Ｖｐｐにレベルシフトすることになり、消去時の選択／非選択を入力アドレス信号に対応させることになり、選択・消去が可能となる。さらに、回路構成が簡素となり、例えば図４に示したように多くの電圧切換回路を用いる必要がなく、面積の縮小が可能となる。
【００６９】
また、実施の形態１と同様に、書き込みと消去時のワード線への印加電圧が逆（書き込み時にワード線に正高電圧、消去時にワード線に負高電圧を印加）となるＣＨＥ書き込み／ＦＮ消去方式の場合は、書き込みと消去の上記動作を置き換えることによりこの回路を適用することが可能である。
【００７０】
【発明の効果】
以上説明したように本発明は、読み出し時電圧供給回路を消去あるいは書き込み電圧供給回路とスイッチング回路で分離することによって、該読み出し時電圧供給回路を３ｖと程度の低い耐圧のトランジスタのみで構成することができるので読み出しが高速となり、また回路面積を小さくすることができる。
【００７１】
また、正電圧を扱う消去／読み出し時電圧供給回路と負高電圧を扱う書き込み時電圧供給回路とをスイッチング回路で分離するようにすると消去電圧は高正電圧を扱うにしても書き込み時に扱う正電圧はさほど高い電圧は必要でないので（例えば５ｖ程度）、上記同様読み出し消去時の高速化及び回路面積を小さくできる効果がある。この効果は書込み時と読み出し時に正電圧を、また、消去時に負電圧を扱うようにしても消去時に扱う正電圧はさほど高い電圧は必要でないので同じとなる。
【００７２】
更に、２つのレベルシフト回路とドライバ回路を組合わせることによって電圧切換回路の数を少なくでき、この場合も回路面積を小さくすることができる効果がある。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態におけるデコーダ回路の回路図
【図２】本発明の第１の実施の形態におけるデコーダ回路の回路図
【図３】本発明の第２の実施の形態におけるデコーダ回路の回路図
【図４】本発明の第４の実施の形態におけるデコーダ回路およびドライバ回路の回路図
【図５】本発明の第５の実施の形態におけるデコーダ回路の回路図
【図６】本発明の第６の実施の形態におけるデコーダ回路の回路図
【図７】従来のデコーダ回路の回路図および各動作時の印加電圧表
【符号の説明】
１００、２００ スイッチング回路
１０１ メモリセルアレイ
１０２ 読み出し時電圧供給回路
１０３ 書き込み／消去時電圧供給回路
１０４ ワード線
１０５ 読み出し時電圧供給回路の出力
１０６ 書き込み／消去時電圧供給回路の出力
１０７、３０７ 高耐圧Ｎchトランジスタ
１０８ ３０８、６０８ 電圧切換回路
１０９、５１３、６０９ 入力アドレス
１１０ メモリセル
２０５ 読み出し時電圧供給回路のドライバ回路
２０６ 読み出し時電圧供給回路のレベルシフト回路
２０７ 書き込み／消去時電圧供給回路のドライバ回路
２０８ 書き込み／消去時電圧供給回路のレベルシフト回路
３０７ 高耐圧Ｐchトランジスタ
５０９、７０６ 正昇圧回路
５１５、５１６、５１７、５１８、５２０ 電圧切換回路
５１９、７１０ 負高電圧昇圧回路
５２１、５２２ 高耐圧Ｐchトランジスタ
５２３ 高耐圧Ｎchトランジスタ
６０２ 正高圧読み出し／消去時電圧供給回路
６０３ 負高耐圧書き込み時電圧供給回路
６０５ 読み出し／消去時電圧供給回路の出力
６０６ 書き込み時電圧供給回路の出力
７０５ ドライバ回路
７０７、７０８ レベルシフト回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a decoder circuit that performs voltage control on a memory cell array, and more particularly to a decoder circuit that controls a word line voltage of a memory cell constituting the memory cell array.
[0002]
[Prior art]
FIG. 7 shows a conventional decoder circuit.
Hereinafter, the configuration of the circuit shown in FIG. 7 will be described together with the operation. First, to correspond to the selected word line 808 at the time of reading, 5v is applied to the gate inputs S1 to S3 of the NAND gate 801, and the output is set to 0v. As a result, the output of the Pch transistor 802 is turned on, and the output Vrdec (5v) of the positive high voltage switching circuit is applied to the gate of the triple well high breakdown voltage Nch transistor 804. At this time, since the predecoder output is 5 v as apparent from the lower table of FIG. 7, the Nch transistor 804 is turned off. On the other hand, the Pch transistor 805 is turned on by the output of the NAND gate 801, and the potential 5v of the predecoder output 810 is output to the word line via the Pch transistor 805.
[0003]
On the other hand, the inputs S1 to S3 of the NAND gate corresponding to the unselected word line are the same 5v as that of the selected word line. As a result, the output of the Pch transistor 802 is turned on and the output of the positive and high voltage switching circuit is the same as in the reading operation. Vrdec of 5v is applied to the gate of the triple well high breakdown voltage Nch transistor 804. However, at this time, the predecoder output Is Since it is 0v, the transistor 804 is turned on. On the other hand, the Pch transistor 805 is turned off by the output of the NAND gate 801 and the predecoder output, and the potential 0v of the predecoder output 810 is applied to the word line. N Output via the ch transistor 804.
[0004]
The same operation as that at the time of reading is performed at the time of writing, but the positive potential is as high as 10.5v. At the time of erasing, 5v is applied to the inputs S1 to S3 of the gate of the NAND gate 801, and the output is set to 0v. At this time, since the negative high voltage Vbb is −10v and the positive high voltage Vrdec is 0v, the high breakdown voltage Nch transistor 803 is turned on and the Pch transistor 802 is turned off. N The ch transistor 804 is turned off. Further, the high breakdown voltage Pch transistor 805 is turned off and the triple well high breakdown voltage Nch transistor 806 is turned on.
[0005]
As a result, the negative high voltage Vbb (−10 v) is applied to the word line.
[0006]
[Problems to be solved by the invention]
In the configuration as described above, since the high voltage 10.5v is used as the selection signal when writing, it is necessary to configure the logic cell (NAND gate 801) also with a high breakdown voltage transistor, and the predecoder output 810 and the positive high voltage switching. A high voltage transistor is also required for a circuit that supplies a voltage to the circuit output 811 and the negative high voltage Vbb output 812. A high-breakdown-voltage transistor has a smaller current capacity than a normal transistor. Therefore, the access speed at the time of reading tends to be slow, and an attempt to increase the current capacity increases the area of the decoder section.
[0007]
Further, when performing selective erasing at the time of erasing, it is necessary to switch the word line voltage (in this case, −10v) from 0v to −10v in the logic cell, and the configuration of the voltage switching circuit for performing this kind of switching is required. It is difficult, and further, a transistor that can withstand a change from 10.5v to -10v has a problem in that a cost disadvantage increases.
[0008]
The present invention has been proposed in view of the above problems, and a read voltage supply circuit (or read / erase voltage supply circuit) that handles a relatively low voltage is used for writing or erasing voltage supply circuit (or By separating from the voltage supply circuit at the time of writing, the read voltage supply circuit (the voltage supply circuit at the time of reading / erasing) is configured with a low breakdown voltage transistor, and an object is to realize high speed read access. Another object of the present invention is to provide a decoder circuit that can be selectively erased by reducing the number of peripheral control circuits by suppressing the increase in area by using two stages of level shift circuits even in the case of using only high voltage transistors. To do.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the decoder circuit of the present invention is configured as follows.
[0010]
That is, according to the present invention, an operation voltage corresponding to erasing, writing, and reading is applied to a word line of a memory cell array arranged two-dimensionally based on an input address signal that determines selection or non-selection of the word line 104. Assume a decoder circuit to be supplied.
[0011]
In the decoder circuit, the present invention includes an erasing / writing voltage supply circuit 102 for supplying a positive or negative high voltage to a word line at the time of erasing or writing based on the address signal, and an erasing / writing at the time of reading based on the address signal. Corresponding to the read voltage supply circuit 103 for supplying a voltage lower than the absolute value of the voltage at the time of writing to the word line and the selected word line at the time of erasing or writing, the voltage at the time of reading is the voltage at the time of erasing / writing. The switching circuit 100 is configured to be cut off from the supply circuit.
[0012]
In this configuration, a positive high voltage erasure voltage or a negative high voltage write voltage is not applied to the read voltage supply circuit 102, and a voltage of about 3 V is sufficient as the read voltage. The supply circuit 103 may be a circuit that handles the standard voltage of about 3v. Therefore, the current capacity can be increased and the operation speed can be increased.
[0013]
The erase / write voltage supply circuit 103 is composed of a combination of a level shift circuit 208 and a driver circuit 207. The driver circuit 207 of the erase / write voltage supply circuit 1103 is at least selected at the time of erase. Corresponding to the first switch element 521 that is turned on corresponding to the word line 104, the second switch element 523 that is turned on corresponding to at least the selected word line 104 at the time of writing, and the selected word line 104 at the time of erasing In this configuration, the third switch element 522 that is turned on only when it is turned on and supplies the output of the first switch element 521 to the word line 104 can be selectively erased.
[0014]
Further, the same effect can be obtained when the switching circuit 200 separates the positive and high voltage read / erase voltage supply circuit 602 that handles positive and high voltages and the negative and high withstand voltage write voltage supply circuit 603 that handles negative and high voltages. Can be obtained.
[0015]
Furthermore, a first level shift circuit 708 that switches and outputs a power supply voltage and a negative high voltage at the time of writing based on the address signal, and at the time of reading and erasing based on the output of the first level shift circuit 708 Based on the output of the second level shift circuit 707 that switches and outputs the positive voltage and the negative high voltage at the time of writing, and at least at the time of reading and erasing based on the output of the second level shift circuit 707 The positive booster circuit 706 that supplies a positive high voltage supplies read and erase voltages to the word line, and is turned on at least at the time of writing based on the output of the second level shift circuit 707, so that a negative high voltage By including a driver circuit that supplies a write voltage to the word line from the negative high voltage booster circuit 710 that supplies the voltage, It is possible to reduce the number of primary-pressure circuit also becomes possible selective erasure.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 shows a circuit diagram of a decoder circuit according to the first embodiment of the present invention, and FIG. 2 shows details of one word line shown in FIG.
[0017]
The read voltage supply circuit 102 includes a driver circuit 205 and a level shift circuit 206. The level shift circuit 206 reads a read voltage Vpr (for example, 3 v) with respect to a selected word line based on an address signal, and with respect to an unselected word line. The driver circuit 205 at the next stage is controlled so that a voltage of 0 V is applied. Further, the output of the driver circuit 205 of the read voltage supply circuit 102 is connected to the word line 104 of the memory cell via the Nch transistor 107. The source and bulk of the Nch transistor 107 are connected to the output of the driver circuit 205 of the read voltage supply circuit 102, and the drain is connected to the word line 104.
[0018]
The write / erase voltage supply circuit 103 includes a driver circuit 207 and a level shift circuit 208. The level shift circuit 208 applies a negative high voltage Vbb (for example, -8V) to the selected word line 104 at the time of writing based on an address signal. Further, the driver circuit 207 of the next stage is controlled so that 0v can be applied to the unselected word line, and a positive high voltage Vpp (for example, 8V) can be applied to the word line 108 at the time of erasing. Ru Thus, the driver circuit 207 is controlled. The output of the driver circuit 207 is directly connected to the drain of the Nch transistor 107, that is, the word line 104.
[0019]
The output of the voltage switching circuit 108 is connected to the gate of the Nch transistor 107 to constitute the switching circuit 100. At the time of reading, a positive high voltage Vpp is output from the voltage switching circuit 108 to turn on the Nch transistor 107. Based on the address signal, the read voltage Vpr (Vpr <Vpp) is output from the read voltage supply circuit 102 as described above corresponding to the selected word line 104.
[0020]
As a result, the read voltage Vpr is output to the selected word line 104. In response to the unselected word line 104, 0V is output from the read voltage supply circuit 102 as described above, and the Nch transistor is turned on. Through The 0v Wa It will be applied to the lead wire.
[0021]
Since the read voltage is slightly higher than 3v in the latest memory cell, a voltage higher than 3v is used as the read voltage Vpr. Therefore, the read voltage supply circuit 102 according to this configuration can be configured with a relatively low withstand voltage transistor (hereinafter referred to as a standard transistor) of about 3 V. Therefore, the current supply capability of the read voltage supply circuit 102 is high. Thus, high-speed reading is possible.
[0022]
Further, when erasing / writing that requires a positive and negative high voltage, a voltage for turning off the Nch transistor 107 is applied from the high voltage switching circuit 108, so that a high voltage from the word line 104 is applied to the standard transistor in the voltage supply circuit 102 at the time of reading. This prevents the voltage from being applied, and thus suppresses the current leak path in the standard transistor.
[0023]
Further, the case of using FN writing / FN erasing (negative high voltage during writing, positive high voltage during erasing) has been described, but the voltage applied to the word line during writing and erasing is reversed (positive high voltage applied to the word line during writing). In the case of the CHE writing / FN erasing method in which a negative high voltage is applied to the word line at the time of erasing, the above operations of writing and erasing can be replaced.
[0024]
(Embodiment 2)
FIG. 3 is a circuit diagram of a decoder circuit according to the second embodiment of the present invention. The difference from the first embodiment shown in FIGS. 1 and 2 is that a Pch transistor 307 is used instead of the Nch transistor 107 constituting the switching circuit 100.
[0025]
That is, as shown in the first embodiment, the read voltage supply circuit 102 further includes a driver circuit 205 and a level shift circuit 206, and the write / erase voltage supply circuit further includes a driver circuit 207 and a level shift circuit. 208. The output of the driver circuit 205 is connected to the word line 104 via the Pch transistor 307, the source and bulk of the Pch transistor 308 are connected to the word line 104, and the drain is the output 105 of the voltage supply circuit 102 at the time of reading. Connected to.
[0026]
In this configuration, at the time of reading, the read voltage supply circuit 102 is activated based on the address signal 109 to output the read voltage Vpr from the driver circuit 205 and 0 V is applied to the gate of the Pch transistor 307 from the voltage switching circuit 308. Thus, the Pch transistor 307 is turned on. As a result, the read voltage Vpr is applied to the word line 104 corresponding to the selected word line 104. On the other hand, 0v is applied to the word line 104 so as not to activate the read voltage supply circuit 102 corresponding to the unselected word line 104.
[0027]
Also in this case, since the read voltage supply circuit 102 is composed of standard transistors, the current supply capability of the transistors is high and high-speed reading is possible. At the time of erasing / writing, the voltage for turning off the Pch transistor at the gate of the Pch transistor 307 Is applied to prevent a high voltage from being applied to the standard transistor in the read voltage supply circuit 102, and the current leakage path is also suppressed.
[0028]
(Embodiment 3)
Various specific examples of the first embodiment can be considered. In particular, when the selective erase function is not provided (when only the collective erase function is provided), the read driver circuit constituting the read voltage supply circuit 102 is provided. 205, the level shift circuit 206, the driver circuit 207 constituting the write / erase voltage supply circuit 103, and the level shift circuit 208 can be realized by using a circuit having the same type of function conventionally used. When the selective erasing function is provided, it can be configured as shown in FIG.
[0029]
Here, the driver circuit 207 of the write / erase voltage supply circuit 103 is configured as described below to enable selective erasure. That is, a conventional level shift circuit configuration is used as the level shift circuit 208 of the write / erase voltage supply circuit 103, and the selection of the erase E, write P, and read R is selected or not selected as the input of the level shift circuit 103. In response to the address signal 513, an address signal 513 having a power supply voltage Vdd or a voltage of 0v is used. The level shift circuit 208 selects and outputs the power supply voltage Vdd at the time of selection (address signals for the erase E, write P, and read R are the power supply voltage Vdd). 0v) selects and outputs the negative high voltage booster circuit 519. As a result, the level shift circuit 208 outputs a voltage as shown in Table 1 below when the erase, write, and read cases are selected or not selected. Since the configuration of the level shift circuit 208 itself is known, the description thereof is omitted here.
[0030]
[Table 1]

[0031]
The driver circuit 207 of the write / erase voltage supply circuit 103 includes three transistors 521, 522, and 523 connected in series. The Pch transistor 521 has a source connected to the output of the voltage switching circuit 515, a drain connected to the source of the Pch transistor 522, a gate connected to the output of the level shift circuit 208, and a bulk connected to the output of the voltage switching circuit 518. ing. Further, as described above, the Pch transistor 522 has a source connected to the drain of the Pch transistor 521, a gate connected to the output of the voltage switching circuit 516, a drain connected to the drain of the Nch transistor 523, and a bulk connected to the voltage switching circuit. 518. Further, the Nch transistor 523 has a source connected to the output of the voltage switching circuit 517, a drain connected to the drain of the Pch transistor 522 as described above, and a gate shared with the gate of the Nch transistor 523 as described above. The bulk is connected to the output of the negative high voltage booster circuit 519.
[0032]
The driver circuit 207 is thus configured, and the output of the voltage switching circuit 515 is set to the high positive voltage Vpp and the output of the voltage switching circuit 516 is set to the power supply voltage Vdd (Vpp> Vdd) corresponding to the selected word line at the time of erasing. By setting the output of the voltage switching circuit 517 to the power supply voltage Vdd (the output of the level shift circuit 208 at this time is the power supply voltage Vdd from Table 1), the Pch transistor 521 is turned on, the Pch transistor 522 is turned on, and the Nch transistor 523 is turned on. The high positive voltage Vpp is applied to the word line.
[0033]
On the other hand, corresponding to the unselected word line 104 at the time of erasing, the output of the voltage switching circuit 515 is set to the high positive voltage Vpp, the output of the voltage switching circuit 516 is set to the high positive voltage Vpp, and the output of the voltage switching circuit 517 is set to the power supply voltage. By setting Vdd (the output of the level shift circuit 208 at this time is 0 v), the Pch transistor 521 is turned on, the Pch transistor 522 is turned off, the Nch transistor 523 is also turned off, and 0 v is applied to the word line. Can be selected and erased.
[0034]
At the time of erasing, the output of the voltage switching circuit 518 connected to the bulk of the Pch transistors 521 and 522 is a positive high voltage Vpp and has the same potential as the voltage applied to the source or drain (the drain of the Pch transistor 522 when not selected). Since only the voltage is 0 V, and therefore the reverse bias is applied between the bulk drains, there is no current leakage. The output of the negative high voltage booster 519 connected to the bulk of the Nch transistor 523 is 0v, and the source or drain and the bulk are reverse biased (only the drain voltage at the time of non-selection is 0v, so the bulk drain is the same. Therefore, there is no current leakage.
[0035]
At the time of writing, corresponding to the selected word line, the output of the voltage switching circuit 515 is set to 0 v, the output of the voltage switching circuit 516 is set to the negative high voltage Vbb, and the output of the voltage switching circuit 517 is also set to the negative high voltage Vbb. At this time, since the output of the level shift circuit 208 is the power supply voltage Vdd, the Pch transistor 521 is turned on, the Pch transistor 522 is turned off, the Nch transistor 523 is turned on, and the negative high voltage Vbb is applied to the word line. .
[0036]
On the other hand, the outputs of the voltage switching circuit 515, the voltage switching circuit 516, and the voltage switching circuit 517 are made to be the same as in the above selection, corresponding to the unselected word lines at the time of writing. At this time, since the output of the level shift circuit 208 is the negative high voltage Vbb, the Pch transistor 521 is turned off, the Pch transistor 522 is also turned off, and the Nch transistor 523 is turned off, so that the output 0v of the voltage switching circuit 515 is connected to the word line. Will be applied.
[0037]
At the time of writing, the output of the voltage switching circuit 518 connected to the bulk of the Pch transistor 521 is the power supply voltage Vdd, and the voltage applied to the source or drain is 0 V, so that the reverse bias is applied. Further, the voltage applied to the bulk of the Pch transistor 522 is the power supply voltage Vdd, the voltage applied to the source is 0 v, the voltage applied to the drain is the negative high voltage Vbb when selected, and 0 v when not selected. In either case, reverse bias is applied. Further, at the time of writing, the output of the negative high voltage booster circuit 519 connected to the bulk of the Nch transistor 523 is the negative high voltage Vbb, and the voltage applied to the source or drain is also the negative high voltage Vbb when selected or not selected Since it is 0V at the time, it becomes the same potential or reverse bias. Therefore, there is no current leakage.
[0038]
Further, at the time of reading, corresponding to the selected word line, the output of the voltage switching circuit 515 is set to 0 v, the output of the voltage switching circuit 516 is set to the reading voltage Vpr, and the output of the voltage switching circuit 517 is also set to the reading voltage Vpr. At this time, since the output of the level shift circuit 208 is the power supply voltage Vdd, the Pch transistor 521 is turned off, the Pch transistor 522 is also turned off, and the Nch transistor 523 is also turned off. Corresponding to the non-selected word line at the time of reading, the outputs of the voltage switching circuit 515, the voltage switching circuit 516, and the voltage switching circuit 517 are made the same as those at the time of selection. At this time, since the output of the level shift circuit 208 is 0 V, the Pch transistor 521 is turned off, the Pch transistor 522 is turned off, and the Nch transistor 523 is also turned off.
[0039]
At this time, the read voltage Vpr is applied from the voltage switching circuits 518 and 517 to the bulk of each of the Pch transistors 521 and 522 and the Nch transistor 523, and applied to the source or drain of each of the transistors 521, 522 and 523. Since the voltage has the same potential or reverse bias, no current leakage occurs.
[0040]
The above description is summarized as a table as shown in the following two tables. In FIG. 5 and Table 2, the relationship with the read voltage Vpr is Vpr> Vdd.
[0041]
[Table 2]

[0042]
Next, voltage control to the word line at the time of reading is performed by the level shift circuit 206 and the driver circuit 205 at the time of reading. The level shift circuit 206 uses the address signal 513 that takes one of the power supply voltages Vdd and 0v according to selection or non-selection of the input, or an inverted signal thereof. Based on the address signal, the positive booster circuit 509 and the ground The voltage is selected. Here, the output of the positive booster circuit 509 is set to power supply voltage Vdd / power supply voltage Vdd / read voltage Vpr in accordance with erasing / writing / reading. As a result, the output of the level shift circuit 206 is as shown in Table 3 below, corresponding to selection and non-selection. Since the configuration of the level shift circuit 206 itself is known, the description thereof is omitted.
[0043]
[Table 3]

[0044]
The driver circuit 205 in the next stage connects the high breakdown voltage Pch transistor and the drain of the Nch transistor to each other, connects the output of the positive booster circuit 509 to the source and bulk of the Pch transistor, and grounds the source of the Nch transistor. Further, the output of the level shift circuit 206 is connected to the gates of both transistors.
[0045]
Basically, in the above configuration, at the time of selection at the time of erasing and writing, the level shift circuit 206 applies 0v to the gates of the Pch transistor and Nch transistor to turn on the Pch transistor and turn off the Nch transistor. As described below, since the Nch transistor 107 connected to the word line is turned off, the positive or negative high voltage applied to the word line is not applied to the driver circuit 205. Similarly to the above, when selecting at the time of reading, the level shift circuit 206 applies 0v to the gates of the Pch transistor and the Nch transistor to turn on the Pch transistor and turn off the Nch transistor. At this time, since the Nch transistor 107 connected to the word line is on, the read voltage Vpr is applied to the word line.
[0046]
In the case of non-selection in each case of erasing, writing, and reading, the output of the level shift circuit 205 is the same as the output of each case of the positive booster circuit 509, so that the Pch transistor of the driver circuit 205 is off, And the Nch transistor is turned on and the word line is grounded. The above is summarized as shown in Table 4 below.
[0047]
[Table 4]

[0048]
Here, the power supply voltage Vdd (the same potential as the source voltage Vdd and lower than the high positive voltage Vpp applied to the word line 104) is applied to the gate of the Nch transistor 107 from the voltage switching circuit 108. Therefore, the Nch transistor 107 is turned off. Further, since a negative high voltage Vbb (a voltage lower than the source voltage Vdd and the same potential as the high positive voltage Vbb applied to the word line 104) is applied at the time of writing, the Nch transistor 107 is turned off in the same manner as at the time of erasing. It becomes.
[0049]
As in the first embodiment, the CHE writing / FN in which the voltage applied to the word line at the time of writing and erasing is reversed (a positive high voltage is applied to the word line at the time of writing and a negative high voltage is applied to the word line at the time of erasing). In the case of the erasing method, this circuit can be applied by replacing the above operations of writing and erasing.
[0050]
(Embodiment 4)
FIG. 5 shows a circuit diagram of a decoder circuit according to Embodiment 4 of the present invention. The memory cell array 101 and the positive high voltage read / erase voltage supply circuit 602 are connected via an Nch transistor 607. The Nch transistor 607 has a drain connected to the word line 104 and a source and a bulk positive voltage read / erase voltage supply circuit 602. Is connected to the output 605. The output 606 of the negative high withstand voltage write voltage supply circuit 603 is connected to the word line 104 of the memory cell array 101, that is, the drain of the Nch transistor 607.
[0051]
Further, the gate of the Nch transistor 607 is connected to the output of the voltage switching circuit 608. The Nch transistor 607 and the voltage switching circuit 608 supply the voltage supply circuit 602 at the time of positive / high voltage read / erase and the voltage supply at the time of negative high withstand voltage writing. A switching circuit 200 that cuts off the circuit 603 is configured.
[0052]
Further, the input address signal 609 is simultaneously input to the positive and high voltage read / erase voltage supply circuit 602 and the negative high withstand voltage write voltage supply circuit 603, and the above-described input signal 609 is input according to the address signal at each operation (read / erase / write). The positive and high voltage read / erase voltage supply circuit 602 and the negative and high withstand voltage write voltage supply circuit 603 output necessary voltages to the word line 104. The voltage switching circuit 608 applies a positive high voltage (Vpp) to the gate of the Nch transistor 607 at the time of reading / erasing to turn on the Nch transistor 607. At the time of writing, the Nch transistor 607 is turned off by applying a voltage that cuts off the word line and the read / erase voltage supply circuit to the gate of the Nch transistor 607, and thereby the positive and high voltage read / erase voltage supply circuit 602. The voltage supply circuit 603 at the time of negative high withstand voltage writing is cut off, and the current leakage path to the voltage supply circuit 602 at the time of positive high voltage read / erase is cut.
[0053]
Further, in the positive / high withstand voltage read / erase voltage supply circuit 602, if the voltage Vpp applied to the word line at the time of erase is about 5 V, the positive / high withstand voltage read / erase voltage supply circuit 602 has a high withstand voltage (tens of volts). It is possible to configure a transistor having a relatively high current supply capability with a withstand voltage of about 5 V, and a high-speed access at the time of reading is possible.
[0054]
The above uses FN writing / FN reading (negative high voltage at writing, positive high voltage at erasing), but the applied voltage to the word line at writing and erasing is reversed (positive high at writing), as in the first embodiment. In the case of the CHE writing / FN erasing method in which a voltage and a negative high voltage are applied at the time of erasing, it can be applied by replacing the above-described operations of writing and erasing. That is, since a very high positive voltage is not required (about 5 V) at the time of writing (electron injection), the same effect as described above can be obtained.
[0055]
Further, FIG. 5 shows a configuration example of the Nch transistor 607 as the separation transistor, but a Pch transistor can be configured as in the second embodiment.
[0056]
(Embodiment 5)
FIG. 6 is a circuit diagram of a decoder circuit according to the fifth embodiment of the present invention. The configuration of the decoder circuit will be described below together with the operation. Since the structure of the level shift circuits 707 and 708 itself is known, the description thereof is omitted here.
[0057]
In FIG. 6, the level shift circuit 708 receives an address signal 709 composed of a combination of the power supply voltages Vdd and 0v or its inverted signal in accordance with selection and non-selection (the address signal 709 is erased when the selected and non-selected voltages are erased). Note that it changes in E, Write P, and Read R). As a result, as shown in Table 5, the output of the level shift circuit 708 is the power supply voltage Vdd or the output of the negative high voltage booster circuit 710 according to erase / write / read (erasure 0v, write Vbb, read) 0v) is selected.
[0058]
[Table 5]

[0059]
In response to the output of the level shift circuit 708 or its inverted signal, the output of the level shift circuit 707 corresponds to the positive booster circuit 706 (erasing Vpp, writing Vdd, reading Vpr) in accordance with erasing / writing / reading. Any voltage of the negative high voltage booster circuit 710 is output as shown in Table 6 below.
[0060]
[Table 6]

[0061]
In response to the output of the level shift circuit 707, the driver circuit 705 selects either the output of the positive booster circuit 706 or the output of the negative high voltage booster circuit 710.
[0062]
The driver circuit 705 connects the high breakdown voltage Pch transistor and the drain of the Nch transistor to each other, connects the output of the positive booster circuit 706 to the source and bulk of the Pch transistor, and switches the negative voltage to the source and bulk of the Nch transistor. The output of the circuit 710 is connected.
[0063]
With the above configuration, the driver circuit 70 corresponds to the selected word line at the time of erasing. Of 5 Since the output is 0 V, the Pch transistor is turned on and the Nch transistor is turned off, and the output of the positive booster circuit 706, that is, the positive high voltage Vpp is output to the word line 104. Conversely, the driver circuit 70 corresponds to the selected word line at the time of erasing. Of 5 Since the output is the positive high voltage Vpp, the Pch transistor is turned off and the Nch transistor is turned on, so that the output of the negative voltage switching circuit 710, that is, 0v is outputted to the word line 104.
[0064]
The driver circuit 70 corresponds to the selected word line at the time of writing. Of 5 Although the output is 0v, the output of the positive booster circuit 706 at this time is 0v and the output of the negative voltage switching circuit 710 is the negative high voltage Vbb. Therefore, the Pch transistor is off and the Nch transistor is on and negative. The output of the voltage switching circuit 710, that is, the negative high voltage Vbb is output to the word line 104. Conversely, the driver circuit 70 corresponds to the selected word line for writing. Of 5 Since the output is the negative high voltage Vbb, the Pch transistor is turned on and the Nch transistor is turned off, and the output of the positive booster circuit 706, that is, 0 v is outputted to the word line 104.
[0065]
Further, the driver circuit 70 corresponds to the selected word line at the time of reading. Of 5 Since the output is 0 V, the Pch transistor is turned on and the Nch transistor is turned off, and the output of the positive booster circuit 706, that is, the read voltage Vpr is output to the word line 104. Conversely, the driver circuit 70 corresponds to the selected word line at the time of erasing. Of 5 Since the output is the positive high voltage Vpp, the Pch transistor is turned off and the Nch transistor is turned on, so that the output of the negative voltage switching circuit 710, that is, 0v is outputted to the word line 104.
[0066]
The above description is summarized as shown in Table 7 below.
[0067]
[Table 7]

[0068]
As described above, with this circuit configuration, the output of the driver circuit 705 at the time of erasure is level-shifted to 0 v / Vpp corresponding to the selection / non-selection, and the selection / non-selection at the time of erasure is used as the input address signal. It is possible to select and delete. Further, the circuit configuration is simplified, and it is not necessary to use many voltage switching circuits as shown in FIG. 4, for example, and the area can be reduced.
[0069]
Similarly to the first embodiment, CHE writing / FN erasing in which the voltage applied to the word line at the time of writing and erasing is reversed (a positive high voltage is applied to the word line at the time of writing and a negative high voltage is applied to the word line at the time of erasing). In the case of the system, this circuit can be applied by replacing the above operations of writing and erasing.
[0070]
【The invention's effect】
As described above, according to the present invention, the read voltage supply circuit is separated by the erasure or write voltage supply circuit and the switching circuit, so that the read voltage supply circuit is configured by only a transistor having a low breakdown voltage of about 3v. Therefore, reading can be performed at high speed and the circuit area can be reduced.
[0071]
In addition, when the erase / read voltage supply circuit handling a positive voltage and the write voltage supply circuit handling a negative high voltage are separated by a switching circuit, the erase voltage is a positive voltage handled at the time of writing even if the high positive voltage is handled. Since a very high voltage is not required (for example, about 5 V), there is an effect that the reading speed can be increased and the circuit area can be reduced similarly to the above. This effect is the same because a positive voltage used at the time of erasing does not require a high voltage even if a positive voltage is handled at the time of writing and reading, and a negative voltage is handled at the time of erasing.
[0072]
Further, by combining the two level shift circuits and the driver circuit, the number of voltage switching circuits can be reduced, and also in this case, the circuit area can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a decoder circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a decoder circuit according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram of a decoder circuit according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram of a decoder circuit and a driver circuit according to a fourth embodiment of the present invention.
FIG. 5 is a circuit diagram of a decoder circuit according to a fifth embodiment of the present invention.
FIG. 6 is a circuit diagram of a decoder circuit according to a sixth embodiment of the present invention.
FIG. 7 is a circuit diagram of a conventional decoder circuit and an applied voltage table in each operation.
[Explanation of symbols]
100, 200 switching circuit
101 memory cell array
102 Voltage supply circuit for reading
103 Voltage supply circuit for writing / erasing
104 word lines
105 Output of voltage supply circuit during reading
106 Output of voltage supply circuit during write / erase
107,307 High voltage Nch transistor
108 308, 608 Voltage switching circuit
109, 513, 609 Input address
110 memory cells
205 Driver circuit of voltage supply circuit at the time of reading
206 Level shift circuit of voltage supply circuit during reading
207 Driver circuit for voltage supply circuit for writing / erasing
208 Level shift circuit of voltage supply circuit for writing / erasing
307 High breakdown voltage Pch transistor
509, 706 Positive booster circuit
515, 516, 517, 518, 520 Voltage switching circuit
519, 710 Negative high voltage booster circuit
521, 522 High voltage Pch transistor
523 High voltage Nch transistor
602 Voltage supply circuit for positive / high voltage read / erase
603 Voltage supply circuit for negative high withstand voltage writing
605 Output of read / erase voltage supply circuit
606 Output of voltage supply circuit during writing
705 Driver circuit
707, 708 level shift circuit

Claims (10)

A decoder for supplying an operating voltage corresponding to each case of erasing, writing, and reading based on an input address signal that determines selection or non-selection of the word line with respect to the word lines of the memory cell array arranged in two dimensions. In the circuit
Based on the address signal, a positive or supplying a negative high voltage to the word line erase / write time of voltage supply circuits corresponding to erase and write of the cases above,
The circuit is provided separately from the voltage supply circuit for erasing / writing , and supplies a voltage corresponding to only reading among the above cases to the word line based on the signal to the address , and the absolute value of the voltage during erasing / writing A read voltage supply circuit for supplying a lower voltage to the word line;
A decoder circuit comprising: a switching circuit for cutting off the read voltage supply circuit from the erase / write voltage supply circuit in correspondence with a selected word line at the time of erasing and writing. The read time of voltage supply circuit selection when each, based on the address signal indicating the non-selection, a level shift circuit for controlling the driver circuit,
2. The decoder circuit according to claim 1, further comprising: a driver circuit that supplies a voltage corresponding to each case to a word line from a voltage switching circuit in accordance with an output of the level shift circuit. The erase / write time of voltage supply circuit selection when each, based on the address signal indicating the non-selection, a level shift circuit for controlling the driver circuit,
2. The decoder circuit according to claim 1, further comprising: a driver circuit that supplies a voltage corresponding to each case to a word line from a voltage switching circuit in accordance with an output of the level shift circuit.   The driver circuit of the erase / write voltage supply circuit is turned on in response to at least the selected word line at the time of erasing, and is turned on in response to at least the selected word line at the time of writing. 4. The decoder according to claim 3, further comprising: a switching element configured to turn on only when corresponding to a selected word line at the time of erasing and supplying an output of the first switching element to the word line. circuit.   5. The decoder circuit according to claim 1, wherein the decoder circuit is applied to FN writing / FN erasing that handles a positive high voltage during erasing and a negative high voltage during writing. 6.   4. The decoder circuit according to claim 1, which is applied to CHE writing / FN erasing that handles a positive high voltage during writing and a negative high voltage during erasing.   This is applied to CHE writing / FN erasing which handles a positive high voltage at the time of writing and a negative high voltage at the time of erasing. The decoder circuit according to claim 4. A decoder circuit for supplying an operating voltage corresponding to each case of erasing, writing, and reading based on an input address signal that determines selection or non-selection of the word line with respect to the word lines of the memory cell array arranged in two dimensions In
Based on the address signal, in the above case , a negative high withstand voltage write voltage supply circuit for supplying a negative high voltage corresponding to only the write to the word line ,
Positive / high voltage read / erase voltage supply that is provided separately from the negative high withstand voltage write voltage supply circuit and supplies a positive voltage corresponding to each of read and erase among the above cases to the word line based on the address signal. Circuit,
Decoder circuit characterized by comprising a switching circuit for interrupting in response to the read and word line at the time of erasing, the positive pressure reading / erasing voltage supply circuit from the negative high resistance to pressure-write voltage supply circuit. In a decoder circuit for supplying an operating voltage corresponding to erasing, writing, and reading based on an input address signal that determines selection or non-selection of the word line with respect to a word line of a memory cell array arranged in two dimensions.
A first level shift circuit for switching and outputting a power supply voltage and a negative high voltage at the time of writing based on the address signal;
A second level shift circuit that switches between a positive voltage at the time of reading and erasing and a negative high voltage at the time of writing based on the output of the first level shift circuit;
Based on the output of the second level shift circuit, it is turned on at least at the time of reading and erasing, and the reading and erasing voltage is supplied to the word line from the voltage switching circuit for supplying a positive high voltage. A decoder circuit comprising a driver circuit that is turned on at least in writing based on the output of the level shift circuit and supplies a write voltage to a word line from a voltage switching circuit that supplies a negative high voltage. 10. The decoder circuit according to claim 9, which is applied to CHE writing / FN erasing by using a positive high voltage when writing and a negative high voltage when erasing.

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