JP3688312B2 - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To provide a miniature, high-performance multichip module and a manufacturing technique therefor. CONSTITUTION: Lead frames mounted with a semiconductor chip are stacked up to a specified number of layers, and sealed in a lump with resin to form a package 2. The obtained package 2 is placed on a mother socket 3. The outer leads 6 of the lead frames, led out of the side of the package 2, are electrically connected with the leads 7 of the mother socket that extend in the direction orthogonal to the direction of the extension of the outer leads 6, and a DRAM module 1 is thereby formed.

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a small and high performance multichip module.
[0002]
[Prior art]
A memory module represented by a single in-line memory module (SIMM) is widely used as a semiconductor memory mounted on an engineering workstation (EWS) or a computer.
[0003]
In SIMM, a semiconductor chip on which a memory LSI such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) is normally formed is sealed in an LSI package such as SOJ (Small Out-line J-leaded Package). A plurality of these are mounted on one side or both sides of a printed wiring board.
[0004]
However, recent EWS and parallel processing computers require a large capacity memory (RAM) to process a large amount of data at high speed. Therefore, in order to cope with this, a three-dimensional technology of the memory module has been studied. This is because, in a method of mounting an LSI package on a printed wiring board in a two-dimensional manner like a conventional SIMM, the size of the printed wiring board is remarkably increased as the memory capacity increases. .
[0005]
As a specific example of the three-dimensional memory module, for example, several layers of ultra-thin LSI packages such as TSOP (Thin Small Out-line Package) are stacked and printed circuit boards are arranged on both side walls, and the leads of each TSOP are arranged. A structure held by this side substrate (Industry Research Committee, published on September 1, 1993, “Electronic Materials” p.33 to p.39) is known.
[0006]
According to this type of three-dimensional memory module, a larger number of LSI packages can be mounted on a printed wiring board having the same area, so that a small and large capacity memory module can be realized. Further, since the wiring length for connecting the packages can be shortened as compared with the case where the LSI package is mounted on the printed wiring board in a plane, there is a great advantage in terms of speeding up.
[0007]
[Problems to be solved by the invention]
However, a three-dimensional memory module having a conventional structure in which ultrathin LSI packages such as TSOP are stacked is difficult to achieve both miniaturization of the module and reduction of the thermal resistance of the package.
[0008]
That is, when LSI packages such as TSOP are stacked, the resin thickness between the upper and lower semiconductor chips is doubled, and the thermal resistance of the package is increased. Therefore, in order to reduce this thermal resistance, an appropriate gap must be provided between the packages, so that the external dimensions in the vertical direction of the module are increased.
[0009]
An effective means for reducing the size of the three-dimensional memory module is to collectively seal a plurality of semiconductor chips in one package. In this case, the thickness of the resin filled between the upper and lower semiconductor chips is reduced, so that not only the vertical dimension of the package is reduced, but also the thermal resistance of the package is reduced.
[0010]
However, it is not possible to obtain a highly reliable memory module by simply collectively sealing a plurality of semiconductor chips in one package.
[0011]
That is, when a plurality of semiconductor chips are collectively sealed in one package, the temperature difference between the central portion and the peripheral portion of the package becomes large, and it is expected that a large thermal stress is generated inside the package. Therefore, it is indispensable to design a structure for quickly radiating the heat at the center of the package to the outside.
[0012]
Further, when a plurality of semiconductor chips are collectively sealed in one package, there is a problem of how to perform testing, sorting, aging, and the like.
[0013]
That is, a module in which a plurality of semiconductor chips are collectively sealed in one package cannot be replaced even if any semiconductor chip is found to be defective after the package is sealed. Therefore, in order to improve the module manufacturing yield, whether or not all semiconductor chips operate normally immediately after the step of sealing the semiconductor chips after mounting the semiconductor chips on the lead frame and performing wire bonding. It is necessary to perform testing, selection, and aging to confirm the above. However, the lead frame before the sealing process is in a state in which all the leads are electrically connected via the tie bars, and thus cannot be tested, sorted, or aged as it is.
[0014]
Further, when a plurality of semiconductor chips are collectively sealed in one package, the yield of the sealing process and the throughput are also problems.
[0015]
Normally, LSI packages such as TSOP are molded by the insert mold method in which a lead frame is sandwiched between an upper mold and a lower mold and resin is injected into the gap. In the case of collective sealing, it is difficult to release the package with a conventional mold composed of an upper mold and a lower mold, and it is necessary to take measures against it. In addition, since it is difficult for the resin to flow into the gap between the overlapping lead frames and voids (voids) are easily generated, measures to prevent this are also necessary.
[0016]
In the conventional three-dimensional memory module, all semiconductor chips are mounted on a lead frame having the same pin arrangement. However, since the connection of data pins differs for each semiconductor chip, the use of lead frames having the same pin arrangement cannot simply connect the lead frames in the vertical direction. Therefore, for example, as in the memory module described in the above-mentioned document, measures such as arranging printed wiring boards on both side walls of the stacked LSI package are required, and downsizing of the module is restricted.
[0017]
Furthermore, it is difficult for the three-dimensional memory module having the conventional structure to cope with the multi-bit configuration. That is, for example, a multi-bit product with a wide data width such as a 36-bit memory module has a large number of data lines, so it is difficult to design a small lead frame, and the package size and bonding wire length must be long. . Therefore, it is difficult to mount a multi-bit product on a small memory module with the prior art.
[0018]
An object of the present invention is to provide a small and high performance multichip module and a manufacturing technique thereof.
[0019]
Another object of the present invention is to provide a technology capable of providing a small and high performance multichip module at low cost.
[0020]
Another object of the present invention is to provide a technique capable of downsizing a multichip module on which a multi-bit product is mounted.
[0021]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0022]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be described as follows.
[0023]
(1) A semiconductor integrated circuit device according to the present invention includes a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, mounted in a socket, and an outer portion of the lead frame drawn out from the resin package. A multichip module in which a lead and the lead of the socket extending in a direction intersecting with a direction in which the outer lead extends are electrically connected.
[0024]
(2) A semiconductor integrated circuit device according to the present invention is the multichip module according to (1), wherein each of the predetermined number of lead frames is individually designed, and the arrangement of data pins is changed for each lead frame. It is.
[0025]
(3) The semiconductor integrated circuit device of the present invention is the multichip module according to (1), wherein the predetermined number of lead frames are formed as a single assembly lead frame by batch patterning in the same process.
[0026]
(4) The semiconductor integrated circuit device of the present invention uses a tape dam type lead frame in which engineering plastic or insulating tape is formed on a mold line in the multichip module of (1).
[0027]
(5). A semiconductor integrated circuit device according to the present invention is the multichip module according to (1), wherein a pair of molding gate holes are provided in each of the predetermined number of lead frames.
[0028]
(6) The semiconductor integrated circuit device according to the present invention is such that in the multichip module of (1), an index hole having a different pattern for each lead frame is provided in each frame portion of the predetermined number of lead frames. .
[0029]
(7) The semiconductor integrated circuit device of the present invention is the multichip module of (1), wherein a half-etch line is provided in each of the predetermined number of lead frames.
[0030]
(8) A semiconductor integrated circuit device according to the present invention includes a capacitor mounted on each of the predetermined number of lead frames in the multichip module of (1).
[0031]
(9) A semiconductor integrated circuit device according to the present invention is a multichip module according to (1) in which a dummy lead frame is accommodated in the resin package.
[0032]
(10). The semiconductor integrated circuit device according to the present invention is the multichip module according to (1), wherein the lead of the socket is made of a conductive material having a thermal expansion coefficient substantially equal to the thermal expansion coefficient of the resin package. is there.
[0033]
(11) The semiconductor integrated circuit device of the present invention is the multichip module according to (1), wherein the leads of the socket are arranged in two rows along two opposite sides of the socket.
[0034]
(12) A semiconductor integrated circuit device according to the present invention is a multichip module according to (1), wherein a heat radiating fin is attached to the resin package.
[0035]
(13) A semiconductor integrated circuit device according to the present invention is a multichip module according to (1), wherein a semiconductor chip is mounted on the predetermined number of lead frames by a lead-on-chip method.
[0036]
(14). The semiconductor integrated circuit device according to the present invention is the multichip module according to (1), wherein the center of the semiconductor chip mounted on each of the predetermined number of lead frames is set to be data of the lead frame rather than the center of the resin package. It is arranged on the pin side.
[0037]
(15). The semiconductor integrated circuit device of the present invention is a multichip module according to (14) in which a dummy chip is accommodated in a resin package.
[0038]
(16). A semiconductor integrated circuit device according to the present invention is the multichip module according to (1), wherein a part of the predetermined number of lead frames is inverted 180 degrees in a horizontal plane with respect to other lead frames. To do.
[0039]
(17). In the semiconductor integrated circuit device according to the above (16), in the multichip module according to (16), among the predetermined number of lead frames, the lead frame arranged to be reversed and another lead frame are reversed. It has a symmetric lead pattern with respect to the axis.
[0040]
(18) A semiconductor integrated circuit device according to the present invention is the multichip module according to the above (1), in which a semiconductor chip electrically connected to a semiconductor chip in the resin package is mounted on the socket.
[0041]
(19). The semiconductor integrated circuit device of the present invention is the multichip module according to (1), wherein each of the semiconductor chips encapsulated in the resin package has a multi-bit input / output terminal and a front end. The resin package includes a predetermined number of input / outputs that are electrically connected to the lead frame throughout the semiconductor chip, including defective terminals that are not electrically connected to the lead frame in a part of the output terminals It constitutes a terminal.
[0042]
(20). The semiconductor integrated circuit device according to the present invention includes an outer lead of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and collectively sealed, and the extension of the outer leads And a lead that extends in a direction intersecting the direction to be crossed, and a lower end portion of the lead is formed into a J shape to constitute an external terminal of the resin package.
[0043]
(21). The semiconductor integrated circuit device according to the present invention is inserted into a gap between each of the upper die and the lower die and the predetermined number of lead frames when the multichip module of (1) or (20) is manufactured. Then, the predetermined number of lead frames are collectively sealed using a mold constituted by a predetermined number of movable molds, each of which can be divided into two.
[0044]
[Action]
According to the above means (1), since a plurality of semiconductor chips are collectively sealed in a package, a module constructed by stacking several layers of LSI packages such as TSOP in which semiconductor chips are sealed with a resin one by one Compared to the above, the outer dimensions can be greatly reduced.
[0045]
Further, by connecting the outer leads drawn out from the package and the leads of the socket so as to intersect with each other, a matrix-like heat dissipation path is formed, and the heat at the center of the package can be quickly dissipated to the outside.
[0046]
Further, since the outer leads are drawn out from the side surfaces of the package to form a leaf spring structure, the expansion and contraction of the resin filled in the gaps between the stacked lead frames can be reduced.
[0047]
According to the above means (2), the stacked lead frames can be directly connected by changing the arrangement of the data pins for each lead frame.
[0048]
According to the above means (3), a series of lead frames with uniform dimensional accuracy can be obtained by forming a predetermined number of lead frames as one set of lead frames by batch patterning in the same process.
[0049]
According to the above means (4), the metal part holding the lead is cut after the wire bonding process by using a tape dam type lead frame in which engineering plastic or insulating tape is formed on the mold line. As a result, each lead can be brought into an electrically floating state, so that testing, sorting, and aging can be performed immediately before the molding step.
[0050]
According to the above means (5), by providing a pair of mold gate holes in each of the lead frames, when the lead frames are stacked and mounted on the mold, the lead frames are vertically penetrated into the mold. Therefore, the resin injected from one gate quickly fills the cavity through the one gate line, resulting in non-uniform resin content such as voids generated inside the mold. Flows out from the opposite gate through the other gate line.
[0051]
According to the means (6) described above, by providing an index hole of a different pattern for each lead frame in each frame portion of the lead frame, the lead frame layer number identification is automatically read during mass production, It can be easily determined whether or not they are stacked in the correct order.
[0052]
According to the above means (7), by providing a half-etch line in each lead frame, it becomes easy to cut and remove unnecessary portions of the lead frame exposed to the outside of the package after molding.
[0053]
According to the above means (8), by mounting the capacitor on the lead frame, it is possible to reduce the power supply impedance when power is supplied to the semiconductor chip, so that a large current can be supplied.
[0054]
According to the above means (9), the bonding strength between the lead and the outer lead can be improved by pulling out the outer lead of the dummy lead frame from the package and connecting it to the lead of the socket. Moreover, since the heat dissipation path of the package is increased, the thermal resistance can be reduced. Furthermore, a dummy lead frame can be used as a wiring connection in the package.
[0055]
According to the above means (10), since the lead of the socket is made of a conductive material having a thermal expansion coefficient substantially equal to the thermal expansion coefficient of the package, the lead can follow the vertical expansion and contraction of the package. Thermal stress stress caused by anisotropic thermal expansion occurring between the vertical direction and the horizontal direction can be reduced.
[0056]
According to the means (11) described above, the socket corresponding to the multi-bit module can be obtained by arranging the socket leads in two rows along two opposing sides.
[0057]
According to the above means (12), a multi-chip module with high cooling efficiency can be obtained by mounting the radiation fins on the package.
[0058]
According to the above means (13), by mounting the semiconductor chip on the lead frame by the lead-on-chip method, the interlayer of the lead frame can be thinned, and the package can be downsized and the thermal resistance can be reduced. be able to. Also, as in the above means (16), when some lead frames are reversed 180 degrees in the horizontal plane with respect to other lead frames, the bonding pads are reversed to the lead frame when placed in reverse. The wire drawing direction can be easily reversed as necessary. This is particularly effective for sharing power supply lines.
[0059]
According to the above means (14), by shifting the center of the semiconductor chip to the data pin side of the lead frame, a sufficient data area can be secured and the routing of the data pin can be reduced.
[0060]
According to the above means (15), by accommodating the dummy chip inside the package, the resin flow during molding can be made uniform even when the semiconductor chip is shifted to the data pin side. . Further, since the resin amount of the entire package can be made uniform, the residual stress of the package can be reduced.
[0061]
According to the means (16) described above, by arranging a part of the lead frame to be inverted 180 degrees in the horizontal plane with respect to the other lead frames, the data pins of the lead frame are concentrated in one direction. Therefore, the lead can be easily routed and the lead frame can be downsized.
[0062]
According to the above means (17), since the number of types of lead frames is half, the manufacturing cost of the lead frames can be reduced. In addition, aging varieties can be reduced.
[0063]
According to the above means (18), by providing various functions to the semiconductor chip mounted on the socket, it is easy to expand the functions of the multichip module, improve the input / output characteristics, repair defects, etc. can do.
[0064]
According to the above means (19), only normal input / output terminals of a multi-bit semiconductor chip including a defective terminal as a part of the input / output terminals are selectively bonded to the lead frame, whereby normal input / output is performed. A multi-bit multichip module having terminals can be obtained.
[0065]
According to the above means (20), since the lead of the resin package can be directly connected to the printed circuit board, the socket of means (1) is not required, and the cost of the multichip module is reduced by reducing the number of parts. And downsizing of the outer dimensions can be realized.
[0066]
According to the above means (21), after molding, the package can be easily released from the mold by dividing each movable mold into left and right parts.
[0067]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0068]
(Example 1)
1 is a front perspective view of a DRAM module according to an embodiment of the present invention, FIG. 2 is a rear perspective view of the DRAM module, FIG. 3 is a front perspective view of a package of the DRAM module, and FIG. FIG. 5 is a front perspective view of the mother socket of the DRAM module, and FIG. 5 is an equivalent circuit diagram of the DRAM module.
[0069]
As shown in FIGS. 1 to 4, the DRAM module 1 of this embodiment includes a package 2 that is a module body and a mother socket 3 on which the package 2 is mounted. The package 2 and the mother socket 3 are made of an epoxy-based synthetic resin, a heat-resistant liquid crystal polymer, or the like, and are insert-molded using a mold described later.
[0070]
Inside the package 2 constituting the module body, nine semiconductor chips (M ₀ ~ M ₈ ) And these semiconductor chips (M ₀ ~ M ₈ A total of 9 lead frames (S) ₁ ~ S ₉ ) Are collectively sealed in a stacked state in the vertical direction.
[0071]
Nine semiconductor chips (M ₀ ~ M ₈ ), A CMOS-DRAM having a large capacity of 16 megabits Mbit and having a configuration of [16777216 words × 1 bit] is formed. These nine semiconductor chips (M ₀ ~ M ₈ ) Are connected to form a DRAM module having a [16777216 words × 9 bits] configuration as shown in FIG.
[0072]
FIG. 6 is a plan view showing a pad layout of a semiconductor chip (M) on which the 16 megabit Mbit DRAM is formed. This semiconductor chip (M) is configured to switch between the [4194304 words × 4 bits] mode and the [16777216 words × 1 bit] mode by a bonding option, and as in this embodiment, [16777216 words × 1 bit]. When operating in the mode, the FP2 pad is shorted to Vss (GND). In order to prevent an increase in the number of pins, Din and Dout shown in FIG. 5 may be internally connected to the same lead during wire bonding.
[0073]
Semiconductor chip (M ₀ ~ M ₈ 9 lead frames (S) ₁ ~ S ₉ ) Is shown in FIGS. As shown, these lead frames (S ₁ ~ S ₉ ) Each have a lead pattern (pin arrangement) designed individually. That is, the power supply (and GND) pins, address pins, and control signal pins are connected to all lead frames (S ₁ ~ S ₉ ), But the arrangement of data pins is different for each lead frame (S ₁ ~ S ₉ ) Is different. Reference numeral 44 denotes an opening for inserting a guide pin.
[0074]
The 9 lead frames (S ₁ ~ S ₉ ) Is the lead frame (S ₁ ) Is arranged on the lowermost layer of the package 2, and another lead frame (S ₂ ~ S ₉ ) Is S from the bottom _2, S _Three ... S ₉ Are stacked in this order. These lead frames (S ₁ ~ S ₉ ) Is composed of 42 alloy, Kovar, etc., and its standard plate thickness is about 0.125 to 0.1 mm. However, in order to reduce the vertical dimension of the DRAM module 1, the plate thickness can be further reduced.
[0075]
FIG. 16 shows the lowermost lead frame (S) on which the semiconductor chip (M) is mounted. ₁ ). The semiconductor chip (M) is mounted on the lead frame (S) by the LOC (Lead On Chip) method using the insulating tape 4. The insulating tape 4 includes a main surface of the semiconductor chip (M) and a lead frame (S ₁ ) And is bonded by thermocompression bonding. Semiconductor chip (M) bonding pad and lead frame (S ₁ ) Of the inner leads are electrically connected by Au wires 5.
[0076]
The insulating tape 4 is divided into four parts in order to relieve the thermal stress generated at the interface with the synthetic resin constituting the package 2. The insulating tape 4 is made of polyimide resin, and its standard thickness is about 0.1 to 0.05 mm. In addition to polyimide resin, the insulating tape 4 can also be made of a high heat-resistant and high-strength liquid crystal polymer (for example, a glass fiber reinforced high heat-resistant liquid crystal polymer such as “Vectra E130” manufactured by Polyplastics).
[0077]
FIG. 16 shows a lead frame (S ₁ ) Pins (pins 1 to 32) are shown. Although only the used pad is shown in the figure, Dout is the IO3 pad shown in FIG. 6 and Din is the Din pad, which are internally connected to the pin 31.
[0078]
The structure of the pin 1 to pin 32 will be described in order. Pin 1 is Vss, pin 2 is NC, and pin 3 is the second layer lead frame (S ₂ ) Data 1 and pin 4 are the lead frame (S _Four ) Data 3 and pin 5 are the lead frame (S ₆ ) Data 5 and pin 6 are the lead frame (S ₈ ) Data 7, pin 7 is bar WE, pin 8 is bar RAS, pin 9 is A (address) 11, pin 10 is A10, pin 11 is A0, pin 12 is A1, pin 13 is A2, pin 14 is A3 Pin 15 is Vcc, Pin 16 is also Vcc, Pin 17 is Vss, Pin 18 is also Vss, Pin 19 is A4, Pin 20 is A5, Pin 21 is A6, Pin 22 is A7, Pin 23 is A8, Pin 24 Is A9, and the pin 25 is the ninth lead frame (S ₉ ) (For parity) bar PCAS (first to eighth lead frames (S ₁ ~ S ₈ ) Is connected to the CAS pad used for the pin 26), and the pin 26 is a bar CAS (lead frame (S ₉ )), The pin 27 is the lead frame (S ₉ ) Parity data 8 and pin 28 are the seventh layer lead frame (S ₇ ) Data 6, pin 29 is the fifth layer lead frame (S _Five ) Data 4 and pin 30 are the lead frame (S _Three ) Data 2 and pin 31 are the lead frame (S ₁ ) Data 0, pin 32 is Vss.
[0079]
The DRAM module 1 of the present embodiment has a configuration in which the package 2 having the internal structure as described above is mounted on a mother socket 3.
[0080]
As shown in FIG. 3, the above-described nine lead frames (S ₁ ~ S ₉ ) Of each outer lead 6 is pulled out in the horizontal direction. An opening 8 is formed at the tip of each outer lead 6.
[0081]
Of the outer leads 6 drawn from the package 2, the outer leads 6 constituting the power supply (and GND) pins, address pins, and control signal pins are all lead frames (S ₁ ~ S ₉ ), The outer leads 6 are overlapped in the vertical direction on the side surface of the package 2. However, the control signal bar CAS is the uppermost lead frame (S ₉ ) Other lead frames (S) ₁ ~ S ₈ ) Is a common arrangement. On the other hand, the outer leads 6 constituting the data pins are not connected to each other so as not to overlap each other. ₁ ~ S ₉ ) Are drawn one by one (1 bit).
[0082]
As shown in FIG. 4, in the mother socket 3, a plurality of leads 7 extending in the vertical direction are arranged in a line along both side surfaces in the long side direction. These leads 7 are arranged in a lead frame (S ₁ ~ S ₉ ) Of the outer lead 6. The lower part of each lead 7 penetrates the mother socket 3 and extends to the back side thereof, and constitutes an external terminal when the DRAM module 1 is mounted on a printed wiring board of SIMM.
[0083]
In order to mount the package 2 on the mother socket 3, the lead 7 of the mother socket 3 is inserted into the opening 8 of the corresponding outer lead 6 of the package 2, and the both are connected by a known means such as soldering, brazing or welding. It is only necessary to fix and electrically connect.
[0084]
The DRAM module 1 of the present embodiment configured as described above includes a plurality of semiconductor chips (M ₀ ~ M ₈ ) Are collectively sealed in the package 2, so that the external dimensions can be greatly reduced compared to a module configured by stacking several layers of LSI packages such as TSOP in which semiconductor chips are sealed with resin one by one. it can. Each semiconductor chip (M ₀ ~ M ₈ ) Can be reduced in thickness, so that the thermal resistance of the package 2 can be reduced.
[0085]
In the DRAM module 1 of this embodiment, the outer leads 6 drawn in the horizontal direction from the side surface of the package 2 are connected so as to intersect the leads 7 of the mother socket 3 extending in the vertical direction. As a result, the heat at the center of the package 2 can be quickly dissipated to the outside, so that the DRAM module 1 with a low thermal resistance can be realized.
[0086]
In the above description, the outer leads 6 constituting the data pins are connected to the respective lead frames (S ₁ ~ S ₉ ), But it is also possible to draw out dummy leads that are not electrically connected. The actual example is the ninth outer lead 6 (pin 25) from the front left side of the package 2 shown in FIG. This pin 25 is connected to the lead frame (S ₉ ), The 9th layer lead frame (S ₉ As shown in FIG. 3, the lower lead frame (S ₁ ~ S ₈ ), The outer leads 6 are pulled out one by one. These eight outer leads 6 are connected to any semiconductor chip (M ₀ ~ M ₈ ) Are dummy leads that are not electrically connected.
[0087]
By pulling out such dummy leads from the package 2 and connecting them to the leads 7 of the mother socket 3, the heat radiation path of the package 2 is increased, so that the thermal resistance can be further reduced. Further, since the number of outer leads 6 connected to the leads 7 of the mother socket 3 is increased, the bonding strength between the leads 7 and the outer leads 6 is also improved.
[0088]
Further, the DRAM module 1 of this embodiment has a leaf spring structure in which the outer leads 6 are drawn from the side surface of the package 2. As a result, the lead frame (S ₁ ~ S ₉ ), The longitudinal expansion and contraction of the resin filled in the gap can be relaxed, so that the reliability of the package 2 can be improved.
[0089]
In addition, the DRAM module 1 of the present embodiment uses a lead frame (S ₁ ~ S ₉ ), The laminated lead frame (S ₁ ~ S ₉ ) Can be connected directly. That is, the lead frame (S ₁ ~ S ₉ Since a printed circuit board for the purpose of connection between them is not necessary, the DRAM module 1 can be reduced in size.
[0090]
Next, a method for manufacturing the package 2 shown in FIG. 3 will be described.
[0091]
17 is a perspective view of a nested mold used for molding the package 2, FIG. 18 is a perspective view showing a state where the upper mold of the mold is lifted, and FIG. 19 is a perspective view showing a state where the mold is divided. FIG. 20 is a perspective view showing a state in which the mold is divided (a view seen obliquely from below), and FIG. 21 is a plan view showing a movable mold of the mold. a) and side view (b).
[0092]
An LSI package such as TSOP is formed by an insert mold method in which a lead frame is sandwiched between an upper mold and a lower mold and resin is injected into the gap, but like the package 2 of the DRAM module 1 of this embodiment, , Multiple lead frames (S ₁ ~ S ₉ ) Are overlapped and collectively sealed, it is difficult to release the mold using a conventional mold composed only of an upper mold and a lower mold.
[0093]
Therefore, in this embodiment, molding is performed using a mold having a detachable nesting mold as shown in FIG. 17 connected to a resin runner in a part of a mold for injecting resin. The nesting mold 10 that can be easily attached and detached includes eight sets of movable molds (spacer molds) 13 in addition to the upper mold 11 and the lower mold 12. These movable molds 13 are composed of nine stacked (chip-bonded) lead frames (S ₁ ~ S ₉ ) Are inserted one by one into the gaps (8 places). As shown in FIG. 21, each movable mold 13 is divided into left and right parts about a parting line (PL) in the horizontal direction, so that the package 2 can be easily released. For example, a draft angle of about 4 ° is provided at four locations in a region orthogonal to the parting line (PL).
[0094]
By using the nested mold 10 provided with the movable mold 13 as described above, a number of lead frames (S ₁ ~ S ₉ ) Can be three-dimensionally arranged with high accuracy without any special structural reinforcement, and after molding, the upper and lower molds are divided in the vertical direction, and each movable mold 13 is divided in two in the horizontal direction. As a result, the package 2 can be easily released from the nested mold 10, so that the yield and throughput of the sealing process can be improved, and the manufacturing cost of the DRAM module 1 can be reduced.
[0095]
The thickness of the movable mold 13 is the thickness of the semiconductor chip (M), the thickness of the insulating tape 4 for LOC, the loop height of the wire 5 of the semiconductor chip (M), and the gap between the semiconductor chips (M). This is the total thickness of the resin to be filled. For example, when the thickness of the semiconductor chip (M) is 0.28 mm, the thickness of the insulating tape 4 is 0.1 mm, the loop height of the wire 5 is 0.15 mm, and the thickness of the resin is 0.15 mm, the movable mold The thickness of 13 is 0.68 mm.
[0096]
The lead frame (S) has a thickness of 0.1 mm, and the upper and lower ends of the package 2 have an upper end including the semiconductor chip (M) of 0.58 mm (the thickness of the insulating tape 4). Thickness of the semiconductor chip (M) + thickness of the resin = 0.1 mm + 0.28 mm + 0.15 mm), and the thickness of the lower end of only the wire 5 not including the semiconductor chip (M) is 0.35 mm (of the wire 5 Calculated as loop height + resin thickness = 0.15 mm + 0.2 mm), the vertical dimension of the package 2 is the thickness of the upper end of the package 2 (0.58 mm) + [lead frame (S) Plate thickness (0.1 mm) × 9] + [Thickness of movable mold 13 (0.68 mm) × 8] + Thickness of lower end portion of package 2 (0.35 mm) = 7.27 mm.
[0097]
The size of the package 2 (7.27 mm) is about 27% smaller than the case where nine TSOPs having a thickness of 1.1 mm are stacked without gaps (1.1 mm × 9 = 9.9 mm), for example. When TSOP is actually stacked, it is necessary to provide a gap of about 1 mm between the packages in consideration of heat dissipation, so that (1.1 mm × 9) + (1 mm × 8) = 18 mm. Therefore, the outer diameter of the package 2 is about 40% of the module in which TSOP is laminated.
[0098]
In this way, by forming the package 2 using the mold 10, the overlapping semiconductor chips (M ₀ ~ M ₈ ) Can be minimized, so that the thermal resistance of the package 2 can be reduced, whereby the temperature rise in the center of the package 2 can be suppressed.
[0099]
The DRAM module 1 according to the present embodiment further reduces the outer shape of the package 2 by further reducing the loop height of the wire 5, the thickness of the insulating tape 4, the thickness of the semiconductor chip (M), the thickness of the resin, and the like. The dimensions can be further reduced.
[0100]
For example, the loop height of the wire 5 is 0.15 mm to 0.12 mm, the thickness of the insulating tape 4 is 0.1 mm to 0.05 mm, and the thickness of the semiconductor chip (M) is 0.28 mm to 0.2 mm. When the lead frame (S) is 0.1 mm thick, the thickness per one lead frame (S) is 0.57 mm.
[0101]
Further, when the connection between the semiconductor chip (M) and the lead frame (S) is changed from the wire bonding method to the bump electrode method, it is not necessary to consider the loop height of the wire 5, so the bump height is set to 0. When the thickness is 0.03 mm, the thickness per lead frame (S) can be reduced to 0.45 mm.
[0102]
When the thickness per lead frame (S) is reduced in this way, the back surface of the upper semiconductor chip (M) and the wire 5 or the lead frame (S) of the lower semiconductor chip (M) are short-circuited. In order to prevent this, a thin insulating resin film may be coated on a part or the entire back surface of the semiconductor chip (M). When crosstalk noise between the lead frames (S) becomes a problem, a shield layer such as a gold foil may be provided on the back surface of the semiconductor chip (M).
[0103]
FIG. 22 shows a DRAM module 1 in which a package 2 having a reduced thickness per lead frame (S) is mounted on a mother socket 3 by the method described above. The dimensions in the height direction are greatly reduced as compared with the DRAM module 1 shown in FIGS.
[0104]
Next, an improved lead frame structure for further improving the yield and throughput of the molding process of the package 2 will be described.
[0105]
The lead frame (S ₁ ~ S ₉ ) Are laminated and molded together, if the epoxy resin used has a high viscosity, the superimposed lead frame (S ₁ ~ S ₉ ), It is difficult for the resin to flow into the gaps, and voids (voids) are easily generated in the gaps.
[0106]
As a countermeasure, a lead frame (S ₁ ~ S ₉ ). These lead frames (S ₁ ~ S ₉ ) Is the lead frame (S) shown in FIGS. ₁ ~ S ₉ ), Each has a individually designed lead pattern (pin arrangement), but one mold gate hole 14 is provided at each of both end portions in the long side direction. Further, a similar gate hole is provided in a corresponding portion of the insert mold.
[0107]
By providing these mold gate holes 14, a lead frame (S ₁ ~ S ₉ ) And are mounted on the insert mold 10 shown in FIGS. 17 to 21, a pair of gate lines penetrating in the vertical direction is formed inside the insert mold 10. Therefore, as shown in FIG. 32, when resin is injected from one gate 15, the injected resin quickly fills the cavity through one gate line 45. Then, non-uniform resin components such as voids generated inside the nested mold 10 flow out from the gate 16 on the opposite side through the other gate line 46. The lead frame (S ₁ ~ S ₉ ) Hole 44 is used as a guide pin hole when assembling the mold, thereby providing a lead frame (S ₁ ~ S ₉ ) Can be aligned with high accuracy.
[0108]
Thus, the lead frame (S ₁ ~ S ₉ ), The overlapping lead frames (S ₁ ~ S ₉ ) Can sufficiently flow into the gap, and a problem that a void is generated in the gap or the like can be prevented, so that the yield of the sealing process of the package 2 can be improved.
[0109]
Further, the lead frame (S ₁ ~ S ₉ ) Is provided with an index hole 17 having a different pattern for each lead frame (S) in the frame portion in the long side direction of each lead frame (S). Thus, the layer number identification of the lead frame (S) is automatically read during mass production, and the lead frame (S ₁ ~ S ₉ ) Can be easily determined whether or not they are stacked in the correct order, so that the yield and throughput of the sealing process of the package 2 can be improved.
[0110]
Further, the lead frame (S ₁ ~ S ₉ ) Are provided with index holes 18 having different patterns for each lead frame (S) at the end of the frame portion in the long side direction of each lead frame (S). By providing an index hole 18 at this position, the lead frame (S ₁ ~ S ₉ ) Can be easily read from the side.
[0111]
Further, the lead frame (S ₁ ~ S ₉ ) Is provided with a center hole 26 on the parting line of each lead frame (S). A lead frame (S ₁ ~ S ₉ ) Is fixed to the mold 10, the package 2 can be fixed when the movable mold 13 is extracted, so that the movable mold 13 can be easily extracted and the throughput of the sealing process of the package 2 is improved. Can be improved.
[0112]
Further, the lead frame (S ₁ ~ S ₉ ) Is provided with a half-etch line 19 in a part of each lead frame (S), the lead frame (S) can be easily cut. Thereby, after molding, unnecessary portions of the lead frame (S) exposed to the outside of the package 2 can be easily removed, so that the yield of the sealing process of the package 2 and the throughput can be improved.
[0113]
Next, the structure and manufacturing method of the mother socket 3 shown in FIG. 4 will be described.
[0114]
The mold used for forming the mother socket 3 is composed of a pair of left and right movable molds 21L and 21R movable in the horizontal direction shown in FIG. 33, and a central mold 22 movable in the vertical direction shown in FIG. The mother socket 3 has two mother socket lead frames 20 shown in FIG. 35. One is between the movable mold 21L and the central mold 22, and the other is the movable mold 22R and the central mold. And the insert hole mold of the opening 48 of the mother socket lead frame 20 and the guide pin 47 of the central mold 22 can be manufactured with high dimensional accuracy.
[0115]
The mother socket lead frame 20 is composed of 42 alloy, Kovar, etc., and its standard thickness is about 0.15 mm. The main body of the mother socket 3 is made of the same epoxy resin as that of the package 2. Alternatively, a high heat-resistant liquid crystal polymer can be used instead. 35, instead of using the mother socket lead frame 20 as a pair, the mother socket lead frame 23L (for the left) shown in FIG. 36 and the mother socket lead frame 23R (for the right) shown in FIG. As described above, the leads 7 connected to the data pins of the package 2 may be combined and used by cutting them in advance to a required length.
[0116]
The lead 7 of the mother socket 3 and the outer lead 6 of the package 2 can be collectively connected using a solder dip device. After the solder dipping, unnecessary solder can be easily removed by centrifugal separation at high speed, so that the lead 7 and the outer lead 6 can be connected with high throughput. Further, the lead 7 and the outer lead 6 can be connected by a reflow soldering method using a solder paste.
[0117]
Further, when a plurality of semiconductor chips (M) are collectively sealed in one package 2 as in the DRAM module 1 of this embodiment, the epoxy resin has a relatively large thermal expansion coefficient of about 10 ppm / ° C. Therefore, anisotropy may occur in the thermal expansion of the package 2 in the vertical direction and the horizontal direction. When anisotropy occurs in the thermal expansion of the package 2, thermal stress stress is applied to the connection portion between the outer lead 6 of the package 2 and the lead 7 of the mother socket 3, and the connection reliability of the connection portion is reduced.
[0118]
As a countermeasure, the lead 7 of the mother socket 3 is made of a material having a thermal expansion coefficient close to that of an epoxy resin, instead of being made of a low expansion coefficient material such as 42 alloy or Kovar. As such a material, for example, a copper alloy such as phosphor bronze is suitable. When such a material is used, since the lead 7 can follow the vertical expansion and contraction of the package 2, thermal stress stress applied to the connection portion between the outer lead 6 and the lead 7 can be reduced. The connection reliability of the connection portion can be improved. Further, since the copper alloy has a good thermal conductivity and a large heat dissipation effect, it can be used as a lead frame material for the package 2 as well as the mother socket 3.
[0119]
In addition, the lead frame (S shown in FIGS. 7 to 15 and FIGS. 23 to 31 is used. ₁ ~ S ₉ ), Each lead frame (S ₁ ~ S ₉ ) Is in a state in which all the leads are electrically connected through the metal tie bars, so that in this state, all the semiconductor chips (M) are normally operated immediately before the step of sealing the semiconductor chip (M). Testing, sorting, and aging to confirm whether or not it works can not be performed.
[0120]
As a countermeasure, a lead frame (S of metal tie bar structure as shown in FIGS. 7 to 15 and FIGS. 23 to 31 is used. ₁ ~ S ₉ 38), a tape dam type lead frame (T) in which an insulating tape 24 is joined on a mold line as shown in FIG. 38 is used. The insulating tape 24 is made of a polyimide resin or a high heat-resistant liquid crystal polymer, like the insulating tape 4. In addition to the method of forming the insulating tape 24 by adhesion, the insulating tape 24 can be formed by, for example, resin molding using an injection molding method.
[0121]
Nine tape dam type lead frames (T) used in the DRAM module 1 of this embodiment. ₁ ~ T ₉ ) Is shown in FIGS. These lead frames (T ₁ ~ T ₉ ), After joining the insulating tape 24, by cutting the metal part holding the leads, each lead can be brought into an electrically floating state. ) Testing, sorting and aging. These lead frames (T ₁ ~ T ₉ ) Is provided with a half-etch line 19 so that the metal part holding the lead can be easily cut.
[0122]
In this way, the tape dam type lead frame (T ₁ ~ T ₉ ), The semiconductor chip (M ₀ ~ M ₈ ) Lead frame (T ₁ ~ T ₉ ) And wire bonding, all semiconductor chips (M ₀ ~ M ₈ Therefore, it is possible to check whether or not the device operates normally, so that the manufacturing yield of the DRAM module 1 can be improved. These lead frames (T ₁ ~ T ₉ ) Can be used, the tie bar cutting step after sealing can be omitted.
[0123]
A lead frame (S) used in the DRAM module 1 of this embodiment. ₁ ~ S ₉ , T ₁ ~ T ₉ ), It is important that the dimensions of each other are aligned with high accuracy. When the dimensional accuracy is low, there is a problem that connection reliability is reduced due to a large stress applied to the connection portion between the lead 7 of the mother socket 3 and the lead frame 6 of the package 2.
[0124]
As a countermeasure, 9 lead frames (S ₁ ~ S ₉ Or T ₁ ~ T ₉ When these are manufactured as a single assembly lead frame, they are batch-etched in the same process. As a result, nine lead frames (S ₁ ~ S ₉ Or T ₁ ~ T ₉ ) Can be superimposed with high dimensional accuracy. 48 shows the nine lead frames (S) shown in FIGS. ₁ ~ S ₉ ) Is created as one set lead frame.
[0125]
As an example, the DRAM module 1 of this embodiment includes nine semiconductor chips (M ₀ ~ M ₈ However, it is needless to say that 10 or more semiconductor chips (M) can be collectively sealed. However, as the number of semiconductor chips (M) increases and the vertical dimension of the package 2 increases, the leads 7 of the mother socket 3 also become longer, and deformation thereof becomes a problem.
[0126]
In such a case, the lead frame (S ₀ ) (An example of a metal tie bar structure) and a lead frame (T ₀ ) As in (Example of insulation tie bar structure), a wire 5 is not connected to the semiconductor chip (M), and a dummy lead frame in which all pins are electrically floating is placed between the lead frames or on the top of the package 2 Place and seal.
[0127]
In this way, the outer lead of the dummy lead frame can be pulled out from the package 2 and connected to the lead 7 of the mother socket 3, so that the bonding strength between the lead 7 and the outer lead 6 is improved and the deformation of the lead 7 is prevented. can do. In addition, since the heat dissipation path of the package 2 is increased, the thermal resistance can be further reduced.
[0128]
(Example 2)
This embodiment is applied to a DRAM module having a multi-bit configuration with a wide data width such as x36 bits.
[0129]
In order to realize a DRAM module having a multi-bit configuration, for example, a DRAM module having a configuration of [4194304 words × 9 bits] is created by using nine 4-megabit DRAM chips configured as (1) [4194304 words × 1 bit]. Are mounted on a SIMM printed circuit board. (2) Four DRAM modules with a configuration of [4194304 words × 8 bits] using eight 4 megabit DRAM chips with a configuration of [4194304 words × 1 bit], and a 4 megabit DRAM chip with a configuration of [4194304 words × 1 bit] 4 sealed SOJs are mounted on a printed wiring board of SIMM. (3) Four DRAM modules with a configuration of [4194304 words × 8 bits] using eight 4 megabit DRAM chips with a configuration of [4194304 words × 1 bit], and 4 dedicated CAS / 2 RAS dedicated parity A method of mounting one SOJ encapsulating a 16 megabit DRAM chip having a configuration of [4194304 words × 4 bits] on a SIMM printed wiring board is conceivable.
[0130]
According to this method, for example, nine 16 megabit DRAMs having a configuration of [16777216 words × 1 bit] are stacked to produce a DRAM module as in the first embodiment, and four of these are mounted on a SIMM printed wiring board. As a result, a DRAM module having a configuration of [16777216 words × 36 bits] can be realized.
[0131]
However, in the above method, since a large number of DRAM modules must be mounted on the printed wiring board of the SIMM, the mounting density decreases. Therefore, for example, when realizing a DRAM module having a [4194304 word × 36 bits] configuration, nine 16 megabit DRAM chips having a [4194304 word × 4 bits] configuration are stacked to form a DRAM module as in the first embodiment. If possible, only one DRAM module needs to be mounted on the printed wiring board of the SIMM, so that the mounting density can be greatly improved.
[0132]
However, since a multi-bit DRAM module has many data lines, simply stacking semiconductor chips concentrates data pins in the same direction, making layout of the lead frame difficult. For example, in the case of a DRAM module having a × 36 bit configuration, when pins are pulled out in a dual in-line manner, the number of rows becomes 18 pins × 2 rows. However, the bonding pad region of the semiconductor chip corresponding to this, that is, the region where the four pads IO0 to IO3 shown in FIG. 6 are arranged is very small. Therefore, the lead routing becomes very long, and the size of the lead frame and thus the package for sealing the lead frame increases.
[0133]
In the following, a method for solving the above-described problems and realizing a small and high-performance DRAM module having a multi-bit configuration is formed by stacking 12 DRAM chips having a configuration of [4194304 words × 4 bits] and a configuration of the × 36 bits shown in FIG. A method for equivalently realizing the DRAM module will be described as an example. In FIG. 51, eight semiconductor chips (D ₀ ~ D ₇ ) Is a 16 megabit DRAM chip having a configuration of [4194304 words × 4 bits], four semiconductor chips (M ₀ ~ M _Three ) Is a 4 megabit DRAM chip having a configuration of [4194304 words × 1 bit].
[0134]
Here, in order to simplify the description, a 4 megabit DRAM chip (M4) configured as [4194304 words × 1 bit] shown in FIG. ₀ ~ M _Three In the following, a case where only one bit of a 16 megabit DRAM chip having a [4194304 word × 4 bits] configuration is used will be described. This will be described with reference to a 4 megabit DRAM chip having a [4194304 word × 1 bit] configuration (M ₀ ~ M _Three It is easy to change the layout.
[0135]
First, in this embodiment, when twelve 16 megabit DRAM chips having a configuration of [4194304 words × 4 bits] are used, the pins are arranged in a dual inline structure with two rows on one side. Also, in this embodiment, when lead frames having semiconductor chips are stacked and sealed in a package, some lead frames are inverted 180 degrees in a horizontal plane and mounted on the inverted lead frame. The pads of the semiconductor chip and the pads of the semiconductor chip mounted on the non-inverted lead frame are arranged in opposite directions around the inversion axis. Furthermore, in this embodiment, the 12 semiconductor chips are divided into two packages, and six of them are collectively sealed, and the two packages are stacked and mounted on the mother socket.
[0136]
FIG. 52 is a pin array of the mother socket 3 when adopting the dual in-line structure (an array viewed from above of a portion connected to the printed wiring board of SIMM). The pin arrangement is a 68-pin structure of 17 pins × 4 rows, and the pins 9 and 60 have an NC or no-pin structure. The pin pitch is 50 mil (1.27 mm) in both the long side direction and the short side direction of the mother socket 3.
[0137]
Vcc is arranged on pins 1, 17, 18, and 34, Vss is arranged on pins 35, 51, 52, and 68, respectively, and impedance reduction during power feeding is realized by parallel connection. The address pins have different correspondence between the inverting chip and the non-inverting chip, but the 10 bits (A0 to A9) that can be shared by the X address and the Y address are made to correspond one to one. The address pin A10 is arranged differently between the inversion chip and the non-inversion chip so that it can cope with the designation of the refresh address and the X address / Y address. In actual use, the address pin (A10) of the inverting chip and the address pin A10 of the non-inverting chip are connected by external connection or internal connection.
[0138]
That is, pin 7 is A4 (A9, inverted chip in parentheses), pin 8 is A5 (A0), pin 10 is A7 (A2), pin 11 is NC, pin 25 is A8 (A3), and pin 26 is A6 ( A1), pin 27 is (A10) and does not support non-inverted chip, pin 42 is A3 (A8), pin 43 is A1 (A6), pin 44 is A10 and does not support inverted chip, pin 58 is A9 (A4), The pin 59 is A0 (A5), the pin 61 is A2 (A7), and the pin 62 is NC. In the bar WE, the non-inverted chip is the pin 41 and the inverted chip is the pin 24. The bar RAS0, bar RAS2, bar CAS0, bar CAS1, bar CAS2, and bar CAS3 shown in FIG. 51 are a pin 28, a pin 45, a pin 6, a pin 29, a pin 57, and a pin 46, respectively. The remaining pins are data pins (DQ0 to DQ35).
[0139]
12 lead frames (L ₁ ~ L ₁₂ ) Layouts are shown in FIGS. In these drawings, the outline of the package 2, the semiconductor chip (M), the bonding pad 30, the wire 5, and the decoupling capacitor 31 are shown. In addition, illustration of the insulating tape which joins a semiconductor chip (M) and a lead frame (L) is abbreviate | omitted.
[0140]
As shown in FIG. 53, the external dimensions of the package 2 are 7.6 mm (short side) × 20.7 mm (long side). The outer leads 6 of the lead frame (L) are of two types, long and short, each having an opening 8 through which the lead 7 of the mother socket 3 passes. The width of the outer lead 6 drawn from one side of the package 2 and the outer lead 6 drawn from the other side is 400 mil (10.16 mm) for the short outer lead 6 around the opening 8 and 500 mil for the long outer lead 6. (12.7 mm). This dimension corresponds to the distance between the two rows of pins of the mother socket 3 shown in FIG. The width of each outer lead 6 is 0.55 mm and the diameter of the opening 8 is 0.25 mm × 0.25 mm. The pitch of the outer leads 6 is determined by the pin pitch (50 mil (1.27 mm)) of the mother socket 3. Narrow is 0.8mm.
[0141]
The 12 lead frames (L ₁ ~ L ₁₂ ) Of the lead frame (L ₁ ~ L _Three ) And the lead frame (L _Four ~ L ₆ ), And the lead frame (L ₇ ~ L ₉ ) And the lead frame (L _Ten ~ L ₁₂ ) Are arranged so that they are reversed 180 degrees from each other in the horizontal plane.
[0142]
Thus, the bonding pad 30 of the semiconductor chip (M) mounted on the inverted lead frame (L) and the pad bonding pad of the semiconductor chip (M) mounted on the non-inverted lead frame (L). 30 are arranged in directions opposite to each other about the inversion axis. As a result, the lead frame (L ₁ ~ L ₁₂ ) Data pins can be prevented from concentrating in one direction, leading to easy lead routing and lead frame (L ₁ ~ L ₁₂ ) Can be miniaturized.
[0143]
The 12 lead frames (L ₁ ~ L ₁₂ ), The lead frame (L) arranged in an inverted manner and the other lead frame (L) have lead patterns that are symmetrical with respect to the inversion axis. That is, the lead frame (L ₁ ) And lead frame (L _Four ), Lead frame (L ₂ ) And lead frame (L _Five ), Lead frame (L _Three ) And lead frame (L ₆ ), Lead frame (L ₇ ) And lead frame (L _Ten ) Lead frame (L ₈ ) And lead frame (L ₁₁ ) Lead frame (L ₉ ) And lead frame (L ₁₂ ) Have the same lead pattern, and one and the other are arranged in an inverted state.
[0144]
In this way, 12 lead frames (L ₁ ~ L ₁₂ ) Half of the varieties (6 varieties), so the lead frame (L ₁ ~ L ₁₂ ) Manufacturing cost can be reduced. In addition, since aging types can be reduced, a DRAM module can be provided at low cost.
[0145]
As shown in FIGS. 53 to 64, the 12 lead frames (L ₁ ~ L ₁₂ The semiconductor chip (M) mounted on each of the semiconductor chips (M) is arranged so that the center thereof is located on the data pin side of the lead frame (L) with respect to the center of the package 2. This center deviation is about 1.6 mm.
[0146]
In this way, the lead frame (L ₁ ~ L ₁₂ ) Even if there are many data pins, the layout area can be sufficiently secured, so that the lead can be easily routed and the lead frame (L ₁ ~ L ₁₂ ) Can be miniaturized.
[0147]
Further, as described above, when the semiconductor chip (M) is arranged shifted to the data pin side, an empty area is generated in the package 2 on the opposite side of the data pin. Therefore, the lead frame (L ₁ ~ L ₁₂ One end of the bus bar lead, which is a power supply (GND) pin, is extended to this empty region, and the decoupling capacitor 31 is mounted on the end. The dimensions of the decoupling capacitor 31 are about 1 mm × 0.5 mm and the thickness is about 0.5 mm.
[0148]
In this way, since the power supply impedance when power is supplied to the semiconductor chip (M) can be reduced, the DRAM module can be stably operated even when a large current is supplied. As a measure for reducing the power supply impedance during power feeding, the decoupling capacitor 31 is connected to a lead frame (L ₁ ~ L ₁₂ ) Instead of means for mounting at one end of each of them, it is mounted near or inside the mother socket 3, or one end of the bus bar lead is extended outside the package 2, and the decoupling capacitor 31 is mounted there May be. Further, when the size of the decoupling capacitor 31 is large, it may be mounted only on a part of the lead frame (L).
[0149]
In addition, as described above, when the semiconductor chip (M) is shifted and arranged on the data pin side, the resin flow becomes uneven when the package 2 is molded, and structural stress is generated inside the package 2. There is. In such a case, if the decoupling capacitor 31 as described above is disposed in the empty region generated on the opposite side of the data pin, the resin flow becomes uniform and structural stress inside the package 2 can be reduced. It becomes possible. Further, when the decoupling capacitor 31 is not arranged in this empty region, the same effect can be obtained by arranging a dummy chip or the like. Further, when a decoupling capacitor is formed on this dummy chip, both stress and power source impedance can be reduced.
[0150]
In addition, when the number of semiconductor chips (M) sealed in the package 2 is large, a plurality of signal pins of the same level may be generated due to restrictions in structural design and bonding pads of the semiconductor chip (M), or chip identification may be performed. Signal may not be generated. In such a case, the lead frame (L ₁ ~ L ₁₂ A dummy lead frame for the purpose of wiring connection in the package 2 may be inserted between the layers.
[0151]
Further, by inserting the dummy lead frame, the outer lead can be pulled out from the package 2 and connected to the lead 7 of the mother socket 3, so that the bonding strength between the lead 7 and the outer lead 6 is improved, and the lead 7 can be prevented. In addition, since the heat dissipation path of the package 2 is increased, the thermal resistance can be further reduced.
[0152]
FIG. 65 is a perspective view of the mother socket 3 of the present embodiment. FIG. 70 is a perspective view of a DRAM module having a [4194304 word × 36 bits] configuration in which two packages 2 are stacked on the mother socket 3. FIG. 69 is a perspective view showing a connection state between the lower package 2 and the mother socket 3.
[0153]
Of the two packages 2, the upper package 2 has six lead frames (L ₁ ~ L ₆ ), And the remaining six lead frames (L ₇ ~ L ₁₂ ) Is sealed. A part of the mother socket 3 is provided with recesses and projections and holes for mounting a radiation fin described later.
[0154]
Two rows of data pins and CAS pins (pins 19 to 23, pins 29 to 33, pins 36 to 40, and pins 46 to 50 shown in FIG. 52) inside the mother socket 3 are only in the lower package 2. Connected. The rear surface side of the mother socket 3 has the pin arrangement shown in FIG. 52, and the upper surface side has the pin arrangement shown in FIG.
[0155]
In order to change the pin arrangement between the back side and the top side of the mother socket 3, the lead frame for mother socket shown in FIGS. 67 and 68 is used. FIG. 67 is a lead frame for two inner rows facing each other, and FIG. 68 is a lead frame for two outer rows facing each other. Both ends of these lead frames are power supply pins (Vcc), and lead frames (L ₁ ~ L ₆ , L ₇ ~ L ₁₂ In order to reduce the power source impedance of), the number of pins is increased by branching into two at the top.
[0156]
The data pins and CAS pins of each package 2 are arranged in a staggered manner in the inner row and the outer row so that the inner 0.8 mm pitch and the outer 0.8 mm pitch can be alternately arranged with a half pitch of 0.4 mm. Therefore, dense mounting is possible. This is because the data pins and CAS pins of the lower package 2 terminate in the lower package 2 and do not extend to the upper package 2. Data pins and CAS pins of the upper package 2 are connected to leads 7 in the outer row of the mother socket 3 through outer leads 6 having a pitch of 500 mil.
[0157]
FIG. 71 shows an example in which radiating fins 41 are attached around the package 2 in order to further reduce the thermal resistance of the DRAM module 40 having the [4194304 words × 36 bits] configuration. FIG. 72 shows the heat dissipating fins 41 cut by a quarter in order to make the internal state easy to see.
[0158]
As shown in FIG. 72, the heat radiating fin 41 has a heat conductive plate constituting a part thereof inserted in a gap between the upper and lower packages 2 and 2. The heat radiating fins 41 are divided into two in the long side direction of the package 2 so as to be able to come into contact with the packages 2 and 2 and the mother socket 3 stacked one above the other in a wide area.
[0159]
73 is a side view of the radiating fin 41, and FIG. 74 is a perspective view of the radiating fin 41. As shown in FIG. As shown in the figure, the bottom surface portion (the portion indicated by arrow A in FIG. 73) of the radiating fin 41 in contact with the mother socket 3 is processed into a bowl shape in order to prevent the mother socket 3 from falling off. When the radiating fins 41 are attached around the package 2, it is necessary to fill the interface with silicone grease or silicone rubber serving as a heat transfer medium.
[0160]
As a method of mounting the heat radiation fin 41, in addition to the method of inserting from the lateral direction of the package 2 as shown in FIGS. 73 and 74, for example, as shown in FIG. 75, the heat radiation fins 41a to 41d divided in the vertical direction. There is also a method of stacking on the package 2. The structure (FIGS. 73 and 74) in which the radiation fins 41 are inserted from the lateral direction can be attached after the leads 7 of the mother socket 3 and the outer leads 6 of the package 2 are connected by soldering or the like. When stacking the divided radiation fins 41a to 41d, the uppermost radiation fin 41a may be attached in the final process of the assembly process.
[0161]
In this embodiment, the case where the present invention is applied to a DRAM module having a [4194304 word × 36 bits] configuration has been described. However, the present embodiment also applies to a DRAM module having a [8388608 word × 36 bits] configuration as shown in FIG. The two RAS packages 2 are combined in a total of four at the bottom and two at the top, and the RAS pins are separated for each package 2 so that the pins 11 and 62 shown in FIG. 52 become RAS3 and RAS1, respectively. Therefore, it can be easily realized.
[0162]
Further, in the mother socket 3 of this embodiment, the inner two opposing rows of data pins and CAS pin leads 7 are shortened and connected only to the lower package 2, but there is sufficient space for the outer leads 6 of the package 2. When there is no possibility that the lead 7 of the mother socket 3 contacts the unnecessary lead 6, the lead 7 of the mother socket 3 does not contact between the outer leads 6 of the package 2 even in a half pitch layout. Can be connected. That is, the lower package 2 and the upper package 2 can be interchanged. At this time, the data pin and CAS pin lead 7 connected to the upper package 2 are shortened.
[0163]
(Example 3)
This embodiment is applied to a DRAM module having a J lead terminal structure.
[0164]
In order to realize a DRAM module having a J lead terminal structure, for example, a package of [16777216 words × 4 bits] configured by stacking four 16 megabit DRAM chips in the vertical direction [16777216 words × 1 bit] is used. Create 2. As shown in FIG. 77, the DRAM chips are electrically connected by leads 7 arranged so as to intersect with the outer leads 6 drawn out from the side surface of the package 2 in the horizontal direction. Is formed into a J shape.
[0165]
In this way, since the lead 7 can be directly connected to the printed wiring board of the SIMM, the mother socket 3 as shown in FIG. 4 is not necessary, and the cost of the DRAM module and the external dimensions are reduced by reducing the number of components. And downsizing can be realized.
[0166]
The lead 7 may be composed of a normal lead frame having a lead pattern formed by pressing or etching, but may be composed of a wire. For example, when the diameter of the lead insertion hole 8 provided in the outer lead 6 is 0.42 mm × 0.42 mm square, it is formed on the surface of a metal wire made of phosphor bronze, beryllium copper, kovar, etc. having a diameter of 0.32 mmφ. Using a wire with an outer diameter of 0.41 mmφ with a solder plating with a melting point higher than eutectic solder (Sn60%, Pb40%), such as Sn90%, Pb10%, Sn10%, Pb90%, etc. To do.
[0167]
When the lead 7 is composed of a wire, the connection between the wire (lead 7) and the outer lead 6 is different from the method described in the first embodiment, and after inserting the wire into the opening 8 of the outer lead 6, the wire is Heat treatment is performed to melt the solder plating on the surface, and the wire and the outer lead 6 are solder-connected in a self-aligning manner. The heat treatment of the wire is performed by, for example, a method of blowing a high-temperature nitrogen gas in an inert gas atmosphere, irradiating with a light beam or a laser beam, or heating in a reflow furnace of an outside air shielding type.
[0168]
The self-aligned solder connection method described above is less likely to cause a solder bridge between the outer leads 6 and 6 because the amount of solder attached to the wire (lead 7) is smaller than the conventional jet solder dip method. There is an effect. In particular, a structure in which a large number of leads 7 and outer leads 6 intersect in a matrix shape like the DRAM module of the present invention has a large surface area on the same principle as a solder sucking wire, so that it is like a parallel lead of a QFP package. In addition, the solder removability is so poor as to be incomparable with a structure capable of making the solder removal direction uniform, and it is very difficult to remove excess solder. Therefore, according to the above-described self-aligned solder connection method, the solder bridge failure of the DRAM module of the present invention can be extremely effectively reduced.
[0169]
Further, if a metal burr is formed on the outer lead 6 in the press molding process or the tie bar cutting process, the molten solder is caught on the burr and becomes the core of the solder bridge, and the bridge occurrence rate increases rapidly. Therefore, the self-aligned solder connection method with less excess solder is also effective in improving the yield of the solder connection process from this point.
[0170]
Furthermore, instead of eutectic solder (Sn 60%, Pb 40%) that melts at a low temperature of about 180 ° C., Sn 90%, Pb 10% solder that melts at a high temperature of 200 ° C. or higher, or Sn 10%, Pb 90% solder is plated. As a result, when the SOJ structure lead 7 is reflow soldered to the printed wiring board of SIMM using eutectic solder, it is possible to prevent the solder at the connection portion between the lead 7 and the outer lead 6 from being remelted. .
[0171]
If the solder at the connection portion between the wire (lead 7) and the outer lead 6 is in a molten state, the connection portion is displaced due to some external force or the weight of the package 2, and the package 2 is lowered. Since the solder flows in the connection portion of the outer lead 6 or a solder recrystallized region having a non-uniform composition is formed in the solder of the connection portion, the connection reliability of the solder is remarkably lowered.
[0172]
This is because if the solder amount of the connection portion cannot be made constant, the solder fillet shape cannot be controlled, and as a result, the solder stress due to the thermal cycle increases, and the progress of cracks inside the solder is promoted, This is because the reliability decreases. In particular, when the amount of solder is large, the thermal expansion / contraction stress of the solder due to the thermal cycle also increases, so that the amount of plastic strain increases and the progress of solder cracks is accelerated.
[0173]
However, the wire (lead 7) subjected to the high melting point solder plating process and the outer lead 6 are solder-connected at a reflow temperature of 200 ° C. or more, and the temperature of the reflow furnace when mounting the DRAM module on the SIMM printed circuit board is set. When the melting point is lower than the melting point of the high melting point solder (for example, 200 ° C. or lower), only the solder at the connection portion between the lead 7 and the printed wiring board is melted in the vicinity of the lead 7. can do.
[0174]
In addition, the self-aligned solder connection method described above makes it easier to control the amount of solder at the connection portion than the solder dipping method. This is because, in the case of the self-aligning solder connection method, the solder of the lead 7 in the middle portion between the upper and lower outer leads 6 and 6 is supplied to the upper and lower outer leads 6 and 6 almost half by half. In other words, in the case of the solder dip method, the amount of solder is likely to vary depending on the surface state of the metal constituting the wire, while in the case of the self-aligned solder connection method, a constant controlled amount of solder is always applied. There is a feature that it can be supplied.
[0175]
If the diameter of the lead 7 is made smaller than the diameter of the opening 8 (or the width of a groove described later) in order to facilitate the operation of inserting the lead 7 into the opening 8 of the outer lead 6, the lead 7 is inserted into the opening 8. If it is just inserted, the lead 7 may be displaced by some external force before solder reflow. As a countermeasure against this, as shown in FIG. 78, flat portions 50 and 51 are provided in a part of the lead 7 with a press and the diameter of the lead 7 is partially increased to prevent the lead 7 from being displaced or disconnected. it can. Alternatively, the diameter of a part of the lead 7 may be expanded by pressing, and the lead 7 may be inserted into the opening 8 by caulking.
[0176]
Further, the lead 7 can be inserted into the opening 8 by a connector method using the pressing of metals. In this way, since the outer lead 6 and the lead 7 can be connected without using solder, an open defect between the outer lead 6 and the lead 7 due to a solder crack can be prevented.
[0177]
The above connector method that does not require the use of solder can be applied to the case where the outer lead 6 and the lead 7 are connected by a crimping cable method, which will be described later, but the assembly man-hours can be reduced by eliminating the solder reflow process. Can do. Further, if the solder connection method and the connector method are used in combination, double reliability can be obtained for the open failure of the outer lead 6 and the lead 7.
[0178]
FIG. 79 shows an example in which the above-described method in which the flat portions 50 and 51 are provided on a part of the lead 7 is applied to the connecting portion between the lead 7 and the printed wiring board. In this case, the width of the J-bend portion of the lead 7 can be freely changed by controlling the width of the flat portion 52. Further, providing the flat portion 52 at the lower end portion of the lead 7 has an advantage that J-bend molding becomes easier as compared with the case of a columnar shape or a prismatic shape. Further, when the flat portion 52 is formed by press working, there is an advantage that the strength of the J-bend portion is increased by work hardening of the metal.
[0179]
Further, depending on the shape of the opening 8 of the outer lead 6, it is possible to use a prismatic wire instead of a circular cross section. However, in comparison with a circular wire, the prismatic wire has a problem that it is difficult to connect the outer lead 6 and the lead 7 when the cross section is rotated by an axial twist.
[0180]
In general, a circular cross section is advantageous for the twist of the wire, but a cross section of the prism is advantageous for the torsional rigidity of the connection portion (J bend portion) to the printed wiring board. Therefore, when a prismatic wire is used, the shape of the opening 8 of the outer lead 6 is a square, thereby preventing the wire from freely rotating and preventing the J bend portion of the lead 7 from rotating. As a result, even if the temperature inside the furnace becomes too high in the reflow process when mounting the DRAM module on the printed circuit board, the high melting point solder at the connecting portion between the outer lead 6 and the lead 7 is remelted. Since the rotation of the J bend portion 7 can be prevented, it is possible to prevent a defect in which the lead 7 is misaligned.
[0181]
In order to prevent a problem that the high melting point solder at the connecting portion between the outer lead 6 and the lead 7 is remelted or an external force is applied to the connecting portion and the pitch of the leads 7 is not uniform, A depression 54 as shown in FIG. 80 may be provided. A method for forming the recess 54 will be described with reference to FIGS.
[0182]
In the case of a normal SOJ type single layer package, the package 53 is released along the direction perpendicular to the main surface of the mold (lower mold) 55 as shown in FIG. Therefore, the recess 54 on the bottom surface of the package 53 is formed at a location away from the side surface s of the package 53 as shown in FIG.
[0183]
On the other hand, in this embodiment, a movable mold 56 similar to the movable mold 13 described in the first embodiment is used. As shown in FIG. 82 (a), the movable mold 56 is divided into two along a direction parallel to the bottom surface of the package 2, so that the depression 54 on the bottom surface of the package 2 is shown in FIG. 82 (b). In this way, the package 2 is formed to reach the side surface s.
[0184]
According to the molding method using the movable mold 56 as described above, not only a large number of semiconductor chips stacked in the vertical direction can be molded at a time, but also as shown in FIG. Since the upper surface of the pair of movable molds 56 forms the lower surface of the upper package 2 and the lower surface forms the upper surface of the lower package 2, a plurality of single layer packages such as SOJ are stacked in the vertical direction. The throughput of the molding process can be greatly improved.
[0185]
In addition, according to the molding method in which multiple packages are stacked in the vertical direction, multiple cavities are taken and the cavities are connected by a gate with a very short distance compared to the conventional molding method in which multiple packages are taken in the horizontal direction. can do. Therefore, compared with the conventional molding method, the amount of useless resin remaining inside the gate can be reduced, and more packages can be obtained from mini-tablets of the same size.
[0186]
The movable mold 56 can be variously modified in accordance with the molding work efficiency, the frictional force at the time of mold release, the gate cut procedure, and the like.
[0187]
The movable mold 56 shown in FIG. 83 (a) has the same structure as the movable mold 56 shown in FIG. 82 (a), and has molding patterns on both upper and lower surfaces. The movable molds 56a and 56b shown in FIG. 8B are obtained by dividing the movable mold 56 of FIG. 82A into two in the vertical direction. The movable molds 56a and 56b are divided into an upper surface of the movable mold 56a and a lower surface of the movable mold 56b. Each has a molding pattern. The movable molds 56a, 56b, and 56c shown in FIG. 8 (c) are obtained by dividing the movable mold 56 of FIG. 82 (a) into three parts, and are respectively provided on the upper surface of the movable mold 56a and the lower surface of the movable mold 56b. A molding pattern is provided.
[0188]
83 (d) is a plan view of the movable mold 56a of FIG. 83 (b) as viewed from above, and FIG. 83 (e) is a plan view of the movable mold 56b of FIG. is there. Reference numeral 57 in the figure denotes a cavity for molding the lower surface of the package, 58 denotes a cavity for molding the lower surface of the package, 59 denotes a guide pin hole for aligning the lead frame on which the semiconductor chip is mounted with the movable molds 56a and 56b, 60 is a guide pin hole for aligning the movable molds 56a and 56b, 61 is a gate hole for allowing the resin to flow in the laminating direction, and 62 is an air vent function for ensuring the uniformity of the resin. This is a dummy gate hole for resin outflow. The movable molds 56a, 56b, and 56c are each composed of a pair of left and right, but only one side is shown in the drawing.
[0189]
In the movable mold 56 shown in FIG. 83 (a), the package is brought into close contact with both upper and lower surfaces, so that the frictional force at the time of mold release increases. On the other hand, the movable molds 56a and 56b shown in FIG. 5B are in close contact with each other, so that the frictional force at the time of mold release is reduced and the package can be easily released. it can.
[0190]
83 (a) is difficult to cut the resin in the gate holes 61 and 62 connected to the upper and lower packages at the time of mold release, the movable mold 56 shown in FIG. 83 (b). The molds 56a and 56b have an advantage that the mold release workability is improved because the resin in the gate holes 61 and 62 can be cracked and cut at the interface (66) between them.
[0191]
The movable molds 56a and 56b are each composed of a pair of left and right (the same applies to the movable molds 56 and 56c). Therefore, if the arrangement of the guide pin holes 59 and 60 and the gate holes 61 and 62 is made symmetrical, the left and right movable molds 56a and 56b can be made compatible with each other. Workability at the time of laminating a plurality of sets in the vertical direction is improved.
[0192]
However, in order to keep the total stack thickness when a plurality of sets of the movable molds 56a and 56b are stacked in the vertical direction, it is preferable that the left and right movable molds are not compatible. The reason is that if the total stack thickness of the left movable mold and the total stack thickness of the right movable mold are not precisely matched when creating the mold, the mold clamping force of the mold will be This is because it becomes uneven between the molds.
[0193]
Even if the stacking order in the vertical direction is changed between the left movable molds or between the right movable molds, the total stacking thickness does not change, so that the clamping force is kept constant. However, if the left and right movable molds are made compatible with each other, and the left and right molds are mixed together and stacked, the height of the left and right movable molds varies. Statistically, the variation is about a value obtained by multiplying the variation in thickness of one movable mold by the square root of the number of layers.
[0194]
As an example, a case will be described in which four module-type packages in which four semiconductor chips are stacked are taken up and down using a mold having a thickness tolerance of ± 5 μm or less by high-precision polishing. .
[0195]
In this case, in order to mold one stacked module type package, a total of five molds including three (movable) molds inserted into the gap between the four semiconductor chips and the upper and lower molds are combined. Therefore, a total of 20 molds are required in the case of 4 pieces. Therefore, the statistical variation in height is a value obtained by multiplying the tolerance of thickness (± 5 μm) per die by the square root of the number of dies (= 20), that is, ± 22 μm.
[0196]
In addition, when the thickness of the lead frame on which the semiconductor chip is mounted is calculated to be 0.125 μm and the thickness of one die is 0.65 mm, the total number of lead frames is 4 for each package and 4 Since there are 16 sheets, the total lamination thickness of the mold is (0.125 × 16) + (0.65 × 20) = 15 mm. Accordingly, the height variation (± 22 μm) with respect to the total thickness of the mold (15 mm), that is, the strain (22 μm / 15 mm = 1.46 × 10). ^-3 ) And Young's modulus of metal (iron) constituting the mold (2 × 10 ^Four kg / mm ² ), A load of 29 kg per unit square millimeter is obtained.
[0197]
Therefore, the pressure receiving area of the mold is 40mm x 20mm = 800mm ² Even if it is relatively small, the difference in clamping force generated between the left and right molds reaches 29 × 800 = 23.2 tons. That is, a clamping force of 23 tons or more is applied to one of the left and right molds, while the other has a phenomenon of no load. From the above, the left and right molds should not be compatible. If interchangeability is not provided, a substantially uniform clamping force can be applied to the left and right molds.
[0198]
When a plurality of sets of the movable molds 56a and 56b are stacked in the vertical direction, the mold resin flows in the vertical direction through the gate holes 61 shown in FIGS. 83 (d) and 83 (e). The other gate hole 62 functions as an air vent, and is a dummy gate that discharges air and non-uniform resin at the tip of the fluid resin to the outside of the cavities 57 and 58. This dummy gate is not necessarily required depending on how the air vent is designed or when a highly uniform resin is used, and can be omitted.
[0199]
Air vent here is a gap of about 1/100 to 3 / 100mm used in normal mold design, and it has the feature that air can enter and exit but resin cannot enter and exit. . On the other hand, the dummy gate (gate hole 62) discharges unnecessary air in the cavities 57 and 58 at the initial stage of the mold, and then the tip of the fluid resin flows into the resin in the cavities 57 and 58. Has the function to flow in evenly. The air vent of the dummy gate (gate hole 62) has a larger opening than the above-described air vent used in a normal mold design, and therefore, unnecessary air in the cavities 57 and 58 is efficiently discharged. Can do.
[0200]
The planar shape of the gate holes 61 and 62 has a predetermined release angle (θ) with respect to the parting line PL as shown in FIG. 83 (f). The release angle (θ) is about 0 <θ <30 °. For example, in an experiment in which θ was set to 15 °, it was confirmed that the mold release property and the space factor were excellent with respect to the thermosetting resin. If the release angle (θ) is 30 ° or more, the gate area becomes large, and the space factor decreases. Further, when θ = 0, the releasability is poor, and resin residue tends to occur in the gate holes 61 and 62. When this resin residue is generated, the gate cross-sectional shape changes during the next molding, and the molding conditions fluctuate, so that uniform molding cannot be performed.
[0201]
The gate hole 61 and the gate hole 62 do not have to be the same size. Since the gate hole 61 is a resin inflow port, if the diameter thereof is reduced, the shear heat generation of the resin increases and the fluidity of the resin increases. Further, if the diameter of the gate hole 62 which is a dummy gate is increased, the air resistance is reduced, so that unnecessary air in the cavities 57 and 58 can be easily discharged.
[0202]
As shown in FIG. 83 (f), the basic shape of the gate holes 61 and 62 is a circular shape in which the radius is r and the parting line PL is in contact with the parting line PL at an angle of (90 ° −θ). It is good to do. At this time, the center of the circle is not necessarily located on the parting line PL. In addition, when the radius r is increased and the center of the circle is placed outside the parting line PL, a part of the arc becomes the release angle (θ), and is shared with the connection portion 67 of (90 ° −θ). can do.
[0203]
The cross sections along the line XX ′ of the gate holes 61 and 62 shown in FIG. 84A can be configured in various shapes (1) to (4) as shown in FIG.
[0204]
The shape (1) is the simplest vertical shape. When wire electric discharge machining and polishing are used in the mold production, the production of the gate holes 61 and 62 is facilitated, so that the production cost of the mold can be reduced. .
[0205]
The procedure for creating the movable mold is the same as that for the movable mold shown in FIGS. 21 and 83. First, as shown in FIG. 85 (a), a mold block is formed by wire electric discharge machining, drilling, polishing, or the like. A block 68 is created from the material. At this time, if the guide pin holes 59 and 60 are also formed at the same time, the alignment accuracy when the movable molds 56a and 56b are stacked is improved.
[0206]
Next, as shown in FIG. 85B, a thin plate-shaped movable mold 69 is obtained by thinly slicing the block 68 according to the cut line 70 using a discharge wire cutting method or the like. At this time, since the gate holes 61 and 62 are extended with respect to the wall surface of the block 68, the shape (1) shown in FIG. 84B is directly obtained.
[0207]
The movable mold 69 shown in FIG. 85 (b) is polished by a plane polishing machine after wire cutting in order to make its thickness highly accurate. By moving the movable mold 69 having the same thickness into the polishing machine at the same time and processing both, the relative variation can be greatly reduced, so that the thickness of the movable mold 69 can be aligned with extremely high accuracy. .
[0208]
By making the cross-sections of the gate holes 61 and 62 into the shapes (2) to (4) in FIG. 85B, the resin remaining in the gate holes 61 and 62 can be easily cut after the package is formed. . In these shapes (2) to (4), since the inner diameter is changed in a part of the cross section, it is possible to cause stress concentration in the resin in the gate holes 61 and 62.
[0209]
Shape (2) is a simple conical shape, and shape (3) is a stepped shape. In this shape (3), the change in stress is large because the change in diameter is steep, so that the resin is easily cut. Shape (4) is an example in which the cross section is indefinite. In this shape (4), since the upper and lower edge portions of the gate holes 61 and 62 are acute, stress concentration can be generated in the resin at the edge portions.
[0210]
The movable molds 56a and 56b shown in FIG. 83 (b) and the gate holes 61 and 62 of the movable molds 56a, 56b and 56c shown in FIG. 83 (c) are shaped as shown in FIG. Any of (4) can be adopted. When the shape (2) is adopted, if the smaller diameter is disposed on the package side, excess resin is less likely to remain on the package side, so workability is improved. In the case of the movable mold 56 shown in FIG. 83A, the same effect as described above can be obtained by adopting the shape (4).
[0211]
FIG. 86 is a configuration diagram of a mold for taking two module-type packages in which four semiconductor chips 79 are stacked and sealed together in the stacking direction.
[0212]
For example, a semiconductor chip 79 in which a 16 megabit DRAM is formed is bonded to a lead frame 78 via an insulating tape 4 made of a thermoplastic resin, and four pieces connected by wires 5 are laminated in two stages.
[0213]
80A is the cavity of the upper package, and 80B is the cavity of the lower package. Each of the cavities 80A and 80B maintains a constant interlayer distance between a mold 71 that molds the upper part of the package, a mold 72 that molds the lower part of the package, and the semiconductor chip 79, and the bottom surface of the semiconductor chip 79 between each layer and the wire 5 It consists of a thin plate-shaped movable mold 69 that controls the distance between them.
[0214]
FIG. 86 is a view of the mold as seen from the Y direction of the four-layer module type package, and the movable mold 13 according to the first embodiment in which the guide pin holes 59 and 60 are formed corresponds to the movable mold 69. . Further, the structure in which the gate 15 of the upper mold 11 shown in FIG. 19 is vertical is a continuous area of the molds 73 and 74 and the movable mold 56b, and the continuous area of the movable mold 56a and the mold 75 is illustrated. This corresponds to the lower mold 12 shown in FIG. The reason why each of the upper mold 11 and the lower mold 12 is constituted by a plurality of assembled molds is to improve the efficiency of the mold release work after molding and reduce the mold release damage to the package, which will be described in detail later.
[0215]
The flowable resin at the time of molding flows from the gate hole 76 that is tapered in the vertical direction, and flows into the upper cavity 80A through the gate hole 61 of the thin plate-shaped movable mold 56b in contact with the mold 74. Then, while filling the cavity 80A, it reaches the cavity 80B through the gate holes 61 of the thin plate-shaped movable molds 56a and 56b disposed at the boundary between the cavity 80A and the lower cavity 80B. Thereafter, the tip of the fluid resin passes through the movable mold 56a gate hole 62 (dummy gate indicated by the broken line in FIG. 86) on the bottom surface of the cavity 80B, and further passes through the gate hole 76 provided in the mold 75. The resin reaches the dummy cavity 77 where the resin is stored, and the molding is completed.
[0216]
The alignment of each layer of the four stacked module type package shown in FIG. 86 is determined by the movable mold 69, the mold 71, and the movable molds 56a and 56b in the stacking direction (z direction). It is determined by extending the guide pins from the uppermost mold 73 to the lowermost mold 75 in the holes 59 and 60. This is because the guide pins polished with high precision are passed through the laminated regions (molds 73 and 74, cavities 80A and 80B, mold 75), so that each mold and the lead frame 78 are on the XY plane. This is because translation and free rotation are lost and the positional relationship is uniquely determined.
[0217]
The gate hole 76 and the dummy cavity 77 of the mold 75 have a structure as shown in FIG. 87 (b), and are formed together with the guide pin holes 59 and 60. 87A is a plan view of FIG. 87B, and FIG. 87C is a cross-sectional view in the YY ′ direction of FIG. 87B. Each of the gate hole 76 and the dummy cavity 77 is provided with a taper angle in order to improve releasability. Further, as shown in FIGS. 5A to 5C, an air vent may be formed by the shallow groove 55, and unnecessary air may be discharged. Further, in order to release the resin in the dummy cavity 77, it is easy to incorporate an ejector pin structure that is provided in a cull portion of a normal mold.
[0218]
The positional relationship between the gate hole 76 of the mold 75 and the dummy gate (gate hole 62) of the thin plate-shaped movable mold 56a in the stacked portion is as shown in FIG. 88 in a plan view. Based on the movable mold 13 of the first embodiment, a resin inflow gate hole 61 and a resin outflow gate hole 62 are provided, and a guide pin hole 60, a lead frame 78, and an alignment guide pin hole 59 of the mold are clearly shown. A description will be given using the movable mold 69.
[0219]
The gate hole 62 of the movable mold 69 and the gate hole 76 of the mold 75 are connected and have a positional relationship as shown in FIG. The movable mold 69 that forms one layer between the left and right two layers has a resin inflow gate hole 61 and a resin outflow gate hole 62 formed on a parting line PL along the Y axis in the figure. Yes. As shown in FIG. 86, the thin plate-like movable mold 56a is in contact with the mold 75, but the relative positional relationship is shown by using the movable mold 69 between the layers defining the package outer shape. In order to improve the resin flow between the layers of the semiconductor chip 79, the movable mold 69 between the layers has a slit gate or a pin gate between the gate hole 61 and the package cavity 81 as shown in FIG. 88 (b). You may connect by.
[0220]
The slit here is a slit gate 82 as shown in FIG. The slit gate 82 is also connected in the stacking direction by the stacked movable molds 69 to form the gate lines 45 and 46 shown in FIG. The feature of the slit gate 82 is that the gate opening area to the cavity 81 can be made large, so that the flow resistance of the resin can be reduced, and the gate shape is z like the manufacturing method described in FIG. Since it is stretched in the direction, it is easy to process.
[0221]
The pin gate has a structure as shown in FIG. A pin gate portion denoted by reference numeral 83 is an inlet to the cavity 81, and an isolated gate region is formed by the region 84 of the movable mold 69 of each layer. The features of the pin gate 83 are that the gate lines 45 and 46 can be easily removed as compared with the slit gate 82, and the resin outflow resistance in the XY plane direction during molding can be controlled widely.
[0222]
The vertical plane of the region 84 of the pin gate 83 is on the parting line PL, and the vicinity of the gate of the cavity 81 in the stacking direction in a pair of left and right is intermittently closed for each layer. Further, the shape of the gate tip from the slit gate 82 to the pin gate 83 is continuous and can be used together depending on the molding conditions. In particular, the resin inflow gate hole 61 and the resin outflow gate hole 62 can be selectively used according to the balance. Furthermore, if the resin flow is very good, only the resin flow in the z direction in the cavity 81 may be sufficient. In this case, the gate may be omitted as necessary. Also, the movable mold 56 shown in FIG. 82 and the gate holes 61 and 62 of the movable molds 56a, 56b, and 56c shown in FIG. 83 may move into the cavity. In this case, it is necessary to install the gate holes 61 and 62 in a place where the gate cut surface does not affect the surface appearance of the package and the semiconductor chip.
[0223]
The mold having the gate hole 76 in the z direction shown in FIG. 86 can use the clamping force very effectively, unlike the conventional mold that draws the gate and runner on the XY plane.
[0224]
An example of a molding apparatus having a gate in the vertical direction is shown in FIG. One of the greatest features of this molding apparatus is that almost all the mold clamping force f of the mold system is loaded in series to the mold 75 via the molds 73 and 74, the movable mold 56b, and the mold 72, There is no loss of power. Therefore, if the pressure receiving area of the laminated mold package is reduced, a very large clamping force per unit area can be obtained.
[0225]
This is because the mold can be miniaturized to the order of several tens of square centimeters instead of the plane size as large as several hundred square centimeters as in the conventional mold. For this reason, the area | region which concentrates the narrow dam-shaped mold clamping force near the cavity boundary essential to the conventional metal mold | die can also be abbreviate | omitted. This facilitates high-precision flattening of the mold and enables countermeasures against mold deterioration due to deformation of the dam-shaped region.
[0226]
A mold 88 shown in FIG. 90 is a temperature-controlled fixed mold for pressing the laminated mold shown in FIG. 86 from above, and includes a transfer mold pot 85a and a plunger mechanism 85b. . The mini tablet 86, which is a mold resin, is put into the pot 85a and injected by the plunger 85b. The cull portion 87 is formed in the cavity of the fixed mold 88 to improve the mold release property of the resin filled in the cull portion 87 after molding.
[0227]
That is, if the resin of the cull portion 87 adheres to the fixed mold 88 when the fixed mold 88 and the movable mold 89 are opened, the plunger 85b is lowered in synchronization with the mold opening to act as an ejector. To do. The fixed mold 88 and the movable mold 89 can be slid up and down across an O-ring 90 that prevents air leakage, and when the number of lamination mold molds shown in FIG. 86 is changed, It is possible to follow variations in the height of different laminated mold dies with a wide z-direction stroke. This means that a plurality of dies having different numbers of stacks can be continuously operated in the same apparatus. The system shown in FIG. 90 is made possible by raising the movable mold 89 until the loaded mold reaches a set clamping force.
[0228]
Further, unnecessary air discharged when the plunger 85b is lowered is preliminarily depressurized from the evacuation hole 91 after the mini tablet 86 is inserted into the pot 85a and the plunger 85b is inserted into the pot 85a. It has a structure that makes the air vent work effectively. Therefore, inflow of other air is prevented by the O-ring 90. When evacuation is not particularly necessary, the evacuation hole 91 may be opened to the atmosphere.
[0229]
FIG. 90 shows that the dummy gate and dummy cavity 77 can be formed not only in the mold 75 but also in the mold 74. This is to effectively discharge the air trap region during molding to the dummy cavity. The thin plate-shaped mold of the laminated mold portion (see FIG. 86) in FIG. 90 is shown in a simplified manner.
[0230]
The purpose of dividing the upper die into 73 and 74 in the laminated die of FIG. 90 is to prevent mechanical damage to the laminated package at the time of releasing after molding. Further, this is because the conical gate hole 76 in the dies 73, 74 is cut by a parting line (HPL2 in FIG. 86) on the XY plane. If the molds 73 and 74 are integrated, the resin in the gate hole 76 does not have an ejector structure inside, so that it becomes difficult to release the mold.
[0231]
This operation will be described with reference to FIG. As the guide pin 59a corresponding to the guide pin hole 59 and the guide pin 60a corresponding to the guide pin hole 60, a laminated mold other than the molds 73 and 74 is defined with the parting surface HPL1 on the XY plane of the molds 73 and 74 as a boundary. The mold is opened in the z direction using the keyway 80. The resin 76a formed by the conical gate hole 76 is cut by the parting surface HPL2 of FIG. 86 where the mold 73 functions as an ejector and stress concentration is large. If the molds 73 and 74 are sufficiently separated in the stacking direction (z direction), the guide pins 59a and 60a are removed from the molds other than the molds 73 and 74. Depending on the workability, the guide pins 59a and 60a may be fastened to the mold 74. This is because the assembly work of the dies 73 and 74 in the next step is faster and the efficiency is higher than when the dies 73 and 74 are completely separated.
[0232]
Next, the resin 87a formed by the cull portion 87 is separated by pushing up 76a from below or by applying a rotational moment with the gate 76 as the central axis on the interface between the mold 73 and the resin 87a. Can be mold.
[0233]
The thin plate-shaped mold regions 80A and 80B from which the guide pins 59a and 60a are removed do not have a strong coupling force to the molds 74 and 75 and can be easily separated. The force required to pull out the guide pins 59a and 60a is received by the die 74 due to the two upper molds, and local stress concentration is not generated in the laminated mold part. For this reason, the stacked package is not subjected to strong mechanical stress. That is, the guide pins 59a and 60a can be pulled out in the vertical direction (z direction) by the rigidity of the mold 74 and the rigidity of the mold 73.
[0234]
For the purpose of reducing the number of molds, two layers of the mold 74 and the mold 56b in contact with the mold 74 are synthesized, and three layers of the mold 74, the mold 56b in contact with the mold 56 and the mold 71 are synthesized, It is also possible to do. The same is possible for the mold 75.
[0235]
The released cavities 80 </ b> A and 80 </ b> B can be released by pulling each other in the positive and negative opposite directions in the x direction using the guide pin holes 60. When the laminated mold package is fixed to either the left or right laminated mold, the mold is released by pulling in the horizontal direction (x direction) using the guide pin hole 59 of the lead frame on the released side. can do.
[0236]
The above is the structure and forming method for the multi-piece forming of the four-layer mold package. This structure and forming method can be freely formed from a single layer to an arbitrary number of layers. Moreover, the transfer mold apparatus does not affect the change in the thickness of the laminated mold shown in FIG. 86, and can always obtain a stable mold clamping force.
[0237]
92 (a) and 92 (b) show the outer lead 6 when a solder-plated wire is used as the lead 7 in FIG. 84 and the solder fillet 93 of the lead 7 crossing between the stacked layers. The opening 8 of the outer lead 6 is connected and buried inside 93 by solder supplied by solder plating. This solder fillet 93 can also be controlled by the plating specifications of the outer leads 6.
[0238]
If the outer lead 6 is plated with Au and the solder is reflowed, the solder wettability is great, and the spread of the solder fillet 93 to the outer lead 6 is increased. Further, when the outer lead 6 is plated with Pd (palladium), since the spread of the solder is small, the solder fillet 93 can be formed with a small amount of solder.
[0239]
When the outer lead 6 is solder-plated, the spread of the solder is large and the solder easily flows through the entire outer lead 6. With this feature, when the lead pitch is narrow, a solder fillet shape that can ensure reliability with a small amount of solder plating can be obtained by using a surface treatment method with low solder wettability such as Pd plating.
[0240]
In addition, Au plating and Sn / Ni plating are processed on the lead frame 6 before die bonding, so that the outer plating is not performed after die bonding, wire bonding, and lamination molding, that is, the outer plating is omitted. Then, the outer lead 6 and the lead 7 can be solder reflowed. This is because Au plating or Sn / Ni plating becomes a strong oxidation-resistant film, and the surface of the outer lead 6 capable of solder reflow can be secured. By omitting the exterior plating (plating on the outer lead 6 after molding), it is possible to reduce the plating cost, plating solution penetration into the resin, and countermeasures against defects such as ion contamination.
[0241]
FIG. 92A shows the relative relationship between the shape of the solder fillet 93 of the lead 7 in which the flat portion 52 is formed in the J bend portion by press and the outer lead 6 portion on the upper portion and the bottom surface portion of the package 2. In order to prevent the lead 7 from being deformed, the bottom of the package 2 is provided with a recess 54 formed by the method shown in FIG. As shown by the thickness portion 94, the lead 7 is made thinner than the metal wire diameter 95 which becomes the base of the solder plating wire, and the width of the J bend portion is increased. Each outer lead 6 can form a uniform solder fillet 93 by solder supplied by a solder plating wire between layers. In order to improve the solder fluidity of the solder plating wire, instead of directly forming the solder plating on the surface of the metal wire, if the surface of the metal wire is plated with Ni etc. Becomes larger.
[0242]
As described above, the condition of solder connection between the outer lead 6 and the lead 7 connecting the stacked layers varies depending on the purpose depending on the shape, cost, heat resistance, etc. of the solder fillet 93.
[0243]
In order to improve workability when the lead 7 is passed through the opening 8 of the outer lead 6, the outer lead 6 as shown in FIGS. 93 (b) and 93 (c) may be used. That is, as shown in FIG. 93 (b), the broken lead 7 is press-fitted into the outer lead 6 provided with the groove 96 through the guide portion 97 into the groove 96 from the external X direction. At this time, in order to prevent the lead 7 from coming off, it is advantageous that the width of the groove 96 is smaller than the diameter of the lead 7. FIG. 93C shows a structure in which a slit 98 is further provided in order to increase the elastic force at the time of press-fitting into the groove 96. The press-fit resistance is characterized in that it can be made smaller in FIG. 93 (c) than in the case of FIG. 93 (b).
[0244]
It is also possible to electrically connect the outer lead 6 simply by press-fitting the lead 7. Further, when used in combination with solder reflow, higher connection reliability can be obtained. This is because, when used together with solder reflow, even if the solder becomes open due to some cause (for example, solder crack), the electrical connection at the intersection is ensured by the crimping effect.
[0245]
In order to press-fit a large number of leads 7 at a time, for example, considering the case where the shape of FIG. 93 (b) is applied to the outer leads of a four-layer module package, the outer leads 6 are arranged between the layers as shown in FIG. 100a is sandwiched by the same width as the interlayer space. Then, pressure is applied in the direction of the arrow 101 from the upper part and the lower part using the holding jigs 100c and 100b. Thereby, the mechanical damage of the outer lead 6 and the package 2 due to the press-fitting of the lead 7 can be reduced. In addition, the outer lead 6 can be prevented from falling or deforming during press-fitting.
[0246]
Next, the lead 7 having the cross section 7a is pressed in the direction of the arrow 102 by the press fitting jig 99 having the cross section 99a, so that four layers are press-fitted simultaneously. By simultaneously press-fitting the number of terminals of the lead 7 by this method, the outer lead 6 and the lead 7 can be cross-connected in a short time.
[0247]
In addition to bending the lead 7 in the Z direction into a J shape, a method of bending a part of the outer lead 6 of the laminated mold package into a J shape to make an SOJ will be described.
[0248]
In FIG. 95, the lowermost outer lead 6 is bent into a J shape. At this time, the lead frame 103 to be J-leaded is used with a terminal shape different from that of other lead frames or by changing the cutting shape of the outer lead 6. Although it is shown by a press-fit type outer lead, this structure is also possible in the shape of the opening 8. However, in order to press-fit the lead 7 by the method of FIG. 94 at the time of press-fitting, the lowermost end 105 of the lead 7 of FIG. 95 must be positioned below.
[0249]
Besides using the lead 7 as an SOJ, the laminated module structure of the present invention can be easily formed into an SO type flat package. FIG. 96 shows the lead shape of the flat package. As an application of the terminal of FIG. 78, the flat lead 107 can be formed using a terminal provided with the flat portion 51. This structure has the advantage that only the flat leads 107 can be heated and mounted on the substrate by the pulse heater method or the light beam soldering method in addition to the easy bending and high workability of the flat leads 107. is there. This is because the tip of the flat lead 107 can be heated without coming into contact with the outer lead 6 of the laminated portion because the foot of the flat lead 107 is outside the outer lead 6 of the laminated portion.
[0250]
As a terminal structure of the laminated mold package, there is a pin grid terminal structure shown in FIG. In order to prevent the narrow pitch of the leads 7 from being brought into the terminal pitch on the mounting board, the user interface is improved by using the multilayer printed circuit board 108 as a pitch conversion board and a face-centered pin grid and IPGA array (101).
[0251]
Further, the pins 110 may be omitted to form a BGA (ball grid array). The vertical lead 7 is solder-connected through a through terminal hole 109 provided in the multilayer printed circuit board 108, and can be converted to an IPGA or SPGA (50 mil pitch PGA) pitch by wiring of the multilayer printed circuit board 108. If the drilling process for the pin grid is omitted, a board layout that becomes a solder bump terminal of the BGA board is also possible.
[0252]
Further, by using the multilayer printed circuit board 108, it is easy to introduce a buffer amplifier such as an address buffer or an I / O buffer, an LSI having an error correction logic, or the like as a plastic PGA or BGA structure.
[0253]
(Example 4)
In this embodiment, a stacked DRAM structure is applied to an incomplete good product of 16MDRAM.
[0254]
The I / O 4bit product of 16MDRAM is normally 4194304 words x 4 bits, but some of the 4bit I / Os became defective during LSI manufacturing, and 4194304 words x 3 bits, 4194304 words x 2 bits, 4194304 words x 1 An incomplete DRAM with good bits can be produced.
[0255]
These are usually treated as defective products and have low merchantability. When commercialized, it disrupts the market in terms of terminal layout, stable supply, and bit price.
[0256]
A method of making these incomplete DRAMs into a complete terminal arrangement by applying this stacking technique will be described.
[0257]
The description shows that three incomplete DRAMs of 4194304 words × 3 bits are stacked to obtain a DRAM module with a constant terminal arrangement of 4194304 words × 9 bits.
[0258]
The lead frame used is shown in FIGS. 98 and 99, and has gate holes 61 and 62 and a guide pin hole 59. Further, in order to prevent deformation of the lead frame in the mold, a tie bar 113 for increasing the structural strength is connected to the tip of each outer lead. A groove 112 is provided by half-etching or the like to form a terminal of the outer lead after the lamination molding, thereby facilitating cutting.
[0259]
The I / O terminals of each lead frame are 9 terminals 111a to 111i. In FIG. 98, 111c, 111f and 111i are removed after cutting the tie bar by the half etching groove 115 provided in the tie bar 114. Similarly, 111a, 111d, 111h and 111e in FIG. 99 are also removed.
[0260]
Since there are three I / Os per DRAM chip, the lead frame of the first layer is bonded to non-defective I / Os on 111b, 111h, and 111e using a lead frame 78 shown in FIG. The lead frame of the second layer is bonded to a non-defective I / O on 111c, 111f, and 111i using a lead frame 78 shown in FIG. The lead frame of the third layer is bonded to a non-defective I / O on 111a, 111d, and 111g using a lead frame 78 shown in FIG. A defective I / O pad is not bonded.
[0261]
When three of these are stacked, 9-bit I / Os 111a to 111i are drawn out.
[0262]
That is, an incomplete 4M word × 3 bit DRAM chip is selectively bonded to a lead frame for stacking only non-defective I / O, thereby stacking 4M × 9 bit with complete I / O terminals after 3 layers. A DRAM can be obtained.
[0263]
Since this three-layer mold package is thinner than the SOJ package and has an integration degree equivalent to 36 megabits, it is possible to reduce the size of a 72 pin SIMM module having a 4M × 35 bit or 8M × 36 bit configuration.
[0264]
That is, normally, 4M × 36 bits must be implemented with a total of 12 4M × 4bit DRAMs, 4M × 4bit DRAMs, 4MM × 1bit DRAMs. Similarly, in the case of 8M × 36 bits, a total of 24 is usually required, but in this stacked module, 8 is sufficient.
[0265]
In addition, the number of wires on the SIMM substrate is small, and noise such as crosstalk between wires can be reduced.
[0266]
FIG. 100 shows an equivalent circuit of an 8M × 36 bit memory module when eight 4M × 9 bit stacked modules M0 to M7 are used.
[0267]
When M1, M5, M3, and M7 in FIG. 100 are not mounted, an equivalent circuit of a 4M × 36 bit memory module is obtained.
[0268]
In the case of a module of 4194304 words × 8 bits, it can be realized by stacking two DRAMs of 4194304 words × 3 bits and one DRAM of 4194304 × 2 bits. In addition, the number of stacked layers may be changed using 4194304 × 1 bits so that the number of bits of the same shape I / O is obtained.
[0269]
For example, as another method for obtaining 4194304 words × 9 bits, four 4194304 words × 2 bits and 4194304 words × 3 bits are combined and stacked.
[0270]
In order to use the lead frame of each layer in the laminated module in common, a bonding region and an outer lead are provided so as to be used in a plurality of layers as in the lead frame of FIG. For example, when nine I / Os 111a to 111i are drawn out completely independently, a module having a × 9 bit configuration can be applied to each layer with one type of lead frame regardless of the number of stacked layers. This has the advantage of greatly simplifying the assembly process and reducing costs.
[0271]
The invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Not too long.
[0272]
In the embodiment, the lead 7 of the mother socket 3 is inserted into the opening 8 of the outer lead 6 of the package 2 and connected to each other. However, the connection between the outer lead 6 of the package 2 and the lead 7 of the mother socket 3 is, for example, 101, a method of connecting the tip of the outer lead 6 against the side wall of the lead 7, and a method of connecting the lead 7 by inserting the lead 7 into a groove provided at the tip of the outer lead 6, as shown in FIG. 103, an opening 43 is provided on the lead 7 side of the mother socket 3, and the outer lead 6 can be inserted into the opening 43 and connected.
[0273]
In the DRAM module of the first embodiment, nine semiconductor chips are collectively sealed in one package. However, like the DRAM module of the second embodiment, the semiconductor module can be divided into a plurality of packages and sealed. In this case, various combinations such as 4 layers + 5 layers, 3 layers + 3 layers + 3 layers, 4 layers + 4 layers + 1 layers (for parity) can be selected. In this case, the heat dissipation efficiency can be further improved by sandwiching a heat diffusion plate made of an Al thin plate or a copper alloy plate having a high thermal conductivity in the gap between the divided packages.
[0274]
The method of sealing the semiconductor chip by dividing it into a plurality of packages can provide a great effect when applied to the multi-bit DRAM module described in the second embodiment or an SRAM module with particularly high power consumption. Another possible method is to reduce the number of stacked semiconductor chips in a region with low heat dissipation efficiency and increase the number of stacks in a region with high heat dissipation efficiency. For example, when the lower package has lower heat dissipation efficiency than the upper package, four semiconductor chips are sealed in the upper package, and two semiconductor chips are sealed in the lower package. A structure in which the above-described radiating fins are attached to the gap and the top and bottom is also possible.
[0275]
A semiconductor chip on which a DRAM controller, memory management, CPU, etc. are formed is mounted in the mother socket of the DRAM module of the first and second embodiments, and this semiconductor chip is electrically connected to the semiconductor chip in the package through the leads of the mother socket. It can also be connected. In this way, the functions of the DRAM module, the input impedance of the package 2 and the output driver capability can be easily improved by simply replacing the mother socket. Further, by providing the semiconductor chip in the mother socket with a redundancy function for relieving the defective memory of the semiconductor chip (M) sealed in the package 2, the manufacturing yield of the DRAM module can be greatly improved. FIG. 104 is a perspective view of a mother socket 49 used when a semiconductor chip is mounted. FIG. 105 is a perspective view of a DRAM module in which the package 2 of the first embodiment or the second embodiment is mounted on the mother socket 49.
[0276]
In the above embodiment, the case where the present invention is applied to a DRAM module has been described. However, the module structure of the present invention is a module using another memory such as an SRAM or a flash memory, or a memory chip and a logic chip mixedly mounted. It can also be applied to modules that have been used.
[0277]
In addition, the memory module of the present invention can be easily developed in various types such as a flat package and a pitgrid array simply by replacing the mother socket on which the package is mounted.
[0278]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.
[0279]
(1) According to the present invention, a plurality of LSI packages such as TSOP in which a plurality of semiconductor chips are sealed in a package at a time, and each semiconductor chip is sealed with a resin are stacked. External dimensions can be greatly reduced compared to modules. Further, by connecting the outer leads drawn out from the package and the leads of the socket so as to intersect with each other, a matrix-like heat dissipation path is formed, and the heat at the center of the package can be quickly dissipated to the outside. Further, since the outer leads are drawn out from the side surfaces of the package to form a leaf spring structure, the expansion and contraction of the resin filled in the gaps between the stacked lead frames can be reduced.
[0280]
As a result, a small and high performance multichip module can be realized.
[0281]
(2). According to the present invention, each lead frame is individually designed, and the arrangement of the data pins is changed by each lead frame, so that the package can be directly connected between the stacked lead frames. Can be
[0282]
(3) According to the present invention, a series of lead frames with uniform dimensional accuracy can be obtained by forming a predetermined number of lead frames as one set of lead frames by batch patterning in the same process. Miniaturization of the chip module can be promoted.
[0283]
(4) According to the present invention, by using a tape dam type lead frame in which an insulating tape is joined on a mold line, testing, sorting, and aging can be performed immediately before the molding process. The module manufacturing yield can be improved.
[0284]
(5) According to the present invention, by providing a pair of floating gate holes in each of the lead frames, the flow of the resin in the mold can be made uniform, improving the reliability and manufacturing yield of the package. To do.
[0285]
(6) According to the present invention, the lead frame layer number identification is automatically read at the time of mass production by providing an index hole of a different pattern for each lead frame in each frame portion of the lead frame. Since it can be easily determined whether or not the layers are stacked in the correct order, the manufacturing yield and throughput of the package can be improved.
[0286]
(7) According to the present invention, by providing a half-etch line on each of the lead frames, it becomes easy to cut and remove unnecessary portions of the lead frame exposed to the outside of the package after molding. Manufacturing yield and throughput can be improved.
[0287]
(8) According to the present invention, by mounting the capacitor on the lead frame, it is possible to reduce the power supply impedance when power is supplied to the semiconductor chip, so that a large current can be supplied.
[0288]
(9) According to the present invention, the joint strength between the lead and the outer lead can be improved by accommodating the dummy lead frame inside the package. Moreover, since the heat dissipation path of the package is increased, the thermal resistance can be reduced. Furthermore, a dummy lead frame can be used as a wiring connection in the package.
[0289]
(10). According to the present invention, the socket lead is made of a conductive material having a thermal expansion coefficient substantially equal to the thermal expansion coefficient of the package, thereby generating an anisotropic effect between the vertical direction and the horizontal direction of the package. Since the thermal stress stress caused by thermal expansion can be reduced, the reliability of the multichip module is improved.
[0290]
(11). According to the present invention, a socket corresponding to a multi-bit module can be obtained by arranging two rows of socket leads along two opposite sides of the socket.
[0291]
(12) According to the present invention, a multi-chip module with high cooling efficiency can be obtained by mounting the radiation fins on the package.
[0292]
(13). According to the present invention, by mounting a semiconductor chip on the lead frame in a lead-on-chip manner, the lead frame layer can be thinned, and the package can be downsized and the thermal resistance can be reduced. be able to.
[0293]
(14). According to the present invention, by arranging the center of the semiconductor chip mounted on each of the lead frames closer to the data pin side of the lead frame than the center of the resin package, the routing of the data pins can be reduced. Therefore, the package can be downsized.
[0294]
(15) According to the present invention, by accommodating the dummy chip inside the package, the flow of the resin when the package is molded can be made uniform, so that the reliability of the multichip module is improved.
[0295]
(16) According to the present invention, a part of the lead frame is inverted 180 degrees in the horizontal plane with respect to the other lead frames, so that the data pins of the lead frame are concentrated in one direction. Therefore, the lead can be easily routed and the lead frame can be downsized.
[0296]
(17). According to the present invention, among the predetermined number of lead frames, the lead frame that is reversed and the other lead frame have a lead pattern that is symmetrical with respect to the reverse axis. The number of lead frame types can be halved, and the manufacturing cost can be reduced. In addition, aging varieties can be reduced.
[0297]
(18). According to the present invention, by incorporating a semiconductor chip having various functions in the socket, it is possible to easily realize the function expansion of the multichip module, the improvement of input / output characteristics, the memory defect repair, and the like. be able to.
[0298]
(19). According to the present invention, there is provided a mold composed of an upper mold and a lower mold, and a predetermined number of movable molds that are inserted into gaps between a predetermined number of lead frames and can be divided into two. The package can be easily released from the mold by batch-sealing a predetermined number of lead frames using, so that the manufacturing yield and throughput of the package can be improved.
[Brief description of the drawings]
FIG. 1 is a front perspective view of a DRAM module according to an embodiment of the present invention.
FIG. 2 is a rear perspective view of a DRAM module according to an embodiment of the present invention.
FIG. 3 is a front perspective view of a package of a DRAM module according to an embodiment of the present invention.
FIG. 4 is a front perspective view of a mother socket of a DRAM module according to an embodiment of the present invention.
FIG. 5 is an equivalent circuit diagram of a DRAM module according to an embodiment of the present invention.
FIG. 6 is a plan view showing a pad layout of a semiconductor chip.
FIG. 7 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 8 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 9 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 10 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 11 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 12 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 13 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 14 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 15 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 16 is a plan view showing a pin arrangement of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 17 is a perspective view of a nested mold used for manufacturing a DRAM module according to an embodiment of the present invention.
FIG. 18 is a perspective view of a nested mold used for manufacturing a DRAM module according to an embodiment of the present invention.
FIG. 19 is an exploded perspective view of a nested mold used for manufacturing a DRAM module according to an embodiment of the present invention.
FIG. 20 is an exploded perspective view of a nested mold used for manufacturing a DRAM module according to an embodiment of the present invention.
FIG. 21 is a plan view (a) and a side view (b) of a movable mold used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 22 is a front perspective view of a DRAM module according to another embodiment of the present invention.
FIG. 23 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 24 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 25 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 26 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 27 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 28 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 29 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
30 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention; FIG.
FIG. 31 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 32 is a perspective view schematically showing the flow of resin inside the mold.
FIG. 33 is a perspective view showing a pair of movable molds of the mold used for manufacturing the mother socket.
FIG. 34 is a perspective view showing a pair of central molds of the mold used for manufacturing the mother socket.
FIG. 35 is a plan view of a lead frame used for manufacturing a mother socket.
FIG. 36 is a plan view of a lead frame used for manufacturing a mother socket.
FIG. 37 is a plan view of a lead frame used for manufacturing a mother socket.
FIG. 38 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 39 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 40 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
41 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention; FIG.
FIG. 42 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 43 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
44 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention; FIG.
FIG. 45 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 46 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
47 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention; FIG.
48 is an overall plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention; FIG.
FIG. 49 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
50 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention; FIG.
FIG. 51 is an equivalent circuit diagram of a DRAM module according to an embodiment of the present invention.
FIG. 52 is a plan view showing a pin arrangement of a DRAM module according to an embodiment of the present invention.
FIG. 53 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 54 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 55 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 56 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 57 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 58 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 59 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 60 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 61 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 62 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
63 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention; FIG.
FIG. 64 is a plan view of a lead frame used for manufacturing a DRAM module according to an embodiment of the present invention;
FIG. 65 is a perspective view of a mother socket of a DRAM module that is an embodiment of the present invention.
FIG. 66 is a plan view showing the pin arrangement on the upper surface of the mother socket.
67 is a plan view of a lead frame for a mother socket. FIG.
68 is a plan view of a lead frame for a mother socket. FIG.
FIG. 69 is a perspective view of a DRAM module according to an embodiment of the present invention.
FIG. 70 is a perspective view of a DRAM module according to an embodiment of the present invention.
71 is a perspective view of a DRAM module according to an embodiment of the present invention. FIG.
72 is a perspective view of a DRAM module according to an embodiment of the present invention. FIG.
FIG. 73 is a side view of a heat radiating fin attached to the DRAM module according to one embodiment of the present invention;
74 is a perspective view of heat radiation fins attached to the DRAM module according to one embodiment of the present invention; FIG.
FIG. 75 is a perspective view of a heat radiating fin attached to a DRAM module according to an embodiment of the present invention.
FIG. 76 is an equivalent circuit diagram of a DRAM module according to an embodiment of the present invention.
FIG. 77 is a front perspective view of a DRAM module according to another embodiment of the present invention.
FIG. 78 is a perspective view showing a method for connecting a lead and an outer lead of a package.
79 is a perspective view showing a lead having a lower end formed into a J shape. FIG.
FIG. 80 is a lower perspective view of a DRAM module according to another embodiment of the present invention.
FIG. 81 is a cross-sectional view (a) and a bottom view (b) showing a conventional method for forming a recess in the bottom of a package.
FIG. 82 is a cross-sectional view (a) and a bottom view (b) showing a method of the present invention for forming a recess in the bottom of a package.
FIG. 83 is a side view of the movable mold (a), (b), (c), plan views (d), (e) of the movable mold shown in (b) and gate holes provided in the movable mold; It is a top view (f).
FIG. 84 is a plan view (a) and a sectional view (b) of a gate hole provided in the movable mold.
85 (a) and 85 (b) are perspective views showing a method for manufacturing a movable mold.
FIG. 86 is a configuration diagram of a mold system that takes two stacked module type packages in the stacking direction.
87 is a plan view (a) of a gate hole and a dummy cavity of a mold, and a sectional view (c) in the YY ′ direction of perspective views (b) and (b). FIG.
FIG. 88 is a plan view (a) and enlarged plan views (b), (c) showing the positional relationship between the gate hole of the movable mold and the gate hole of the mold.
FIG. 89 is an enlarged perspective view (a) of the slit gate and an enlarged perspective view (b) of the pin gate.
FIG. 90 is a schematic configuration diagram of a molding apparatus having a gate in the vertical direction.
91 is a perspective view for explaining a mold release method of the molding apparatus shown in FIG. 90. FIG.
FIG. 92 is a side view (a) and a perspective view (b) showing a solder fillet of a lead connected to an outer lead.
93 (a), (b), and (c) are enlarged plan views showing modifications of the outer lead. FIG.
FIG. 94 is an explanatory diagram showing a method for press-fitting a lead into an outer lead.
FIG. 95 is an enlarged perspective view showing a modification of the lead.
FIG. 96 is an enlarged perspective view showing a modification of the lead.
FIG. 97 is a lower perspective view of a DRAM module according to another embodiment of the present invention.
FIG. 98 is a plan view of a lead frame used for manufacturing a DRAM module according to another embodiment of the present invention;
FIG. 99 is a plan view of a lead frame used for manufacturing a DRAM module according to another embodiment of the present invention;
FIG. 100 is an equivalent circuit diagram of a DRAM module according to another embodiment of the present invention.
FIG. 101 is a plan view (a) and a side view (b) showing a method for connecting the lead of the mother socket and the outer lead of the package.
FIG. 102 is a plan view (a) and a side view (b) showing a method of connecting the lead of the mother socket and the outer lead of the package.
FIG. 103 is a perspective view showing a method for connecting the lead of the mother socket and the outer lead of the package.
FIG. 104 is a front perspective view of a mother socket of a DRAM module according to another embodiment of the present invention.
FIG. 105 is a front perspective view of a DRAM module according to another embodiment of the present invention.
[Explanation of symbols]
1 DRAM module
2 packages
3 Mother socket
4 Insulation tape
5 wires
6 Outer lead
7 Lead
8 Opening
10 Nested mold
11 Upper mold
12 Lower mold
13 Movable mold
14 Mold gate hole
15 Gate
16 gate
17 Index hole
18 Index hole
19 Half etch line
20 Lead frame for mother socket
21L movable mold
21R movable mold
22 Central mold
Lead frame for 23L mother socket
Lead frame for 23R mother socket
24 Insulation tape
26 Center hole
30 Bonding pads
31 Decoupling capacitor
40 DRAM module
41 Heat radiation fin
44 Opening
45 Gate line
46 Gate line
47 Guide pin
48 Opening
49 Mother socket
50 Flat part
51 Flat part
52 Flat part
53 packages
54 depression
55 groove
56 Movable mold
56a Movable mold
56b Movable mold
56c movable mold
57 cavity
58 cavity
59 Guide pin hole
59a Guide pin
60 Guide pin hole
60a guide pin
61 Gate hole
62 Gate hole
67 Connection
68 blocks
69 Movable mold
70 cut line
71 mold
72 Mold
73 Mold
74 Mold
75 mold
76 Gate hole
77 dummy cavity
78 Lead frame
79 Semiconductor chip
80 key groove
80A cavity
80B cavity
81 cavities
82 Slit gate
83 pin gate
84 areas
85a pot
85b Plunger
87 Cal
87a resin
88 mold
89 Movable mold
90 O-ring
91 holes
93 Solder fillet
94 Thickness part
95 Metal wire diameter
96 grooves
97 Guide
98 slits
99 Press-fitting jig
99a cross section
101 arrow
101a prism
101b Holding jig
101c Holding jig
102 arrow
103 Lead frame
105 Bottom end
107 flat lead
108 Multilayer printed circuit board
109 Through terminal hole
110 pins
111a to 111i terminals
112 groove
113 Thai Bar
114 tie bar
115 Half-etched groove
M, M ₀ ~ M ₁₁ Semiconductor chip
S, S ₀ ~ S ₉ Lead frame
T, T ₀ ~ T ₉ Lead frame
L ₁ ~ L ₁₂ Lead frame
PL parting line

Claims (22)

  A resin package in which a predetermined number of lead frames on which semiconductor chips are mounted is stacked and sealed together is mounted on a socket, and the outer lead of the lead frame drawn out from the resin package intersects the extending direction of the outer lead. A semiconductor integrated circuit device in which the leads of the socket extending in a direction to be connected are electrically connected, wherein the predetermined number of lead frames include ones having different data pin arrangements. apparatus.   A resin package in which a predetermined number of lead frames on which semiconductor chips are mounted is stacked and sealed together is mounted on a socket, and the outer lead of the lead frame drawn out from the resin package intersects the extending direction of the outer lead. A semiconductor integrated circuit device in which leads of the socket extending in a direction to be connected are electrically connected, and the predetermined number of lead frames are tape dam type lead frames in which an insulating tape is bonded onto a mold line. A semiconductor integrated circuit device.   A resin package in which a predetermined number of lead frames on which semiconductor chips are mounted is stacked and sealed together is mounted on a socket, and the outer lead of the lead frame drawn out from the resin package intersects the extending direction of the outer lead. A semiconductor integrated circuit device in which leads of the socket extending in a direction to be connected are electrically connected, wherein a pair of molding gate holes are provided in each of the predetermined number of lead frames. Circuit device.   A resin package in which a predetermined number of lead frames on which semiconductor chips are mounted is stacked and sealed together is mounted on a socket, and the outer lead of the lead frame drawn out from the resin package intersects the extending direction of the outer lead. A semiconductor integrated circuit device in which leads of the socket extending in a direction to be connected are electrically connected, wherein the predetermined number of lead frames are formed by resin molding of tie bar portions for joining the leads. A semiconductor integrated circuit device.   A resin package in which a predetermined number of lead frames on which semiconductor chips are mounted is stacked and sealed together is mounted on a socket, and the outer lead of the lead frame drawn out from the resin package intersects the extending direction of the outer lead. A semiconductor integrated circuit device in which a lead of the socket extending in a direction is electrically connected, and a half-etch line is provided in each of the predetermined number of lead frames.   A resin package in which a predetermined number of lead frames on which semiconductor chips are mounted is stacked and sealed together is mounted on a socket, and the outer lead of the lead frame drawn out from the resin package intersects the extending direction of the outer lead. A semiconductor integrated circuit device in which a lead of the socket extending in a direction to be connected is electrically connected, and a dummy lead frame is accommodated in the resin package. A resin package in which a predetermined number of lead frames on which semiconductor chips are mounted is stacked and sealed together is mounted on a socket, and the outer lead of the lead frame drawn out from the resin package intersects with the extending direction of the outer lead. A semiconductor integrated circuit device electrically connected to the socket leads extending in the direction of the conductive material, the conductive material having a thermal expansion coefficient capable of following the vertical expansion and contraction of the resin package. A semiconductor integrated circuit device comprising a copper alloy .   A resin package in which a predetermined number of lead frames on which semiconductor chips are mounted is stacked and sealed together is mounted on a socket, and the outer lead of the lead frame drawn out from the resin package intersects the extending direction of the outer lead. A semiconductor integrated circuit device in which the leads of the socket extending in the direction to be connected are electrically connected, and a part of the predetermined number of lead frames is inverted 180 degrees in a horizontal plane with respect to other lead frames. A semiconductor integrated circuit device characterized by being arranged.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A semiconductor integrated circuit device that is electrically connected and has a lower end portion of the lead formed into a J shape to constitute an external terminal of the resin package, wherein the predetermined number of lead frames have different data pin arrangements A semiconductor integrated circuit device comprising:   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads The semiconductor integrated circuit device is configured to be electrically connected and to form an external terminal of the resin package by forming a lower end portion of the lead into a J shape, and the predetermined number of lead frames are provided with an insulating tape on a mold line. A semiconductor integrated circuit device, wherein the lead frame is a bonded tape dam type lead frame.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A semiconductor integrated circuit device which is electrically connected and has a lower end portion of the lead formed into a J shape to constitute an external terminal of the resin package, wherein a pair of molding gate holes are formed in each of the predetermined number of lead frames. A semiconductor integrated circuit device comprising:   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A semiconductor integrated circuit device which is electrically connected and has a lower end portion of the lead formed into a J shape to constitute an external terminal of the resin package, wherein the predetermined number of lead frames are tie bar portions for joining the leads. Is formed by resin molding. A semiconductor integrated circuit device.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A semiconductor integrated circuit device which is electrically connected and has a lower end portion of the lead formed into a J shape to constitute an external terminal of the resin package, wherein a half-etch line is provided in each of the predetermined number of lead frames. A semiconductor integrated circuit device.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A semiconductor integrated circuit device which is electrically connected and has a lower end portion of the lead formed into a J shape to constitute an external terminal of the resin package, wherein a dummy lead frame is accommodated inside the resin package. A semiconductor integrated circuit device.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A semiconductor integrated circuit device which is electrically connected and has a lower end portion of the lead formed into a J shape to constitute an external terminal of the resin package, wherein a part of the predetermined number of lead frames is a part of another lead frame. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is disposed by being inverted 180 degrees in a horizontal plane.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A predetermined number of the semiconductor integrated circuit devices, wherein the predetermined number of outer leads are electrically connected and outer terminals located in the lowermost layer of the resin package among the outer leads are molded into a J shape. The semiconductor integrated circuit device according to claim 1, wherein the lead frame includes one having a different data pin arrangement.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A predetermined number of the semiconductor integrated circuit devices, wherein the predetermined number of outer leads are electrically connected and outer terminals located in the lowermost layer of the resin package among the outer leads are molded into a J shape. The semiconductor integrated circuit device is characterized in that the lead frame is a tape dam type lead frame in which an insulating tape is joined on a mold line.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A predetermined number of the semiconductor integrated circuit devices, wherein the predetermined number of outer leads are electrically connected and outer terminals located in the lowermost layer of the resin package among the outer leads are molded into a J shape. A semiconductor integrated circuit device, wherein a pair of molding gate holes is provided in each of the lead frames.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A predetermined number of the semiconductor integrated circuit devices, wherein the predetermined number of outer leads are electrically connected and outer terminals located in the lowermost layer of the resin package among the outer leads are molded into a J shape. The lead frame is a semiconductor integrated circuit device in which a tie bar portion for joining the leads is formed by resin molding.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A predetermined number of the semiconductor integrated circuit devices, wherein the predetermined number of outer leads are electrically connected and outer terminals located in the lowermost layer of the resin package among the outer leads are molded into a J shape. A semiconductor integrated circuit device, wherein a half-etch line is provided in each of the lead frames.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A semiconductor integrated circuit device which is electrically connected and an outer lead located in the lowermost layer of the resin package among the outer leads is formed into a J shape to constitute an external terminal of the resin package, wherein the resin package A semiconductor integrated circuit device characterized in that a dummy lead frame is housed inside.   Outer leads of the lead frame drawn from a resin package in which a predetermined number of lead frames on which semiconductor chips are mounted are stacked and sealed together, and leads extending in a direction intersecting with the extending direction of the outer leads A predetermined number of the semiconductor integrated circuit devices, wherein the predetermined number of outer leads are electrically connected and outer terminals located in the lowermost layer of the resin package among the outer leads are molded into a J shape. A part of the lead frame of the semiconductor integrated circuit device is arranged to be inverted 180 degrees in a horizontal plane with respect to the other lead frame.

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